cache-l2x0.c 48 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756
  1. /*
  2. * arch/arm/mm/cache-l2x0.c - L210/L220/L310 cache controller support
  3. *
  4. * Copyright (C) 2007 ARM Limited
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <linux/cpu.h>
  20. #include <linux/err.h>
  21. #include <linux/init.h>
  22. #include <linux/smp.h>
  23. #include <linux/spinlock.h>
  24. #include <linux/log2.h>
  25. #include <linux/io.h>
  26. #include <linux/of.h>
  27. #include <linux/of_address.h>
  28. #include <asm/cacheflush.h>
  29. #include <asm/cp15.h>
  30. #include <asm/cputype.h>
  31. #include <asm/hardware/cache-l2x0.h>
  32. #include "cache-tauros3.h"
  33. #include "cache-aurora-l2.h"
  34. struct l2c_init_data {
  35. const char *type;
  36. unsigned way_size_0;
  37. unsigned num_lock;
  38. void (*of_parse)(const struct device_node *, u32 *, u32 *);
  39. void (*enable)(void __iomem *, unsigned);
  40. void (*fixup)(void __iomem *, u32, struct outer_cache_fns *);
  41. void (*save)(void __iomem *);
  42. void (*configure)(void __iomem *);
  43. void (*unlock)(void __iomem *, unsigned);
  44. struct outer_cache_fns outer_cache;
  45. };
  46. #define CACHE_LINE_SIZE 32
  47. static void __iomem *l2x0_base;
  48. static const struct l2c_init_data *l2x0_data;
  49. static DEFINE_RAW_SPINLOCK(l2x0_lock);
  50. static u32 l2x0_way_mask; /* Bitmask of active ways */
  51. static u32 l2x0_size;
  52. static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
  53. struct l2x0_regs l2x0_saved_regs;
  54. /*
  55. * Common code for all cache controllers.
  56. */
  57. static inline void l2c_wait_mask(void __iomem *reg, unsigned long mask)
  58. {
  59. /* wait for cache operation by line or way to complete */
  60. while (readl_relaxed(reg) & mask)
  61. cpu_relax();
  62. }
  63. /*
  64. * By default, we write directly to secure registers. Platforms must
  65. * override this if they are running non-secure.
  66. */
  67. static void l2c_write_sec(unsigned long val, void __iomem *base, unsigned reg)
  68. {
  69. if (val == readl_relaxed(base + reg))
  70. return;
  71. if (outer_cache.write_sec)
  72. outer_cache.write_sec(val, reg);
  73. else
  74. writel_relaxed(val, base + reg);
  75. }
  76. /*
  77. * This should only be called when we have a requirement that the
  78. * register be written due to a work-around, as platforms running
  79. * in non-secure mode may not be able to access this register.
  80. */
  81. static inline void l2c_set_debug(void __iomem *base, unsigned long val)
  82. {
  83. l2c_write_sec(val, base, L2X0_DEBUG_CTRL);
  84. }
  85. static void __l2c_op_way(void __iomem *reg)
  86. {
  87. writel_relaxed(l2x0_way_mask, reg);
  88. l2c_wait_mask(reg, l2x0_way_mask);
  89. }
  90. static inline void l2c_unlock(void __iomem *base, unsigned num)
  91. {
  92. unsigned i;
  93. for (i = 0; i < num; i++) {
  94. writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_D_BASE +
  95. i * L2X0_LOCKDOWN_STRIDE);
  96. writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_I_BASE +
  97. i * L2X0_LOCKDOWN_STRIDE);
  98. }
  99. }
  100. static void l2c_configure(void __iomem *base)
  101. {
  102. l2c_write_sec(l2x0_saved_regs.aux_ctrl, base, L2X0_AUX_CTRL);
  103. }
  104. /*
  105. * Enable the L2 cache controller. This function must only be
  106. * called when the cache controller is known to be disabled.
  107. */
  108. static void l2c_enable(void __iomem *base, unsigned num_lock)
  109. {
  110. unsigned long flags;
  111. if (outer_cache.configure)
  112. outer_cache.configure(&l2x0_saved_regs);
  113. else
  114. l2x0_data->configure(base);
  115. l2x0_data->unlock(base, num_lock);
  116. local_irq_save(flags);
  117. __l2c_op_way(base + L2X0_INV_WAY);
  118. writel_relaxed(0, base + sync_reg_offset);
  119. l2c_wait_mask(base + sync_reg_offset, 1);
  120. local_irq_restore(flags);
  121. l2c_write_sec(L2X0_CTRL_EN, base, L2X0_CTRL);
  122. }
  123. static void l2c_disable(void)
  124. {
  125. void __iomem *base = l2x0_base;
  126. outer_cache.flush_all();
  127. l2c_write_sec(0, base, L2X0_CTRL);
  128. dsb(st);
  129. }
  130. static void l2c_save(void __iomem *base)
  131. {
  132. l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
  133. }
  134. static void l2c_resume(void)
  135. {
  136. void __iomem *base = l2x0_base;
  137. /* Do not touch the controller if already enabled. */
  138. if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN))
  139. l2c_enable(base, l2x0_data->num_lock);
  140. }
  141. /*
  142. * L2C-210 specific code.
  143. *
  144. * The L2C-2x0 PA, set/way and sync operations are atomic, but we must
  145. * ensure that no background operation is running. The way operations
  146. * are all background tasks.
  147. *
  148. * While a background operation is in progress, any new operation is
  149. * ignored (unspecified whether this causes an error.) Thankfully, not
  150. * used on SMP.
  151. *
  152. * Never has a different sync register other than L2X0_CACHE_SYNC, but
  153. * we use sync_reg_offset here so we can share some of this with L2C-310.
  154. */
  155. static void __l2c210_cache_sync(void __iomem *base)
  156. {
  157. writel_relaxed(0, base + sync_reg_offset);
  158. }
  159. static void __l2c210_op_pa_range(void __iomem *reg, unsigned long start,
  160. unsigned long end)
  161. {
  162. while (start < end) {
  163. writel_relaxed(start, reg);
  164. start += CACHE_LINE_SIZE;
  165. }
  166. }
  167. static void l2c210_inv_range(unsigned long start, unsigned long end)
  168. {
  169. void __iomem *base = l2x0_base;
  170. if (start & (CACHE_LINE_SIZE - 1)) {
  171. start &= ~(CACHE_LINE_SIZE - 1);
  172. writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA);
  173. start += CACHE_LINE_SIZE;
  174. }
  175. if (end & (CACHE_LINE_SIZE - 1)) {
  176. end &= ~(CACHE_LINE_SIZE - 1);
  177. writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA);
  178. }
  179. __l2c210_op_pa_range(base + L2X0_INV_LINE_PA, start, end);
  180. __l2c210_cache_sync(base);
  181. }
  182. static void l2c210_clean_range(unsigned long start, unsigned long end)
  183. {
  184. void __iomem *base = l2x0_base;
  185. start &= ~(CACHE_LINE_SIZE - 1);
  186. __l2c210_op_pa_range(base + L2X0_CLEAN_LINE_PA, start, end);
  187. __l2c210_cache_sync(base);
  188. }
  189. static void l2c210_flush_range(unsigned long start, unsigned long end)
  190. {
  191. void __iomem *base = l2x0_base;
  192. start &= ~(CACHE_LINE_SIZE - 1);
  193. __l2c210_op_pa_range(base + L2X0_CLEAN_INV_LINE_PA, start, end);
  194. __l2c210_cache_sync(base);
  195. }
  196. static void l2c210_flush_all(void)
  197. {
  198. void __iomem *base = l2x0_base;
  199. BUG_ON(!irqs_disabled());
  200. __l2c_op_way(base + L2X0_CLEAN_INV_WAY);
  201. __l2c210_cache_sync(base);
  202. }
  203. static void l2c210_sync(void)
  204. {
  205. __l2c210_cache_sync(l2x0_base);
  206. }
  207. static const struct l2c_init_data l2c210_data __initconst = {
  208. .type = "L2C-210",
  209. .way_size_0 = SZ_8K,
  210. .num_lock = 1,
  211. .enable = l2c_enable,
  212. .save = l2c_save,
  213. .configure = l2c_configure,
  214. .unlock = l2c_unlock,
  215. .outer_cache = {
  216. .inv_range = l2c210_inv_range,
  217. .clean_range = l2c210_clean_range,
  218. .flush_range = l2c210_flush_range,
  219. .flush_all = l2c210_flush_all,
  220. .disable = l2c_disable,
  221. .sync = l2c210_sync,
  222. .resume = l2c_resume,
  223. },
  224. };
  225. /*
  226. * L2C-220 specific code.
  227. *
  228. * All operations are background operations: they have to be waited for.
  229. * Conflicting requests generate a slave error (which will cause an
  230. * imprecise abort.) Never uses sync_reg_offset, so we hard-code the
  231. * sync register here.
  232. *
  233. * However, we can re-use the l2c210_resume call.
  234. */
  235. static inline void __l2c220_cache_sync(void __iomem *base)
  236. {
  237. writel_relaxed(0, base + L2X0_CACHE_SYNC);
  238. l2c_wait_mask(base + L2X0_CACHE_SYNC, 1);
  239. }
  240. static void l2c220_op_way(void __iomem *base, unsigned reg)
  241. {
  242. unsigned long flags;
  243. raw_spin_lock_irqsave(&l2x0_lock, flags);
  244. __l2c_op_way(base + reg);
  245. __l2c220_cache_sync(base);
  246. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  247. }
  248. static unsigned long l2c220_op_pa_range(void __iomem *reg, unsigned long start,
  249. unsigned long end, unsigned long flags)
  250. {
  251. raw_spinlock_t *lock = &l2x0_lock;
  252. while (start < end) {
  253. unsigned long blk_end = start + min(end - start, 4096UL);
  254. while (start < blk_end) {
  255. l2c_wait_mask(reg, 1);
  256. writel_relaxed(start, reg);
  257. start += CACHE_LINE_SIZE;
  258. }
  259. if (blk_end < end) {
  260. raw_spin_unlock_irqrestore(lock, flags);
  261. raw_spin_lock_irqsave(lock, flags);
  262. }
  263. }
  264. return flags;
  265. }
  266. static void l2c220_inv_range(unsigned long start, unsigned long end)
  267. {
  268. void __iomem *base = l2x0_base;
  269. unsigned long flags;
  270. raw_spin_lock_irqsave(&l2x0_lock, flags);
  271. if ((start | end) & (CACHE_LINE_SIZE - 1)) {
  272. if (start & (CACHE_LINE_SIZE - 1)) {
  273. start &= ~(CACHE_LINE_SIZE - 1);
  274. writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA);
  275. start += CACHE_LINE_SIZE;
  276. }
  277. if (end & (CACHE_LINE_SIZE - 1)) {
  278. end &= ~(CACHE_LINE_SIZE - 1);
  279. l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1);
  280. writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA);
  281. }
  282. }
  283. flags = l2c220_op_pa_range(base + L2X0_INV_LINE_PA,
  284. start, end, flags);
  285. l2c_wait_mask(base + L2X0_INV_LINE_PA, 1);
  286. __l2c220_cache_sync(base);
  287. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  288. }
  289. static void l2c220_clean_range(unsigned long start, unsigned long end)
  290. {
  291. void __iomem *base = l2x0_base;
  292. unsigned long flags;
  293. start &= ~(CACHE_LINE_SIZE - 1);
  294. if ((end - start) >= l2x0_size) {
  295. l2c220_op_way(base, L2X0_CLEAN_WAY);
  296. return;
  297. }
  298. raw_spin_lock_irqsave(&l2x0_lock, flags);
  299. flags = l2c220_op_pa_range(base + L2X0_CLEAN_LINE_PA,
  300. start, end, flags);
  301. l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1);
  302. __l2c220_cache_sync(base);
  303. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  304. }
  305. static void l2c220_flush_range(unsigned long start, unsigned long end)
  306. {
  307. void __iomem *base = l2x0_base;
  308. unsigned long flags;
  309. start &= ~(CACHE_LINE_SIZE - 1);
  310. if ((end - start) >= l2x0_size) {
  311. l2c220_op_way(base, L2X0_CLEAN_INV_WAY);
  312. return;
  313. }
  314. raw_spin_lock_irqsave(&l2x0_lock, flags);
  315. flags = l2c220_op_pa_range(base + L2X0_CLEAN_INV_LINE_PA,
  316. start, end, flags);
  317. l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1);
  318. __l2c220_cache_sync(base);
  319. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  320. }
  321. static void l2c220_flush_all(void)
  322. {
  323. l2c220_op_way(l2x0_base, L2X0_CLEAN_INV_WAY);
  324. }
  325. static void l2c220_sync(void)
  326. {
  327. unsigned long flags;
  328. raw_spin_lock_irqsave(&l2x0_lock, flags);
  329. __l2c220_cache_sync(l2x0_base);
  330. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  331. }
  332. static void l2c220_enable(void __iomem *base, unsigned num_lock)
  333. {
  334. /*
  335. * Always enable non-secure access to the lockdown registers -
  336. * we write to them as part of the L2C enable sequence so they
  337. * need to be accessible.
  338. */
  339. l2x0_saved_regs.aux_ctrl |= L220_AUX_CTRL_NS_LOCKDOWN;
  340. l2c_enable(base, num_lock);
  341. }
  342. static void l2c220_unlock(void __iomem *base, unsigned num_lock)
  343. {
  344. if (readl_relaxed(base + L2X0_AUX_CTRL) & L220_AUX_CTRL_NS_LOCKDOWN)
  345. l2c_unlock(base, num_lock);
  346. }
  347. static const struct l2c_init_data l2c220_data = {
  348. .type = "L2C-220",
  349. .way_size_0 = SZ_8K,
  350. .num_lock = 1,
  351. .enable = l2c220_enable,
  352. .save = l2c_save,
  353. .configure = l2c_configure,
  354. .unlock = l2c220_unlock,
  355. .outer_cache = {
  356. .inv_range = l2c220_inv_range,
  357. .clean_range = l2c220_clean_range,
  358. .flush_range = l2c220_flush_range,
  359. .flush_all = l2c220_flush_all,
  360. .disable = l2c_disable,
  361. .sync = l2c220_sync,
  362. .resume = l2c_resume,
  363. },
  364. };
  365. /*
  366. * L2C-310 specific code.
  367. *
  368. * Very similar to L2C-210, the PA, set/way and sync operations are atomic,
  369. * and the way operations are all background tasks. However, issuing an
  370. * operation while a background operation is in progress results in a
  371. * SLVERR response. We can reuse:
  372. *
  373. * __l2c210_cache_sync (using sync_reg_offset)
  374. * l2c210_sync
  375. * l2c210_inv_range (if 588369 is not applicable)
  376. * l2c210_clean_range
  377. * l2c210_flush_range (if 588369 is not applicable)
  378. * l2c210_flush_all (if 727915 is not applicable)
  379. *
  380. * Errata:
  381. * 588369: PL310 R0P0->R1P0, fixed R2P0.
  382. * Affects: all clean+invalidate operations
  383. * clean and invalidate skips the invalidate step, so we need to issue
  384. * separate operations. We also require the above debug workaround
  385. * enclosing this code fragment on affected parts. On unaffected parts,
  386. * we must not use this workaround without the debug register writes
  387. * to avoid exposing a problem similar to 727915.
  388. *
  389. * 727915: PL310 R2P0->R3P0, fixed R3P1.
  390. * Affects: clean+invalidate by way
  391. * clean and invalidate by way runs in the background, and a store can
  392. * hit the line between the clean operation and invalidate operation,
  393. * resulting in the store being lost.
  394. *
  395. * 752271: PL310 R3P0->R3P1-50REL0, fixed R3P2.
  396. * Affects: 8x64-bit (double fill) line fetches
  397. * double fill line fetches can fail to cause dirty data to be evicted
  398. * from the cache before the new data overwrites the second line.
  399. *
  400. * 753970: PL310 R3P0, fixed R3P1.
  401. * Affects: sync
  402. * prevents merging writes after the sync operation, until another L2C
  403. * operation is performed (or a number of other conditions.)
  404. *
  405. * 769419: PL310 R0P0->R3P1, fixed R3P2.
  406. * Affects: store buffer
  407. * store buffer is not automatically drained.
  408. */
  409. static void l2c310_inv_range_erratum(unsigned long start, unsigned long end)
  410. {
  411. void __iomem *base = l2x0_base;
  412. if ((start | end) & (CACHE_LINE_SIZE - 1)) {
  413. unsigned long flags;
  414. /* Erratum 588369 for both clean+invalidate operations */
  415. raw_spin_lock_irqsave(&l2x0_lock, flags);
  416. l2c_set_debug(base, 0x03);
  417. if (start & (CACHE_LINE_SIZE - 1)) {
  418. start &= ~(CACHE_LINE_SIZE - 1);
  419. writel_relaxed(start, base + L2X0_CLEAN_LINE_PA);
  420. writel_relaxed(start, base + L2X0_INV_LINE_PA);
  421. start += CACHE_LINE_SIZE;
  422. }
  423. if (end & (CACHE_LINE_SIZE - 1)) {
  424. end &= ~(CACHE_LINE_SIZE - 1);
  425. writel_relaxed(end, base + L2X0_CLEAN_LINE_PA);
  426. writel_relaxed(end, base + L2X0_INV_LINE_PA);
  427. }
  428. l2c_set_debug(base, 0x00);
  429. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  430. }
  431. __l2c210_op_pa_range(base + L2X0_INV_LINE_PA, start, end);
  432. __l2c210_cache_sync(base);
  433. }
  434. static void l2c310_flush_range_erratum(unsigned long start, unsigned long end)
  435. {
  436. raw_spinlock_t *lock = &l2x0_lock;
  437. unsigned long flags;
  438. void __iomem *base = l2x0_base;
  439. raw_spin_lock_irqsave(lock, flags);
  440. while (start < end) {
  441. unsigned long blk_end = start + min(end - start, 4096UL);
  442. l2c_set_debug(base, 0x03);
  443. while (start < blk_end) {
  444. writel_relaxed(start, base + L2X0_CLEAN_LINE_PA);
  445. writel_relaxed(start, base + L2X0_INV_LINE_PA);
  446. start += CACHE_LINE_SIZE;
  447. }
  448. l2c_set_debug(base, 0x00);
  449. if (blk_end < end) {
  450. raw_spin_unlock_irqrestore(lock, flags);
  451. raw_spin_lock_irqsave(lock, flags);
  452. }
  453. }
  454. raw_spin_unlock_irqrestore(lock, flags);
  455. __l2c210_cache_sync(base);
  456. }
  457. static void l2c310_flush_all_erratum(void)
  458. {
  459. void __iomem *base = l2x0_base;
  460. unsigned long flags;
  461. raw_spin_lock_irqsave(&l2x0_lock, flags);
  462. l2c_set_debug(base, 0x03);
  463. __l2c_op_way(base + L2X0_CLEAN_INV_WAY);
  464. l2c_set_debug(base, 0x00);
  465. __l2c210_cache_sync(base);
  466. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  467. }
  468. static void __init l2c310_save(void __iomem *base)
  469. {
  470. unsigned revision;
  471. l2c_save(base);
  472. l2x0_saved_regs.tag_latency = readl_relaxed(base +
  473. L310_TAG_LATENCY_CTRL);
  474. l2x0_saved_regs.data_latency = readl_relaxed(base +
  475. L310_DATA_LATENCY_CTRL);
  476. l2x0_saved_regs.filter_end = readl_relaxed(base +
  477. L310_ADDR_FILTER_END);
  478. l2x0_saved_regs.filter_start = readl_relaxed(base +
  479. L310_ADDR_FILTER_START);
  480. revision = readl_relaxed(base + L2X0_CACHE_ID) &
  481. L2X0_CACHE_ID_RTL_MASK;
  482. /* From r2p0, there is Prefetch offset/control register */
  483. if (revision >= L310_CACHE_ID_RTL_R2P0)
  484. l2x0_saved_regs.prefetch_ctrl = readl_relaxed(base +
  485. L310_PREFETCH_CTRL);
  486. /* From r3p0, there is Power control register */
  487. if (revision >= L310_CACHE_ID_RTL_R3P0)
  488. l2x0_saved_regs.pwr_ctrl = readl_relaxed(base +
  489. L310_POWER_CTRL);
  490. }
  491. static void l2c310_configure(void __iomem *base)
  492. {
  493. unsigned revision;
  494. l2c_configure(base);
  495. /* restore pl310 setup */
  496. l2c_write_sec(l2x0_saved_regs.tag_latency, base,
  497. L310_TAG_LATENCY_CTRL);
  498. l2c_write_sec(l2x0_saved_regs.data_latency, base,
  499. L310_DATA_LATENCY_CTRL);
  500. l2c_write_sec(l2x0_saved_regs.filter_end, base,
  501. L310_ADDR_FILTER_END);
  502. l2c_write_sec(l2x0_saved_regs.filter_start, base,
  503. L310_ADDR_FILTER_START);
  504. revision = readl_relaxed(base + L2X0_CACHE_ID) &
  505. L2X0_CACHE_ID_RTL_MASK;
  506. if (revision >= L310_CACHE_ID_RTL_R2P0)
  507. l2c_write_sec(l2x0_saved_regs.prefetch_ctrl, base,
  508. L310_PREFETCH_CTRL);
  509. if (revision >= L310_CACHE_ID_RTL_R3P0)
  510. l2c_write_sec(l2x0_saved_regs.pwr_ctrl, base,
  511. L310_POWER_CTRL);
  512. }
  513. static int l2c310_cpu_enable_flz(struct notifier_block *nb, unsigned long act, void *data)
  514. {
  515. switch (act & ~CPU_TASKS_FROZEN) {
  516. case CPU_STARTING:
  517. set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1));
  518. break;
  519. case CPU_DYING:
  520. set_auxcr(get_auxcr() & ~(BIT(3) | BIT(2) | BIT(1)));
  521. break;
  522. }
  523. return NOTIFY_OK;
  524. }
  525. static void __init l2c310_enable(void __iomem *base, unsigned num_lock)
  526. {
  527. unsigned rev = readl_relaxed(base + L2X0_CACHE_ID) & L2X0_CACHE_ID_RTL_MASK;
  528. bool cortex_a9 = read_cpuid_part() == ARM_CPU_PART_CORTEX_A9;
  529. u32 aux = l2x0_saved_regs.aux_ctrl;
  530. if (rev >= L310_CACHE_ID_RTL_R2P0) {
  531. if (cortex_a9) {
  532. aux |= L310_AUX_CTRL_EARLY_BRESP;
  533. pr_info("L2C-310 enabling early BRESP for Cortex-A9\n");
  534. } else if (aux & L310_AUX_CTRL_EARLY_BRESP) {
  535. pr_warn("L2C-310 early BRESP only supported with Cortex-A9\n");
  536. aux &= ~L310_AUX_CTRL_EARLY_BRESP;
  537. }
  538. }
  539. if (cortex_a9) {
  540. u32 aux_cur = readl_relaxed(base + L2X0_AUX_CTRL);
  541. u32 acr = get_auxcr();
  542. pr_debug("Cortex-A9 ACR=0x%08x\n", acr);
  543. if (acr & BIT(3) && !(aux_cur & L310_AUX_CTRL_FULL_LINE_ZERO))
  544. pr_err("L2C-310: full line of zeros enabled in Cortex-A9 but not L2C-310 - invalid\n");
  545. if (aux & L310_AUX_CTRL_FULL_LINE_ZERO && !(acr & BIT(3)))
  546. pr_err("L2C-310: enabling full line of zeros but not enabled in Cortex-A9\n");
  547. if (!(aux & L310_AUX_CTRL_FULL_LINE_ZERO) && !outer_cache.write_sec) {
  548. aux |= L310_AUX_CTRL_FULL_LINE_ZERO;
  549. pr_info("L2C-310 full line of zeros enabled for Cortex-A9\n");
  550. }
  551. } else if (aux & (L310_AUX_CTRL_FULL_LINE_ZERO | L310_AUX_CTRL_EARLY_BRESP)) {
  552. pr_err("L2C-310: disabling Cortex-A9 specific feature bits\n");
  553. aux &= ~(L310_AUX_CTRL_FULL_LINE_ZERO | L310_AUX_CTRL_EARLY_BRESP);
  554. }
  555. /* r3p0 or later has power control register */
  556. if (rev >= L310_CACHE_ID_RTL_R3P0)
  557. l2x0_saved_regs.pwr_ctrl = L310_DYNAMIC_CLK_GATING_EN |
  558. L310_STNDBY_MODE_EN;
  559. /*
  560. * Always enable non-secure access to the lockdown registers -
  561. * we write to them as part of the L2C enable sequence so they
  562. * need to be accessible.
  563. */
  564. l2x0_saved_regs.aux_ctrl = aux | L310_AUX_CTRL_NS_LOCKDOWN;
  565. l2c_enable(base, num_lock);
  566. /* Read back resulting AUX_CTRL value as it could have been altered. */
  567. aux = readl_relaxed(base + L2X0_AUX_CTRL);
  568. if (aux & (L310_AUX_CTRL_DATA_PREFETCH | L310_AUX_CTRL_INSTR_PREFETCH)) {
  569. u32 prefetch = readl_relaxed(base + L310_PREFETCH_CTRL);
  570. pr_info("L2C-310 %s%s prefetch enabled, offset %u lines\n",
  571. aux & L310_AUX_CTRL_INSTR_PREFETCH ? "I" : "",
  572. aux & L310_AUX_CTRL_DATA_PREFETCH ? "D" : "",
  573. 1 + (prefetch & L310_PREFETCH_CTRL_OFFSET_MASK));
  574. }
  575. /* r3p0 or later has power control register */
  576. if (rev >= L310_CACHE_ID_RTL_R3P0) {
  577. u32 power_ctrl;
  578. power_ctrl = readl_relaxed(base + L310_POWER_CTRL);
  579. pr_info("L2C-310 dynamic clock gating %sabled, standby mode %sabled\n",
  580. power_ctrl & L310_DYNAMIC_CLK_GATING_EN ? "en" : "dis",
  581. power_ctrl & L310_STNDBY_MODE_EN ? "en" : "dis");
  582. }
  583. if (aux & L310_AUX_CTRL_FULL_LINE_ZERO) {
  584. set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1));
  585. cpu_notifier(l2c310_cpu_enable_flz, 0);
  586. }
  587. }
  588. static void __init l2c310_fixup(void __iomem *base, u32 cache_id,
  589. struct outer_cache_fns *fns)
  590. {
  591. unsigned revision = cache_id & L2X0_CACHE_ID_RTL_MASK;
  592. const char *errata[8];
  593. unsigned n = 0;
  594. if (IS_ENABLED(CONFIG_PL310_ERRATA_588369) &&
  595. revision < L310_CACHE_ID_RTL_R2P0 &&
  596. /* For bcm compatibility */
  597. fns->inv_range == l2c210_inv_range) {
  598. fns->inv_range = l2c310_inv_range_erratum;
  599. fns->flush_range = l2c310_flush_range_erratum;
  600. errata[n++] = "588369";
  601. }
  602. if (IS_ENABLED(CONFIG_PL310_ERRATA_727915) &&
  603. revision >= L310_CACHE_ID_RTL_R2P0 &&
  604. revision < L310_CACHE_ID_RTL_R3P1) {
  605. fns->flush_all = l2c310_flush_all_erratum;
  606. errata[n++] = "727915";
  607. }
  608. if (revision >= L310_CACHE_ID_RTL_R3P0 &&
  609. revision < L310_CACHE_ID_RTL_R3P2) {
  610. u32 val = l2x0_saved_regs.prefetch_ctrl;
  611. /* I don't think bit23 is required here... but iMX6 does so */
  612. if (val & (BIT(30) | BIT(23))) {
  613. val &= ~(BIT(30) | BIT(23));
  614. l2x0_saved_regs.prefetch_ctrl = val;
  615. errata[n++] = "752271";
  616. }
  617. }
  618. if (IS_ENABLED(CONFIG_PL310_ERRATA_753970) &&
  619. revision == L310_CACHE_ID_RTL_R3P0) {
  620. sync_reg_offset = L2X0_DUMMY_REG;
  621. errata[n++] = "753970";
  622. }
  623. if (IS_ENABLED(CONFIG_PL310_ERRATA_769419))
  624. errata[n++] = "769419";
  625. if (n) {
  626. unsigned i;
  627. pr_info("L2C-310 errat%s", n > 1 ? "a" : "um");
  628. for (i = 0; i < n; i++)
  629. pr_cont(" %s", errata[i]);
  630. pr_cont(" enabled\n");
  631. }
  632. }
  633. static void l2c310_disable(void)
  634. {
  635. /*
  636. * If full-line-of-zeros is enabled, we must first disable it in the
  637. * Cortex-A9 auxiliary control register before disabling the L2 cache.
  638. */
  639. if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_FULL_LINE_ZERO)
  640. set_auxcr(get_auxcr() & ~(BIT(3) | BIT(2) | BIT(1)));
  641. l2c_disable();
  642. }
  643. static void l2c310_resume(void)
  644. {
  645. l2c_resume();
  646. /* Re-enable full-line-of-zeros for Cortex-A9 */
  647. if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_FULL_LINE_ZERO)
  648. set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1));
  649. }
  650. static void l2c310_unlock(void __iomem *base, unsigned num_lock)
  651. {
  652. if (readl_relaxed(base + L2X0_AUX_CTRL) & L310_AUX_CTRL_NS_LOCKDOWN)
  653. l2c_unlock(base, num_lock);
  654. }
  655. static const struct l2c_init_data l2c310_init_fns __initconst = {
  656. .type = "L2C-310",
  657. .way_size_0 = SZ_8K,
  658. .num_lock = 8,
  659. .enable = l2c310_enable,
  660. .fixup = l2c310_fixup,
  661. .save = l2c310_save,
  662. .configure = l2c310_configure,
  663. .unlock = l2c310_unlock,
  664. .outer_cache = {
  665. .inv_range = l2c210_inv_range,
  666. .clean_range = l2c210_clean_range,
  667. .flush_range = l2c210_flush_range,
  668. .flush_all = l2c210_flush_all,
  669. .disable = l2c310_disable,
  670. .sync = l2c210_sync,
  671. .resume = l2c310_resume,
  672. },
  673. };
  674. static int __init __l2c_init(const struct l2c_init_data *data,
  675. u32 aux_val, u32 aux_mask, u32 cache_id)
  676. {
  677. struct outer_cache_fns fns;
  678. unsigned way_size_bits, ways;
  679. u32 aux, old_aux;
  680. /*
  681. * Save the pointer globally so that callbacks which do not receive
  682. * context from callers can access the structure.
  683. */
  684. l2x0_data = kmemdup(data, sizeof(*data), GFP_KERNEL);
  685. if (!l2x0_data)
  686. return -ENOMEM;
  687. /*
  688. * Sanity check the aux values. aux_mask is the bits we preserve
  689. * from reading the hardware register, and aux_val is the bits we
  690. * set.
  691. */
  692. if (aux_val & aux_mask)
  693. pr_alert("L2C: platform provided aux values permit register corruption.\n");
  694. old_aux = aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
  695. aux &= aux_mask;
  696. aux |= aux_val;
  697. if (old_aux != aux)
  698. pr_warn("L2C: DT/platform modifies aux control register: 0x%08x -> 0x%08x\n",
  699. old_aux, aux);
  700. /* Determine the number of ways */
  701. switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
  702. case L2X0_CACHE_ID_PART_L310:
  703. if ((aux_val | ~aux_mask) & (L2C_AUX_CTRL_WAY_SIZE_MASK | L310_AUX_CTRL_ASSOCIATIVITY_16))
  704. pr_warn("L2C: DT/platform tries to modify or specify cache size\n");
  705. if (aux & (1 << 16))
  706. ways = 16;
  707. else
  708. ways = 8;
  709. break;
  710. case L2X0_CACHE_ID_PART_L210:
  711. case L2X0_CACHE_ID_PART_L220:
  712. ways = (aux >> 13) & 0xf;
  713. break;
  714. case AURORA_CACHE_ID:
  715. ways = (aux >> 13) & 0xf;
  716. ways = 2 << ((ways + 1) >> 2);
  717. break;
  718. default:
  719. /* Assume unknown chips have 8 ways */
  720. ways = 8;
  721. break;
  722. }
  723. l2x0_way_mask = (1 << ways) - 1;
  724. /*
  725. * way_size_0 is the size that a way_size value of zero would be
  726. * given the calculation: way_size = way_size_0 << way_size_bits.
  727. * So, if way_size_bits=0 is reserved, but way_size_bits=1 is 16k,
  728. * then way_size_0 would be 8k.
  729. *
  730. * L2 cache size = number of ways * way size.
  731. */
  732. way_size_bits = (aux & L2C_AUX_CTRL_WAY_SIZE_MASK) >>
  733. L2C_AUX_CTRL_WAY_SIZE_SHIFT;
  734. l2x0_size = ways * (data->way_size_0 << way_size_bits);
  735. fns = data->outer_cache;
  736. fns.write_sec = outer_cache.write_sec;
  737. fns.configure = outer_cache.configure;
  738. if (data->fixup)
  739. data->fixup(l2x0_base, cache_id, &fns);
  740. /*
  741. * Check if l2x0 controller is already enabled. If we are booting
  742. * in non-secure mode accessing the below registers will fault.
  743. */
  744. if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
  745. l2x0_saved_regs.aux_ctrl = aux;
  746. data->enable(l2x0_base, data->num_lock);
  747. }
  748. outer_cache = fns;
  749. /*
  750. * It is strange to save the register state before initialisation,
  751. * but hey, this is what the DT implementations decided to do.
  752. */
  753. if (data->save)
  754. data->save(l2x0_base);
  755. /* Re-read it in case some bits are reserved. */
  756. aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
  757. pr_info("%s cache controller enabled, %d ways, %d kB\n",
  758. data->type, ways, l2x0_size >> 10);
  759. pr_info("%s: CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n",
  760. data->type, cache_id, aux);
  761. return 0;
  762. }
  763. void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
  764. {
  765. const struct l2c_init_data *data;
  766. u32 cache_id;
  767. l2x0_base = base;
  768. cache_id = readl_relaxed(base + L2X0_CACHE_ID);
  769. switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
  770. default:
  771. case L2X0_CACHE_ID_PART_L210:
  772. data = &l2c210_data;
  773. break;
  774. case L2X0_CACHE_ID_PART_L220:
  775. data = &l2c220_data;
  776. break;
  777. case L2X0_CACHE_ID_PART_L310:
  778. data = &l2c310_init_fns;
  779. break;
  780. }
  781. /* Read back current (default) hardware configuration */
  782. if (data->save)
  783. data->save(l2x0_base);
  784. __l2c_init(data, aux_val, aux_mask, cache_id);
  785. }
  786. #ifdef CONFIG_OF
  787. static int l2_wt_override;
  788. /* Aurora don't have the cache ID register available, so we have to
  789. * pass it though the device tree */
  790. static u32 cache_id_part_number_from_dt;
  791. /**
  792. * l2x0_cache_size_of_parse() - read cache size parameters from DT
  793. * @np: the device tree node for the l2 cache
  794. * @aux_val: pointer to machine-supplied auxilary register value, to
  795. * be augmented by the call (bits to be set to 1)
  796. * @aux_mask: pointer to machine-supplied auxilary register mask, to
  797. * be augmented by the call (bits to be set to 0)
  798. * @associativity: variable to return the calculated associativity in
  799. * @max_way_size: the maximum size in bytes for the cache ways
  800. */
  801. static int __init l2x0_cache_size_of_parse(const struct device_node *np,
  802. u32 *aux_val, u32 *aux_mask,
  803. u32 *associativity,
  804. u32 max_way_size)
  805. {
  806. u32 mask = 0, val = 0;
  807. u32 cache_size = 0, sets = 0;
  808. u32 way_size_bits = 1;
  809. u32 way_size = 0;
  810. u32 block_size = 0;
  811. u32 line_size = 0;
  812. of_property_read_u32(np, "cache-size", &cache_size);
  813. of_property_read_u32(np, "cache-sets", &sets);
  814. of_property_read_u32(np, "cache-block-size", &block_size);
  815. of_property_read_u32(np, "cache-line-size", &line_size);
  816. if (!cache_size || !sets)
  817. return -ENODEV;
  818. /* All these l2 caches have the same line = block size actually */
  819. if (!line_size) {
  820. if (block_size) {
  821. /* If linesize is not given, it is equal to blocksize */
  822. line_size = block_size;
  823. } else {
  824. /* Fall back to known size */
  825. pr_warn("L2C OF: no cache block/line size given: "
  826. "falling back to default size %d bytes\n",
  827. CACHE_LINE_SIZE);
  828. line_size = CACHE_LINE_SIZE;
  829. }
  830. }
  831. if (line_size != CACHE_LINE_SIZE)
  832. pr_warn("L2C OF: DT supplied line size %d bytes does "
  833. "not match hardware line size of %d bytes\n",
  834. line_size,
  835. CACHE_LINE_SIZE);
  836. /*
  837. * Since:
  838. * set size = cache size / sets
  839. * ways = cache size / (sets * line size)
  840. * way size = cache size / (cache size / (sets * line size))
  841. * way size = sets * line size
  842. * associativity = ways = cache size / way size
  843. */
  844. way_size = sets * line_size;
  845. *associativity = cache_size / way_size;
  846. if (way_size > max_way_size) {
  847. pr_err("L2C OF: set size %dKB is too large\n", way_size);
  848. return -EINVAL;
  849. }
  850. pr_info("L2C OF: override cache size: %d bytes (%dKB)\n",
  851. cache_size, cache_size >> 10);
  852. pr_info("L2C OF: override line size: %d bytes\n", line_size);
  853. pr_info("L2C OF: override way size: %d bytes (%dKB)\n",
  854. way_size, way_size >> 10);
  855. pr_info("L2C OF: override associativity: %d\n", *associativity);
  856. /*
  857. * Calculates the bits 17:19 to set for way size:
  858. * 512KB -> 6, 256KB -> 5, ... 16KB -> 1
  859. */
  860. way_size_bits = ilog2(way_size >> 10) - 3;
  861. if (way_size_bits < 1 || way_size_bits > 6) {
  862. pr_err("L2C OF: cache way size illegal: %dKB is not mapped\n",
  863. way_size);
  864. return -EINVAL;
  865. }
  866. mask |= L2C_AUX_CTRL_WAY_SIZE_MASK;
  867. val |= (way_size_bits << L2C_AUX_CTRL_WAY_SIZE_SHIFT);
  868. *aux_val &= ~mask;
  869. *aux_val |= val;
  870. *aux_mask &= ~mask;
  871. return 0;
  872. }
  873. static void __init l2x0_of_parse(const struct device_node *np,
  874. u32 *aux_val, u32 *aux_mask)
  875. {
  876. u32 data[2] = { 0, 0 };
  877. u32 tag = 0;
  878. u32 dirty = 0;
  879. u32 val = 0, mask = 0;
  880. u32 assoc;
  881. int ret;
  882. of_property_read_u32(np, "arm,tag-latency", &tag);
  883. if (tag) {
  884. mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK;
  885. val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT;
  886. }
  887. of_property_read_u32_array(np, "arm,data-latency",
  888. data, ARRAY_SIZE(data));
  889. if (data[0] && data[1]) {
  890. mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK |
  891. L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK;
  892. val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) |
  893. ((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT);
  894. }
  895. of_property_read_u32(np, "arm,dirty-latency", &dirty);
  896. if (dirty) {
  897. mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK;
  898. val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT;
  899. }
  900. ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_256K);
  901. if (ret)
  902. return;
  903. if (assoc > 8) {
  904. pr_err("l2x0 of: cache setting yield too high associativity\n");
  905. pr_err("l2x0 of: %d calculated, max 8\n", assoc);
  906. } else {
  907. mask |= L2X0_AUX_CTRL_ASSOC_MASK;
  908. val |= (assoc << L2X0_AUX_CTRL_ASSOC_SHIFT);
  909. }
  910. *aux_val &= ~mask;
  911. *aux_val |= val;
  912. *aux_mask &= ~mask;
  913. }
  914. static const struct l2c_init_data of_l2c210_data __initconst = {
  915. .type = "L2C-210",
  916. .way_size_0 = SZ_8K,
  917. .num_lock = 1,
  918. .of_parse = l2x0_of_parse,
  919. .enable = l2c_enable,
  920. .save = l2c_save,
  921. .configure = l2c_configure,
  922. .unlock = l2c_unlock,
  923. .outer_cache = {
  924. .inv_range = l2c210_inv_range,
  925. .clean_range = l2c210_clean_range,
  926. .flush_range = l2c210_flush_range,
  927. .flush_all = l2c210_flush_all,
  928. .disable = l2c_disable,
  929. .sync = l2c210_sync,
  930. .resume = l2c_resume,
  931. },
  932. };
  933. static const struct l2c_init_data of_l2c220_data __initconst = {
  934. .type = "L2C-220",
  935. .way_size_0 = SZ_8K,
  936. .num_lock = 1,
  937. .of_parse = l2x0_of_parse,
  938. .enable = l2c220_enable,
  939. .save = l2c_save,
  940. .configure = l2c_configure,
  941. .unlock = l2c220_unlock,
  942. .outer_cache = {
  943. .inv_range = l2c220_inv_range,
  944. .clean_range = l2c220_clean_range,
  945. .flush_range = l2c220_flush_range,
  946. .flush_all = l2c220_flush_all,
  947. .disable = l2c_disable,
  948. .sync = l2c220_sync,
  949. .resume = l2c_resume,
  950. },
  951. };
  952. static void __init l2c310_of_parse(const struct device_node *np,
  953. u32 *aux_val, u32 *aux_mask)
  954. {
  955. u32 data[3] = { 0, 0, 0 };
  956. u32 tag[3] = { 0, 0, 0 };
  957. u32 filter[2] = { 0, 0 };
  958. u32 assoc;
  959. u32 prefetch;
  960. u32 val;
  961. int ret;
  962. of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
  963. if (tag[0] && tag[1] && tag[2])
  964. l2x0_saved_regs.tag_latency =
  965. L310_LATENCY_CTRL_RD(tag[0] - 1) |
  966. L310_LATENCY_CTRL_WR(tag[1] - 1) |
  967. L310_LATENCY_CTRL_SETUP(tag[2] - 1);
  968. of_property_read_u32_array(np, "arm,data-latency",
  969. data, ARRAY_SIZE(data));
  970. if (data[0] && data[1] && data[2])
  971. l2x0_saved_regs.data_latency =
  972. L310_LATENCY_CTRL_RD(data[0] - 1) |
  973. L310_LATENCY_CTRL_WR(data[1] - 1) |
  974. L310_LATENCY_CTRL_SETUP(data[2] - 1);
  975. of_property_read_u32_array(np, "arm,filter-ranges",
  976. filter, ARRAY_SIZE(filter));
  977. if (filter[1]) {
  978. l2x0_saved_regs.filter_end =
  979. ALIGN(filter[0] + filter[1], SZ_1M);
  980. l2x0_saved_regs.filter_start = (filter[0] & ~(SZ_1M - 1))
  981. | L310_ADDR_FILTER_EN;
  982. }
  983. ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_512K);
  984. if (!ret) {
  985. switch (assoc) {
  986. case 16:
  987. *aux_val &= ~L2X0_AUX_CTRL_ASSOC_MASK;
  988. *aux_val |= L310_AUX_CTRL_ASSOCIATIVITY_16;
  989. *aux_mask &= ~L2X0_AUX_CTRL_ASSOC_MASK;
  990. break;
  991. case 8:
  992. *aux_val &= ~L2X0_AUX_CTRL_ASSOC_MASK;
  993. *aux_mask &= ~L2X0_AUX_CTRL_ASSOC_MASK;
  994. break;
  995. default:
  996. pr_err("L2C-310 OF cache associativity %d invalid, only 8 or 16 permitted\n",
  997. assoc);
  998. break;
  999. }
  1000. }
  1001. prefetch = l2x0_saved_regs.prefetch_ctrl;
  1002. ret = of_property_read_u32(np, "arm,double-linefill", &val);
  1003. if (ret == 0) {
  1004. if (val)
  1005. prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL;
  1006. else
  1007. prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL;
  1008. } else if (ret != -EINVAL) {
  1009. pr_err("L2C-310 OF arm,double-linefill property value is missing\n");
  1010. }
  1011. ret = of_property_read_u32(np, "arm,double-linefill-incr", &val);
  1012. if (ret == 0) {
  1013. if (val)
  1014. prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL_INCR;
  1015. else
  1016. prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL_INCR;
  1017. } else if (ret != -EINVAL) {
  1018. pr_err("L2C-310 OF arm,double-linefill-incr property value is missing\n");
  1019. }
  1020. ret = of_property_read_u32(np, "arm,double-linefill-wrap", &val);
  1021. if (ret == 0) {
  1022. if (!val)
  1023. prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP;
  1024. else
  1025. prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP;
  1026. } else if (ret != -EINVAL) {
  1027. pr_err("L2C-310 OF arm,double-linefill-wrap property value is missing\n");
  1028. }
  1029. ret = of_property_read_u32(np, "arm,prefetch-drop", &val);
  1030. if (ret == 0) {
  1031. if (val)
  1032. prefetch |= L310_PREFETCH_CTRL_PREFETCH_DROP;
  1033. else
  1034. prefetch &= ~L310_PREFETCH_CTRL_PREFETCH_DROP;
  1035. } else if (ret != -EINVAL) {
  1036. pr_err("L2C-310 OF arm,prefetch-drop property value is missing\n");
  1037. }
  1038. ret = of_property_read_u32(np, "arm,prefetch-offset", &val);
  1039. if (ret == 0) {
  1040. prefetch &= ~L310_PREFETCH_CTRL_OFFSET_MASK;
  1041. prefetch |= val & L310_PREFETCH_CTRL_OFFSET_MASK;
  1042. } else if (ret != -EINVAL) {
  1043. pr_err("L2C-310 OF arm,prefetch-offset property value is missing\n");
  1044. }
  1045. ret = of_property_read_u32(np, "prefetch-data", &val);
  1046. if (ret == 0) {
  1047. if (val)
  1048. prefetch |= L310_PREFETCH_CTRL_DATA_PREFETCH;
  1049. else
  1050. prefetch &= ~L310_PREFETCH_CTRL_DATA_PREFETCH;
  1051. } else if (ret != -EINVAL) {
  1052. pr_err("L2C-310 OF prefetch-data property value is missing\n");
  1053. }
  1054. ret = of_property_read_u32(np, "prefetch-instr", &val);
  1055. if (ret == 0) {
  1056. if (val)
  1057. prefetch |= L310_PREFETCH_CTRL_INSTR_PREFETCH;
  1058. else
  1059. prefetch &= ~L310_PREFETCH_CTRL_INSTR_PREFETCH;
  1060. } else if (ret != -EINVAL) {
  1061. pr_err("L2C-310 OF prefetch-instr property value is missing\n");
  1062. }
  1063. l2x0_saved_regs.prefetch_ctrl = prefetch;
  1064. }
  1065. static const struct l2c_init_data of_l2c310_data __initconst = {
  1066. .type = "L2C-310",
  1067. .way_size_0 = SZ_8K,
  1068. .num_lock = 8,
  1069. .of_parse = l2c310_of_parse,
  1070. .enable = l2c310_enable,
  1071. .fixup = l2c310_fixup,
  1072. .save = l2c310_save,
  1073. .configure = l2c310_configure,
  1074. .unlock = l2c310_unlock,
  1075. .outer_cache = {
  1076. .inv_range = l2c210_inv_range,
  1077. .clean_range = l2c210_clean_range,
  1078. .flush_range = l2c210_flush_range,
  1079. .flush_all = l2c210_flush_all,
  1080. .disable = l2c310_disable,
  1081. .sync = l2c210_sync,
  1082. .resume = l2c310_resume,
  1083. },
  1084. };
  1085. /*
  1086. * This is a variant of the of_l2c310_data with .sync set to
  1087. * NULL. Outer sync operations are not needed when the system is I/O
  1088. * coherent, and potentially harmful in certain situations (PCIe/PL310
  1089. * deadlock on Armada 375/38x due to hardware I/O coherency). The
  1090. * other operations are kept because they are infrequent (therefore do
  1091. * not cause the deadlock in practice) and needed for secondary CPU
  1092. * boot and other power management activities.
  1093. */
  1094. static const struct l2c_init_data of_l2c310_coherent_data __initconst = {
  1095. .type = "L2C-310 Coherent",
  1096. .way_size_0 = SZ_8K,
  1097. .num_lock = 8,
  1098. .of_parse = l2c310_of_parse,
  1099. .enable = l2c310_enable,
  1100. .fixup = l2c310_fixup,
  1101. .save = l2c310_save,
  1102. .configure = l2c310_configure,
  1103. .unlock = l2c310_unlock,
  1104. .outer_cache = {
  1105. .inv_range = l2c210_inv_range,
  1106. .clean_range = l2c210_clean_range,
  1107. .flush_range = l2c210_flush_range,
  1108. .flush_all = l2c210_flush_all,
  1109. .disable = l2c310_disable,
  1110. .resume = l2c310_resume,
  1111. },
  1112. };
  1113. /*
  1114. * Note that the end addresses passed to Linux primitives are
  1115. * noninclusive, while the hardware cache range operations use
  1116. * inclusive start and end addresses.
  1117. */
  1118. static unsigned long aurora_range_end(unsigned long start, unsigned long end)
  1119. {
  1120. /*
  1121. * Limit the number of cache lines processed at once,
  1122. * since cache range operations stall the CPU pipeline
  1123. * until completion.
  1124. */
  1125. if (end > start + MAX_RANGE_SIZE)
  1126. end = start + MAX_RANGE_SIZE;
  1127. /*
  1128. * Cache range operations can't straddle a page boundary.
  1129. */
  1130. if (end > PAGE_ALIGN(start+1))
  1131. end = PAGE_ALIGN(start+1);
  1132. return end;
  1133. }
  1134. static void aurora_pa_range(unsigned long start, unsigned long end,
  1135. unsigned long offset)
  1136. {
  1137. void __iomem *base = l2x0_base;
  1138. unsigned long range_end;
  1139. unsigned long flags;
  1140. /*
  1141. * round start and end adresses up to cache line size
  1142. */
  1143. start &= ~(CACHE_LINE_SIZE - 1);
  1144. end = ALIGN(end, CACHE_LINE_SIZE);
  1145. /*
  1146. * perform operation on all full cache lines between 'start' and 'end'
  1147. */
  1148. while (start < end) {
  1149. range_end = aurora_range_end(start, end);
  1150. raw_spin_lock_irqsave(&l2x0_lock, flags);
  1151. writel_relaxed(start, base + AURORA_RANGE_BASE_ADDR_REG);
  1152. writel_relaxed(range_end - CACHE_LINE_SIZE, base + offset);
  1153. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  1154. writel_relaxed(0, base + AURORA_SYNC_REG);
  1155. start = range_end;
  1156. }
  1157. }
  1158. static void aurora_inv_range(unsigned long start, unsigned long end)
  1159. {
  1160. aurora_pa_range(start, end, AURORA_INVAL_RANGE_REG);
  1161. }
  1162. static void aurora_clean_range(unsigned long start, unsigned long end)
  1163. {
  1164. /*
  1165. * If L2 is forced to WT, the L2 will always be clean and we
  1166. * don't need to do anything here.
  1167. */
  1168. if (!l2_wt_override)
  1169. aurora_pa_range(start, end, AURORA_CLEAN_RANGE_REG);
  1170. }
  1171. static void aurora_flush_range(unsigned long start, unsigned long end)
  1172. {
  1173. if (l2_wt_override)
  1174. aurora_pa_range(start, end, AURORA_INVAL_RANGE_REG);
  1175. else
  1176. aurora_pa_range(start, end, AURORA_FLUSH_RANGE_REG);
  1177. }
  1178. static void aurora_flush_all(void)
  1179. {
  1180. void __iomem *base = l2x0_base;
  1181. unsigned long flags;
  1182. /* clean all ways */
  1183. raw_spin_lock_irqsave(&l2x0_lock, flags);
  1184. __l2c_op_way(base + L2X0_CLEAN_INV_WAY);
  1185. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  1186. writel_relaxed(0, base + AURORA_SYNC_REG);
  1187. }
  1188. static void aurora_cache_sync(void)
  1189. {
  1190. writel_relaxed(0, l2x0_base + AURORA_SYNC_REG);
  1191. }
  1192. static void aurora_disable(void)
  1193. {
  1194. void __iomem *base = l2x0_base;
  1195. unsigned long flags;
  1196. raw_spin_lock_irqsave(&l2x0_lock, flags);
  1197. __l2c_op_way(base + L2X0_CLEAN_INV_WAY);
  1198. writel_relaxed(0, base + AURORA_SYNC_REG);
  1199. l2c_write_sec(0, base, L2X0_CTRL);
  1200. dsb(st);
  1201. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  1202. }
  1203. static void aurora_save(void __iomem *base)
  1204. {
  1205. l2x0_saved_regs.ctrl = readl_relaxed(base + L2X0_CTRL);
  1206. l2x0_saved_regs.aux_ctrl = readl_relaxed(base + L2X0_AUX_CTRL);
  1207. }
  1208. /*
  1209. * For Aurora cache in no outer mode, enable via the CP15 coprocessor
  1210. * broadcasting of cache commands to L2.
  1211. */
  1212. static void __init aurora_enable_no_outer(void __iomem *base,
  1213. unsigned num_lock)
  1214. {
  1215. u32 u;
  1216. asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u));
  1217. u |= AURORA_CTRL_FW; /* Set the FW bit */
  1218. asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));
  1219. isb();
  1220. l2c_enable(base, num_lock);
  1221. }
  1222. static void __init aurora_fixup(void __iomem *base, u32 cache_id,
  1223. struct outer_cache_fns *fns)
  1224. {
  1225. sync_reg_offset = AURORA_SYNC_REG;
  1226. }
  1227. static void __init aurora_of_parse(const struct device_node *np,
  1228. u32 *aux_val, u32 *aux_mask)
  1229. {
  1230. u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU;
  1231. u32 mask = AURORA_ACR_REPLACEMENT_MASK;
  1232. of_property_read_u32(np, "cache-id-part",
  1233. &cache_id_part_number_from_dt);
  1234. /* Determine and save the write policy */
  1235. l2_wt_override = of_property_read_bool(np, "wt-override");
  1236. if (l2_wt_override) {
  1237. val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY;
  1238. mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK;
  1239. }
  1240. *aux_val &= ~mask;
  1241. *aux_val |= val;
  1242. *aux_mask &= ~mask;
  1243. }
  1244. static const struct l2c_init_data of_aurora_with_outer_data __initconst = {
  1245. .type = "Aurora",
  1246. .way_size_0 = SZ_4K,
  1247. .num_lock = 4,
  1248. .of_parse = aurora_of_parse,
  1249. .enable = l2c_enable,
  1250. .fixup = aurora_fixup,
  1251. .save = aurora_save,
  1252. .configure = l2c_configure,
  1253. .unlock = l2c_unlock,
  1254. .outer_cache = {
  1255. .inv_range = aurora_inv_range,
  1256. .clean_range = aurora_clean_range,
  1257. .flush_range = aurora_flush_range,
  1258. .flush_all = aurora_flush_all,
  1259. .disable = aurora_disable,
  1260. .sync = aurora_cache_sync,
  1261. .resume = l2c_resume,
  1262. },
  1263. };
  1264. static const struct l2c_init_data of_aurora_no_outer_data __initconst = {
  1265. .type = "Aurora",
  1266. .way_size_0 = SZ_4K,
  1267. .num_lock = 4,
  1268. .of_parse = aurora_of_parse,
  1269. .enable = aurora_enable_no_outer,
  1270. .fixup = aurora_fixup,
  1271. .save = aurora_save,
  1272. .configure = l2c_configure,
  1273. .unlock = l2c_unlock,
  1274. .outer_cache = {
  1275. .resume = l2c_resume,
  1276. },
  1277. };
  1278. /*
  1279. * For certain Broadcom SoCs, depending on the address range, different offsets
  1280. * need to be added to the address before passing it to L2 for
  1281. * invalidation/clean/flush
  1282. *
  1283. * Section Address Range Offset EMI
  1284. * 1 0x00000000 - 0x3FFFFFFF 0x80000000 VC
  1285. * 2 0x40000000 - 0xBFFFFFFF 0x40000000 SYS
  1286. * 3 0xC0000000 - 0xFFFFFFFF 0x80000000 VC
  1287. *
  1288. * When the start and end addresses have crossed two different sections, we
  1289. * need to break the L2 operation into two, each within its own section.
  1290. * For example, if we need to invalidate addresses starts at 0xBFFF0000 and
  1291. * ends at 0xC0001000, we need do invalidate 1) 0xBFFF0000 - 0xBFFFFFFF and 2)
  1292. * 0xC0000000 - 0xC0001000
  1293. *
  1294. * Note 1:
  1295. * By breaking a single L2 operation into two, we may potentially suffer some
  1296. * performance hit, but keep in mind the cross section case is very rare
  1297. *
  1298. * Note 2:
  1299. * We do not need to handle the case when the start address is in
  1300. * Section 1 and the end address is in Section 3, since it is not a valid use
  1301. * case
  1302. *
  1303. * Note 3:
  1304. * Section 1 in practical terms can no longer be used on rev A2. Because of
  1305. * that the code does not need to handle section 1 at all.
  1306. *
  1307. */
  1308. #define BCM_SYS_EMI_START_ADDR 0x40000000UL
  1309. #define BCM_VC_EMI_SEC3_START_ADDR 0xC0000000UL
  1310. #define BCM_SYS_EMI_OFFSET 0x40000000UL
  1311. #define BCM_VC_EMI_OFFSET 0x80000000UL
  1312. static inline int bcm_addr_is_sys_emi(unsigned long addr)
  1313. {
  1314. return (addr >= BCM_SYS_EMI_START_ADDR) &&
  1315. (addr < BCM_VC_EMI_SEC3_START_ADDR);
  1316. }
  1317. static inline unsigned long bcm_l2_phys_addr(unsigned long addr)
  1318. {
  1319. if (bcm_addr_is_sys_emi(addr))
  1320. return addr + BCM_SYS_EMI_OFFSET;
  1321. else
  1322. return addr + BCM_VC_EMI_OFFSET;
  1323. }
  1324. static void bcm_inv_range(unsigned long start, unsigned long end)
  1325. {
  1326. unsigned long new_start, new_end;
  1327. BUG_ON(start < BCM_SYS_EMI_START_ADDR);
  1328. if (unlikely(end <= start))
  1329. return;
  1330. new_start = bcm_l2_phys_addr(start);
  1331. new_end = bcm_l2_phys_addr(end);
  1332. /* normal case, no cross section between start and end */
  1333. if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
  1334. l2c210_inv_range(new_start, new_end);
  1335. return;
  1336. }
  1337. /* They cross sections, so it can only be a cross from section
  1338. * 2 to section 3
  1339. */
  1340. l2c210_inv_range(new_start,
  1341. bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
  1342. l2c210_inv_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
  1343. new_end);
  1344. }
  1345. static void bcm_clean_range(unsigned long start, unsigned long end)
  1346. {
  1347. unsigned long new_start, new_end;
  1348. BUG_ON(start < BCM_SYS_EMI_START_ADDR);
  1349. if (unlikely(end <= start))
  1350. return;
  1351. new_start = bcm_l2_phys_addr(start);
  1352. new_end = bcm_l2_phys_addr(end);
  1353. /* normal case, no cross section between start and end */
  1354. if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
  1355. l2c210_clean_range(new_start, new_end);
  1356. return;
  1357. }
  1358. /* They cross sections, so it can only be a cross from section
  1359. * 2 to section 3
  1360. */
  1361. l2c210_clean_range(new_start,
  1362. bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
  1363. l2c210_clean_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
  1364. new_end);
  1365. }
  1366. static void bcm_flush_range(unsigned long start, unsigned long end)
  1367. {
  1368. unsigned long new_start, new_end;
  1369. BUG_ON(start < BCM_SYS_EMI_START_ADDR);
  1370. if (unlikely(end <= start))
  1371. return;
  1372. if ((end - start) >= l2x0_size) {
  1373. outer_cache.flush_all();
  1374. return;
  1375. }
  1376. new_start = bcm_l2_phys_addr(start);
  1377. new_end = bcm_l2_phys_addr(end);
  1378. /* normal case, no cross section between start and end */
  1379. if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
  1380. l2c210_flush_range(new_start, new_end);
  1381. return;
  1382. }
  1383. /* They cross sections, so it can only be a cross from section
  1384. * 2 to section 3
  1385. */
  1386. l2c210_flush_range(new_start,
  1387. bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
  1388. l2c210_flush_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
  1389. new_end);
  1390. }
  1391. /* Broadcom L2C-310 start from ARMs R3P2 or later, and require no fixups */
  1392. static const struct l2c_init_data of_bcm_l2x0_data __initconst = {
  1393. .type = "BCM-L2C-310",
  1394. .way_size_0 = SZ_8K,
  1395. .num_lock = 8,
  1396. .of_parse = l2c310_of_parse,
  1397. .enable = l2c310_enable,
  1398. .save = l2c310_save,
  1399. .configure = l2c310_configure,
  1400. .unlock = l2c310_unlock,
  1401. .outer_cache = {
  1402. .inv_range = bcm_inv_range,
  1403. .clean_range = bcm_clean_range,
  1404. .flush_range = bcm_flush_range,
  1405. .flush_all = l2c210_flush_all,
  1406. .disable = l2c310_disable,
  1407. .sync = l2c210_sync,
  1408. .resume = l2c310_resume,
  1409. },
  1410. };
  1411. static void __init tauros3_save(void __iomem *base)
  1412. {
  1413. l2c_save(base);
  1414. l2x0_saved_regs.aux2_ctrl =
  1415. readl_relaxed(base + TAUROS3_AUX2_CTRL);
  1416. l2x0_saved_regs.prefetch_ctrl =
  1417. readl_relaxed(base + L310_PREFETCH_CTRL);
  1418. }
  1419. static void tauros3_configure(void __iomem *base)
  1420. {
  1421. l2c_configure(base);
  1422. writel_relaxed(l2x0_saved_regs.aux2_ctrl,
  1423. base + TAUROS3_AUX2_CTRL);
  1424. writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
  1425. base + L310_PREFETCH_CTRL);
  1426. }
  1427. static const struct l2c_init_data of_tauros3_data __initconst = {
  1428. .type = "Tauros3",
  1429. .way_size_0 = SZ_8K,
  1430. .num_lock = 8,
  1431. .enable = l2c_enable,
  1432. .save = tauros3_save,
  1433. .configure = tauros3_configure,
  1434. .unlock = l2c_unlock,
  1435. /* Tauros3 broadcasts L1 cache operations to L2 */
  1436. .outer_cache = {
  1437. .resume = l2c_resume,
  1438. },
  1439. };
  1440. #define L2C_ID(name, fns) { .compatible = name, .data = (void *)&fns }
  1441. static const struct of_device_id l2x0_ids[] __initconst = {
  1442. L2C_ID("arm,l210-cache", of_l2c210_data),
  1443. L2C_ID("arm,l220-cache", of_l2c220_data),
  1444. L2C_ID("arm,pl310-cache", of_l2c310_data),
  1445. L2C_ID("brcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data),
  1446. L2C_ID("marvell,aurora-outer-cache", of_aurora_with_outer_data),
  1447. L2C_ID("marvell,aurora-system-cache", of_aurora_no_outer_data),
  1448. L2C_ID("marvell,tauros3-cache", of_tauros3_data),
  1449. /* Deprecated IDs */
  1450. L2C_ID("bcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data),
  1451. {}
  1452. };
  1453. int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
  1454. {
  1455. const struct l2c_init_data *data;
  1456. struct device_node *np;
  1457. struct resource res;
  1458. u32 cache_id, old_aux;
  1459. u32 cache_level = 2;
  1460. np = of_find_matching_node(NULL, l2x0_ids);
  1461. if (!np)
  1462. return -ENODEV;
  1463. if (of_address_to_resource(np, 0, &res))
  1464. return -ENODEV;
  1465. l2x0_base = ioremap(res.start, resource_size(&res));
  1466. if (!l2x0_base)
  1467. return -ENOMEM;
  1468. l2x0_saved_regs.phy_base = res.start;
  1469. data = of_match_node(l2x0_ids, np)->data;
  1470. if (of_device_is_compatible(np, "arm,pl310-cache") &&
  1471. of_property_read_bool(np, "arm,io-coherent"))
  1472. data = &of_l2c310_coherent_data;
  1473. old_aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
  1474. if (old_aux != ((old_aux & aux_mask) | aux_val)) {
  1475. pr_warn("L2C: platform modifies aux control register: 0x%08x -> 0x%08x\n",
  1476. old_aux, (old_aux & aux_mask) | aux_val);
  1477. } else if (aux_mask != ~0U && aux_val != 0) {
  1478. pr_alert("L2C: platform provided aux values match the hardware, so have no effect. Please remove them.\n");
  1479. }
  1480. /* All L2 caches are unified, so this property should be specified */
  1481. if (!of_property_read_bool(np, "cache-unified"))
  1482. pr_err("L2C: device tree omits to specify unified cache\n");
  1483. if (of_property_read_u32(np, "cache-level", &cache_level))
  1484. pr_err("L2C: device tree omits to specify cache-level\n");
  1485. if (cache_level != 2)
  1486. pr_err("L2C: device tree specifies invalid cache level\n");
  1487. /* Read back current (default) hardware configuration */
  1488. if (data->save)
  1489. data->save(l2x0_base);
  1490. /* L2 configuration can only be changed if the cache is disabled */
  1491. if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN))
  1492. if (data->of_parse)
  1493. data->of_parse(np, &aux_val, &aux_mask);
  1494. if (cache_id_part_number_from_dt)
  1495. cache_id = cache_id_part_number_from_dt;
  1496. else
  1497. cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
  1498. return __l2c_init(data, aux_val, aux_mask, cache_id);
  1499. }
  1500. #endif