irq.c 9.2 KB

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  1. /*
  2. * Copyright IBM Corp. 2004, 2011
  3. * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>,
  4. * Holger Smolinski <Holger.Smolinski@de.ibm.com>,
  5. * Thomas Spatzier <tspat@de.ibm.com>,
  6. *
  7. * This file contains interrupt related functions.
  8. */
  9. #include <linux/kernel_stat.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/seq_file.h>
  12. #include <linux/proc_fs.h>
  13. #include <linux/profile.h>
  14. #include <linux/module.h>
  15. #include <linux/kernel.h>
  16. #include <linux/ftrace.h>
  17. #include <linux/errno.h>
  18. #include <linux/slab.h>
  19. #include <linux/cpu.h>
  20. #include <linux/irq.h>
  21. #include <asm/irq_regs.h>
  22. #include <asm/cputime.h>
  23. #include <asm/lowcore.h>
  24. #include <asm/irq.h>
  25. #include <asm/hw_irq.h>
  26. #include "entry.h"
  27. DEFINE_PER_CPU_SHARED_ALIGNED(struct irq_stat, irq_stat);
  28. EXPORT_PER_CPU_SYMBOL_GPL(irq_stat);
  29. struct irq_class {
  30. int irq;
  31. char *name;
  32. char *desc;
  33. };
  34. /*
  35. * The list of "main" irq classes on s390. This is the list of interrupts
  36. * that appear both in /proc/stat ("intr" line) and /proc/interrupts.
  37. * Historically only external and I/O interrupts have been part of /proc/stat.
  38. * We can't add the split external and I/O sub classes since the first field
  39. * in the "intr" line in /proc/stat is supposed to be the sum of all other
  40. * fields.
  41. * Since the external and I/O interrupt fields are already sums we would end
  42. * up with having a sum which accounts each interrupt twice.
  43. */
  44. static const struct irq_class irqclass_main_desc[NR_IRQS_BASE] = {
  45. {.irq = EXT_INTERRUPT, .name = "EXT"},
  46. {.irq = IO_INTERRUPT, .name = "I/O"},
  47. {.irq = THIN_INTERRUPT, .name = "AIO"},
  48. };
  49. /*
  50. * The list of split external and I/O interrupts that appear only in
  51. * /proc/interrupts.
  52. * In addition this list contains non external / I/O events like NMIs.
  53. */
  54. static const struct irq_class irqclass_sub_desc[NR_ARCH_IRQS] = {
  55. {.irq = IRQEXT_CLK, .name = "CLK", .desc = "[EXT] Clock Comparator"},
  56. {.irq = IRQEXT_EXC, .name = "EXC", .desc = "[EXT] External Call"},
  57. {.irq = IRQEXT_EMS, .name = "EMS", .desc = "[EXT] Emergency Signal"},
  58. {.irq = IRQEXT_TMR, .name = "TMR", .desc = "[EXT] CPU Timer"},
  59. {.irq = IRQEXT_TLA, .name = "TAL", .desc = "[EXT] Timing Alert"},
  60. {.irq = IRQEXT_PFL, .name = "PFL", .desc = "[EXT] Pseudo Page Fault"},
  61. {.irq = IRQEXT_DSD, .name = "DSD", .desc = "[EXT] DASD Diag"},
  62. {.irq = IRQEXT_VRT, .name = "VRT", .desc = "[EXT] Virtio"},
  63. {.irq = IRQEXT_SCP, .name = "SCP", .desc = "[EXT] Service Call"},
  64. {.irq = IRQEXT_IUC, .name = "IUC", .desc = "[EXT] IUCV"},
  65. {.irq = IRQEXT_CMS, .name = "CMS", .desc = "[EXT] CPU-Measurement: Sampling"},
  66. {.irq = IRQEXT_CMC, .name = "CMC", .desc = "[EXT] CPU-Measurement: Counter"},
  67. {.irq = IRQEXT_CMR, .name = "CMR", .desc = "[EXT] CPU-Measurement: RI"},
  68. {.irq = IRQIO_CIO, .name = "CIO", .desc = "[I/O] Common I/O Layer Interrupt"},
  69. {.irq = IRQIO_QAI, .name = "QAI", .desc = "[I/O] QDIO Adapter Interrupt"},
  70. {.irq = IRQIO_DAS, .name = "DAS", .desc = "[I/O] DASD"},
  71. {.irq = IRQIO_C15, .name = "C15", .desc = "[I/O] 3215"},
  72. {.irq = IRQIO_C70, .name = "C70", .desc = "[I/O] 3270"},
  73. {.irq = IRQIO_TAP, .name = "TAP", .desc = "[I/O] Tape"},
  74. {.irq = IRQIO_VMR, .name = "VMR", .desc = "[I/O] Unit Record Devices"},
  75. {.irq = IRQIO_LCS, .name = "LCS", .desc = "[I/O] LCS"},
  76. {.irq = IRQIO_CLW, .name = "CLW", .desc = "[I/O] CLAW"},
  77. {.irq = IRQIO_CTC, .name = "CTC", .desc = "[I/O] CTC"},
  78. {.irq = IRQIO_APB, .name = "APB", .desc = "[I/O] AP Bus"},
  79. {.irq = IRQIO_ADM, .name = "ADM", .desc = "[I/O] EADM Subchannel"},
  80. {.irq = IRQIO_CSC, .name = "CSC", .desc = "[I/O] CHSC Subchannel"},
  81. {.irq = IRQIO_PCI, .name = "PCI", .desc = "[I/O] PCI Interrupt" },
  82. {.irq = IRQIO_MSI, .name = "MSI", .desc = "[I/O] MSI Interrupt" },
  83. {.irq = IRQIO_VIR, .name = "VIR", .desc = "[I/O] Virtual I/O Devices"},
  84. {.irq = IRQIO_VAI, .name = "VAI", .desc = "[I/O] Virtual I/O Devices AI"},
  85. {.irq = NMI_NMI, .name = "NMI", .desc = "[NMI] Machine Check"},
  86. {.irq = CPU_RST, .name = "RST", .desc = "[CPU] CPU Restart"},
  87. };
  88. void __init init_IRQ(void)
  89. {
  90. init_cio_interrupts();
  91. init_airq_interrupts();
  92. init_ext_interrupts();
  93. }
  94. void do_IRQ(struct pt_regs *regs, int irq)
  95. {
  96. struct pt_regs *old_regs;
  97. old_regs = set_irq_regs(regs);
  98. irq_enter();
  99. if (S390_lowcore.int_clock >= S390_lowcore.clock_comparator)
  100. /* Serve timer interrupts first. */
  101. clock_comparator_work();
  102. generic_handle_irq(irq);
  103. irq_exit();
  104. set_irq_regs(old_regs);
  105. }
  106. /*
  107. * show_interrupts is needed by /proc/interrupts.
  108. */
  109. int show_interrupts(struct seq_file *p, void *v)
  110. {
  111. int index = *(loff_t *) v;
  112. int cpu, irq;
  113. get_online_cpus();
  114. if (index == 0) {
  115. seq_puts(p, " ");
  116. for_each_online_cpu(cpu)
  117. seq_printf(p, "CPU%d ", cpu);
  118. seq_putc(p, '\n');
  119. goto out;
  120. }
  121. if (index < NR_IRQS) {
  122. if (index >= NR_IRQS_BASE)
  123. goto out;
  124. /* Adjust index to process irqclass_main_desc array entries */
  125. index--;
  126. seq_printf(p, "%s: ", irqclass_main_desc[index].name);
  127. irq = irqclass_main_desc[index].irq;
  128. for_each_online_cpu(cpu)
  129. seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu));
  130. seq_putc(p, '\n');
  131. goto out;
  132. }
  133. for (index = 0; index < NR_ARCH_IRQS; index++) {
  134. seq_printf(p, "%s: ", irqclass_sub_desc[index].name);
  135. irq = irqclass_sub_desc[index].irq;
  136. for_each_online_cpu(cpu)
  137. seq_printf(p, "%10u ",
  138. per_cpu(irq_stat, cpu).irqs[irq]);
  139. if (irqclass_sub_desc[index].desc)
  140. seq_printf(p, " %s", irqclass_sub_desc[index].desc);
  141. seq_putc(p, '\n');
  142. }
  143. out:
  144. put_online_cpus();
  145. return 0;
  146. }
  147. unsigned int arch_dynirq_lower_bound(unsigned int from)
  148. {
  149. return from < THIN_INTERRUPT ? THIN_INTERRUPT : from;
  150. }
  151. /*
  152. * Switch to the asynchronous interrupt stack for softirq execution.
  153. */
  154. void do_softirq_own_stack(void)
  155. {
  156. unsigned long old, new;
  157. /* Get current stack pointer. */
  158. asm volatile("la %0,0(15)" : "=a" (old));
  159. /* Check against async. stack address range. */
  160. new = S390_lowcore.async_stack;
  161. if (((new - old) >> (PAGE_SHIFT + THREAD_ORDER)) != 0) {
  162. /* Need to switch to the async. stack. */
  163. new -= STACK_FRAME_OVERHEAD;
  164. ((struct stack_frame *) new)->back_chain = old;
  165. asm volatile(" la 15,0(%0)\n"
  166. " basr 14,%2\n"
  167. " la 15,0(%1)\n"
  168. : : "a" (new), "a" (old),
  169. "a" (__do_softirq)
  170. : "0", "1", "2", "3", "4", "5", "14",
  171. "cc", "memory" );
  172. } else {
  173. /* We are already on the async stack. */
  174. __do_softirq();
  175. }
  176. }
  177. /*
  178. * ext_int_hash[index] is the list head for all external interrupts that hash
  179. * to this index.
  180. */
  181. static struct hlist_head ext_int_hash[32] ____cacheline_aligned;
  182. struct ext_int_info {
  183. ext_int_handler_t handler;
  184. struct hlist_node entry;
  185. struct rcu_head rcu;
  186. u16 code;
  187. };
  188. /* ext_int_hash_lock protects the handler lists for external interrupts */
  189. static DEFINE_SPINLOCK(ext_int_hash_lock);
  190. static inline int ext_hash(u16 code)
  191. {
  192. BUILD_BUG_ON(!is_power_of_2(ARRAY_SIZE(ext_int_hash)));
  193. return (code + (code >> 9)) & (ARRAY_SIZE(ext_int_hash) - 1);
  194. }
  195. int register_external_irq(u16 code, ext_int_handler_t handler)
  196. {
  197. struct ext_int_info *p;
  198. unsigned long flags;
  199. int index;
  200. p = kmalloc(sizeof(*p), GFP_ATOMIC);
  201. if (!p)
  202. return -ENOMEM;
  203. p->code = code;
  204. p->handler = handler;
  205. index = ext_hash(code);
  206. spin_lock_irqsave(&ext_int_hash_lock, flags);
  207. hlist_add_head_rcu(&p->entry, &ext_int_hash[index]);
  208. spin_unlock_irqrestore(&ext_int_hash_lock, flags);
  209. return 0;
  210. }
  211. EXPORT_SYMBOL(register_external_irq);
  212. int unregister_external_irq(u16 code, ext_int_handler_t handler)
  213. {
  214. struct ext_int_info *p;
  215. unsigned long flags;
  216. int index = ext_hash(code);
  217. spin_lock_irqsave(&ext_int_hash_lock, flags);
  218. hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
  219. if (p->code == code && p->handler == handler) {
  220. hlist_del_rcu(&p->entry);
  221. kfree_rcu(p, rcu);
  222. }
  223. }
  224. spin_unlock_irqrestore(&ext_int_hash_lock, flags);
  225. return 0;
  226. }
  227. EXPORT_SYMBOL(unregister_external_irq);
  228. static irqreturn_t do_ext_interrupt(int irq, void *dummy)
  229. {
  230. struct pt_regs *regs = get_irq_regs();
  231. struct ext_code ext_code;
  232. struct ext_int_info *p;
  233. int index;
  234. ext_code = *(struct ext_code *) &regs->int_code;
  235. if (ext_code.code != EXT_IRQ_CLK_COMP)
  236. __get_cpu_var(s390_idle).nohz_delay = 1;
  237. index = ext_hash(ext_code.code);
  238. rcu_read_lock();
  239. hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
  240. if (unlikely(p->code != ext_code.code))
  241. continue;
  242. p->handler(ext_code, regs->int_parm, regs->int_parm_long);
  243. }
  244. rcu_read_unlock();
  245. return IRQ_HANDLED;
  246. }
  247. static struct irqaction external_interrupt = {
  248. .name = "EXT",
  249. .handler = do_ext_interrupt,
  250. };
  251. void __init init_ext_interrupts(void)
  252. {
  253. int idx;
  254. for (idx = 0; idx < ARRAY_SIZE(ext_int_hash); idx++)
  255. INIT_HLIST_HEAD(&ext_int_hash[idx]);
  256. irq_set_chip_and_handler(EXT_INTERRUPT,
  257. &dummy_irq_chip, handle_percpu_irq);
  258. setup_irq(EXT_INTERRUPT, &external_interrupt);
  259. }
  260. static DEFINE_SPINLOCK(irq_subclass_lock);
  261. static unsigned char irq_subclass_refcount[64];
  262. void irq_subclass_register(enum irq_subclass subclass)
  263. {
  264. spin_lock(&irq_subclass_lock);
  265. if (!irq_subclass_refcount[subclass])
  266. ctl_set_bit(0, subclass);
  267. irq_subclass_refcount[subclass]++;
  268. spin_unlock(&irq_subclass_lock);
  269. }
  270. EXPORT_SYMBOL(irq_subclass_register);
  271. void irq_subclass_unregister(enum irq_subclass subclass)
  272. {
  273. spin_lock(&irq_subclass_lock);
  274. irq_subclass_refcount[subclass]--;
  275. if (!irq_subclass_refcount[subclass])
  276. ctl_clear_bit(0, subclass);
  277. spin_unlock(&irq_subclass_lock);
  278. }
  279. EXPORT_SYMBOL(irq_subclass_unregister);