mtu3_plat.c 11 KB

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  1. /*
  2. * Copyright (C) 2016 MediaTek Inc.
  3. *
  4. * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
  5. *
  6. * This software is licensed under the terms of the GNU General Public
  7. * License version 2, as published by the Free Software Foundation, and
  8. * may be copied, distributed, and modified under those terms.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. */
  16. #include <linux/clk.h>
  17. #include <linux/dma-mapping.h>
  18. #include <linux/iopoll.h>
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/of_address.h>
  22. #include <linux/of_irq.h>
  23. #include <linux/pinctrl/consumer.h>
  24. #include <linux/platform_device.h>
  25. #include "mtu3.h"
  26. #include "mtu3_dr.h"
  27. /* u2-port0 should be powered on and enabled; */
  28. int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks)
  29. {
  30. void __iomem *ibase = ssusb->ippc_base;
  31. u32 value, check_val;
  32. int ret;
  33. check_val = ex_clks | SSUSB_SYS125_RST_B_STS | SSUSB_SYSPLL_STABLE |
  34. SSUSB_REF_RST_B_STS;
  35. ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value,
  36. (check_val == (value & check_val)), 100, 20000);
  37. if (ret) {
  38. dev_err(ssusb->dev, "clks of sts1 are not stable!\n");
  39. return ret;
  40. }
  41. ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS2, value,
  42. (value & SSUSB_U2_MAC_SYS_RST_B_STS), 100, 10000);
  43. if (ret) {
  44. dev_err(ssusb->dev, "mac2 clock is not stable\n");
  45. return ret;
  46. }
  47. return 0;
  48. }
  49. static int ssusb_phy_init(struct ssusb_mtk *ssusb)
  50. {
  51. int i;
  52. int ret;
  53. for (i = 0; i < ssusb->num_phys; i++) {
  54. ret = phy_init(ssusb->phys[i]);
  55. if (ret)
  56. goto exit_phy;
  57. }
  58. return 0;
  59. exit_phy:
  60. for (; i > 0; i--)
  61. phy_exit(ssusb->phys[i - 1]);
  62. return ret;
  63. }
  64. static int ssusb_phy_exit(struct ssusb_mtk *ssusb)
  65. {
  66. int i;
  67. for (i = 0; i < ssusb->num_phys; i++)
  68. phy_exit(ssusb->phys[i]);
  69. return 0;
  70. }
  71. static int ssusb_phy_power_on(struct ssusb_mtk *ssusb)
  72. {
  73. int i;
  74. int ret;
  75. for (i = 0; i < ssusb->num_phys; i++) {
  76. ret = phy_power_on(ssusb->phys[i]);
  77. if (ret)
  78. goto power_off_phy;
  79. }
  80. return 0;
  81. power_off_phy:
  82. for (; i > 0; i--)
  83. phy_power_off(ssusb->phys[i - 1]);
  84. return ret;
  85. }
  86. static void ssusb_phy_power_off(struct ssusb_mtk *ssusb)
  87. {
  88. unsigned int i;
  89. for (i = 0; i < ssusb->num_phys; i++)
  90. phy_power_off(ssusb->phys[i]);
  91. }
  92. static int ssusb_rscs_init(struct ssusb_mtk *ssusb)
  93. {
  94. int ret = 0;
  95. ret = regulator_enable(ssusb->vusb33);
  96. if (ret) {
  97. dev_err(ssusb->dev, "failed to enable vusb33\n");
  98. goto vusb33_err;
  99. }
  100. ret = clk_prepare_enable(ssusb->sys_clk);
  101. if (ret) {
  102. dev_err(ssusb->dev, "failed to enable sys_clk\n");
  103. goto sys_clk_err;
  104. }
  105. ret = clk_prepare_enable(ssusb->ref_clk);
  106. if (ret) {
  107. dev_err(ssusb->dev, "failed to enable ref_clk\n");
  108. goto ref_clk_err;
  109. }
  110. ret = ssusb_phy_init(ssusb);
  111. if (ret) {
  112. dev_err(ssusb->dev, "failed to init phy\n");
  113. goto phy_init_err;
  114. }
  115. ret = ssusb_phy_power_on(ssusb);
  116. if (ret) {
  117. dev_err(ssusb->dev, "failed to power on phy\n");
  118. goto phy_err;
  119. }
  120. return 0;
  121. phy_err:
  122. ssusb_phy_exit(ssusb);
  123. phy_init_err:
  124. clk_disable_unprepare(ssusb->ref_clk);
  125. ref_clk_err:
  126. clk_disable_unprepare(ssusb->sys_clk);
  127. sys_clk_err:
  128. regulator_disable(ssusb->vusb33);
  129. vusb33_err:
  130. return ret;
  131. }
  132. static void ssusb_rscs_exit(struct ssusb_mtk *ssusb)
  133. {
  134. clk_disable_unprepare(ssusb->sys_clk);
  135. clk_disable_unprepare(ssusb->ref_clk);
  136. regulator_disable(ssusb->vusb33);
  137. ssusb_phy_power_off(ssusb);
  138. ssusb_phy_exit(ssusb);
  139. }
  140. static void ssusb_ip_sw_reset(struct ssusb_mtk *ssusb)
  141. {
  142. /* reset whole ip (xhci & u3d) */
  143. mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
  144. udelay(1);
  145. mtu3_clrbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
  146. }
  147. static int get_iddig_pinctrl(struct ssusb_mtk *ssusb)
  148. {
  149. struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
  150. otg_sx->id_pinctrl = devm_pinctrl_get(ssusb->dev);
  151. if (IS_ERR(otg_sx->id_pinctrl)) {
  152. dev_err(ssusb->dev, "Cannot find id pinctrl!\n");
  153. return PTR_ERR(otg_sx->id_pinctrl);
  154. }
  155. otg_sx->id_float =
  156. pinctrl_lookup_state(otg_sx->id_pinctrl, "id_float");
  157. if (IS_ERR(otg_sx->id_float)) {
  158. dev_err(ssusb->dev, "Cannot find pinctrl id_float!\n");
  159. return PTR_ERR(otg_sx->id_float);
  160. }
  161. otg_sx->id_ground =
  162. pinctrl_lookup_state(otg_sx->id_pinctrl, "id_ground");
  163. if (IS_ERR(otg_sx->id_ground)) {
  164. dev_err(ssusb->dev, "Cannot find pinctrl id_ground!\n");
  165. return PTR_ERR(otg_sx->id_ground);
  166. }
  167. return 0;
  168. }
  169. static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
  170. {
  171. struct device_node *node = pdev->dev.of_node;
  172. struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
  173. struct device *dev = &pdev->dev;
  174. struct regulator *vbus;
  175. struct resource *res;
  176. int i;
  177. int ret;
  178. ssusb->vusb33 = devm_regulator_get(&pdev->dev, "vusb33");
  179. if (IS_ERR(ssusb->vusb33)) {
  180. dev_err(dev, "failed to get vusb33\n");
  181. return PTR_ERR(ssusb->vusb33);
  182. }
  183. ssusb->sys_clk = devm_clk_get(dev, "sys_ck");
  184. if (IS_ERR(ssusb->sys_clk)) {
  185. dev_err(dev, "failed to get sys clock\n");
  186. return PTR_ERR(ssusb->sys_clk);
  187. }
  188. ssusb->ref_clk = devm_clk_get(dev, "ref_ck");
  189. if (IS_ERR(ssusb->ref_clk)) {
  190. dev_err(dev, "failed to get ref clock\n");
  191. return PTR_ERR(ssusb->ref_clk);
  192. }
  193. ssusb->num_phys = of_count_phandle_with_args(node,
  194. "phys", "#phy-cells");
  195. if (ssusb->num_phys > 0) {
  196. ssusb->phys = devm_kcalloc(dev, ssusb->num_phys,
  197. sizeof(*ssusb->phys), GFP_KERNEL);
  198. if (!ssusb->phys)
  199. return -ENOMEM;
  200. } else {
  201. ssusb->num_phys = 0;
  202. }
  203. for (i = 0; i < ssusb->num_phys; i++) {
  204. ssusb->phys[i] = devm_of_phy_get_by_index(dev, node, i);
  205. if (IS_ERR(ssusb->phys[i])) {
  206. dev_err(dev, "failed to get phy-%d\n", i);
  207. return PTR_ERR(ssusb->phys[i]);
  208. }
  209. }
  210. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc");
  211. ssusb->ippc_base = devm_ioremap_resource(dev, res);
  212. if (IS_ERR(ssusb->ippc_base)) {
  213. dev_err(dev, "failed to map memory for ippc\n");
  214. return PTR_ERR(ssusb->ippc_base);
  215. }
  216. ssusb->dr_mode = usb_get_dr_mode(dev);
  217. if (ssusb->dr_mode == USB_DR_MODE_UNKNOWN) {
  218. dev_err(dev, "dr_mode is error\n");
  219. return -EINVAL;
  220. }
  221. if (ssusb->dr_mode == USB_DR_MODE_PERIPHERAL)
  222. return 0;
  223. /* if host role is supported */
  224. ret = ssusb_wakeup_of_property_parse(ssusb, node);
  225. if (ret)
  226. return ret;
  227. if (ssusb->dr_mode != USB_DR_MODE_OTG)
  228. return 0;
  229. /* if dual-role mode is supported */
  230. vbus = devm_regulator_get(&pdev->dev, "vbus");
  231. if (IS_ERR(vbus)) {
  232. dev_err(dev, "failed to get vbus\n");
  233. return PTR_ERR(vbus);
  234. }
  235. otg_sx->vbus = vbus;
  236. otg_sx->is_u3_drd = of_property_read_bool(node, "mediatek,usb3-drd");
  237. otg_sx->manual_drd_enabled =
  238. of_property_read_bool(node, "enable-manual-drd");
  239. if (of_property_read_bool(node, "extcon")) {
  240. otg_sx->edev = extcon_get_edev_by_phandle(ssusb->dev, 0);
  241. if (IS_ERR(otg_sx->edev)) {
  242. dev_err(ssusb->dev, "couldn't get extcon device\n");
  243. return -EPROBE_DEFER;
  244. }
  245. if (otg_sx->manual_drd_enabled) {
  246. ret = get_iddig_pinctrl(ssusb);
  247. if (ret)
  248. return ret;
  249. }
  250. }
  251. dev_info(dev, "dr_mode: %d, is_u3_dr: %d\n",
  252. ssusb->dr_mode, otg_sx->is_u3_drd);
  253. return 0;
  254. }
  255. static int mtu3_probe(struct platform_device *pdev)
  256. {
  257. struct device_node *node = pdev->dev.of_node;
  258. struct device *dev = &pdev->dev;
  259. struct ssusb_mtk *ssusb;
  260. int ret = -ENOMEM;
  261. /* all elements are set to ZERO as default value */
  262. ssusb = devm_kzalloc(dev, sizeof(*ssusb), GFP_KERNEL);
  263. if (!ssusb)
  264. return -ENOMEM;
  265. ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
  266. if (ret) {
  267. dev_err(dev, "No suitable DMA config available\n");
  268. return -ENOTSUPP;
  269. }
  270. platform_set_drvdata(pdev, ssusb);
  271. ssusb->dev = dev;
  272. ret = get_ssusb_rscs(pdev, ssusb);
  273. if (ret)
  274. return ret;
  275. /* enable power domain */
  276. pm_runtime_enable(dev);
  277. pm_runtime_get_sync(dev);
  278. device_enable_async_suspend(dev);
  279. ret = ssusb_rscs_init(ssusb);
  280. if (ret)
  281. goto comm_init_err;
  282. ssusb_ip_sw_reset(ssusb);
  283. if (IS_ENABLED(CONFIG_USB_MTU3_HOST))
  284. ssusb->dr_mode = USB_DR_MODE_HOST;
  285. else if (IS_ENABLED(CONFIG_USB_MTU3_GADGET))
  286. ssusb->dr_mode = USB_DR_MODE_PERIPHERAL;
  287. /* default as host */
  288. ssusb->is_host = !(ssusb->dr_mode == USB_DR_MODE_PERIPHERAL);
  289. switch (ssusb->dr_mode) {
  290. case USB_DR_MODE_PERIPHERAL:
  291. ret = ssusb_gadget_init(ssusb);
  292. if (ret) {
  293. dev_err(dev, "failed to initialize gadget\n");
  294. goto comm_exit;
  295. }
  296. break;
  297. case USB_DR_MODE_HOST:
  298. ret = ssusb_host_init(ssusb, node);
  299. if (ret) {
  300. dev_err(dev, "failed to initialize host\n");
  301. goto comm_exit;
  302. }
  303. break;
  304. case USB_DR_MODE_OTG:
  305. ret = ssusb_gadget_init(ssusb);
  306. if (ret) {
  307. dev_err(dev, "failed to initialize gadget\n");
  308. goto comm_exit;
  309. }
  310. ret = ssusb_host_init(ssusb, node);
  311. if (ret) {
  312. dev_err(dev, "failed to initialize host\n");
  313. goto gadget_exit;
  314. }
  315. ssusb_otg_switch_init(ssusb);
  316. break;
  317. default:
  318. dev_err(dev, "unsupported mode: %d\n", ssusb->dr_mode);
  319. ret = -EINVAL;
  320. goto comm_exit;
  321. }
  322. return 0;
  323. gadget_exit:
  324. ssusb_gadget_exit(ssusb);
  325. comm_exit:
  326. ssusb_rscs_exit(ssusb);
  327. comm_init_err:
  328. pm_runtime_put_sync(dev);
  329. pm_runtime_disable(dev);
  330. return ret;
  331. }
  332. static int mtu3_remove(struct platform_device *pdev)
  333. {
  334. struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
  335. switch (ssusb->dr_mode) {
  336. case USB_DR_MODE_PERIPHERAL:
  337. ssusb_gadget_exit(ssusb);
  338. break;
  339. case USB_DR_MODE_HOST:
  340. ssusb_host_exit(ssusb);
  341. break;
  342. case USB_DR_MODE_OTG:
  343. ssusb_otg_switch_exit(ssusb);
  344. ssusb_gadget_exit(ssusb);
  345. ssusb_host_exit(ssusb);
  346. break;
  347. default:
  348. return -EINVAL;
  349. }
  350. ssusb_rscs_exit(ssusb);
  351. pm_runtime_put_sync(&pdev->dev);
  352. pm_runtime_disable(&pdev->dev);
  353. return 0;
  354. }
  355. /*
  356. * when support dual-role mode, we reject suspend when
  357. * it works as device mode;
  358. */
  359. static int __maybe_unused mtu3_suspend(struct device *dev)
  360. {
  361. struct platform_device *pdev = to_platform_device(dev);
  362. struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
  363. dev_dbg(dev, "%s\n", __func__);
  364. /* REVISIT: disconnect it for only device mode? */
  365. if (!ssusb->is_host)
  366. return 0;
  367. ssusb_host_disable(ssusb, true);
  368. ssusb_phy_power_off(ssusb);
  369. clk_disable_unprepare(ssusb->sys_clk);
  370. clk_disable_unprepare(ssusb->ref_clk);
  371. ssusb_wakeup_enable(ssusb);
  372. return 0;
  373. }
  374. static int __maybe_unused mtu3_resume(struct device *dev)
  375. {
  376. struct platform_device *pdev = to_platform_device(dev);
  377. struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
  378. dev_dbg(dev, "%s\n", __func__);
  379. if (!ssusb->is_host)
  380. return 0;
  381. ssusb_wakeup_disable(ssusb);
  382. clk_prepare_enable(ssusb->sys_clk);
  383. clk_prepare_enable(ssusb->ref_clk);
  384. ssusb_phy_power_on(ssusb);
  385. ssusb_host_enable(ssusb);
  386. return 0;
  387. }
  388. static const struct dev_pm_ops mtu3_pm_ops = {
  389. SET_SYSTEM_SLEEP_PM_OPS(mtu3_suspend, mtu3_resume)
  390. };
  391. #define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &mtu3_pm_ops : NULL)
  392. #ifdef CONFIG_OF
  393. static const struct of_device_id mtu3_of_match[] = {
  394. {.compatible = "mediatek,mt8173-mtu3",},
  395. {},
  396. };
  397. MODULE_DEVICE_TABLE(of, mtu3_of_match);
  398. #endif
  399. static struct platform_driver mtu3_driver = {
  400. .probe = mtu3_probe,
  401. .remove = mtu3_remove,
  402. .driver = {
  403. .name = MTU3_DRIVER_NAME,
  404. .pm = DEV_PM_OPS,
  405. .of_match_table = of_match_ptr(mtu3_of_match),
  406. },
  407. };
  408. module_platform_driver(mtu3_driver);
  409. MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
  410. MODULE_LICENSE("GPL v2");
  411. MODULE_DESCRIPTION("MediaTek USB3 DRD Controller Driver");