pmc.c 6.6 KB

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  1. /*
  2. * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. *
  9. */
  10. #include <linux/clk-provider.h>
  11. #include <linux/clkdev.h>
  12. #include <linux/clk/at91_pmc.h>
  13. #include <linux/of.h>
  14. #include <linux/mfd/syscon.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/regmap.h>
  17. #include <linux/syscore_ops.h>
  18. #include <asm/proc-fns.h>
  19. #include <dt-bindings/clock/at91.h>
  20. #include "pmc.h"
  21. #define PMC_MAX_IDS 128
  22. #define PMC_MAX_PCKS 8
  23. int of_at91_get_clk_range(struct device_node *np, const char *propname,
  24. struct clk_range *range)
  25. {
  26. u32 min, max;
  27. int ret;
  28. ret = of_property_read_u32_index(np, propname, 0, &min);
  29. if (ret)
  30. return ret;
  31. ret = of_property_read_u32_index(np, propname, 1, &max);
  32. if (ret)
  33. return ret;
  34. if (range) {
  35. range->min = min;
  36. range->max = max;
  37. }
  38. return 0;
  39. }
  40. EXPORT_SYMBOL_GPL(of_at91_get_clk_range);
  41. struct clk_hw *of_clk_hw_pmc_get(struct of_phandle_args *clkspec, void *data)
  42. {
  43. unsigned int type = clkspec->args[0];
  44. unsigned int idx = clkspec->args[1];
  45. struct pmc_data *pmc_data = data;
  46. switch (type) {
  47. case PMC_TYPE_CORE:
  48. if (idx < pmc_data->ncore)
  49. return pmc_data->chws[idx];
  50. break;
  51. case PMC_TYPE_SYSTEM:
  52. if (idx < pmc_data->nsystem)
  53. return pmc_data->shws[idx];
  54. break;
  55. case PMC_TYPE_PERIPHERAL:
  56. if (idx < pmc_data->nperiph)
  57. return pmc_data->phws[idx];
  58. break;
  59. case PMC_TYPE_GCK:
  60. if (idx < pmc_data->ngck)
  61. return pmc_data->ghws[idx];
  62. break;
  63. default:
  64. break;
  65. }
  66. pr_err("%s: invalid type (%u) or index (%u)\n", __func__, type, idx);
  67. return ERR_PTR(-EINVAL);
  68. }
  69. void pmc_data_free(struct pmc_data *pmc_data)
  70. {
  71. kfree(pmc_data->chws);
  72. kfree(pmc_data->shws);
  73. kfree(pmc_data->phws);
  74. kfree(pmc_data->ghws);
  75. }
  76. struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem,
  77. unsigned int nperiph, unsigned int ngck)
  78. {
  79. struct pmc_data *pmc_data = kzalloc(sizeof(*pmc_data), GFP_KERNEL);
  80. if (!pmc_data)
  81. return NULL;
  82. pmc_data->ncore = ncore;
  83. pmc_data->chws = kcalloc(ncore, sizeof(struct clk_hw *), GFP_KERNEL);
  84. if (!pmc_data->chws)
  85. goto err;
  86. pmc_data->nsystem = nsystem;
  87. pmc_data->shws = kcalloc(nsystem, sizeof(struct clk_hw *), GFP_KERNEL);
  88. if (!pmc_data->shws)
  89. goto err;
  90. pmc_data->nperiph = nperiph;
  91. pmc_data->phws = kcalloc(nperiph, sizeof(struct clk_hw *), GFP_KERNEL);
  92. if (!pmc_data->phws)
  93. goto err;
  94. pmc_data->ngck = ngck;
  95. pmc_data->ghws = kcalloc(ngck, sizeof(struct clk_hw *), GFP_KERNEL);
  96. if (!pmc_data->ghws)
  97. goto err;
  98. return pmc_data;
  99. err:
  100. pmc_data_free(pmc_data);
  101. return NULL;
  102. }
  103. #ifdef CONFIG_PM
  104. static struct regmap *pmcreg;
  105. static u8 registered_ids[PMC_MAX_IDS];
  106. static u8 registered_pcks[PMC_MAX_PCKS];
  107. static struct
  108. {
  109. u32 scsr;
  110. u32 pcsr0;
  111. u32 uckr;
  112. u32 mor;
  113. u32 mcfr;
  114. u32 pllar;
  115. u32 mckr;
  116. u32 usb;
  117. u32 imr;
  118. u32 pcsr1;
  119. u32 pcr[PMC_MAX_IDS];
  120. u32 audio_pll0;
  121. u32 audio_pll1;
  122. u32 pckr[PMC_MAX_PCKS];
  123. } pmc_cache;
  124. /*
  125. * As Peripheral ID 0 is invalid on AT91 chips, the identifier is stored
  126. * without alteration in the table, and 0 is for unused clocks.
  127. */
  128. void pmc_register_id(u8 id)
  129. {
  130. int i;
  131. for (i = 0; i < PMC_MAX_IDS; i++) {
  132. if (registered_ids[i] == 0) {
  133. registered_ids[i] = id;
  134. break;
  135. }
  136. if (registered_ids[i] == id)
  137. break;
  138. }
  139. }
  140. /*
  141. * As Programmable Clock 0 is valid on AT91 chips, there is an offset
  142. * of 1 between the stored value and the real clock ID.
  143. */
  144. void pmc_register_pck(u8 pck)
  145. {
  146. int i;
  147. for (i = 0; i < PMC_MAX_PCKS; i++) {
  148. if (registered_pcks[i] == 0) {
  149. registered_pcks[i] = pck + 1;
  150. break;
  151. }
  152. if (registered_pcks[i] == (pck + 1))
  153. break;
  154. }
  155. }
  156. static int pmc_suspend(void)
  157. {
  158. int i;
  159. u8 num;
  160. regmap_read(pmcreg, AT91_PMC_SCSR, &pmc_cache.scsr);
  161. regmap_read(pmcreg, AT91_PMC_PCSR, &pmc_cache.pcsr0);
  162. regmap_read(pmcreg, AT91_CKGR_UCKR, &pmc_cache.uckr);
  163. regmap_read(pmcreg, AT91_CKGR_MOR, &pmc_cache.mor);
  164. regmap_read(pmcreg, AT91_CKGR_MCFR, &pmc_cache.mcfr);
  165. regmap_read(pmcreg, AT91_CKGR_PLLAR, &pmc_cache.pllar);
  166. regmap_read(pmcreg, AT91_PMC_MCKR, &pmc_cache.mckr);
  167. regmap_read(pmcreg, AT91_PMC_USB, &pmc_cache.usb);
  168. regmap_read(pmcreg, AT91_PMC_IMR, &pmc_cache.imr);
  169. regmap_read(pmcreg, AT91_PMC_PCSR1, &pmc_cache.pcsr1);
  170. for (i = 0; registered_ids[i]; i++) {
  171. regmap_write(pmcreg, AT91_PMC_PCR,
  172. (registered_ids[i] & AT91_PMC_PCR_PID_MASK));
  173. regmap_read(pmcreg, AT91_PMC_PCR,
  174. &pmc_cache.pcr[registered_ids[i]]);
  175. }
  176. for (i = 0; registered_pcks[i]; i++) {
  177. num = registered_pcks[i] - 1;
  178. regmap_read(pmcreg, AT91_PMC_PCKR(num), &pmc_cache.pckr[num]);
  179. }
  180. return 0;
  181. }
  182. static bool pmc_ready(unsigned int mask)
  183. {
  184. unsigned int status;
  185. regmap_read(pmcreg, AT91_PMC_SR, &status);
  186. return ((status & mask) == mask) ? 1 : 0;
  187. }
  188. static void pmc_resume(void)
  189. {
  190. int i;
  191. u8 num;
  192. u32 tmp;
  193. u32 mask = AT91_PMC_MCKRDY | AT91_PMC_LOCKA;
  194. regmap_read(pmcreg, AT91_PMC_MCKR, &tmp);
  195. if (pmc_cache.mckr != tmp)
  196. pr_warn("MCKR was not configured properly by the firmware\n");
  197. regmap_read(pmcreg, AT91_CKGR_PLLAR, &tmp);
  198. if (pmc_cache.pllar != tmp)
  199. pr_warn("PLLAR was not configured properly by the firmware\n");
  200. regmap_write(pmcreg, AT91_PMC_SCER, pmc_cache.scsr);
  201. regmap_write(pmcreg, AT91_PMC_PCER, pmc_cache.pcsr0);
  202. regmap_write(pmcreg, AT91_CKGR_UCKR, pmc_cache.uckr);
  203. regmap_write(pmcreg, AT91_CKGR_MOR, pmc_cache.mor);
  204. regmap_write(pmcreg, AT91_CKGR_MCFR, pmc_cache.mcfr);
  205. regmap_write(pmcreg, AT91_PMC_USB, pmc_cache.usb);
  206. regmap_write(pmcreg, AT91_PMC_IMR, pmc_cache.imr);
  207. regmap_write(pmcreg, AT91_PMC_PCER1, pmc_cache.pcsr1);
  208. for (i = 0; registered_ids[i]; i++) {
  209. regmap_write(pmcreg, AT91_PMC_PCR,
  210. pmc_cache.pcr[registered_ids[i]] |
  211. AT91_PMC_PCR_CMD);
  212. }
  213. for (i = 0; registered_pcks[i]; i++) {
  214. num = registered_pcks[i] - 1;
  215. regmap_write(pmcreg, AT91_PMC_PCKR(num), pmc_cache.pckr[num]);
  216. }
  217. if (pmc_cache.uckr & AT91_PMC_UPLLEN)
  218. mask |= AT91_PMC_LOCKU;
  219. while (!pmc_ready(mask))
  220. cpu_relax();
  221. }
  222. static struct syscore_ops pmc_syscore_ops = {
  223. .suspend = pmc_suspend,
  224. .resume = pmc_resume,
  225. };
  226. static const struct of_device_id sama5d2_pmc_dt_ids[] = {
  227. { .compatible = "atmel,sama5d2-pmc" },
  228. { /* sentinel */ }
  229. };
  230. static int __init pmc_register_ops(void)
  231. {
  232. struct device_node *np;
  233. np = of_find_matching_node(NULL, sama5d2_pmc_dt_ids);
  234. pmcreg = syscon_node_to_regmap(np);
  235. if (IS_ERR(pmcreg))
  236. return PTR_ERR(pmcreg);
  237. register_syscore_ops(&pmc_syscore_ops);
  238. return 0;
  239. }
  240. /* This has to happen before arch_initcall because of the tcb_clksrc driver */
  241. postcore_initcall(pmc_register_ops);
  242. #endif