at91sam9x5.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <linux/clk-provider.h>
  3. #include <linux/mfd/syscon.h>
  4. #include <linux/slab.h>
  5. #include <dt-bindings/clock/at91.h>
  6. #include "pmc.h"
  7. static const struct clk_master_characteristics mck_characteristics = {
  8. .output = { .min = 0, .max = 133333333 },
  9. .divisors = { 1, 2, 4, 3 },
  10. .have_div3_pres = 1,
  11. };
  12. static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 };
  13. static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 };
  14. static struct clk_range plla_outputs[] = {
  15. { .min = 745000000, .max = 800000000 },
  16. { .min = 695000000, .max = 750000000 },
  17. { .min = 645000000, .max = 700000000 },
  18. { .min = 595000000, .max = 650000000 },
  19. { .min = 545000000, .max = 600000000 },
  20. { .min = 495000000, .max = 555000000 },
  21. { .min = 445000000, .max = 500000000 },
  22. { .min = 400000000, .max = 450000000 },
  23. };
  24. static const struct clk_pll_characteristics plla_characteristics = {
  25. .input = { .min = 2000000, .max = 32000000 },
  26. .num_output = ARRAY_SIZE(plla_outputs),
  27. .output = plla_outputs,
  28. .icpll = plla_icpll,
  29. .out = plla_out,
  30. };
  31. static const struct {
  32. char *n;
  33. char *p;
  34. u8 id;
  35. } at91sam9x5_systemck[] = {
  36. { .n = "ddrck", .p = "masterck", .id = 2 },
  37. { .n = "smdck", .p = "smdclk", .id = 4 },
  38. { .n = "uhpck", .p = "usbck", .id = 6 },
  39. { .n = "udpck", .p = "usbck", .id = 7 },
  40. { .n = "pck0", .p = "prog0", .id = 8 },
  41. { .n = "pck1", .p = "prog1", .id = 9 },
  42. };
  43. struct pck {
  44. char *n;
  45. u8 id;
  46. };
  47. static const struct pck at91sam9x5_periphck[] = {
  48. { .n = "pioAB_clk", .id = 2, },
  49. { .n = "pioCD_clk", .id = 3, },
  50. { .n = "smd_clk", .id = 4, },
  51. { .n = "usart0_clk", .id = 5, },
  52. { .n = "usart1_clk", .id = 6, },
  53. { .n = "usart2_clk", .id = 7, },
  54. { .n = "twi0_clk", .id = 9, },
  55. { .n = "twi1_clk", .id = 10, },
  56. { .n = "twi2_clk", .id = 11, },
  57. { .n = "mci0_clk", .id = 12, },
  58. { .n = "spi0_clk", .id = 13, },
  59. { .n = "spi1_clk", .id = 14, },
  60. { .n = "uart0_clk", .id = 15, },
  61. { .n = "uart1_clk", .id = 16, },
  62. { .n = "tcb0_clk", .id = 17, },
  63. { .n = "pwm_clk", .id = 18, },
  64. { .n = "adc_clk", .id = 19, },
  65. { .n = "dma0_clk", .id = 20, },
  66. { .n = "dma1_clk", .id = 21, },
  67. { .n = "uhphs_clk", .id = 22, },
  68. { .n = "udphs_clk", .id = 23, },
  69. { .n = "mci1_clk", .id = 26, },
  70. { .n = "ssc0_clk", .id = 28, },
  71. };
  72. static const struct pck at91sam9g15_periphck[] = {
  73. { .n = "lcdc_clk", .id = 25, },
  74. { /* sentinel */}
  75. };
  76. static const struct pck at91sam9g25_periphck[] = {
  77. { .n = "usart3_clk", .id = 8, },
  78. { .n = "macb0_clk", .id = 24, },
  79. { .n = "isi_clk", .id = 25, },
  80. { /* sentinel */}
  81. };
  82. static const struct pck at91sam9g35_periphck[] = {
  83. { .n = "macb0_clk", .id = 24, },
  84. { .n = "lcdc_clk", .id = 25, },
  85. { /* sentinel */}
  86. };
  87. static const struct pck at91sam9x25_periphck[] = {
  88. { .n = "usart3_clk", .id = 8, },
  89. { .n = "macb0_clk", .id = 24, },
  90. { .n = "macb1_clk", .id = 27, },
  91. { .n = "can0_clk", .id = 29, },
  92. { .n = "can1_clk", .id = 30, },
  93. { /* sentinel */}
  94. };
  95. static const struct pck at91sam9x35_periphck[] = {
  96. { .n = "macb0_clk", .id = 24, },
  97. { .n = "lcdc_clk", .id = 25, },
  98. { .n = "can0_clk", .id = 29, },
  99. { .n = "can1_clk", .id = 30, },
  100. { /* sentinel */}
  101. };
  102. static void __init at91sam9x5_pmc_setup(struct device_node *np,
  103. const struct pck *extra_pcks,
  104. bool has_lcdck)
  105. {
  106. struct clk_range range = CLK_RANGE(0, 0);
  107. const char *slck_name, *mainxtal_name;
  108. struct pmc_data *at91sam9x5_pmc;
  109. const char *parent_names[6];
  110. struct regmap *regmap;
  111. struct clk_hw *hw;
  112. int i;
  113. bool bypass;
  114. i = of_property_match_string(np, "clock-names", "slow_clk");
  115. if (i < 0)
  116. return;
  117. slck_name = of_clk_get_parent_name(np, i);
  118. i = of_property_match_string(np, "clock-names", "main_xtal");
  119. if (i < 0)
  120. return;
  121. mainxtal_name = of_clk_get_parent_name(np, i);
  122. regmap = syscon_node_to_regmap(np);
  123. if (IS_ERR(regmap))
  124. return;
  125. at91sam9x5_pmc = pmc_data_allocate(PMC_MAIN + 1,
  126. nck(at91sam9x5_systemck),
  127. nck(at91sam9x35_periphck), 0);
  128. if (!at91sam9x5_pmc)
  129. return;
  130. hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
  131. 50000000);
  132. if (IS_ERR(hw))
  133. goto err_free;
  134. bypass = of_property_read_bool(np, "atmel,osc-bypass");
  135. hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
  136. bypass);
  137. if (IS_ERR(hw))
  138. goto err_free;
  139. parent_names[0] = "main_rc_osc";
  140. parent_names[1] = "main_osc";
  141. hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
  142. if (IS_ERR(hw))
  143. goto err_free;
  144. at91sam9x5_pmc->chws[PMC_MAIN] = hw;
  145. hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
  146. &at91rm9200_pll_layout, &plla_characteristics);
  147. if (IS_ERR(hw))
  148. goto err_free;
  149. hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
  150. if (IS_ERR(hw))
  151. goto err_free;
  152. hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
  153. if (IS_ERR(hw))
  154. goto err_free;
  155. at91sam9x5_pmc->chws[PMC_UTMI] = hw;
  156. parent_names[0] = slck_name;
  157. parent_names[1] = "mainck";
  158. parent_names[2] = "plladivck";
  159. parent_names[3] = "utmick";
  160. hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
  161. &at91sam9x5_master_layout,
  162. &mck_characteristics);
  163. if (IS_ERR(hw))
  164. goto err_free;
  165. at91sam9x5_pmc->chws[PMC_MCK] = hw;
  166. parent_names[0] = "plladivck";
  167. parent_names[1] = "utmick";
  168. hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
  169. if (IS_ERR(hw))
  170. goto err_free;
  171. hw = at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2);
  172. if (IS_ERR(hw))
  173. goto err_free;
  174. parent_names[0] = slck_name;
  175. parent_names[1] = "mainck";
  176. parent_names[2] = "plladivck";
  177. parent_names[3] = "utmick";
  178. parent_names[4] = "mck";
  179. for (i = 0; i < 2; i++) {
  180. char name[6];
  181. snprintf(name, sizeof(name), "prog%d", i);
  182. hw = at91_clk_register_programmable(regmap, name,
  183. parent_names, 5, i,
  184. &at91sam9x5_programmable_layout);
  185. if (IS_ERR(hw))
  186. goto err_free;
  187. }
  188. for (i = 0; i < ARRAY_SIZE(at91sam9x5_systemck); i++) {
  189. hw = at91_clk_register_system(regmap, at91sam9x5_systemck[i].n,
  190. at91sam9x5_systemck[i].p,
  191. at91sam9x5_systemck[i].id);
  192. if (IS_ERR(hw))
  193. goto err_free;
  194. at91sam9x5_pmc->shws[at91sam9x5_systemck[i].id] = hw;
  195. }
  196. if (has_lcdck) {
  197. hw = at91_clk_register_system(regmap, "lcdck", "masterck", 3);
  198. if (IS_ERR(hw))
  199. goto err_free;
  200. at91sam9x5_pmc->shws[3] = hw;
  201. }
  202. for (i = 0; i < ARRAY_SIZE(at91sam9x5_periphck); i++) {
  203. hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
  204. at91sam9x5_periphck[i].n,
  205. "masterck",
  206. at91sam9x5_periphck[i].id,
  207. &range);
  208. if (IS_ERR(hw))
  209. goto err_free;
  210. at91sam9x5_pmc->phws[at91sam9x5_periphck[i].id] = hw;
  211. }
  212. for (i = 0; extra_pcks[i].id; i++) {
  213. hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
  214. extra_pcks[i].n,
  215. "masterck",
  216. extra_pcks[i].id,
  217. &range);
  218. if (IS_ERR(hw))
  219. goto err_free;
  220. at91sam9x5_pmc->phws[extra_pcks[i].id] = hw;
  221. }
  222. of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9x5_pmc);
  223. return;
  224. err_free:
  225. pmc_data_free(at91sam9x5_pmc);
  226. }
  227. static void __init at91sam9g15_pmc_setup(struct device_node *np)
  228. {
  229. at91sam9x5_pmc_setup(np, at91sam9g15_periphck, true);
  230. }
  231. CLK_OF_DECLARE_DRIVER(at91sam9g15_pmc, "atmel,at91sam9g15-pmc",
  232. at91sam9g15_pmc_setup);
  233. static void __init at91sam9g25_pmc_setup(struct device_node *np)
  234. {
  235. at91sam9x5_pmc_setup(np, at91sam9g25_periphck, false);
  236. }
  237. CLK_OF_DECLARE_DRIVER(at91sam9g25_pmc, "atmel,at91sam9g25-pmc",
  238. at91sam9g25_pmc_setup);
  239. static void __init at91sam9g35_pmc_setup(struct device_node *np)
  240. {
  241. at91sam9x5_pmc_setup(np, at91sam9g35_periphck, true);
  242. }
  243. CLK_OF_DECLARE_DRIVER(at91sam9g35_pmc, "atmel,at91sam9g35-pmc",
  244. at91sam9g35_pmc_setup);
  245. static void __init at91sam9x25_pmc_setup(struct device_node *np)
  246. {
  247. at91sam9x5_pmc_setup(np, at91sam9x25_periphck, false);
  248. }
  249. CLK_OF_DECLARE_DRIVER(at91sam9x25_pmc, "atmel,at91sam9x25-pmc",
  250. at91sam9x25_pmc_setup);
  251. static void __init at91sam9x35_pmc_setup(struct device_node *np)
  252. {
  253. at91sam9x5_pmc_setup(np, at91sam9x35_periphck, true);
  254. }
  255. CLK_OF_DECLARE_DRIVER(at91sam9x35_pmc, "atmel,at91sam9x35-pmc",
  256. at91sam9x35_pmc_setup);