soc.c 6.6 KB

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  1. /*
  2. * Copyright (C) 2015 Atmel
  3. *
  4. * Alexandre Belloni <alexandre.belloni@free-electrons.com
  5. * Boris Brezillon <boris.brezillon@free-electrons.com
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. *
  11. */
  12. #define pr_fmt(fmt) "AT91: " fmt
  13. #include <linux/io.h>
  14. #include <linux/of.h>
  15. #include <linux/of_address.h>
  16. #include <linux/of_platform.h>
  17. #include <linux/slab.h>
  18. #include <linux/sys_soc.h>
  19. #include "soc.h"
  20. #define AT91_DBGU_CIDR 0x40
  21. #define AT91_DBGU_EXID 0x44
  22. #define AT91_CHIPID_CIDR 0x00
  23. #define AT91_CHIPID_EXID 0x04
  24. #define AT91_CIDR_VERSION(x) ((x) & 0x1f)
  25. #define AT91_CIDR_EXT BIT(31)
  26. #define AT91_CIDR_MATCH_MASK 0x7fffffe0
  27. static const struct at91_soc __initconst socs[] = {
  28. #ifdef CONFIG_SOC_AT91RM9200
  29. AT91_SOC(AT91RM9200_CIDR_MATCH, 0, "at91rm9200 BGA", "at91rm9200"),
  30. #endif
  31. #ifdef CONFIG_SOC_AT91SAM9
  32. AT91_SOC(AT91SAM9260_CIDR_MATCH, 0, "at91sam9260", NULL),
  33. AT91_SOC(AT91SAM9261_CIDR_MATCH, 0, "at91sam9261", NULL),
  34. AT91_SOC(AT91SAM9263_CIDR_MATCH, 0, "at91sam9263", NULL),
  35. AT91_SOC(AT91SAM9G20_CIDR_MATCH, 0, "at91sam9g20", NULL),
  36. AT91_SOC(AT91SAM9RL64_CIDR_MATCH, 0, "at91sam9rl64", NULL),
  37. AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M11_EXID_MATCH,
  38. "at91sam9m11", "at91sam9g45"),
  39. AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M10_EXID_MATCH,
  40. "at91sam9m10", "at91sam9g45"),
  41. AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G46_EXID_MATCH,
  42. "at91sam9g46", "at91sam9g45"),
  43. AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G45_EXID_MATCH,
  44. "at91sam9g45", "at91sam9g45"),
  45. AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G15_EXID_MATCH,
  46. "at91sam9g15", "at91sam9x5"),
  47. AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G35_EXID_MATCH,
  48. "at91sam9g35", "at91sam9x5"),
  49. AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X35_EXID_MATCH,
  50. "at91sam9x35", "at91sam9x5"),
  51. AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G25_EXID_MATCH,
  52. "at91sam9g25", "at91sam9x5"),
  53. AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X25_EXID_MATCH,
  54. "at91sam9x25", "at91sam9x5"),
  55. AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN12_EXID_MATCH,
  56. "at91sam9cn12", "at91sam9n12"),
  57. AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9N12_EXID_MATCH,
  58. "at91sam9n12", "at91sam9n12"),
  59. AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN11_EXID_MATCH,
  60. "at91sam9cn11", "at91sam9n12"),
  61. AT91_SOC(AT91SAM9XE128_CIDR_MATCH, 0, "at91sam9xe128", "at91sam9xe128"),
  62. AT91_SOC(AT91SAM9XE256_CIDR_MATCH, 0, "at91sam9xe256", "at91sam9xe256"),
  63. AT91_SOC(AT91SAM9XE512_CIDR_MATCH, 0, "at91sam9xe512", "at91sam9xe512"),
  64. #endif
  65. #ifdef CONFIG_SOC_SAMA5
  66. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D21CU_EXID_MATCH,
  67. "sama5d21", "sama5d2"),
  68. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D22CU_EXID_MATCH,
  69. "sama5d22", "sama5d2"),
  70. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D23CU_EXID_MATCH,
  71. "sama5d23", "sama5d2"),
  72. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CX_EXID_MATCH,
  73. "sama5d24", "sama5d2"),
  74. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CU_EXID_MATCH,
  75. "sama5d24", "sama5d2"),
  76. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D26CU_EXID_MATCH,
  77. "sama5d26", "sama5d2"),
  78. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CU_EXID_MATCH,
  79. "sama5d27", "sama5d2"),
  80. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CN_EXID_MATCH,
  81. "sama5d27", "sama5d2"),
  82. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CU_EXID_MATCH,
  83. "sama5d28", "sama5d2"),
  84. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CN_EXID_MATCH,
  85. "sama5d28", "sama5d2"),
  86. AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D31_EXID_MATCH,
  87. "sama5d31", "sama5d3"),
  88. AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D33_EXID_MATCH,
  89. "sama5d33", "sama5d3"),
  90. AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D34_EXID_MATCH,
  91. "sama5d34", "sama5d3"),
  92. AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D35_EXID_MATCH,
  93. "sama5d35", "sama5d3"),
  94. AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D36_EXID_MATCH,
  95. "sama5d36", "sama5d3"),
  96. AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D41_EXID_MATCH,
  97. "sama5d41", "sama5d4"),
  98. AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D42_EXID_MATCH,
  99. "sama5d42", "sama5d4"),
  100. AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D43_EXID_MATCH,
  101. "sama5d43", "sama5d4"),
  102. AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D44_EXID_MATCH,
  103. "sama5d44", "sama5d4"),
  104. #endif
  105. { /* sentinel */ },
  106. };
  107. static int __init at91_get_cidr_exid_from_dbgu(u32 *cidr, u32 *exid)
  108. {
  109. struct device_node *np;
  110. void __iomem *regs;
  111. np = of_find_compatible_node(NULL, NULL, "atmel,at91rm9200-dbgu");
  112. if (!np)
  113. np = of_find_compatible_node(NULL, NULL,
  114. "atmel,at91sam9260-dbgu");
  115. if (!np)
  116. return -ENODEV;
  117. regs = of_iomap(np, 0);
  118. of_node_put(np);
  119. if (!regs) {
  120. pr_warn("Could not map DBGU iomem range");
  121. return -ENXIO;
  122. }
  123. *cidr = readl(regs + AT91_DBGU_CIDR);
  124. *exid = readl(regs + AT91_DBGU_EXID);
  125. iounmap(regs);
  126. return 0;
  127. }
  128. static int __init at91_get_cidr_exid_from_chipid(u32 *cidr, u32 *exid)
  129. {
  130. struct device_node *np;
  131. void __iomem *regs;
  132. np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-chipid");
  133. if (!np)
  134. return -ENODEV;
  135. regs = of_iomap(np, 0);
  136. of_node_put(np);
  137. if (!regs) {
  138. pr_warn("Could not map DBGU iomem range");
  139. return -ENXIO;
  140. }
  141. *cidr = readl(regs + AT91_CHIPID_CIDR);
  142. *exid = readl(regs + AT91_CHIPID_EXID);
  143. iounmap(regs);
  144. return 0;
  145. }
  146. struct soc_device * __init at91_soc_init(const struct at91_soc *socs)
  147. {
  148. struct soc_device_attribute *soc_dev_attr;
  149. const struct at91_soc *soc;
  150. struct soc_device *soc_dev;
  151. u32 cidr, exid;
  152. int ret;
  153. /*
  154. * With SAMA5D2 and later SoCs, CIDR and EXID registers are no more
  155. * in the dbgu device but in the chipid device whose purpose is only
  156. * to expose these two registers.
  157. */
  158. ret = at91_get_cidr_exid_from_dbgu(&cidr, &exid);
  159. if (ret)
  160. ret = at91_get_cidr_exid_from_chipid(&cidr, &exid);
  161. if (ret) {
  162. if (ret == -ENODEV)
  163. pr_warn("Could not find identification node");
  164. return NULL;
  165. }
  166. for (soc = socs; soc->name; soc++) {
  167. if (soc->cidr_match != (cidr & AT91_CIDR_MATCH_MASK))
  168. continue;
  169. if (!(cidr & AT91_CIDR_EXT) || soc->exid_match == exid)
  170. break;
  171. }
  172. if (!soc->name) {
  173. pr_warn("Could not find matching SoC description\n");
  174. return NULL;
  175. }
  176. soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
  177. if (!soc_dev_attr)
  178. return NULL;
  179. soc_dev_attr->family = soc->family;
  180. soc_dev_attr->soc_id = soc->name;
  181. soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%X",
  182. AT91_CIDR_VERSION(cidr));
  183. soc_dev = soc_device_register(soc_dev_attr);
  184. if (IS_ERR(soc_dev)) {
  185. kfree(soc_dev_attr->revision);
  186. kfree(soc_dev_attr);
  187. pr_warn("Could not register SoC device\n");
  188. return NULL;
  189. }
  190. if (soc->family)
  191. pr_info("Detected SoC family: %s\n", soc->family);
  192. pr_info("Detected SoC: %s, revision %X\n", soc->name,
  193. AT91_CIDR_VERSION(cidr));
  194. return soc_dev;
  195. }
  196. static int __init atmel_soc_device_init(void)
  197. {
  198. at91_soc_init(socs);
  199. return 0;
  200. }
  201. subsys_initcall(atmel_soc_device_init);