phy-bcm-ns-usb3.c 7.4 KB

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  1. /*
  2. * Broadcom Northstar USB 3.0 PHY Driver
  3. *
  4. * Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
  5. * Copyright (C) 2016 Broadcom
  6. *
  7. * All magic values used for initialization (and related comments) were obtained
  8. * from Broadcom's SDK:
  9. * Copyright (c) Broadcom Corp, 2012
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. #include <linux/bcma/bcma.h>
  16. #include <linux/delay.h>
  17. #include <linux/err.h>
  18. #include <linux/module.h>
  19. #include <linux/of_platform.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/phy/phy.h>
  22. #include <linux/slab.h>
  23. #define BCM_NS_USB3_MII_MNG_TIMEOUT_US 1000 /* usecs */
  24. #define BCM_NS_USB3_PHY_BASE_ADDR_REG 0x1f
  25. #define BCM_NS_USB3_PHY_PLL30_BLOCK 0x8000
  26. #define BCM_NS_USB3_PHY_TX_PMD_BLOCK 0x8040
  27. #define BCM_NS_USB3_PHY_PIPE_BLOCK 0x8060
  28. /* Registers of PLL30 block */
  29. #define BCM_NS_USB3_PLL_CONTROL 0x01
  30. #define BCM_NS_USB3_PLLA_CONTROL0 0x0a
  31. #define BCM_NS_USB3_PLLA_CONTROL1 0x0b
  32. /* Registers of TX PMD block */
  33. #define BCM_NS_USB3_TX_PMD_CONTROL1 0x01
  34. /* Registers of PIPE block */
  35. #define BCM_NS_USB3_LFPS_CMP 0x02
  36. #define BCM_NS_USB3_LFPS_DEGLITCH 0x03
  37. enum bcm_ns_family {
  38. BCM_NS_UNKNOWN,
  39. BCM_NS_AX,
  40. BCM_NS_BX,
  41. };
  42. struct bcm_ns_usb3 {
  43. struct device *dev;
  44. enum bcm_ns_family family;
  45. void __iomem *dmp;
  46. void __iomem *ccb_mii;
  47. struct phy *phy;
  48. };
  49. static const struct of_device_id bcm_ns_usb3_id_table[] = {
  50. {
  51. .compatible = "brcm,ns-ax-usb3-phy",
  52. .data = (int *)BCM_NS_AX,
  53. },
  54. {
  55. .compatible = "brcm,ns-bx-usb3-phy",
  56. .data = (int *)BCM_NS_BX,
  57. },
  58. {},
  59. };
  60. MODULE_DEVICE_TABLE(of, bcm_ns_usb3_id_table);
  61. static int bcm_ns_usb3_wait_reg(struct bcm_ns_usb3 *usb3, void __iomem *addr,
  62. u32 mask, u32 value, unsigned long timeout)
  63. {
  64. unsigned long deadline = jiffies + timeout;
  65. u32 val;
  66. do {
  67. val = readl(addr);
  68. if ((val & mask) == value)
  69. return 0;
  70. cpu_relax();
  71. udelay(10);
  72. } while (!time_after_eq(jiffies, deadline));
  73. dev_err(usb3->dev, "Timeout waiting for register %p\n", addr);
  74. return -EBUSY;
  75. }
  76. static inline int bcm_ns_usb3_mii_mng_wait_idle(struct bcm_ns_usb3 *usb3)
  77. {
  78. return bcm_ns_usb3_wait_reg(usb3, usb3->ccb_mii + BCMA_CCB_MII_MNG_CTL,
  79. 0x0100, 0x0000,
  80. usecs_to_jiffies(BCM_NS_USB3_MII_MNG_TIMEOUT_US));
  81. }
  82. static int bcm_ns_usb3_mdio_phy_write(struct bcm_ns_usb3 *usb3, u16 reg,
  83. u16 value)
  84. {
  85. u32 tmp = 0;
  86. int err;
  87. err = bcm_ns_usb3_mii_mng_wait_idle(usb3);
  88. if (err < 0) {
  89. dev_err(usb3->dev, "Couldn't write 0x%08x value\n", value);
  90. return err;
  91. }
  92. /* TODO: Use a proper MDIO bus layer */
  93. tmp |= 0x58020000; /* Magic value for MDIO PHY write */
  94. tmp |= reg << 18;
  95. tmp |= value;
  96. writel(tmp, usb3->ccb_mii + BCMA_CCB_MII_MNG_CMD_DATA);
  97. return 0;
  98. }
  99. static int bcm_ns_usb3_phy_init_ns_bx(struct bcm_ns_usb3 *usb3)
  100. {
  101. int err;
  102. /* Enable MDIO. Setting MDCDIV as 26 */
  103. writel(0x0000009a, usb3->ccb_mii + BCMA_CCB_MII_MNG_CTL);
  104. /* Wait for MDIO? */
  105. udelay(2);
  106. /* USB3 PLL Block */
  107. err = bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG,
  108. BCM_NS_USB3_PHY_PLL30_BLOCK);
  109. if (err < 0)
  110. return err;
  111. /* Assert Ana_Pllseq start */
  112. bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLL_CONTROL, 0x1000);
  113. /* Assert CML Divider ratio to 26 */
  114. bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLLA_CONTROL0, 0x6400);
  115. /* Asserting PLL Reset */
  116. bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLLA_CONTROL1, 0xc000);
  117. /* Deaaserting PLL Reset */
  118. bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLLA_CONTROL1, 0x8000);
  119. /* Waiting MII Mgt interface idle */
  120. bcm_ns_usb3_mii_mng_wait_idle(usb3);
  121. /* Deasserting USB3 system reset */
  122. writel(0, usb3->dmp + BCMA_RESET_CTL);
  123. /* PLL frequency monitor enable */
  124. bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLL_CONTROL, 0x9000);
  125. /* PIPE Block */
  126. bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG,
  127. BCM_NS_USB3_PHY_PIPE_BLOCK);
  128. /* CMPMAX & CMPMINTH setting */
  129. bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_LFPS_CMP, 0xf30d);
  130. /* DEGLITCH MIN & MAX setting */
  131. bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_LFPS_DEGLITCH, 0x6302);
  132. /* TXPMD block */
  133. bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG,
  134. BCM_NS_USB3_PHY_TX_PMD_BLOCK);
  135. /* Enabling SSC */
  136. bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_TX_PMD_CONTROL1, 0x1003);
  137. /* Waiting MII Mgt interface idle */
  138. bcm_ns_usb3_mii_mng_wait_idle(usb3);
  139. return 0;
  140. }
  141. static int bcm_ns_usb3_phy_init_ns_ax(struct bcm_ns_usb3 *usb3)
  142. {
  143. int err;
  144. /* Enable MDIO. Setting MDCDIV as 26 */
  145. writel(0x0000009a, usb3->ccb_mii + BCMA_CCB_MII_MNG_CTL);
  146. /* Wait for MDIO? */
  147. udelay(2);
  148. /* PLL30 block */
  149. err = bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG,
  150. BCM_NS_USB3_PHY_PLL30_BLOCK);
  151. if (err < 0)
  152. return err;
  153. bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLLA_CONTROL0, 0x6400);
  154. bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG, 0x80e0);
  155. bcm_ns_usb3_mdio_phy_write(usb3, 0x02, 0x009c);
  156. /* Enable SSC */
  157. bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG,
  158. BCM_NS_USB3_PHY_TX_PMD_BLOCK);
  159. bcm_ns_usb3_mdio_phy_write(usb3, 0x02, 0x21d3);
  160. bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_TX_PMD_CONTROL1, 0x1003);
  161. /* Waiting MII Mgt interface idle */
  162. bcm_ns_usb3_mii_mng_wait_idle(usb3);
  163. /* Deasserting USB3 system reset */
  164. writel(0, usb3->dmp + BCMA_RESET_CTL);
  165. return 0;
  166. }
  167. static int bcm_ns_usb3_phy_init(struct phy *phy)
  168. {
  169. struct bcm_ns_usb3 *usb3 = phy_get_drvdata(phy);
  170. int err;
  171. /* Perform USB3 system soft reset */
  172. writel(BCMA_RESET_CTL_RESET, usb3->dmp + BCMA_RESET_CTL);
  173. switch (usb3->family) {
  174. case BCM_NS_AX:
  175. err = bcm_ns_usb3_phy_init_ns_ax(usb3);
  176. break;
  177. case BCM_NS_BX:
  178. err = bcm_ns_usb3_phy_init_ns_bx(usb3);
  179. break;
  180. default:
  181. WARN_ON(1);
  182. err = -ENOTSUPP;
  183. }
  184. return err;
  185. }
  186. static const struct phy_ops ops = {
  187. .init = bcm_ns_usb3_phy_init,
  188. .owner = THIS_MODULE,
  189. };
  190. static int bcm_ns_usb3_probe(struct platform_device *pdev)
  191. {
  192. struct device *dev = &pdev->dev;
  193. const struct of_device_id *of_id;
  194. struct bcm_ns_usb3 *usb3;
  195. struct resource *res;
  196. struct phy_provider *phy_provider;
  197. usb3 = devm_kzalloc(dev, sizeof(*usb3), GFP_KERNEL);
  198. if (!usb3)
  199. return -ENOMEM;
  200. usb3->dev = dev;
  201. of_id = of_match_device(bcm_ns_usb3_id_table, dev);
  202. if (!of_id)
  203. return -EINVAL;
  204. usb3->family = (enum bcm_ns_family)of_id->data;
  205. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dmp");
  206. usb3->dmp = devm_ioremap_resource(dev, res);
  207. if (IS_ERR(usb3->dmp)) {
  208. dev_err(dev, "Failed to map DMP regs\n");
  209. return PTR_ERR(usb3->dmp);
  210. }
  211. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ccb-mii");
  212. usb3->ccb_mii = devm_ioremap_resource(dev, res);
  213. if (IS_ERR(usb3->ccb_mii)) {
  214. dev_err(dev, "Failed to map ChipCommon B MII regs\n");
  215. return PTR_ERR(usb3->ccb_mii);
  216. }
  217. usb3->phy = devm_phy_create(dev, NULL, &ops);
  218. if (IS_ERR(usb3->phy)) {
  219. dev_err(dev, "Failed to create PHY\n");
  220. return PTR_ERR(usb3->phy);
  221. }
  222. phy_set_drvdata(usb3->phy, usb3);
  223. platform_set_drvdata(pdev, usb3);
  224. phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
  225. if (!IS_ERR(phy_provider))
  226. dev_info(dev, "Registered Broadcom Northstar USB 3.0 PHY driver\n");
  227. return PTR_ERR_OR_ZERO(phy_provider);
  228. }
  229. static struct platform_driver bcm_ns_usb3_driver = {
  230. .probe = bcm_ns_usb3_probe,
  231. .driver = {
  232. .name = "bcm_ns_usb3",
  233. .of_match_table = bcm_ns_usb3_id_table,
  234. },
  235. };
  236. module_platform_driver(bcm_ns_usb3_driver);
  237. MODULE_LICENSE("GPL v2");