pci-epf-test.c 12 KB

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  1. /**
  2. * Test driver to test endpoint functionality
  3. *
  4. * Copyright (C) 2017 Texas Instruments
  5. * Author: Kishon Vijay Abraham I <kishon@ti.com>
  6. *
  7. * This program is free software: you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 of
  9. * the License as published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include <linux/crc32.h>
  20. #include <linux/delay.h>
  21. #include <linux/io.h>
  22. #include <linux/module.h>
  23. #include <linux/slab.h>
  24. #include <linux/pci_ids.h>
  25. #include <linux/random.h>
  26. #include <linux/pci-epc.h>
  27. #include <linux/pci-epf.h>
  28. #include <linux/pci_regs.h>
  29. #define COMMAND_RAISE_LEGACY_IRQ BIT(0)
  30. #define COMMAND_RAISE_MSI_IRQ BIT(1)
  31. #define MSI_NUMBER_SHIFT 2
  32. #define MSI_NUMBER_MASK (0x3f << MSI_NUMBER_SHIFT)
  33. #define COMMAND_READ BIT(8)
  34. #define COMMAND_WRITE BIT(9)
  35. #define COMMAND_COPY BIT(10)
  36. #define STATUS_READ_SUCCESS BIT(0)
  37. #define STATUS_READ_FAIL BIT(1)
  38. #define STATUS_WRITE_SUCCESS BIT(2)
  39. #define STATUS_WRITE_FAIL BIT(3)
  40. #define STATUS_COPY_SUCCESS BIT(4)
  41. #define STATUS_COPY_FAIL BIT(5)
  42. #define STATUS_IRQ_RAISED BIT(6)
  43. #define STATUS_SRC_ADDR_INVALID BIT(7)
  44. #define STATUS_DST_ADDR_INVALID BIT(8)
  45. #define TIMER_RESOLUTION 1
  46. static struct workqueue_struct *kpcitest_workqueue;
  47. struct pci_epf_test {
  48. void *reg[6];
  49. struct pci_epf *epf;
  50. struct delayed_work cmd_handler;
  51. };
  52. struct pci_epf_test_reg {
  53. u32 magic;
  54. u32 command;
  55. u32 status;
  56. u64 src_addr;
  57. u64 dst_addr;
  58. u32 size;
  59. u32 checksum;
  60. } __packed;
  61. static struct pci_epf_header test_header = {
  62. .vendorid = PCI_ANY_ID,
  63. .deviceid = PCI_ANY_ID,
  64. .baseclass_code = PCI_CLASS_OTHERS,
  65. .interrupt_pin = PCI_INTERRUPT_INTA,
  66. };
  67. static int bar_size[] = { 512, 1024, 16384, 131072, 1048576 };
  68. static int pci_epf_test_copy(struct pci_epf_test *epf_test)
  69. {
  70. int ret;
  71. void __iomem *src_addr;
  72. void __iomem *dst_addr;
  73. phys_addr_t src_phys_addr;
  74. phys_addr_t dst_phys_addr;
  75. struct pci_epf *epf = epf_test->epf;
  76. struct device *dev = &epf->dev;
  77. struct pci_epc *epc = epf->epc;
  78. struct pci_epf_test_reg *reg = epf_test->reg[0];
  79. src_addr = pci_epc_mem_alloc_addr(epc, &src_phys_addr, reg->size);
  80. if (!src_addr) {
  81. dev_err(dev, "failed to allocate source address\n");
  82. reg->status = STATUS_SRC_ADDR_INVALID;
  83. ret = -ENOMEM;
  84. goto err;
  85. }
  86. ret = pci_epc_map_addr(epc, src_phys_addr, reg->src_addr, reg->size);
  87. if (ret) {
  88. dev_err(dev, "failed to map source address\n");
  89. reg->status = STATUS_SRC_ADDR_INVALID;
  90. goto err_src_addr;
  91. }
  92. dst_addr = pci_epc_mem_alloc_addr(epc, &dst_phys_addr, reg->size);
  93. if (!dst_addr) {
  94. dev_err(dev, "failed to allocate destination address\n");
  95. reg->status = STATUS_DST_ADDR_INVALID;
  96. ret = -ENOMEM;
  97. goto err_src_map_addr;
  98. }
  99. ret = pci_epc_map_addr(epc, dst_phys_addr, reg->dst_addr, reg->size);
  100. if (ret) {
  101. dev_err(dev, "failed to map destination address\n");
  102. reg->status = STATUS_DST_ADDR_INVALID;
  103. goto err_dst_addr;
  104. }
  105. memcpy(dst_addr, src_addr, reg->size);
  106. pci_epc_unmap_addr(epc, dst_phys_addr);
  107. err_dst_addr:
  108. pci_epc_mem_free_addr(epc, dst_phys_addr, dst_addr, reg->size);
  109. err_src_map_addr:
  110. pci_epc_unmap_addr(epc, src_phys_addr);
  111. err_src_addr:
  112. pci_epc_mem_free_addr(epc, src_phys_addr, src_addr, reg->size);
  113. err:
  114. return ret;
  115. }
  116. static int pci_epf_test_read(struct pci_epf_test *epf_test)
  117. {
  118. int ret;
  119. void __iomem *src_addr;
  120. void *buf;
  121. u32 crc32;
  122. phys_addr_t phys_addr;
  123. struct pci_epf *epf = epf_test->epf;
  124. struct device *dev = &epf->dev;
  125. struct pci_epc *epc = epf->epc;
  126. struct pci_epf_test_reg *reg = epf_test->reg[0];
  127. src_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, reg->size);
  128. if (!src_addr) {
  129. dev_err(dev, "failed to allocate address\n");
  130. reg->status = STATUS_SRC_ADDR_INVALID;
  131. ret = -ENOMEM;
  132. goto err;
  133. }
  134. ret = pci_epc_map_addr(epc, phys_addr, reg->src_addr, reg->size);
  135. if (ret) {
  136. dev_err(dev, "failed to map address\n");
  137. reg->status = STATUS_SRC_ADDR_INVALID;
  138. goto err_addr;
  139. }
  140. buf = kzalloc(reg->size, GFP_KERNEL);
  141. if (!buf) {
  142. ret = -ENOMEM;
  143. goto err_map_addr;
  144. }
  145. memcpy(buf, src_addr, reg->size);
  146. crc32 = crc32_le(~0, buf, reg->size);
  147. if (crc32 != reg->checksum)
  148. ret = -EIO;
  149. kfree(buf);
  150. err_map_addr:
  151. pci_epc_unmap_addr(epc, phys_addr);
  152. err_addr:
  153. pci_epc_mem_free_addr(epc, phys_addr, src_addr, reg->size);
  154. err:
  155. return ret;
  156. }
  157. static int pci_epf_test_write(struct pci_epf_test *epf_test)
  158. {
  159. int ret;
  160. void __iomem *dst_addr;
  161. void *buf;
  162. phys_addr_t phys_addr;
  163. struct pci_epf *epf = epf_test->epf;
  164. struct device *dev = &epf->dev;
  165. struct pci_epc *epc = epf->epc;
  166. struct pci_epf_test_reg *reg = epf_test->reg[0];
  167. dst_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, reg->size);
  168. if (!dst_addr) {
  169. dev_err(dev, "failed to allocate address\n");
  170. reg->status = STATUS_DST_ADDR_INVALID;
  171. ret = -ENOMEM;
  172. goto err;
  173. }
  174. ret = pci_epc_map_addr(epc, phys_addr, reg->dst_addr, reg->size);
  175. if (ret) {
  176. dev_err(dev, "failed to map address\n");
  177. reg->status = STATUS_DST_ADDR_INVALID;
  178. goto err_addr;
  179. }
  180. buf = kzalloc(reg->size, GFP_KERNEL);
  181. if (!buf) {
  182. ret = -ENOMEM;
  183. goto err_map_addr;
  184. }
  185. get_random_bytes(buf, reg->size);
  186. reg->checksum = crc32_le(~0, buf, reg->size);
  187. memcpy(dst_addr, buf, reg->size);
  188. /*
  189. * wait 1ms inorder for the write to complete. Without this delay L3
  190. * error in observed in the host system.
  191. */
  192. mdelay(1);
  193. kfree(buf);
  194. err_map_addr:
  195. pci_epc_unmap_addr(epc, phys_addr);
  196. err_addr:
  197. pci_epc_mem_free_addr(epc, phys_addr, dst_addr, reg->size);
  198. err:
  199. return ret;
  200. }
  201. static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test)
  202. {
  203. u8 irq;
  204. u8 msi_count;
  205. struct pci_epf *epf = epf_test->epf;
  206. struct pci_epc *epc = epf->epc;
  207. struct pci_epf_test_reg *reg = epf_test->reg[0];
  208. reg->status |= STATUS_IRQ_RAISED;
  209. msi_count = pci_epc_get_msi(epc);
  210. irq = (reg->command & MSI_NUMBER_MASK) >> MSI_NUMBER_SHIFT;
  211. if (irq > msi_count || msi_count <= 0)
  212. pci_epc_raise_irq(epc, PCI_EPC_IRQ_LEGACY, 0);
  213. else
  214. pci_epc_raise_irq(epc, PCI_EPC_IRQ_MSI, irq);
  215. }
  216. static void pci_epf_test_cmd_handler(struct work_struct *work)
  217. {
  218. int ret;
  219. u8 irq;
  220. u8 msi_count;
  221. struct pci_epf_test *epf_test = container_of(work, struct pci_epf_test,
  222. cmd_handler.work);
  223. struct pci_epf *epf = epf_test->epf;
  224. struct pci_epc *epc = epf->epc;
  225. struct pci_epf_test_reg *reg = epf_test->reg[0];
  226. if (!reg->command)
  227. goto reset_handler;
  228. if (reg->command & COMMAND_RAISE_LEGACY_IRQ) {
  229. reg->status = STATUS_IRQ_RAISED;
  230. pci_epc_raise_irq(epc, PCI_EPC_IRQ_LEGACY, 0);
  231. goto reset_handler;
  232. }
  233. if (reg->command & COMMAND_WRITE) {
  234. ret = pci_epf_test_write(epf_test);
  235. if (ret)
  236. reg->status |= STATUS_WRITE_FAIL;
  237. else
  238. reg->status |= STATUS_WRITE_SUCCESS;
  239. pci_epf_test_raise_irq(epf_test);
  240. goto reset_handler;
  241. }
  242. if (reg->command & COMMAND_READ) {
  243. ret = pci_epf_test_read(epf_test);
  244. if (!ret)
  245. reg->status |= STATUS_READ_SUCCESS;
  246. else
  247. reg->status |= STATUS_READ_FAIL;
  248. pci_epf_test_raise_irq(epf_test);
  249. goto reset_handler;
  250. }
  251. if (reg->command & COMMAND_COPY) {
  252. ret = pci_epf_test_copy(epf_test);
  253. if (!ret)
  254. reg->status |= STATUS_COPY_SUCCESS;
  255. else
  256. reg->status |= STATUS_COPY_FAIL;
  257. pci_epf_test_raise_irq(epf_test);
  258. goto reset_handler;
  259. }
  260. if (reg->command & COMMAND_RAISE_MSI_IRQ) {
  261. msi_count = pci_epc_get_msi(epc);
  262. irq = (reg->command & MSI_NUMBER_MASK) >> MSI_NUMBER_SHIFT;
  263. if (irq > msi_count || msi_count <= 0)
  264. goto reset_handler;
  265. reg->status = STATUS_IRQ_RAISED;
  266. pci_epc_raise_irq(epc, PCI_EPC_IRQ_MSI, irq);
  267. goto reset_handler;
  268. }
  269. reset_handler:
  270. reg->command = 0;
  271. queue_delayed_work(kpcitest_workqueue, &epf_test->cmd_handler,
  272. msecs_to_jiffies(1));
  273. }
  274. static void pci_epf_test_linkup(struct pci_epf *epf)
  275. {
  276. struct pci_epf_test *epf_test = epf_get_drvdata(epf);
  277. queue_delayed_work(kpcitest_workqueue, &epf_test->cmd_handler,
  278. msecs_to_jiffies(1));
  279. }
  280. static void pci_epf_test_unbind(struct pci_epf *epf)
  281. {
  282. struct pci_epf_test *epf_test = epf_get_drvdata(epf);
  283. struct pci_epc *epc = epf->epc;
  284. int bar;
  285. cancel_delayed_work(&epf_test->cmd_handler);
  286. pci_epc_stop(epc);
  287. for (bar = BAR_0; bar <= BAR_5; bar++) {
  288. if (epf_test->reg[bar]) {
  289. pci_epf_free_space(epf, epf_test->reg[bar], bar);
  290. pci_epc_clear_bar(epc, bar);
  291. }
  292. }
  293. }
  294. static int pci_epf_test_set_bar(struct pci_epf *epf)
  295. {
  296. int flags;
  297. int bar;
  298. int ret;
  299. struct pci_epf_bar *epf_bar;
  300. struct pci_epc *epc = epf->epc;
  301. struct device *dev = &epf->dev;
  302. struct pci_epf_test *epf_test = epf_get_drvdata(epf);
  303. flags = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_32;
  304. if (sizeof(dma_addr_t) == 0x8)
  305. flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
  306. for (bar = BAR_0; bar <= BAR_5; bar++) {
  307. epf_bar = &epf->bar[bar];
  308. ret = pci_epc_set_bar(epc, bar, epf_bar->phys_addr,
  309. epf_bar->size, flags);
  310. if (ret) {
  311. pci_epf_free_space(epf, epf_test->reg[bar], bar);
  312. dev_err(dev, "failed to set BAR%d\n", bar);
  313. if (bar == BAR_0)
  314. return ret;
  315. }
  316. }
  317. return 0;
  318. }
  319. static int pci_epf_test_alloc_space(struct pci_epf *epf)
  320. {
  321. struct pci_epf_test *epf_test = epf_get_drvdata(epf);
  322. struct device *dev = &epf->dev;
  323. void *base;
  324. int bar;
  325. base = pci_epf_alloc_space(epf, sizeof(struct pci_epf_test_reg),
  326. BAR_0);
  327. if (!base) {
  328. dev_err(dev, "failed to allocated register space\n");
  329. return -ENOMEM;
  330. }
  331. epf_test->reg[0] = base;
  332. for (bar = BAR_1; bar <= BAR_5; bar++) {
  333. base = pci_epf_alloc_space(epf, bar_size[bar - 1], bar);
  334. if (!base)
  335. dev_err(dev, "failed to allocate space for BAR%d\n",
  336. bar);
  337. epf_test->reg[bar] = base;
  338. }
  339. return 0;
  340. }
  341. static int pci_epf_test_bind(struct pci_epf *epf)
  342. {
  343. int ret;
  344. struct pci_epf_header *header = epf->header;
  345. struct pci_epc *epc = epf->epc;
  346. struct device *dev = &epf->dev;
  347. if (WARN_ON_ONCE(!epc))
  348. return -EINVAL;
  349. ret = pci_epc_write_header(epc, header);
  350. if (ret) {
  351. dev_err(dev, "configuration header write failed\n");
  352. return ret;
  353. }
  354. ret = pci_epf_test_alloc_space(epf);
  355. if (ret)
  356. return ret;
  357. ret = pci_epf_test_set_bar(epf);
  358. if (ret)
  359. return ret;
  360. ret = pci_epc_set_msi(epc, epf->msi_interrupts);
  361. if (ret)
  362. return ret;
  363. return 0;
  364. }
  365. static int pci_epf_test_probe(struct pci_epf *epf)
  366. {
  367. struct pci_epf_test *epf_test;
  368. struct device *dev = &epf->dev;
  369. epf_test = devm_kzalloc(dev, sizeof(*epf_test), GFP_KERNEL);
  370. if (!epf_test)
  371. return -ENOMEM;
  372. epf->header = &test_header;
  373. epf_test->epf = epf;
  374. INIT_DELAYED_WORK(&epf_test->cmd_handler, pci_epf_test_cmd_handler);
  375. epf_set_drvdata(epf, epf_test);
  376. return 0;
  377. }
  378. static int pci_epf_test_remove(struct pci_epf *epf)
  379. {
  380. struct pci_epf_test *epf_test = epf_get_drvdata(epf);
  381. kfree(epf_test);
  382. return 0;
  383. }
  384. static struct pci_epf_ops ops = {
  385. .unbind = pci_epf_test_unbind,
  386. .bind = pci_epf_test_bind,
  387. .linkup = pci_epf_test_linkup,
  388. };
  389. static const struct pci_epf_device_id pci_epf_test_ids[] = {
  390. {
  391. .name = "pci_epf_test",
  392. },
  393. {},
  394. };
  395. static struct pci_epf_driver test_driver = {
  396. .driver.name = "pci_epf_test",
  397. .probe = pci_epf_test_probe,
  398. .remove = pci_epf_test_remove,
  399. .id_table = pci_epf_test_ids,
  400. .ops = &ops,
  401. .owner = THIS_MODULE,
  402. };
  403. static int __init pci_epf_test_init(void)
  404. {
  405. int ret;
  406. kpcitest_workqueue = alloc_workqueue("kpcitest",
  407. WQ_MEM_RECLAIM | WQ_HIGHPRI, 0);
  408. ret = pci_epf_register_driver(&test_driver);
  409. if (ret) {
  410. pr_err("failed to register pci epf test driver --> %d\n", ret);
  411. return ret;
  412. }
  413. return 0;
  414. }
  415. module_init(pci_epf_test_init);
  416. static void __exit pci_epf_test_exit(void)
  417. {
  418. pci_epf_unregister_driver(&test_driver);
  419. }
  420. module_exit(pci_epf_test_exit);
  421. MODULE_DESCRIPTION("PCI EPF TEST DRIVER");
  422. MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
  423. MODULE_LICENSE("GPL v2");