phy.h 3.2 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2012 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * The full GNU General Public License is included in this distribution in the
  15. * file called LICENSE.
  16. *
  17. * Contact Information:
  18. * wlanfae <wlanfae@realtek.com>
  19. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20. * Hsinchu 300, Taiwan.
  21. *
  22. * Larry Finger <Larry.Finger@lwfinger.net>
  23. *
  24. *****************************************************************************/
  25. #ifndef __RTL92S_PHY_H__
  26. #define __RTL92S_PHY_H__
  27. #define MAX_TXPWR_IDX_NMODE_92S 63
  28. #define MAX_DOZE_WAITING_TIMES_9x 64
  29. /* Channel switch:The size of
  30. * command tables for switch channel */
  31. #define MAX_PRECMD_CNT 16
  32. #define MAX_RFDEPENDCMD_CNT 16
  33. #define MAX_POSTCMD_CNT 16
  34. #define RF90_PATH_MAX 4
  35. #define RF6052_MAX_PATH 2
  36. enum version_8192s {
  37. VERSION_8192S_ACUT,
  38. VERSION_8192S_BCUT,
  39. VERSION_8192S_CCUT
  40. };
  41. enum swchnlcmd_id {
  42. CMDID_END,
  43. CMDID_SET_TXPOWEROWER_LEVEL,
  44. CMDID_BBREGWRITE10,
  45. CMDID_WRITEPORT_ULONG,
  46. CMDID_WRITEPORT_USHORT,
  47. CMDID_WRITEPORT_UCHAR,
  48. CMDID_RF_WRITEREG,
  49. };
  50. struct swchnlcmd {
  51. enum swchnlcmd_id cmdid;
  52. u32 para1;
  53. u32 para2;
  54. u32 msdelay;
  55. };
  56. enum baseband_config_type {
  57. /* Radio Path A */
  58. BASEBAND_CONFIG_PHY_REG = 0,
  59. /* Radio Path B */
  60. BASEBAND_CONFIG_AGC_TAB = 1,
  61. };
  62. #define hal_get_firmwareversion(rtlpriv) \
  63. (((struct rt_firmware *)(rtlpriv->rtlhal.pfirmware))->firmwareversion)
  64. u32 rtl92s_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
  65. void rtl92s_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
  66. u32 data);
  67. void rtl92s_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation);
  68. u32 rtl92s_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
  69. u32 regaddr, u32 bitmask);
  70. void rtl92s_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
  71. u32 regaddr, u32 bitmask, u32 data);
  72. void rtl92s_phy_set_bw_mode(struct ieee80211_hw *hw,
  73. enum nl80211_channel_type ch_type);
  74. u8 rtl92s_phy_sw_chnl(struct ieee80211_hw *hw);
  75. bool rtl92s_phy_set_rf_power_state(struct ieee80211_hw *hw,
  76. enum rf_pwrstate rfpower_state);
  77. bool rtl92s_phy_mac_config(struct ieee80211_hw *hw);
  78. void rtl92s_phy_switch_ephy_parameter(struct ieee80211_hw *hw);
  79. bool rtl92s_phy_bb_config(struct ieee80211_hw *hw);
  80. bool rtl92s_phy_rf_config(struct ieee80211_hw *hw);
  81. void rtl92s_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
  82. void rtl92s_phy_set_txpower(struct ieee80211_hw *hw, u8 channel);
  83. bool rtl92s_phy_set_fw_cmd(struct ieee80211_hw *hw, enum fwcmd_iotype fwcmd_io);
  84. void rtl92s_phy_chk_fwcmd_iodone(struct ieee80211_hw *hw);
  85. void rtl92s_phy_set_beacon_hwreg(struct ieee80211_hw *hw, u16 beaconinterval);
  86. u8 rtl92s_phy_config_rf(struct ieee80211_hw *hw, enum radio_path rfpath) ;
  87. #endif