core.c 64 KB

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  1. /*
  2. * Copyright (c) 2005-2011 Atheros Communications Inc.
  3. * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/firmware.h>
  19. #include <linux/of.h>
  20. #include <linux/dmi.h>
  21. #include <linux/ctype.h>
  22. #include <asm/byteorder.h>
  23. #include "core.h"
  24. #include "mac.h"
  25. #include "htc.h"
  26. #include "hif.h"
  27. #include "wmi.h"
  28. #include "bmi.h"
  29. #include "debug.h"
  30. #include "htt.h"
  31. #include "testmode.h"
  32. #include "wmi-ops.h"
  33. unsigned int ath10k_debug_mask;
  34. static unsigned int ath10k_cryptmode_param;
  35. static bool uart_print;
  36. static bool skip_otp;
  37. static bool rawmode;
  38. module_param_named(debug_mask, ath10k_debug_mask, uint, 0644);
  39. module_param_named(cryptmode, ath10k_cryptmode_param, uint, 0644);
  40. module_param(uart_print, bool, 0644);
  41. module_param(skip_otp, bool, 0644);
  42. module_param(rawmode, bool, 0644);
  43. MODULE_PARM_DESC(debug_mask, "Debugging mask");
  44. MODULE_PARM_DESC(uart_print, "Uart target debugging");
  45. MODULE_PARM_DESC(skip_otp, "Skip otp failure for calibration in testmode");
  46. MODULE_PARM_DESC(cryptmode, "Crypto mode: 0-hardware, 1-software");
  47. MODULE_PARM_DESC(rawmode, "Use raw 802.11 frame datapath");
  48. static const struct ath10k_hw_params ath10k_hw_params_list[] = {
  49. {
  50. .id = QCA988X_HW_2_0_VERSION,
  51. .dev_id = QCA988X_2_0_DEVICE_ID,
  52. .name = "qca988x hw2.0",
  53. .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR,
  54. .uart_pin = 7,
  55. .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,
  56. .otp_exe_param = 0,
  57. .channel_counters_freq_hz = 88000,
  58. .max_probe_resp_desc_thres = 0,
  59. .cal_data_len = 2116,
  60. .fw = {
  61. .dir = QCA988X_HW_2_0_FW_DIR,
  62. .board = QCA988X_HW_2_0_BOARD_DATA_FILE,
  63. .board_size = QCA988X_BOARD_DATA_SZ,
  64. .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ,
  65. },
  66. .hw_ops = &qca988x_ops,
  67. .decap_align_bytes = 4,
  68. .spectral_bin_discard = 0,
  69. },
  70. {
  71. .id = QCA9887_HW_1_0_VERSION,
  72. .dev_id = QCA9887_1_0_DEVICE_ID,
  73. .name = "qca9887 hw1.0",
  74. .patch_load_addr = QCA9887_HW_1_0_PATCH_LOAD_ADDR,
  75. .uart_pin = 7,
  76. .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,
  77. .otp_exe_param = 0,
  78. .channel_counters_freq_hz = 88000,
  79. .max_probe_resp_desc_thres = 0,
  80. .cal_data_len = 2116,
  81. .fw = {
  82. .dir = QCA9887_HW_1_0_FW_DIR,
  83. .board = QCA9887_HW_1_0_BOARD_DATA_FILE,
  84. .board_size = QCA9887_BOARD_DATA_SZ,
  85. .board_ext_size = QCA9887_BOARD_EXT_DATA_SZ,
  86. },
  87. .hw_ops = &qca988x_ops,
  88. .decap_align_bytes = 4,
  89. .spectral_bin_discard = 0,
  90. },
  91. {
  92. .id = QCA6174_HW_2_1_VERSION,
  93. .dev_id = QCA6164_2_1_DEVICE_ID,
  94. .name = "qca6164 hw2.1",
  95. .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
  96. .uart_pin = 6,
  97. .otp_exe_param = 0,
  98. .channel_counters_freq_hz = 88000,
  99. .max_probe_resp_desc_thres = 0,
  100. .cal_data_len = 8124,
  101. .fw = {
  102. .dir = QCA6174_HW_2_1_FW_DIR,
  103. .board = QCA6174_HW_2_1_BOARD_DATA_FILE,
  104. .board_size = QCA6174_BOARD_DATA_SZ,
  105. .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
  106. },
  107. .hw_ops = &qca988x_ops,
  108. .decap_align_bytes = 4,
  109. .spectral_bin_discard = 0,
  110. },
  111. {
  112. .id = QCA6174_HW_2_1_VERSION,
  113. .dev_id = QCA6174_2_1_DEVICE_ID,
  114. .name = "qca6174 hw2.1",
  115. .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
  116. .uart_pin = 6,
  117. .otp_exe_param = 0,
  118. .channel_counters_freq_hz = 88000,
  119. .max_probe_resp_desc_thres = 0,
  120. .cal_data_len = 8124,
  121. .fw = {
  122. .dir = QCA6174_HW_2_1_FW_DIR,
  123. .board = QCA6174_HW_2_1_BOARD_DATA_FILE,
  124. .board_size = QCA6174_BOARD_DATA_SZ,
  125. .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
  126. },
  127. .hw_ops = &qca988x_ops,
  128. .decap_align_bytes = 4,
  129. .spectral_bin_discard = 0,
  130. },
  131. {
  132. .id = QCA6174_HW_3_0_VERSION,
  133. .dev_id = QCA6174_2_1_DEVICE_ID,
  134. .name = "qca6174 hw3.0",
  135. .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
  136. .uart_pin = 6,
  137. .otp_exe_param = 0,
  138. .channel_counters_freq_hz = 88000,
  139. .max_probe_resp_desc_thres = 0,
  140. .cal_data_len = 8124,
  141. .fw = {
  142. .dir = QCA6174_HW_3_0_FW_DIR,
  143. .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
  144. .board_size = QCA6174_BOARD_DATA_SZ,
  145. .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
  146. },
  147. .hw_ops = &qca988x_ops,
  148. .decap_align_bytes = 4,
  149. .spectral_bin_discard = 0,
  150. },
  151. {
  152. .id = QCA6174_HW_3_2_VERSION,
  153. .dev_id = QCA6174_2_1_DEVICE_ID,
  154. .name = "qca6174 hw3.2",
  155. .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
  156. .uart_pin = 6,
  157. .otp_exe_param = 0,
  158. .channel_counters_freq_hz = 88000,
  159. .max_probe_resp_desc_thres = 0,
  160. .cal_data_len = 8124,
  161. .fw = {
  162. /* uses same binaries as hw3.0 */
  163. .dir = QCA6174_HW_3_0_FW_DIR,
  164. .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
  165. .board_size = QCA6174_BOARD_DATA_SZ,
  166. .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
  167. },
  168. .hw_ops = &qca6174_ops,
  169. .hw_clk = qca6174_clk,
  170. .target_cpu_freq = 176000000,
  171. .decap_align_bytes = 4,
  172. .spectral_bin_discard = 0,
  173. },
  174. {
  175. .id = QCA99X0_HW_2_0_DEV_VERSION,
  176. .dev_id = QCA99X0_2_0_DEVICE_ID,
  177. .name = "qca99x0 hw2.0",
  178. .patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR,
  179. .uart_pin = 7,
  180. .otp_exe_param = 0x00000700,
  181. .continuous_frag_desc = true,
  182. .cck_rate_map_rev2 = true,
  183. .channel_counters_freq_hz = 150000,
  184. .max_probe_resp_desc_thres = 24,
  185. .tx_chain_mask = 0xf,
  186. .rx_chain_mask = 0xf,
  187. .max_spatial_stream = 4,
  188. .cal_data_len = 12064,
  189. .fw = {
  190. .dir = QCA99X0_HW_2_0_FW_DIR,
  191. .board = QCA99X0_HW_2_0_BOARD_DATA_FILE,
  192. .board_size = QCA99X0_BOARD_DATA_SZ,
  193. .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
  194. },
  195. .sw_decrypt_mcast_mgmt = true,
  196. .hw_ops = &qca99x0_ops,
  197. .decap_align_bytes = 1,
  198. .spectral_bin_discard = 4,
  199. },
  200. {
  201. .id = QCA9984_HW_1_0_DEV_VERSION,
  202. .dev_id = QCA9984_1_0_DEVICE_ID,
  203. .name = "qca9984/qca9994 hw1.0",
  204. .patch_load_addr = QCA9984_HW_1_0_PATCH_LOAD_ADDR,
  205. .uart_pin = 7,
  206. .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,
  207. .otp_exe_param = 0x00000700,
  208. .continuous_frag_desc = true,
  209. .cck_rate_map_rev2 = true,
  210. .channel_counters_freq_hz = 150000,
  211. .max_probe_resp_desc_thres = 24,
  212. .tx_chain_mask = 0xf,
  213. .rx_chain_mask = 0xf,
  214. .max_spatial_stream = 4,
  215. .cal_data_len = 12064,
  216. .fw = {
  217. .dir = QCA9984_HW_1_0_FW_DIR,
  218. .board = QCA9984_HW_1_0_BOARD_DATA_FILE,
  219. .board_size = QCA99X0_BOARD_DATA_SZ,
  220. .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
  221. },
  222. .sw_decrypt_mcast_mgmt = true,
  223. .hw_ops = &qca99x0_ops,
  224. .decap_align_bytes = 1,
  225. .spectral_bin_discard = 12,
  226. },
  227. {
  228. .id = QCA9888_HW_2_0_DEV_VERSION,
  229. .dev_id = QCA9888_2_0_DEVICE_ID,
  230. .name = "qca9888 hw2.0",
  231. .patch_load_addr = QCA9888_HW_2_0_PATCH_LOAD_ADDR,
  232. .uart_pin = 7,
  233. .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,
  234. .otp_exe_param = 0x00000700,
  235. .continuous_frag_desc = true,
  236. .channel_counters_freq_hz = 150000,
  237. .max_probe_resp_desc_thres = 24,
  238. .tx_chain_mask = 3,
  239. .rx_chain_mask = 3,
  240. .max_spatial_stream = 2,
  241. .cal_data_len = 12064,
  242. .fw = {
  243. .dir = QCA9888_HW_2_0_FW_DIR,
  244. .board = QCA9888_HW_2_0_BOARD_DATA_FILE,
  245. .board_size = QCA99X0_BOARD_DATA_SZ,
  246. .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
  247. },
  248. .sw_decrypt_mcast_mgmt = true,
  249. .hw_ops = &qca99x0_ops,
  250. .decap_align_bytes = 1,
  251. .spectral_bin_discard = 12,
  252. },
  253. {
  254. .id = QCA9377_HW_1_0_DEV_VERSION,
  255. .dev_id = QCA9377_1_0_DEVICE_ID,
  256. .name = "qca9377 hw1.0",
  257. .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
  258. .uart_pin = 6,
  259. .otp_exe_param = 0,
  260. .channel_counters_freq_hz = 88000,
  261. .max_probe_resp_desc_thres = 0,
  262. .cal_data_len = 8124,
  263. .fw = {
  264. .dir = QCA9377_HW_1_0_FW_DIR,
  265. .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
  266. .board_size = QCA9377_BOARD_DATA_SZ,
  267. .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
  268. },
  269. .hw_ops = &qca988x_ops,
  270. .decap_align_bytes = 4,
  271. .spectral_bin_discard = 0,
  272. },
  273. {
  274. .id = QCA9377_HW_1_1_DEV_VERSION,
  275. .dev_id = QCA9377_1_0_DEVICE_ID,
  276. .name = "qca9377 hw1.1",
  277. .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
  278. .uart_pin = 6,
  279. .otp_exe_param = 0,
  280. .channel_counters_freq_hz = 88000,
  281. .max_probe_resp_desc_thres = 0,
  282. .cal_data_len = 8124,
  283. .fw = {
  284. .dir = QCA9377_HW_1_0_FW_DIR,
  285. .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
  286. .board_size = QCA9377_BOARD_DATA_SZ,
  287. .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
  288. },
  289. .hw_ops = &qca6174_ops,
  290. .hw_clk = qca6174_clk,
  291. .target_cpu_freq = 176000000,
  292. .decap_align_bytes = 4,
  293. .spectral_bin_discard = 0,
  294. },
  295. {
  296. .id = QCA4019_HW_1_0_DEV_VERSION,
  297. .dev_id = 0,
  298. .name = "qca4019 hw1.0",
  299. .patch_load_addr = QCA4019_HW_1_0_PATCH_LOAD_ADDR,
  300. .uart_pin = 7,
  301. .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,
  302. .otp_exe_param = 0x0010000,
  303. .continuous_frag_desc = true,
  304. .cck_rate_map_rev2 = true,
  305. .channel_counters_freq_hz = 125000,
  306. .max_probe_resp_desc_thres = 24,
  307. .tx_chain_mask = 0x3,
  308. .rx_chain_mask = 0x3,
  309. .max_spatial_stream = 2,
  310. .cal_data_len = 12064,
  311. .fw = {
  312. .dir = QCA4019_HW_1_0_FW_DIR,
  313. .board = QCA4019_HW_1_0_BOARD_DATA_FILE,
  314. .board_size = QCA4019_BOARD_DATA_SZ,
  315. .board_ext_size = QCA4019_BOARD_EXT_DATA_SZ,
  316. },
  317. .sw_decrypt_mcast_mgmt = true,
  318. .hw_ops = &qca99x0_ops,
  319. .decap_align_bytes = 1,
  320. .spectral_bin_discard = 4,
  321. },
  322. };
  323. static const char *const ath10k_core_fw_feature_str[] = {
  324. [ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX] = "wmi-mgmt-rx",
  325. [ATH10K_FW_FEATURE_WMI_10X] = "wmi-10.x",
  326. [ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX] = "has-wmi-mgmt-tx",
  327. [ATH10K_FW_FEATURE_NO_P2P] = "no-p2p",
  328. [ATH10K_FW_FEATURE_WMI_10_2] = "wmi-10.2",
  329. [ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT] = "multi-vif-ps",
  330. [ATH10K_FW_FEATURE_WOWLAN_SUPPORT] = "wowlan",
  331. [ATH10K_FW_FEATURE_IGNORE_OTP_RESULT] = "ignore-otp",
  332. [ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING] = "no-4addr-pad",
  333. [ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT] = "skip-clock-init",
  334. [ATH10K_FW_FEATURE_RAW_MODE_SUPPORT] = "raw-mode",
  335. [ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA] = "adaptive-cca",
  336. [ATH10K_FW_FEATURE_MFP_SUPPORT] = "mfp",
  337. [ATH10K_FW_FEATURE_PEER_FLOW_CONTROL] = "peer-flow-ctrl",
  338. [ATH10K_FW_FEATURE_BTCOEX_PARAM] = "btcoex-param",
  339. [ATH10K_FW_FEATURE_SKIP_NULL_FUNC_WAR] = "skip-null-func-war",
  340. [ATH10K_FW_FEATURE_ALLOWS_MESH_BCAST] = "allows-mesh-bcast",
  341. };
  342. static unsigned int ath10k_core_get_fw_feature_str(char *buf,
  343. size_t buf_len,
  344. enum ath10k_fw_features feat)
  345. {
  346. /* make sure that ath10k_core_fw_feature_str[] gets updated */
  347. BUILD_BUG_ON(ARRAY_SIZE(ath10k_core_fw_feature_str) !=
  348. ATH10K_FW_FEATURE_COUNT);
  349. if (feat >= ARRAY_SIZE(ath10k_core_fw_feature_str) ||
  350. WARN_ON(!ath10k_core_fw_feature_str[feat])) {
  351. return scnprintf(buf, buf_len, "bit%d", feat);
  352. }
  353. return scnprintf(buf, buf_len, "%s", ath10k_core_fw_feature_str[feat]);
  354. }
  355. void ath10k_core_get_fw_features_str(struct ath10k *ar,
  356. char *buf,
  357. size_t buf_len)
  358. {
  359. size_t len = 0;
  360. int i;
  361. for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) {
  362. if (test_bit(i, ar->normal_mode_fw.fw_file.fw_features)) {
  363. if (len > 0)
  364. len += scnprintf(buf + len, buf_len - len, ",");
  365. len += ath10k_core_get_fw_feature_str(buf + len,
  366. buf_len - len,
  367. i);
  368. }
  369. }
  370. }
  371. static void ath10k_send_suspend_complete(struct ath10k *ar)
  372. {
  373. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot suspend complete\n");
  374. complete(&ar->target_suspend);
  375. }
  376. static int ath10k_init_configure_target(struct ath10k *ar)
  377. {
  378. u32 param_host;
  379. int ret;
  380. /* tell target which HTC version it is used*/
  381. ret = ath10k_bmi_write32(ar, hi_app_host_interest,
  382. HTC_PROTOCOL_VERSION);
  383. if (ret) {
  384. ath10k_err(ar, "settings HTC version failed\n");
  385. return ret;
  386. }
  387. /* set the firmware mode to STA/IBSS/AP */
  388. ret = ath10k_bmi_read32(ar, hi_option_flag, &param_host);
  389. if (ret) {
  390. ath10k_err(ar, "setting firmware mode (1/2) failed\n");
  391. return ret;
  392. }
  393. /* TODO following parameters need to be re-visited. */
  394. /* num_device */
  395. param_host |= (1 << HI_OPTION_NUM_DEV_SHIFT);
  396. /* Firmware mode */
  397. /* FIXME: Why FW_MODE_AP ??.*/
  398. param_host |= (HI_OPTION_FW_MODE_AP << HI_OPTION_FW_MODE_SHIFT);
  399. /* mac_addr_method */
  400. param_host |= (1 << HI_OPTION_MAC_ADDR_METHOD_SHIFT);
  401. /* firmware_bridge */
  402. param_host |= (0 << HI_OPTION_FW_BRIDGE_SHIFT);
  403. /* fwsubmode */
  404. param_host |= (0 << HI_OPTION_FW_SUBMODE_SHIFT);
  405. ret = ath10k_bmi_write32(ar, hi_option_flag, param_host);
  406. if (ret) {
  407. ath10k_err(ar, "setting firmware mode (2/2) failed\n");
  408. return ret;
  409. }
  410. /* We do all byte-swapping on the host */
  411. ret = ath10k_bmi_write32(ar, hi_be, 0);
  412. if (ret) {
  413. ath10k_err(ar, "setting host CPU BE mode failed\n");
  414. return ret;
  415. }
  416. /* FW descriptor/Data swap flags */
  417. ret = ath10k_bmi_write32(ar, hi_fw_swap, 0);
  418. if (ret) {
  419. ath10k_err(ar, "setting FW data/desc swap flags failed\n");
  420. return ret;
  421. }
  422. /* Some devices have a special sanity check that verifies the PCI
  423. * Device ID is written to this host interest var. It is known to be
  424. * required to boot QCA6164.
  425. */
  426. ret = ath10k_bmi_write32(ar, hi_hci_uart_pwr_mgmt_params_ext,
  427. ar->dev_id);
  428. if (ret) {
  429. ath10k_err(ar, "failed to set pwr_mgmt_params: %d\n", ret);
  430. return ret;
  431. }
  432. return 0;
  433. }
  434. static const struct firmware *ath10k_fetch_fw_file(struct ath10k *ar,
  435. const char *dir,
  436. const char *file)
  437. {
  438. char filename[100];
  439. const struct firmware *fw;
  440. int ret;
  441. if (file == NULL)
  442. return ERR_PTR(-ENOENT);
  443. if (dir == NULL)
  444. dir = ".";
  445. snprintf(filename, sizeof(filename), "%s/%s", dir, file);
  446. ret = request_firmware_direct(&fw, filename, ar->dev);
  447. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot fw request '%s': %d\n",
  448. filename, ret);
  449. if (ret)
  450. return ERR_PTR(ret);
  451. return fw;
  452. }
  453. static int ath10k_push_board_ext_data(struct ath10k *ar, const void *data,
  454. size_t data_len)
  455. {
  456. u32 board_data_size = ar->hw_params.fw.board_size;
  457. u32 board_ext_data_size = ar->hw_params.fw.board_ext_size;
  458. u32 board_ext_data_addr;
  459. int ret;
  460. ret = ath10k_bmi_read32(ar, hi_board_ext_data, &board_ext_data_addr);
  461. if (ret) {
  462. ath10k_err(ar, "could not read board ext data addr (%d)\n",
  463. ret);
  464. return ret;
  465. }
  466. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  467. "boot push board extended data addr 0x%x\n",
  468. board_ext_data_addr);
  469. if (board_ext_data_addr == 0)
  470. return 0;
  471. if (data_len != (board_data_size + board_ext_data_size)) {
  472. ath10k_err(ar, "invalid board (ext) data sizes %zu != %d+%d\n",
  473. data_len, board_data_size, board_ext_data_size);
  474. return -EINVAL;
  475. }
  476. ret = ath10k_bmi_write_memory(ar, board_ext_data_addr,
  477. data + board_data_size,
  478. board_ext_data_size);
  479. if (ret) {
  480. ath10k_err(ar, "could not write board ext data (%d)\n", ret);
  481. return ret;
  482. }
  483. ret = ath10k_bmi_write32(ar, hi_board_ext_data_config,
  484. (board_ext_data_size << 16) | 1);
  485. if (ret) {
  486. ath10k_err(ar, "could not write board ext data bit (%d)\n",
  487. ret);
  488. return ret;
  489. }
  490. return 0;
  491. }
  492. static int ath10k_download_board_data(struct ath10k *ar, const void *data,
  493. size_t data_len)
  494. {
  495. u32 board_data_size = ar->hw_params.fw.board_size;
  496. u32 address;
  497. int ret;
  498. ret = ath10k_push_board_ext_data(ar, data, data_len);
  499. if (ret) {
  500. ath10k_err(ar, "could not push board ext data (%d)\n", ret);
  501. goto exit;
  502. }
  503. ret = ath10k_bmi_read32(ar, hi_board_data, &address);
  504. if (ret) {
  505. ath10k_err(ar, "could not read board data addr (%d)\n", ret);
  506. goto exit;
  507. }
  508. ret = ath10k_bmi_write_memory(ar, address, data,
  509. min_t(u32, board_data_size,
  510. data_len));
  511. if (ret) {
  512. ath10k_err(ar, "could not write board data (%d)\n", ret);
  513. goto exit;
  514. }
  515. ret = ath10k_bmi_write32(ar, hi_board_data_initialized, 1);
  516. if (ret) {
  517. ath10k_err(ar, "could not write board data bit (%d)\n", ret);
  518. goto exit;
  519. }
  520. exit:
  521. return ret;
  522. }
  523. static int ath10k_download_cal_file(struct ath10k *ar,
  524. const struct firmware *file)
  525. {
  526. int ret;
  527. if (!file)
  528. return -ENOENT;
  529. if (IS_ERR(file))
  530. return PTR_ERR(file);
  531. ret = ath10k_download_board_data(ar, file->data, file->size);
  532. if (ret) {
  533. ath10k_err(ar, "failed to download cal_file data: %d\n", ret);
  534. return ret;
  535. }
  536. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cal file downloaded\n");
  537. return 0;
  538. }
  539. static int ath10k_download_cal_dt(struct ath10k *ar, const char *dt_name)
  540. {
  541. struct device_node *node;
  542. int data_len;
  543. void *data;
  544. int ret;
  545. node = ar->dev->of_node;
  546. if (!node)
  547. /* Device Tree is optional, don't print any warnings if
  548. * there's no node for ath10k.
  549. */
  550. return -ENOENT;
  551. if (!of_get_property(node, dt_name, &data_len)) {
  552. /* The calibration data node is optional */
  553. return -ENOENT;
  554. }
  555. if (data_len != ar->hw_params.cal_data_len) {
  556. ath10k_warn(ar, "invalid calibration data length in DT: %d\n",
  557. data_len);
  558. ret = -EMSGSIZE;
  559. goto out;
  560. }
  561. data = kmalloc(data_len, GFP_KERNEL);
  562. if (!data) {
  563. ret = -ENOMEM;
  564. goto out;
  565. }
  566. ret = of_property_read_u8_array(node, dt_name, data, data_len);
  567. if (ret) {
  568. ath10k_warn(ar, "failed to read calibration data from DT: %d\n",
  569. ret);
  570. goto out_free;
  571. }
  572. ret = ath10k_download_board_data(ar, data, data_len);
  573. if (ret) {
  574. ath10k_warn(ar, "failed to download calibration data from Device Tree: %d\n",
  575. ret);
  576. goto out_free;
  577. }
  578. ret = 0;
  579. out_free:
  580. kfree(data);
  581. out:
  582. return ret;
  583. }
  584. static int ath10k_download_cal_eeprom(struct ath10k *ar)
  585. {
  586. size_t data_len;
  587. void *data = NULL;
  588. int ret;
  589. ret = ath10k_hif_fetch_cal_eeprom(ar, &data, &data_len);
  590. if (ret) {
  591. if (ret != -EOPNOTSUPP)
  592. ath10k_warn(ar, "failed to read calibration data from EEPROM: %d\n",
  593. ret);
  594. goto out_free;
  595. }
  596. ret = ath10k_download_board_data(ar, data, data_len);
  597. if (ret) {
  598. ath10k_warn(ar, "failed to download calibration data from EEPROM: %d\n",
  599. ret);
  600. goto out_free;
  601. }
  602. ret = 0;
  603. out_free:
  604. kfree(data);
  605. return ret;
  606. }
  607. static int ath10k_core_get_board_id_from_otp(struct ath10k *ar)
  608. {
  609. u32 result, address;
  610. u8 board_id, chip_id;
  611. int ret;
  612. address = ar->hw_params.patch_load_addr;
  613. if (!ar->normal_mode_fw.fw_file.otp_data ||
  614. !ar->normal_mode_fw.fw_file.otp_len) {
  615. ath10k_warn(ar,
  616. "failed to retrieve board id because of invalid otp\n");
  617. return -ENODATA;
  618. }
  619. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  620. "boot upload otp to 0x%x len %zd for board id\n",
  621. address, ar->normal_mode_fw.fw_file.otp_len);
  622. ret = ath10k_bmi_fast_download(ar, address,
  623. ar->normal_mode_fw.fw_file.otp_data,
  624. ar->normal_mode_fw.fw_file.otp_len);
  625. if (ret) {
  626. ath10k_err(ar, "could not write otp for board id check: %d\n",
  627. ret);
  628. return ret;
  629. }
  630. ret = ath10k_bmi_execute(ar, address, BMI_PARAM_GET_EEPROM_BOARD_ID,
  631. &result);
  632. if (ret) {
  633. ath10k_err(ar, "could not execute otp for board id check: %d\n",
  634. ret);
  635. return ret;
  636. }
  637. board_id = MS(result, ATH10K_BMI_BOARD_ID_FROM_OTP);
  638. chip_id = MS(result, ATH10K_BMI_CHIP_ID_FROM_OTP);
  639. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  640. "boot get otp board id result 0x%08x board_id %d chip_id %d\n",
  641. result, board_id, chip_id);
  642. if ((result & ATH10K_BMI_BOARD_ID_STATUS_MASK) != 0 ||
  643. (board_id == 0)) {
  644. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  645. "board id does not exist in otp, ignore it\n");
  646. return -EOPNOTSUPP;
  647. }
  648. ar->id.bmi_ids_valid = true;
  649. ar->id.bmi_board_id = board_id;
  650. ar->id.bmi_chip_id = chip_id;
  651. return 0;
  652. }
  653. static void ath10k_core_check_bdfext(const struct dmi_header *hdr, void *data)
  654. {
  655. struct ath10k *ar = data;
  656. const char *bdf_ext;
  657. const char *magic = ATH10K_SMBIOS_BDF_EXT_MAGIC;
  658. u8 bdf_enabled;
  659. int i;
  660. if (hdr->type != ATH10K_SMBIOS_BDF_EXT_TYPE)
  661. return;
  662. if (hdr->length != ATH10K_SMBIOS_BDF_EXT_LENGTH) {
  663. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  664. "wrong smbios bdf ext type length (%d).\n",
  665. hdr->length);
  666. return;
  667. }
  668. bdf_enabled = *((u8 *)hdr + ATH10K_SMBIOS_BDF_EXT_OFFSET);
  669. if (!bdf_enabled) {
  670. ath10k_dbg(ar, ATH10K_DBG_BOOT, "bdf variant name not found.\n");
  671. return;
  672. }
  673. /* Only one string exists (per spec) */
  674. bdf_ext = (char *)hdr + hdr->length;
  675. if (memcmp(bdf_ext, magic, strlen(magic)) != 0) {
  676. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  677. "bdf variant magic does not match.\n");
  678. return;
  679. }
  680. for (i = 0; i < strlen(bdf_ext); i++) {
  681. if (!isascii(bdf_ext[i]) || !isprint(bdf_ext[i])) {
  682. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  683. "bdf variant name contains non ascii chars.\n");
  684. return;
  685. }
  686. }
  687. /* Copy extension name without magic suffix */
  688. if (strscpy(ar->id.bdf_ext, bdf_ext + strlen(magic),
  689. sizeof(ar->id.bdf_ext)) < 0) {
  690. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  691. "bdf variant string is longer than the buffer can accommodate (variant: %s)\n",
  692. bdf_ext);
  693. return;
  694. }
  695. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  696. "found and validated bdf variant smbios_type 0x%x bdf %s\n",
  697. ATH10K_SMBIOS_BDF_EXT_TYPE, bdf_ext);
  698. }
  699. static int ath10k_core_check_smbios(struct ath10k *ar)
  700. {
  701. ar->id.bdf_ext[0] = '\0';
  702. dmi_walk(ath10k_core_check_bdfext, ar);
  703. if (ar->id.bdf_ext[0] == '\0')
  704. return -ENODATA;
  705. return 0;
  706. }
  707. static int ath10k_download_and_run_otp(struct ath10k *ar)
  708. {
  709. u32 result, address = ar->hw_params.patch_load_addr;
  710. u32 bmi_otp_exe_param = ar->hw_params.otp_exe_param;
  711. int ret;
  712. ret = ath10k_download_board_data(ar,
  713. ar->running_fw->board_data,
  714. ar->running_fw->board_len);
  715. if (ret) {
  716. ath10k_err(ar, "failed to download board data: %d\n", ret);
  717. return ret;
  718. }
  719. /* OTP is optional */
  720. if (!ar->running_fw->fw_file.otp_data ||
  721. !ar->running_fw->fw_file.otp_len) {
  722. ath10k_warn(ar, "Not running otp, calibration will be incorrect (otp-data %pK otp_len %zd)!\n",
  723. ar->running_fw->fw_file.otp_data,
  724. ar->running_fw->fw_file.otp_len);
  725. return 0;
  726. }
  727. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot upload otp to 0x%x len %zd\n",
  728. address, ar->running_fw->fw_file.otp_len);
  729. ret = ath10k_bmi_fast_download(ar, address,
  730. ar->running_fw->fw_file.otp_data,
  731. ar->running_fw->fw_file.otp_len);
  732. if (ret) {
  733. ath10k_err(ar, "could not write otp (%d)\n", ret);
  734. return ret;
  735. }
  736. ret = ath10k_bmi_execute(ar, address, bmi_otp_exe_param, &result);
  737. if (ret) {
  738. ath10k_err(ar, "could not execute otp (%d)\n", ret);
  739. return ret;
  740. }
  741. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot otp execute result %d\n", result);
  742. if (!(skip_otp || test_bit(ATH10K_FW_FEATURE_IGNORE_OTP_RESULT,
  743. ar->running_fw->fw_file.fw_features)) &&
  744. result != 0) {
  745. ath10k_err(ar, "otp calibration failed: %d", result);
  746. return -EINVAL;
  747. }
  748. return 0;
  749. }
  750. static int ath10k_download_fw(struct ath10k *ar)
  751. {
  752. u32 address, data_len;
  753. const void *data;
  754. int ret;
  755. address = ar->hw_params.patch_load_addr;
  756. data = ar->running_fw->fw_file.firmware_data;
  757. data_len = ar->running_fw->fw_file.firmware_len;
  758. ret = ath10k_swap_code_seg_configure(ar, &ar->running_fw->fw_file);
  759. if (ret) {
  760. ath10k_err(ar, "failed to configure fw code swap: %d\n",
  761. ret);
  762. return ret;
  763. }
  764. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  765. "boot uploading firmware image %pK len %d\n",
  766. data, data_len);
  767. ret = ath10k_bmi_fast_download(ar, address, data, data_len);
  768. if (ret) {
  769. ath10k_err(ar, "failed to download firmware: %d\n",
  770. ret);
  771. return ret;
  772. }
  773. return ret;
  774. }
  775. static void ath10k_core_free_board_files(struct ath10k *ar)
  776. {
  777. if (!IS_ERR(ar->normal_mode_fw.board))
  778. release_firmware(ar->normal_mode_fw.board);
  779. ar->normal_mode_fw.board = NULL;
  780. ar->normal_mode_fw.board_data = NULL;
  781. ar->normal_mode_fw.board_len = 0;
  782. }
  783. static void ath10k_core_free_firmware_files(struct ath10k *ar)
  784. {
  785. if (!IS_ERR(ar->normal_mode_fw.fw_file.firmware))
  786. release_firmware(ar->normal_mode_fw.fw_file.firmware);
  787. if (!IS_ERR(ar->cal_file))
  788. release_firmware(ar->cal_file);
  789. if (!IS_ERR(ar->pre_cal_file))
  790. release_firmware(ar->pre_cal_file);
  791. ath10k_swap_code_seg_release(ar, &ar->normal_mode_fw.fw_file);
  792. ar->normal_mode_fw.fw_file.otp_data = NULL;
  793. ar->normal_mode_fw.fw_file.otp_len = 0;
  794. ar->normal_mode_fw.fw_file.firmware = NULL;
  795. ar->normal_mode_fw.fw_file.firmware_data = NULL;
  796. ar->normal_mode_fw.fw_file.firmware_len = 0;
  797. ar->cal_file = NULL;
  798. ar->pre_cal_file = NULL;
  799. }
  800. static int ath10k_fetch_cal_file(struct ath10k *ar)
  801. {
  802. char filename[100];
  803. /* pre-cal-<bus>-<id>.bin */
  804. scnprintf(filename, sizeof(filename), "pre-cal-%s-%s.bin",
  805. ath10k_bus_str(ar->hif.bus), dev_name(ar->dev));
  806. ar->pre_cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename);
  807. if (!IS_ERR(ar->pre_cal_file))
  808. goto success;
  809. /* cal-<bus>-<id>.bin */
  810. scnprintf(filename, sizeof(filename), "cal-%s-%s.bin",
  811. ath10k_bus_str(ar->hif.bus), dev_name(ar->dev));
  812. ar->cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename);
  813. if (IS_ERR(ar->cal_file))
  814. /* calibration file is optional, don't print any warnings */
  815. return PTR_ERR(ar->cal_file);
  816. success:
  817. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found calibration file %s/%s\n",
  818. ATH10K_FW_DIR, filename);
  819. return 0;
  820. }
  821. static int ath10k_core_fetch_board_data_api_1(struct ath10k *ar)
  822. {
  823. if (!ar->hw_params.fw.board) {
  824. ath10k_err(ar, "failed to find board file fw entry\n");
  825. return -EINVAL;
  826. }
  827. ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar,
  828. ar->hw_params.fw.dir,
  829. ar->hw_params.fw.board);
  830. if (IS_ERR(ar->normal_mode_fw.board))
  831. return PTR_ERR(ar->normal_mode_fw.board);
  832. ar->normal_mode_fw.board_data = ar->normal_mode_fw.board->data;
  833. ar->normal_mode_fw.board_len = ar->normal_mode_fw.board->size;
  834. return 0;
  835. }
  836. static int ath10k_core_parse_bd_ie_board(struct ath10k *ar,
  837. const void *buf, size_t buf_len,
  838. const char *boardname)
  839. {
  840. const struct ath10k_fw_ie *hdr;
  841. bool name_match_found;
  842. int ret, board_ie_id;
  843. size_t board_ie_len;
  844. const void *board_ie_data;
  845. name_match_found = false;
  846. /* go through ATH10K_BD_IE_BOARD_ elements */
  847. while (buf_len > sizeof(struct ath10k_fw_ie)) {
  848. hdr = buf;
  849. board_ie_id = le32_to_cpu(hdr->id);
  850. board_ie_len = le32_to_cpu(hdr->len);
  851. board_ie_data = hdr->data;
  852. buf_len -= sizeof(*hdr);
  853. buf += sizeof(*hdr);
  854. if (buf_len < ALIGN(board_ie_len, 4)) {
  855. ath10k_err(ar, "invalid ATH10K_BD_IE_BOARD length: %zu < %zu\n",
  856. buf_len, ALIGN(board_ie_len, 4));
  857. ret = -EINVAL;
  858. goto out;
  859. }
  860. switch (board_ie_id) {
  861. case ATH10K_BD_IE_BOARD_NAME:
  862. ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "board name", "",
  863. board_ie_data, board_ie_len);
  864. if (board_ie_len != strlen(boardname))
  865. break;
  866. ret = memcmp(board_ie_data, boardname, strlen(boardname));
  867. if (ret)
  868. break;
  869. name_match_found = true;
  870. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  871. "boot found match for name '%s'",
  872. boardname);
  873. break;
  874. case ATH10K_BD_IE_BOARD_DATA:
  875. if (!name_match_found)
  876. /* no match found */
  877. break;
  878. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  879. "boot found board data for '%s'",
  880. boardname);
  881. ar->normal_mode_fw.board_data = board_ie_data;
  882. ar->normal_mode_fw.board_len = board_ie_len;
  883. ret = 0;
  884. goto out;
  885. default:
  886. ath10k_warn(ar, "unknown ATH10K_BD_IE_BOARD found: %d\n",
  887. board_ie_id);
  888. break;
  889. }
  890. /* jump over the padding */
  891. board_ie_len = ALIGN(board_ie_len, 4);
  892. buf_len -= board_ie_len;
  893. buf += board_ie_len;
  894. }
  895. /* no match found */
  896. ret = -ENOENT;
  897. out:
  898. return ret;
  899. }
  900. static int ath10k_core_fetch_board_data_api_n(struct ath10k *ar,
  901. const char *boardname,
  902. const char *filename)
  903. {
  904. size_t len, magic_len, ie_len;
  905. struct ath10k_fw_ie *hdr;
  906. const u8 *data;
  907. int ret, ie_id;
  908. ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar,
  909. ar->hw_params.fw.dir,
  910. filename);
  911. if (IS_ERR(ar->normal_mode_fw.board))
  912. return PTR_ERR(ar->normal_mode_fw.board);
  913. data = ar->normal_mode_fw.board->data;
  914. len = ar->normal_mode_fw.board->size;
  915. /* magic has extra null byte padded */
  916. magic_len = strlen(ATH10K_BOARD_MAGIC) + 1;
  917. if (len < magic_len) {
  918. ath10k_err(ar, "failed to find magic value in %s/%s, file too short: %zu\n",
  919. ar->hw_params.fw.dir, filename, len);
  920. ret = -EINVAL;
  921. goto err;
  922. }
  923. if (memcmp(data, ATH10K_BOARD_MAGIC, magic_len)) {
  924. ath10k_err(ar, "found invalid board magic\n");
  925. ret = -EINVAL;
  926. goto err;
  927. }
  928. /* magic is padded to 4 bytes */
  929. magic_len = ALIGN(magic_len, 4);
  930. if (len < magic_len) {
  931. ath10k_err(ar, "failed: %s/%s too small to contain board data, len: %zu\n",
  932. ar->hw_params.fw.dir, filename, len);
  933. ret = -EINVAL;
  934. goto err;
  935. }
  936. data += magic_len;
  937. len -= magic_len;
  938. while (len > sizeof(struct ath10k_fw_ie)) {
  939. hdr = (struct ath10k_fw_ie *)data;
  940. ie_id = le32_to_cpu(hdr->id);
  941. ie_len = le32_to_cpu(hdr->len);
  942. len -= sizeof(*hdr);
  943. data = hdr->data;
  944. if (len < ALIGN(ie_len, 4)) {
  945. ath10k_err(ar, "invalid length for board ie_id %d ie_len %zu len %zu\n",
  946. ie_id, ie_len, len);
  947. ret = -EINVAL;
  948. goto err;
  949. }
  950. switch (ie_id) {
  951. case ATH10K_BD_IE_BOARD:
  952. ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len,
  953. boardname);
  954. if (ret == -ENOENT && ar->id.bdf_ext[0] != '\0') {
  955. /* try default bdf if variant was not found */
  956. char *s, *v = ",variant=";
  957. char boardname2[100];
  958. strlcpy(boardname2, boardname,
  959. sizeof(boardname2));
  960. s = strstr(boardname2, v);
  961. if (s)
  962. *s = '\0'; /* strip ",variant=%s" */
  963. ret = ath10k_core_parse_bd_ie_board(ar, data,
  964. ie_len,
  965. boardname2);
  966. }
  967. if (ret == -ENOENT)
  968. /* no match found, continue */
  969. break;
  970. else if (ret)
  971. /* there was an error, bail out */
  972. goto err;
  973. /* board data found */
  974. goto out;
  975. }
  976. /* jump over the padding */
  977. ie_len = ALIGN(ie_len, 4);
  978. len -= ie_len;
  979. data += ie_len;
  980. }
  981. out:
  982. if (!ar->normal_mode_fw.board_data || !ar->normal_mode_fw.board_len) {
  983. ath10k_err(ar,
  984. "failed to fetch board data for %s from %s/%s\n",
  985. boardname, ar->hw_params.fw.dir, filename);
  986. ret = -ENODATA;
  987. goto err;
  988. }
  989. return 0;
  990. err:
  991. ath10k_core_free_board_files(ar);
  992. return ret;
  993. }
  994. static int ath10k_core_create_board_name(struct ath10k *ar, char *name,
  995. size_t name_len)
  996. {
  997. /* strlen(',variant=') + strlen(ar->id.bdf_ext) */
  998. char variant[9 + ATH10K_SMBIOS_BDF_EXT_STR_LENGTH] = { 0 };
  999. if (ar->id.bmi_ids_valid) {
  1000. scnprintf(name, name_len,
  1001. "bus=%s,bmi-chip-id=%d,bmi-board-id=%d",
  1002. ath10k_bus_str(ar->hif.bus),
  1003. ar->id.bmi_chip_id,
  1004. ar->id.bmi_board_id);
  1005. goto out;
  1006. }
  1007. if (ar->id.bdf_ext[0] != '\0')
  1008. scnprintf(variant, sizeof(variant), ",variant=%s",
  1009. ar->id.bdf_ext);
  1010. scnprintf(name, name_len,
  1011. "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x%s",
  1012. ath10k_bus_str(ar->hif.bus),
  1013. ar->id.vendor, ar->id.device,
  1014. ar->id.subsystem_vendor, ar->id.subsystem_device, variant);
  1015. out:
  1016. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using board name '%s'\n", name);
  1017. return 0;
  1018. }
  1019. static int ath10k_core_fetch_board_file(struct ath10k *ar)
  1020. {
  1021. char boardname[100];
  1022. int ret;
  1023. ret = ath10k_core_create_board_name(ar, boardname, sizeof(boardname));
  1024. if (ret) {
  1025. ath10k_err(ar, "failed to create board name: %d", ret);
  1026. return ret;
  1027. }
  1028. ar->bd_api = 2;
  1029. ret = ath10k_core_fetch_board_data_api_n(ar, boardname,
  1030. ATH10K_BOARD_API2_FILE);
  1031. if (!ret)
  1032. goto success;
  1033. ar->bd_api = 1;
  1034. ret = ath10k_core_fetch_board_data_api_1(ar);
  1035. if (ret) {
  1036. ath10k_err(ar, "failed to fetch board-2.bin or board.bin from %s\n",
  1037. ar->hw_params.fw.dir);
  1038. return ret;
  1039. }
  1040. success:
  1041. ath10k_dbg(ar, ATH10K_DBG_BOOT, "using board api %d\n", ar->bd_api);
  1042. return 0;
  1043. }
  1044. int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name,
  1045. struct ath10k_fw_file *fw_file)
  1046. {
  1047. size_t magic_len, len, ie_len;
  1048. int ie_id, i, index, bit, ret;
  1049. struct ath10k_fw_ie *hdr;
  1050. const u8 *data;
  1051. __le32 *timestamp, *version;
  1052. /* first fetch the firmware file (firmware-*.bin) */
  1053. fw_file->firmware = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir,
  1054. name);
  1055. if (IS_ERR(fw_file->firmware))
  1056. return PTR_ERR(fw_file->firmware);
  1057. data = fw_file->firmware->data;
  1058. len = fw_file->firmware->size;
  1059. /* magic also includes the null byte, check that as well */
  1060. magic_len = strlen(ATH10K_FIRMWARE_MAGIC) + 1;
  1061. if (len < magic_len) {
  1062. ath10k_err(ar, "firmware file '%s/%s' too small to contain magic: %zu\n",
  1063. ar->hw_params.fw.dir, name, len);
  1064. ret = -EINVAL;
  1065. goto err;
  1066. }
  1067. if (memcmp(data, ATH10K_FIRMWARE_MAGIC, magic_len) != 0) {
  1068. ath10k_err(ar, "invalid firmware magic\n");
  1069. ret = -EINVAL;
  1070. goto err;
  1071. }
  1072. /* jump over the padding */
  1073. magic_len = ALIGN(magic_len, 4);
  1074. len -= magic_len;
  1075. data += magic_len;
  1076. /* loop elements */
  1077. while (len > sizeof(struct ath10k_fw_ie)) {
  1078. hdr = (struct ath10k_fw_ie *)data;
  1079. ie_id = le32_to_cpu(hdr->id);
  1080. ie_len = le32_to_cpu(hdr->len);
  1081. len -= sizeof(*hdr);
  1082. data += sizeof(*hdr);
  1083. if (len < ie_len) {
  1084. ath10k_err(ar, "invalid length for FW IE %d (%zu < %zu)\n",
  1085. ie_id, len, ie_len);
  1086. ret = -EINVAL;
  1087. goto err;
  1088. }
  1089. switch (ie_id) {
  1090. case ATH10K_FW_IE_FW_VERSION:
  1091. if (ie_len > sizeof(fw_file->fw_version) - 1)
  1092. break;
  1093. memcpy(fw_file->fw_version, data, ie_len);
  1094. fw_file->fw_version[ie_len] = '\0';
  1095. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1096. "found fw version %s\n",
  1097. fw_file->fw_version);
  1098. break;
  1099. case ATH10K_FW_IE_TIMESTAMP:
  1100. if (ie_len != sizeof(u32))
  1101. break;
  1102. timestamp = (__le32 *)data;
  1103. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw timestamp %d\n",
  1104. le32_to_cpup(timestamp));
  1105. break;
  1106. case ATH10K_FW_IE_FEATURES:
  1107. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1108. "found firmware features ie (%zd B)\n",
  1109. ie_len);
  1110. for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) {
  1111. index = i / 8;
  1112. bit = i % 8;
  1113. if (index == ie_len)
  1114. break;
  1115. if (data[index] & (1 << bit)) {
  1116. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1117. "Enabling feature bit: %i\n",
  1118. i);
  1119. __set_bit(i, fw_file->fw_features);
  1120. }
  1121. }
  1122. ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "features", "",
  1123. fw_file->fw_features,
  1124. sizeof(fw_file->fw_features));
  1125. break;
  1126. case ATH10K_FW_IE_FW_IMAGE:
  1127. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1128. "found fw image ie (%zd B)\n",
  1129. ie_len);
  1130. fw_file->firmware_data = data;
  1131. fw_file->firmware_len = ie_len;
  1132. break;
  1133. case ATH10K_FW_IE_OTP_IMAGE:
  1134. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1135. "found otp image ie (%zd B)\n",
  1136. ie_len);
  1137. fw_file->otp_data = data;
  1138. fw_file->otp_len = ie_len;
  1139. break;
  1140. case ATH10K_FW_IE_WMI_OP_VERSION:
  1141. if (ie_len != sizeof(u32))
  1142. break;
  1143. version = (__le32 *)data;
  1144. fw_file->wmi_op_version = le32_to_cpup(version);
  1145. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie wmi op version %d\n",
  1146. fw_file->wmi_op_version);
  1147. break;
  1148. case ATH10K_FW_IE_HTT_OP_VERSION:
  1149. if (ie_len != sizeof(u32))
  1150. break;
  1151. version = (__le32 *)data;
  1152. fw_file->htt_op_version = le32_to_cpup(version);
  1153. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie htt op version %d\n",
  1154. fw_file->htt_op_version);
  1155. break;
  1156. case ATH10K_FW_IE_FW_CODE_SWAP_IMAGE:
  1157. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1158. "found fw code swap image ie (%zd B)\n",
  1159. ie_len);
  1160. fw_file->codeswap_data = data;
  1161. fw_file->codeswap_len = ie_len;
  1162. break;
  1163. default:
  1164. ath10k_warn(ar, "Unknown FW IE: %u\n",
  1165. le32_to_cpu(hdr->id));
  1166. break;
  1167. }
  1168. /* jump over the padding */
  1169. ie_len = ALIGN(ie_len, 4);
  1170. len -= ie_len;
  1171. data += ie_len;
  1172. }
  1173. if (!fw_file->firmware_data ||
  1174. !fw_file->firmware_len) {
  1175. ath10k_warn(ar, "No ATH10K_FW_IE_FW_IMAGE found from '%s/%s', skipping\n",
  1176. ar->hw_params.fw.dir, name);
  1177. ret = -ENOMEDIUM;
  1178. goto err;
  1179. }
  1180. return 0;
  1181. err:
  1182. ath10k_core_free_firmware_files(ar);
  1183. return ret;
  1184. }
  1185. static void ath10k_core_get_fw_name(struct ath10k *ar, char *fw_name,
  1186. size_t fw_name_len, int fw_api)
  1187. {
  1188. scnprintf(fw_name, fw_name_len, "%s-%d.bin", ATH10K_FW_FILE_BASE, fw_api);
  1189. }
  1190. static int ath10k_core_fetch_firmware_files(struct ath10k *ar)
  1191. {
  1192. int ret, i;
  1193. char fw_name[100];
  1194. /* calibration file is optional, don't check for any errors */
  1195. ath10k_fetch_cal_file(ar);
  1196. for (i = ATH10K_FW_API_MAX; i >= ATH10K_FW_API_MIN; i--) {
  1197. ar->fw_api = i;
  1198. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n",
  1199. ar->fw_api);
  1200. ath10k_core_get_fw_name(ar, fw_name, sizeof(fw_name), ar->fw_api);
  1201. ret = ath10k_core_fetch_firmware_api_n(ar, fw_name,
  1202. &ar->normal_mode_fw.fw_file);
  1203. if (!ret)
  1204. goto success;
  1205. }
  1206. /* we end up here if we couldn't fetch any firmware */
  1207. ath10k_err(ar, "Failed to find firmware-N.bin (N between %d and %d) from %s: %d",
  1208. ATH10K_FW_API_MIN, ATH10K_FW_API_MAX, ar->hw_params.fw.dir,
  1209. ret);
  1210. return ret;
  1211. success:
  1212. ath10k_dbg(ar, ATH10K_DBG_BOOT, "using fw api %d\n", ar->fw_api);
  1213. return 0;
  1214. }
  1215. static int ath10k_core_pre_cal_download(struct ath10k *ar)
  1216. {
  1217. int ret;
  1218. ret = ath10k_download_cal_file(ar, ar->pre_cal_file);
  1219. if (ret == 0) {
  1220. ar->cal_mode = ATH10K_PRE_CAL_MODE_FILE;
  1221. goto success;
  1222. }
  1223. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1224. "boot did not find a pre calibration file, try DT next: %d\n",
  1225. ret);
  1226. ret = ath10k_download_cal_dt(ar, "qcom,ath10k-pre-calibration-data");
  1227. if (ret) {
  1228. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1229. "unable to load pre cal data from DT: %d\n", ret);
  1230. return ret;
  1231. }
  1232. ar->cal_mode = ATH10K_PRE_CAL_MODE_DT;
  1233. success:
  1234. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n",
  1235. ath10k_cal_mode_str(ar->cal_mode));
  1236. return 0;
  1237. }
  1238. static int ath10k_core_pre_cal_config(struct ath10k *ar)
  1239. {
  1240. int ret;
  1241. ret = ath10k_core_pre_cal_download(ar);
  1242. if (ret) {
  1243. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1244. "failed to load pre cal data: %d\n", ret);
  1245. return ret;
  1246. }
  1247. ret = ath10k_core_get_board_id_from_otp(ar);
  1248. if (ret) {
  1249. ath10k_err(ar, "failed to get board id: %d\n", ret);
  1250. return ret;
  1251. }
  1252. ret = ath10k_download_and_run_otp(ar);
  1253. if (ret) {
  1254. ath10k_err(ar, "failed to run otp: %d\n", ret);
  1255. return ret;
  1256. }
  1257. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1258. "pre cal configuration done successfully\n");
  1259. return 0;
  1260. }
  1261. static int ath10k_download_cal_data(struct ath10k *ar)
  1262. {
  1263. int ret;
  1264. ret = ath10k_core_pre_cal_config(ar);
  1265. if (ret == 0)
  1266. return 0;
  1267. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1268. "pre cal download procedure failed, try cal file: %d\n",
  1269. ret);
  1270. ret = ath10k_download_cal_file(ar, ar->cal_file);
  1271. if (ret == 0) {
  1272. ar->cal_mode = ATH10K_CAL_MODE_FILE;
  1273. goto done;
  1274. }
  1275. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1276. "boot did not find a calibration file, try DT next: %d\n",
  1277. ret);
  1278. ret = ath10k_download_cal_dt(ar, "qcom,ath10k-calibration-data");
  1279. if (ret == 0) {
  1280. ar->cal_mode = ATH10K_CAL_MODE_DT;
  1281. goto done;
  1282. }
  1283. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1284. "boot did not find DT entry, try target EEPROM next: %d\n",
  1285. ret);
  1286. ret = ath10k_download_cal_eeprom(ar);
  1287. if (ret == 0) {
  1288. ar->cal_mode = ATH10K_CAL_MODE_EEPROM;
  1289. goto done;
  1290. }
  1291. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1292. "boot did not find target EEPROM entry, try OTP next: %d\n",
  1293. ret);
  1294. ret = ath10k_download_and_run_otp(ar);
  1295. if (ret) {
  1296. ath10k_err(ar, "failed to run otp: %d\n", ret);
  1297. return ret;
  1298. }
  1299. ar->cal_mode = ATH10K_CAL_MODE_OTP;
  1300. done:
  1301. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n",
  1302. ath10k_cal_mode_str(ar->cal_mode));
  1303. return 0;
  1304. }
  1305. static int ath10k_init_uart(struct ath10k *ar)
  1306. {
  1307. int ret;
  1308. /*
  1309. * Explicitly setting UART prints to zero as target turns it on
  1310. * based on scratch registers.
  1311. */
  1312. ret = ath10k_bmi_write32(ar, hi_serial_enable, 0);
  1313. if (ret) {
  1314. ath10k_warn(ar, "could not disable UART prints (%d)\n", ret);
  1315. return ret;
  1316. }
  1317. if (!uart_print)
  1318. return 0;
  1319. ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, ar->hw_params.uart_pin);
  1320. if (ret) {
  1321. ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
  1322. return ret;
  1323. }
  1324. ret = ath10k_bmi_write32(ar, hi_serial_enable, 1);
  1325. if (ret) {
  1326. ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
  1327. return ret;
  1328. }
  1329. /* Set the UART baud rate to 19200. */
  1330. ret = ath10k_bmi_write32(ar, hi_desired_baud_rate, 19200);
  1331. if (ret) {
  1332. ath10k_warn(ar, "could not set the baud rate (%d)\n", ret);
  1333. return ret;
  1334. }
  1335. ath10k_info(ar, "UART prints enabled\n");
  1336. return 0;
  1337. }
  1338. static int ath10k_init_hw_params(struct ath10k *ar)
  1339. {
  1340. const struct ath10k_hw_params *uninitialized_var(hw_params);
  1341. int i;
  1342. for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) {
  1343. hw_params = &ath10k_hw_params_list[i];
  1344. if (hw_params->id == ar->target_version &&
  1345. hw_params->dev_id == ar->dev_id)
  1346. break;
  1347. }
  1348. if (i == ARRAY_SIZE(ath10k_hw_params_list)) {
  1349. ath10k_err(ar, "Unsupported hardware version: 0x%x\n",
  1350. ar->target_version);
  1351. return -EINVAL;
  1352. }
  1353. ar->hw_params = *hw_params;
  1354. ath10k_dbg(ar, ATH10K_DBG_BOOT, "Hardware name %s version 0x%x\n",
  1355. ar->hw_params.name, ar->target_version);
  1356. return 0;
  1357. }
  1358. static void ath10k_core_restart(struct work_struct *work)
  1359. {
  1360. struct ath10k *ar = container_of(work, struct ath10k, restart_work);
  1361. int ret;
  1362. set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
  1363. /* Place a barrier to make sure the compiler doesn't reorder
  1364. * CRASH_FLUSH and calling other functions.
  1365. */
  1366. barrier();
  1367. ieee80211_stop_queues(ar->hw);
  1368. ath10k_drain_tx(ar);
  1369. complete(&ar->scan.started);
  1370. complete(&ar->scan.completed);
  1371. complete(&ar->scan.on_channel);
  1372. complete(&ar->offchan_tx_completed);
  1373. complete(&ar->install_key_done);
  1374. complete(&ar->vdev_setup_done);
  1375. complete(&ar->thermal.wmi_sync);
  1376. complete(&ar->bss_survey_done);
  1377. wake_up(&ar->htt.empty_tx_wq);
  1378. wake_up(&ar->wmi.tx_credits_wq);
  1379. wake_up(&ar->peer_mapping_wq);
  1380. /* TODO: We can have one instance of cancelling coverage_class_work by
  1381. * moving it to ath10k_halt(), so that both stop() and restart() would
  1382. * call that but it takes conf_mutex() and if we call cancel_work_sync()
  1383. * with conf_mutex it will deadlock.
  1384. */
  1385. cancel_work_sync(&ar->set_coverage_class_work);
  1386. mutex_lock(&ar->conf_mutex);
  1387. switch (ar->state) {
  1388. case ATH10K_STATE_ON:
  1389. ar->state = ATH10K_STATE_RESTARTING;
  1390. ath10k_halt(ar);
  1391. ath10k_scan_finish(ar);
  1392. ieee80211_restart_hw(ar->hw);
  1393. break;
  1394. case ATH10K_STATE_OFF:
  1395. /* this can happen if driver is being unloaded
  1396. * or if the crash happens during FW probing
  1397. */
  1398. ath10k_warn(ar, "cannot restart a device that hasn't been started\n");
  1399. break;
  1400. case ATH10K_STATE_RESTARTING:
  1401. /* hw restart might be requested from multiple places */
  1402. break;
  1403. case ATH10K_STATE_RESTARTED:
  1404. ar->state = ATH10K_STATE_WEDGED;
  1405. /* fall through */
  1406. case ATH10K_STATE_WEDGED:
  1407. ath10k_warn(ar, "device is wedged, will not restart\n");
  1408. break;
  1409. case ATH10K_STATE_UTF:
  1410. ath10k_warn(ar, "firmware restart in UTF mode not supported\n");
  1411. break;
  1412. }
  1413. mutex_unlock(&ar->conf_mutex);
  1414. ret = ath10k_debug_fw_devcoredump(ar);
  1415. if (ret)
  1416. ath10k_warn(ar, "failed to send firmware crash dump via devcoredump: %d",
  1417. ret);
  1418. }
  1419. static void ath10k_core_set_coverage_class_work(struct work_struct *work)
  1420. {
  1421. struct ath10k *ar = container_of(work, struct ath10k,
  1422. set_coverage_class_work);
  1423. if (ar->hw_params.hw_ops->set_coverage_class)
  1424. ar->hw_params.hw_ops->set_coverage_class(ar, -1);
  1425. }
  1426. static int ath10k_core_init_firmware_features(struct ath10k *ar)
  1427. {
  1428. struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file;
  1429. if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, fw_file->fw_features) &&
  1430. !test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) {
  1431. ath10k_err(ar, "feature bits corrupted: 10.2 feature requires 10.x feature to be set as well");
  1432. return -EINVAL;
  1433. }
  1434. if (fw_file->wmi_op_version >= ATH10K_FW_WMI_OP_VERSION_MAX) {
  1435. ath10k_err(ar, "unsupported WMI OP version (max %d): %d\n",
  1436. ATH10K_FW_WMI_OP_VERSION_MAX, fw_file->wmi_op_version);
  1437. return -EINVAL;
  1438. }
  1439. ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_NATIVE_WIFI;
  1440. switch (ath10k_cryptmode_param) {
  1441. case ATH10K_CRYPT_MODE_HW:
  1442. clear_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
  1443. clear_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags);
  1444. break;
  1445. case ATH10K_CRYPT_MODE_SW:
  1446. if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT,
  1447. fw_file->fw_features)) {
  1448. ath10k_err(ar, "cryptmode > 0 requires raw mode support from firmware");
  1449. return -EINVAL;
  1450. }
  1451. set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
  1452. set_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags);
  1453. break;
  1454. default:
  1455. ath10k_info(ar, "invalid cryptmode: %d\n",
  1456. ath10k_cryptmode_param);
  1457. return -EINVAL;
  1458. }
  1459. ar->htt.max_num_amsdu = ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT;
  1460. ar->htt.max_num_ampdu = ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT;
  1461. if (rawmode) {
  1462. if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT,
  1463. fw_file->fw_features)) {
  1464. ath10k_err(ar, "rawmode = 1 requires support from firmware");
  1465. return -EINVAL;
  1466. }
  1467. set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
  1468. }
  1469. if (test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) {
  1470. ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_RAW;
  1471. /* Workaround:
  1472. *
  1473. * Firmware A-MSDU aggregation breaks with RAW Tx encap mode
  1474. * and causes enormous performance issues (malformed frames,
  1475. * etc).
  1476. *
  1477. * Disabling A-MSDU makes RAW mode stable with heavy traffic
  1478. * albeit a bit slower compared to regular operation.
  1479. */
  1480. ar->htt.max_num_amsdu = 1;
  1481. }
  1482. /* Backwards compatibility for firmwares without
  1483. * ATH10K_FW_IE_WMI_OP_VERSION.
  1484. */
  1485. if (fw_file->wmi_op_version == ATH10K_FW_WMI_OP_VERSION_UNSET) {
  1486. if (test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) {
  1487. if (test_bit(ATH10K_FW_FEATURE_WMI_10_2,
  1488. fw_file->fw_features))
  1489. fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_2;
  1490. else
  1491. fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_1;
  1492. } else {
  1493. fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_MAIN;
  1494. }
  1495. }
  1496. switch (fw_file->wmi_op_version) {
  1497. case ATH10K_FW_WMI_OP_VERSION_MAIN:
  1498. ar->max_num_peers = TARGET_NUM_PEERS;
  1499. ar->max_num_stations = TARGET_NUM_STATIONS;
  1500. ar->max_num_vdevs = TARGET_NUM_VDEVS;
  1501. ar->htt.max_num_pending_tx = TARGET_NUM_MSDU_DESC;
  1502. ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV |
  1503. WMI_STAT_PEER;
  1504. ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
  1505. break;
  1506. case ATH10K_FW_WMI_OP_VERSION_10_1:
  1507. case ATH10K_FW_WMI_OP_VERSION_10_2:
  1508. case ATH10K_FW_WMI_OP_VERSION_10_2_4:
  1509. if (ath10k_peer_stats_enabled(ar)) {
  1510. ar->max_num_peers = TARGET_10X_TX_STATS_NUM_PEERS;
  1511. ar->max_num_stations = TARGET_10X_TX_STATS_NUM_STATIONS;
  1512. } else {
  1513. ar->max_num_peers = TARGET_10X_NUM_PEERS;
  1514. ar->max_num_stations = TARGET_10X_NUM_STATIONS;
  1515. }
  1516. ar->max_num_vdevs = TARGET_10X_NUM_VDEVS;
  1517. ar->htt.max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC;
  1518. ar->fw_stats_req_mask = WMI_STAT_PEER;
  1519. ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
  1520. break;
  1521. case ATH10K_FW_WMI_OP_VERSION_TLV:
  1522. ar->max_num_peers = TARGET_TLV_NUM_PEERS;
  1523. ar->max_num_stations = TARGET_TLV_NUM_STATIONS;
  1524. ar->max_num_vdevs = TARGET_TLV_NUM_VDEVS;
  1525. ar->max_num_tdls_vdevs = TARGET_TLV_NUM_TDLS_VDEVS;
  1526. ar->htt.max_num_pending_tx = TARGET_TLV_NUM_MSDU_DESC;
  1527. ar->wow.max_num_patterns = TARGET_TLV_NUM_WOW_PATTERNS;
  1528. ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV |
  1529. WMI_STAT_PEER;
  1530. ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
  1531. break;
  1532. case ATH10K_FW_WMI_OP_VERSION_10_4:
  1533. ar->max_num_peers = TARGET_10_4_NUM_PEERS;
  1534. ar->max_num_stations = TARGET_10_4_NUM_STATIONS;
  1535. ar->num_active_peers = TARGET_10_4_ACTIVE_PEERS;
  1536. ar->max_num_vdevs = TARGET_10_4_NUM_VDEVS;
  1537. ar->num_tids = TARGET_10_4_TGT_NUM_TIDS;
  1538. ar->fw_stats_req_mask = WMI_10_4_STAT_PEER |
  1539. WMI_10_4_STAT_PEER_EXTD;
  1540. ar->max_spatial_stream = ar->hw_params.max_spatial_stream;
  1541. if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL,
  1542. fw_file->fw_features))
  1543. ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC_PFC;
  1544. else
  1545. ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC;
  1546. break;
  1547. case ATH10K_FW_WMI_OP_VERSION_UNSET:
  1548. case ATH10K_FW_WMI_OP_VERSION_MAX:
  1549. WARN_ON(1);
  1550. return -EINVAL;
  1551. }
  1552. /* Backwards compatibility for firmwares without
  1553. * ATH10K_FW_IE_HTT_OP_VERSION.
  1554. */
  1555. if (fw_file->htt_op_version == ATH10K_FW_HTT_OP_VERSION_UNSET) {
  1556. switch (fw_file->wmi_op_version) {
  1557. case ATH10K_FW_WMI_OP_VERSION_MAIN:
  1558. fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_MAIN;
  1559. break;
  1560. case ATH10K_FW_WMI_OP_VERSION_10_1:
  1561. case ATH10K_FW_WMI_OP_VERSION_10_2:
  1562. case ATH10K_FW_WMI_OP_VERSION_10_2_4:
  1563. fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_10_1;
  1564. break;
  1565. case ATH10K_FW_WMI_OP_VERSION_TLV:
  1566. fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_TLV;
  1567. break;
  1568. case ATH10K_FW_WMI_OP_VERSION_10_4:
  1569. case ATH10K_FW_WMI_OP_VERSION_UNSET:
  1570. case ATH10K_FW_WMI_OP_VERSION_MAX:
  1571. ath10k_err(ar, "htt op version not found from fw meta data");
  1572. return -EINVAL;
  1573. }
  1574. }
  1575. return 0;
  1576. }
  1577. static int ath10k_core_reset_rx_filter(struct ath10k *ar)
  1578. {
  1579. int ret;
  1580. int vdev_id;
  1581. int vdev_type;
  1582. int vdev_subtype;
  1583. const u8 *vdev_addr;
  1584. vdev_id = 0;
  1585. vdev_type = WMI_VDEV_TYPE_STA;
  1586. vdev_subtype = ath10k_wmi_get_vdev_subtype(ar, WMI_VDEV_SUBTYPE_NONE);
  1587. vdev_addr = ar->mac_addr;
  1588. ret = ath10k_wmi_vdev_create(ar, vdev_id, vdev_type, vdev_subtype,
  1589. vdev_addr);
  1590. if (ret) {
  1591. ath10k_err(ar, "failed to create dummy vdev: %d\n", ret);
  1592. return ret;
  1593. }
  1594. ret = ath10k_wmi_vdev_delete(ar, vdev_id);
  1595. if (ret) {
  1596. ath10k_err(ar, "failed to delete dummy vdev: %d\n", ret);
  1597. return ret;
  1598. }
  1599. /* WMI and HTT may use separate HIF pipes and are not guaranteed to be
  1600. * serialized properly implicitly.
  1601. *
  1602. * Moreover (most) WMI commands have no explicit acknowledges. It is
  1603. * possible to infer it implicitly by poking firmware with echo
  1604. * command - getting a reply means all preceding comments have been
  1605. * (mostly) processed.
  1606. *
  1607. * In case of vdev create/delete this is sufficient.
  1608. *
  1609. * Without this it's possible to end up with a race when HTT Rx ring is
  1610. * started before vdev create/delete hack is complete allowing a short
  1611. * window of opportunity to receive (and Tx ACK) a bunch of frames.
  1612. */
  1613. ret = ath10k_wmi_barrier(ar);
  1614. if (ret) {
  1615. ath10k_err(ar, "failed to ping firmware: %d\n", ret);
  1616. return ret;
  1617. }
  1618. return 0;
  1619. }
  1620. int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode,
  1621. const struct ath10k_fw_components *fw)
  1622. {
  1623. int status;
  1624. u32 val;
  1625. lockdep_assert_held(&ar->conf_mutex);
  1626. clear_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
  1627. ar->running_fw = fw;
  1628. ath10k_bmi_start(ar);
  1629. if (ath10k_init_configure_target(ar)) {
  1630. status = -EINVAL;
  1631. goto err;
  1632. }
  1633. status = ath10k_download_cal_data(ar);
  1634. if (status)
  1635. goto err;
  1636. /* Some of of qca988x solutions are having global reset issue
  1637. * during target initialization. Bypassing PLL setting before
  1638. * downloading firmware and letting the SoC run on REF_CLK is
  1639. * fixing the problem. Corresponding firmware change is also needed
  1640. * to set the clock source once the target is initialized.
  1641. */
  1642. if (test_bit(ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT,
  1643. ar->running_fw->fw_file.fw_features)) {
  1644. status = ath10k_bmi_write32(ar, hi_skip_clock_init, 1);
  1645. if (status) {
  1646. ath10k_err(ar, "could not write to skip_clock_init: %d\n",
  1647. status);
  1648. goto err;
  1649. }
  1650. }
  1651. status = ath10k_download_fw(ar);
  1652. if (status)
  1653. goto err;
  1654. status = ath10k_init_uart(ar);
  1655. if (status)
  1656. goto err;
  1657. ar->htc.htc_ops.target_send_suspend_complete =
  1658. ath10k_send_suspend_complete;
  1659. status = ath10k_htc_init(ar);
  1660. if (status) {
  1661. ath10k_err(ar, "could not init HTC (%d)\n", status);
  1662. goto err;
  1663. }
  1664. status = ath10k_bmi_done(ar);
  1665. if (status)
  1666. goto err;
  1667. status = ath10k_wmi_attach(ar);
  1668. if (status) {
  1669. ath10k_err(ar, "WMI attach failed: %d\n", status);
  1670. goto err;
  1671. }
  1672. status = ath10k_htt_init(ar);
  1673. if (status) {
  1674. ath10k_err(ar, "failed to init htt: %d\n", status);
  1675. goto err_wmi_detach;
  1676. }
  1677. status = ath10k_htt_tx_start(&ar->htt);
  1678. if (status) {
  1679. ath10k_err(ar, "failed to alloc htt tx: %d\n", status);
  1680. goto err_wmi_detach;
  1681. }
  1682. status = ath10k_htt_rx_alloc(&ar->htt);
  1683. if (status) {
  1684. ath10k_err(ar, "failed to alloc htt rx: %d\n", status);
  1685. goto err_htt_tx_detach;
  1686. }
  1687. status = ath10k_hif_start(ar);
  1688. if (status) {
  1689. ath10k_err(ar, "could not start HIF: %d\n", status);
  1690. goto err_htt_rx_detach;
  1691. }
  1692. status = ath10k_htc_wait_target(&ar->htc);
  1693. if (status) {
  1694. ath10k_err(ar, "failed to connect to HTC: %d\n", status);
  1695. goto err_hif_stop;
  1696. }
  1697. if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
  1698. status = ath10k_htt_connect(&ar->htt);
  1699. if (status) {
  1700. ath10k_err(ar, "failed to connect htt (%d)\n", status);
  1701. goto err_hif_stop;
  1702. }
  1703. }
  1704. status = ath10k_wmi_connect(ar);
  1705. if (status) {
  1706. ath10k_err(ar, "could not connect wmi: %d\n", status);
  1707. goto err_hif_stop;
  1708. }
  1709. status = ath10k_htc_start(&ar->htc);
  1710. if (status) {
  1711. ath10k_err(ar, "failed to start htc: %d\n", status);
  1712. goto err_hif_stop;
  1713. }
  1714. if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
  1715. status = ath10k_wmi_wait_for_service_ready(ar);
  1716. if (status) {
  1717. ath10k_warn(ar, "wmi service ready event not received");
  1718. goto err_hif_stop;
  1719. }
  1720. }
  1721. ath10k_dbg(ar, ATH10K_DBG_BOOT, "firmware %s booted\n",
  1722. ar->hw->wiphy->fw_version);
  1723. if (test_bit(WMI_SERVICE_EXT_RES_CFG_SUPPORT, ar->wmi.svc_map) &&
  1724. mode == ATH10K_FIRMWARE_MODE_NORMAL) {
  1725. val = 0;
  1726. if (ath10k_peer_stats_enabled(ar))
  1727. val = WMI_10_4_PEER_STATS;
  1728. if (test_bit(WMI_SERVICE_BSS_CHANNEL_INFO_64, ar->wmi.svc_map))
  1729. val |= WMI_10_4_BSS_CHANNEL_INFO_64;
  1730. /* 10.4 firmware supports BT-Coex without reloading firmware
  1731. * via pdev param. To support Bluetooth coexistence pdev param,
  1732. * WMI_COEX_GPIO_SUPPORT of extended resource config should be
  1733. * enabled always.
  1734. */
  1735. if (test_bit(WMI_SERVICE_COEX_GPIO, ar->wmi.svc_map) &&
  1736. test_bit(ATH10K_FW_FEATURE_BTCOEX_PARAM,
  1737. ar->running_fw->fw_file.fw_features))
  1738. val |= WMI_10_4_COEX_GPIO_SUPPORT;
  1739. status = ath10k_mac_ext_resource_config(ar, val);
  1740. if (status) {
  1741. ath10k_err(ar,
  1742. "failed to send ext resource cfg command : %d\n",
  1743. status);
  1744. goto err_hif_stop;
  1745. }
  1746. }
  1747. status = ath10k_wmi_cmd_init(ar);
  1748. if (status) {
  1749. ath10k_err(ar, "could not send WMI init command (%d)\n",
  1750. status);
  1751. goto err_hif_stop;
  1752. }
  1753. status = ath10k_wmi_wait_for_unified_ready(ar);
  1754. if (status) {
  1755. ath10k_err(ar, "wmi unified ready event not received\n");
  1756. goto err_hif_stop;
  1757. }
  1758. /* Some firmware revisions do not properly set up hardware rx filter
  1759. * registers.
  1760. *
  1761. * A known example from QCA9880 and 10.2.4 is that MAC_PCU_ADDR1_MASK
  1762. * is filled with 0s instead of 1s allowing HW to respond with ACKs to
  1763. * any frames that matches MAC_PCU_RX_FILTER which is also
  1764. * misconfigured to accept anything.
  1765. *
  1766. * The ADDR1 is programmed using internal firmware structure field and
  1767. * can't be (easily/sanely) reached from the driver explicitly. It is
  1768. * possible to implicitly make it correct by creating a dummy vdev and
  1769. * then deleting it.
  1770. */
  1771. if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
  1772. status = ath10k_core_reset_rx_filter(ar);
  1773. if (status) {
  1774. ath10k_err(ar,
  1775. "failed to reset rx filter: %d\n", status);
  1776. goto err_hif_stop;
  1777. }
  1778. }
  1779. /* If firmware indicates Full Rx Reorder support it must be used in a
  1780. * slightly different manner. Let HTT code know.
  1781. */
  1782. ar->htt.rx_ring.in_ord_rx = !!(test_bit(WMI_SERVICE_RX_FULL_REORDER,
  1783. ar->wmi.svc_map));
  1784. status = ath10k_htt_rx_ring_refill(ar);
  1785. if (status) {
  1786. ath10k_err(ar, "failed to refill htt rx ring: %d\n", status);
  1787. goto err_hif_stop;
  1788. }
  1789. if (ar->max_num_vdevs >= 64)
  1790. ar->free_vdev_map = 0xFFFFFFFFFFFFFFFFLL;
  1791. else
  1792. ar->free_vdev_map = (1LL << ar->max_num_vdevs) - 1;
  1793. INIT_LIST_HEAD(&ar->arvifs);
  1794. /* we don't care about HTT in UTF mode */
  1795. if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
  1796. status = ath10k_htt_setup(&ar->htt);
  1797. if (status) {
  1798. ath10k_err(ar, "failed to setup htt: %d\n", status);
  1799. goto err_hif_stop;
  1800. }
  1801. }
  1802. status = ath10k_debug_start(ar);
  1803. if (status)
  1804. goto err_hif_stop;
  1805. return 0;
  1806. err_hif_stop:
  1807. ath10k_hif_stop(ar);
  1808. err_htt_rx_detach:
  1809. ath10k_htt_rx_free(&ar->htt);
  1810. err_htt_tx_detach:
  1811. ath10k_htt_tx_free(&ar->htt);
  1812. err_wmi_detach:
  1813. ath10k_wmi_detach(ar);
  1814. err:
  1815. return status;
  1816. }
  1817. EXPORT_SYMBOL(ath10k_core_start);
  1818. int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt)
  1819. {
  1820. int ret;
  1821. unsigned long time_left;
  1822. reinit_completion(&ar->target_suspend);
  1823. ret = ath10k_wmi_pdev_suspend_target(ar, suspend_opt);
  1824. if (ret) {
  1825. ath10k_warn(ar, "could not suspend target (%d)\n", ret);
  1826. return ret;
  1827. }
  1828. time_left = wait_for_completion_timeout(&ar->target_suspend, 1 * HZ);
  1829. if (!time_left) {
  1830. ath10k_warn(ar, "suspend timed out - target pause event never came\n");
  1831. return -ETIMEDOUT;
  1832. }
  1833. return 0;
  1834. }
  1835. void ath10k_core_stop(struct ath10k *ar)
  1836. {
  1837. lockdep_assert_held(&ar->conf_mutex);
  1838. ath10k_debug_stop(ar);
  1839. /* try to suspend target */
  1840. if (ar->state != ATH10K_STATE_RESTARTING &&
  1841. ar->state != ATH10K_STATE_UTF)
  1842. ath10k_wait_for_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR);
  1843. ath10k_hif_stop(ar);
  1844. ath10k_htt_tx_stop(&ar->htt);
  1845. ath10k_htt_rx_free(&ar->htt);
  1846. ath10k_wmi_detach(ar);
  1847. }
  1848. EXPORT_SYMBOL(ath10k_core_stop);
  1849. /* mac80211 manages fw/hw initialization through start/stop hooks. However in
  1850. * order to know what hw capabilities should be advertised to mac80211 it is
  1851. * necessary to load the firmware (and tear it down immediately since start
  1852. * hook will try to init it again) before registering
  1853. */
  1854. static int ath10k_core_probe_fw(struct ath10k *ar)
  1855. {
  1856. struct bmi_target_info target_info;
  1857. int ret = 0;
  1858. ret = ath10k_hif_power_up(ar);
  1859. if (ret) {
  1860. ath10k_err(ar, "could not start pci hif (%d)\n", ret);
  1861. return ret;
  1862. }
  1863. memset(&target_info, 0, sizeof(target_info));
  1864. ret = ath10k_bmi_get_target_info(ar, &target_info);
  1865. if (ret) {
  1866. ath10k_err(ar, "could not get target info (%d)\n", ret);
  1867. goto err_power_down;
  1868. }
  1869. ar->target_version = target_info.version;
  1870. ar->hw->wiphy->hw_version = target_info.version;
  1871. ret = ath10k_init_hw_params(ar);
  1872. if (ret) {
  1873. ath10k_err(ar, "could not get hw params (%d)\n", ret);
  1874. goto err_power_down;
  1875. }
  1876. ret = ath10k_core_fetch_firmware_files(ar);
  1877. if (ret) {
  1878. ath10k_err(ar, "could not fetch firmware files (%d)\n", ret);
  1879. goto err_power_down;
  1880. }
  1881. BUILD_BUG_ON(sizeof(ar->hw->wiphy->fw_version) !=
  1882. sizeof(ar->normal_mode_fw.fw_file.fw_version));
  1883. memcpy(ar->hw->wiphy->fw_version, ar->normal_mode_fw.fw_file.fw_version,
  1884. sizeof(ar->hw->wiphy->fw_version));
  1885. ath10k_debug_print_hwfw_info(ar);
  1886. ret = ath10k_core_pre_cal_download(ar);
  1887. if (ret) {
  1888. /* pre calibration data download is not necessary
  1889. * for all the chipsets. Ignore failures and continue.
  1890. */
  1891. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1892. "could not load pre cal data: %d\n", ret);
  1893. }
  1894. ret = ath10k_core_get_board_id_from_otp(ar);
  1895. if (ret && ret != -EOPNOTSUPP) {
  1896. ath10k_err(ar, "failed to get board id from otp: %d\n",
  1897. ret);
  1898. goto err_free_firmware_files;
  1899. }
  1900. ret = ath10k_core_check_smbios(ar);
  1901. if (ret)
  1902. ath10k_dbg(ar, ATH10K_DBG_BOOT, "bdf variant name not set.\n");
  1903. ret = ath10k_core_fetch_board_file(ar);
  1904. if (ret) {
  1905. ath10k_err(ar, "failed to fetch board file: %d\n", ret);
  1906. goto err_free_firmware_files;
  1907. }
  1908. ath10k_debug_print_board_info(ar);
  1909. ret = ath10k_core_init_firmware_features(ar);
  1910. if (ret) {
  1911. ath10k_err(ar, "fatal problem with firmware features: %d\n",
  1912. ret);
  1913. goto err_free_firmware_files;
  1914. }
  1915. ret = ath10k_swap_code_seg_init(ar, &ar->normal_mode_fw.fw_file);
  1916. if (ret) {
  1917. ath10k_err(ar, "failed to initialize code swap segment: %d\n",
  1918. ret);
  1919. goto err_free_firmware_files;
  1920. }
  1921. mutex_lock(&ar->conf_mutex);
  1922. ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL,
  1923. &ar->normal_mode_fw);
  1924. if (ret) {
  1925. ath10k_err(ar, "could not init core (%d)\n", ret);
  1926. goto err_unlock;
  1927. }
  1928. ath10k_debug_print_boot_info(ar);
  1929. ath10k_core_stop(ar);
  1930. mutex_unlock(&ar->conf_mutex);
  1931. ath10k_hif_power_down(ar);
  1932. return 0;
  1933. err_unlock:
  1934. mutex_unlock(&ar->conf_mutex);
  1935. err_free_firmware_files:
  1936. ath10k_core_free_firmware_files(ar);
  1937. err_power_down:
  1938. ath10k_hif_power_down(ar);
  1939. return ret;
  1940. }
  1941. static void ath10k_core_register_work(struct work_struct *work)
  1942. {
  1943. struct ath10k *ar = container_of(work, struct ath10k, register_work);
  1944. int status;
  1945. /* peer stats are enabled by default */
  1946. set_bit(ATH10K_FLAG_PEER_STATS, &ar->dev_flags);
  1947. status = ath10k_core_probe_fw(ar);
  1948. if (status) {
  1949. ath10k_err(ar, "could not probe fw (%d)\n", status);
  1950. goto err;
  1951. }
  1952. status = ath10k_mac_register(ar);
  1953. if (status) {
  1954. ath10k_err(ar, "could not register to mac80211 (%d)\n", status);
  1955. goto err_release_fw;
  1956. }
  1957. status = ath10k_debug_register(ar);
  1958. if (status) {
  1959. ath10k_err(ar, "unable to initialize debugfs\n");
  1960. goto err_unregister_mac;
  1961. }
  1962. status = ath10k_spectral_create(ar);
  1963. if (status) {
  1964. ath10k_err(ar, "failed to initialize spectral\n");
  1965. goto err_debug_destroy;
  1966. }
  1967. status = ath10k_thermal_register(ar);
  1968. if (status) {
  1969. ath10k_err(ar, "could not register thermal device: %d\n",
  1970. status);
  1971. goto err_spectral_destroy;
  1972. }
  1973. set_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags);
  1974. return;
  1975. err_spectral_destroy:
  1976. ath10k_spectral_destroy(ar);
  1977. err_debug_destroy:
  1978. ath10k_debug_destroy(ar);
  1979. err_unregister_mac:
  1980. ath10k_mac_unregister(ar);
  1981. err_release_fw:
  1982. ath10k_core_free_firmware_files(ar);
  1983. err:
  1984. /* TODO: It's probably a good idea to release device from the driver
  1985. * but calling device_release_driver() here will cause a deadlock.
  1986. */
  1987. return;
  1988. }
  1989. int ath10k_core_register(struct ath10k *ar, u32 chip_id)
  1990. {
  1991. ar->chip_id = chip_id;
  1992. queue_work(ar->workqueue, &ar->register_work);
  1993. return 0;
  1994. }
  1995. EXPORT_SYMBOL(ath10k_core_register);
  1996. void ath10k_core_unregister(struct ath10k *ar)
  1997. {
  1998. cancel_work_sync(&ar->register_work);
  1999. if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags))
  2000. return;
  2001. ath10k_thermal_unregister(ar);
  2002. /* Stop spectral before unregistering from mac80211 to remove the
  2003. * relayfs debugfs file cleanly. Otherwise the parent debugfs tree
  2004. * would be already be free'd recursively, leading to a double free.
  2005. */
  2006. ath10k_spectral_destroy(ar);
  2007. /* We must unregister from mac80211 before we stop HTC and HIF.
  2008. * Otherwise we will fail to submit commands to FW and mac80211 will be
  2009. * unhappy about callback failures.
  2010. */
  2011. ath10k_mac_unregister(ar);
  2012. ath10k_testmode_destroy(ar);
  2013. ath10k_core_free_firmware_files(ar);
  2014. ath10k_core_free_board_files(ar);
  2015. ath10k_debug_unregister(ar);
  2016. }
  2017. EXPORT_SYMBOL(ath10k_core_unregister);
  2018. struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
  2019. enum ath10k_bus bus,
  2020. enum ath10k_hw_rev hw_rev,
  2021. const struct ath10k_hif_ops *hif_ops)
  2022. {
  2023. struct ath10k *ar;
  2024. int ret;
  2025. ar = ath10k_mac_create(priv_size);
  2026. if (!ar)
  2027. return NULL;
  2028. ar->ath_common.priv = ar;
  2029. ar->ath_common.hw = ar->hw;
  2030. ar->dev = dev;
  2031. ar->hw_rev = hw_rev;
  2032. ar->hif.ops = hif_ops;
  2033. ar->hif.bus = bus;
  2034. switch (hw_rev) {
  2035. case ATH10K_HW_QCA988X:
  2036. case ATH10K_HW_QCA9887:
  2037. ar->regs = &qca988x_regs;
  2038. ar->hw_values = &qca988x_values;
  2039. break;
  2040. case ATH10K_HW_QCA6174:
  2041. case ATH10K_HW_QCA9377:
  2042. ar->regs = &qca6174_regs;
  2043. ar->hw_values = &qca6174_values;
  2044. break;
  2045. case ATH10K_HW_QCA99X0:
  2046. case ATH10K_HW_QCA9984:
  2047. ar->regs = &qca99x0_regs;
  2048. ar->hw_values = &qca99x0_values;
  2049. break;
  2050. case ATH10K_HW_QCA9888:
  2051. ar->regs = &qca99x0_regs;
  2052. ar->hw_values = &qca9888_values;
  2053. break;
  2054. case ATH10K_HW_QCA4019:
  2055. ar->regs = &qca4019_regs;
  2056. ar->hw_values = &qca4019_values;
  2057. break;
  2058. default:
  2059. ath10k_err(ar, "unsupported core hardware revision %d\n",
  2060. hw_rev);
  2061. ret = -ENOTSUPP;
  2062. goto err_free_mac;
  2063. }
  2064. init_completion(&ar->scan.started);
  2065. init_completion(&ar->scan.completed);
  2066. init_completion(&ar->scan.on_channel);
  2067. init_completion(&ar->target_suspend);
  2068. init_completion(&ar->wow.wakeup_completed);
  2069. init_completion(&ar->install_key_done);
  2070. init_completion(&ar->vdev_setup_done);
  2071. init_completion(&ar->thermal.wmi_sync);
  2072. init_completion(&ar->bss_survey_done);
  2073. INIT_DELAYED_WORK(&ar->scan.timeout, ath10k_scan_timeout_work);
  2074. ar->workqueue = create_singlethread_workqueue("ath10k_wq");
  2075. if (!ar->workqueue)
  2076. goto err_free_mac;
  2077. ar->workqueue_aux = create_singlethread_workqueue("ath10k_aux_wq");
  2078. if (!ar->workqueue_aux)
  2079. goto err_free_wq;
  2080. mutex_init(&ar->conf_mutex);
  2081. spin_lock_init(&ar->data_lock);
  2082. spin_lock_init(&ar->txqs_lock);
  2083. INIT_LIST_HEAD(&ar->txqs);
  2084. INIT_LIST_HEAD(&ar->peers);
  2085. init_waitqueue_head(&ar->peer_mapping_wq);
  2086. init_waitqueue_head(&ar->htt.empty_tx_wq);
  2087. init_waitqueue_head(&ar->wmi.tx_credits_wq);
  2088. init_completion(&ar->offchan_tx_completed);
  2089. INIT_WORK(&ar->offchan_tx_work, ath10k_offchan_tx_work);
  2090. skb_queue_head_init(&ar->offchan_tx_queue);
  2091. INIT_WORK(&ar->wmi_mgmt_tx_work, ath10k_mgmt_over_wmi_tx_work);
  2092. skb_queue_head_init(&ar->wmi_mgmt_tx_queue);
  2093. INIT_WORK(&ar->register_work, ath10k_core_register_work);
  2094. INIT_WORK(&ar->restart_work, ath10k_core_restart);
  2095. INIT_WORK(&ar->set_coverage_class_work,
  2096. ath10k_core_set_coverage_class_work);
  2097. init_dummy_netdev(&ar->napi_dev);
  2098. ret = ath10k_debug_create(ar);
  2099. if (ret)
  2100. goto err_free_aux_wq;
  2101. return ar;
  2102. err_free_aux_wq:
  2103. destroy_workqueue(ar->workqueue_aux);
  2104. err_free_wq:
  2105. destroy_workqueue(ar->workqueue);
  2106. err_free_mac:
  2107. ath10k_mac_destroy(ar);
  2108. return NULL;
  2109. }
  2110. EXPORT_SYMBOL(ath10k_core_create);
  2111. void ath10k_core_destroy(struct ath10k *ar)
  2112. {
  2113. flush_workqueue(ar->workqueue);
  2114. destroy_workqueue(ar->workqueue);
  2115. flush_workqueue(ar->workqueue_aux);
  2116. destroy_workqueue(ar->workqueue_aux);
  2117. ath10k_debug_destroy(ar);
  2118. ath10k_htt_tx_destroy(&ar->htt);
  2119. ath10k_wmi_free_host_mem(ar);
  2120. ath10k_mac_destroy(ar);
  2121. }
  2122. EXPORT_SYMBOL(ath10k_core_destroy);
  2123. MODULE_AUTHOR("Qualcomm Atheros");
  2124. MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ac wireless LAN cards.");
  2125. MODULE_LICENSE("Dual BSD/GPL");