ca8210.c 84 KB

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  1. /*
  2. * http://www.cascoda.com/products/ca-821x/
  3. * Copyright (c) 2016, Cascoda, Ltd.
  4. * All rights reserved.
  5. *
  6. * This code is dual-licensed under both GPLv2 and 3-clause BSD. What follows is
  7. * the license notice for both respectively.
  8. *
  9. *******************************************************************************
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License
  13. * as published by the Free Software Foundation; either version 2
  14. * of the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. *******************************************************************************
  22. *
  23. * Redistribution and use in source and binary forms, with or without
  24. * modification, are permitted provided that the following conditions are met:
  25. *
  26. * 1. Redistributions of source code must retain the above copyright notice,
  27. * this list of conditions and the following disclaimer.
  28. *
  29. * 2. Redistributions in binary form must reproduce the above copyright notice,
  30. * this list of conditions and the following disclaimer in the documentation
  31. * and/or other materials provided with the distribution.
  32. *
  33. * 3. Neither the name of the copyright holder nor the names of its contributors
  34. * may be used to endorse or promote products derived from this software without
  35. * specific prior written permission.
  36. *
  37. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  38. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  39. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  40. * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
  41. * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  42. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  43. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  44. * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  45. * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  46. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  47. * POSSIBILITY OF SUCH DAMAGE.
  48. */
  49. #include <linux/cdev.h>
  50. #include <linux/clk-provider.h>
  51. #include <linux/debugfs.h>
  52. #include <linux/delay.h>
  53. #include <linux/gpio.h>
  54. #include <linux/ieee802154.h>
  55. #include <linux/kfifo.h>
  56. #include <linux/of.h>
  57. #include <linux/of_device.h>
  58. #include <linux/of_gpio.h>
  59. #include <linux/module.h>
  60. #include <linux/mutex.h>
  61. #include <linux/poll.h>
  62. #include <linux/skbuff.h>
  63. #include <linux/slab.h>
  64. #include <linux/spi/spi.h>
  65. #include <linux/spinlock.h>
  66. #include <linux/string.h>
  67. #include <linux/workqueue.h>
  68. #include <net/ieee802154_netdev.h>
  69. #include <net/mac802154.h>
  70. #define DRIVER_NAME "ca8210"
  71. /* external clock frequencies */
  72. #define ONE_MHZ 1000000
  73. #define TWO_MHZ (2 * ONE_MHZ)
  74. #define FOUR_MHZ (4 * ONE_MHZ)
  75. #define EIGHT_MHZ (8 * ONE_MHZ)
  76. #define SIXTEEN_MHZ (16 * ONE_MHZ)
  77. /* spi constants */
  78. #define CA8210_SPI_BUF_SIZE 256
  79. #define CA8210_SYNC_TIMEOUT 1000 /* Timeout for synchronous commands [ms] */
  80. /* test interface constants */
  81. #define CA8210_TEST_INT_FILE_NAME "ca8210_test"
  82. #define CA8210_TEST_INT_FIFO_SIZE 256
  83. /* MAC status enumerations */
  84. #define MAC_SUCCESS (0x00)
  85. #define MAC_ERROR (0x01)
  86. #define MAC_CANCELLED (0x02)
  87. #define MAC_READY_FOR_POLL (0x03)
  88. #define MAC_COUNTER_ERROR (0xDB)
  89. #define MAC_IMPROPER_KEY_TYPE (0xDC)
  90. #define MAC_IMPROPER_SECURITY_LEVEL (0xDD)
  91. #define MAC_UNSUPPORTED_LEGACY (0xDE)
  92. #define MAC_UNSUPPORTED_SECURITY (0xDF)
  93. #define MAC_BEACON_LOST (0xE0)
  94. #define MAC_CHANNEL_ACCESS_FAILURE (0xE1)
  95. #define MAC_DENIED (0xE2)
  96. #define MAC_DISABLE_TRX_FAILURE (0xE3)
  97. #define MAC_SECURITY_ERROR (0xE4)
  98. #define MAC_FRAME_TOO_LONG (0xE5)
  99. #define MAC_INVALID_GTS (0xE6)
  100. #define MAC_INVALID_HANDLE (0xE7)
  101. #define MAC_INVALID_PARAMETER (0xE8)
  102. #define MAC_NO_ACK (0xE9)
  103. #define MAC_NO_BEACON (0xEA)
  104. #define MAC_NO_DATA (0xEB)
  105. #define MAC_NO_SHORT_ADDRESS (0xEC)
  106. #define MAC_OUT_OF_CAP (0xED)
  107. #define MAC_PAN_ID_CONFLICT (0xEE)
  108. #define MAC_REALIGNMENT (0xEF)
  109. #define MAC_TRANSACTION_EXPIRED (0xF0)
  110. #define MAC_TRANSACTION_OVERFLOW (0xF1)
  111. #define MAC_TX_ACTIVE (0xF2)
  112. #define MAC_UNAVAILABLE_KEY (0xF3)
  113. #define MAC_UNSUPPORTED_ATTRIBUTE (0xF4)
  114. #define MAC_INVALID_ADDRESS (0xF5)
  115. #define MAC_ON_TIME_TOO_LONG (0xF6)
  116. #define MAC_PAST_TIME (0xF7)
  117. #define MAC_TRACKING_OFF (0xF8)
  118. #define MAC_INVALID_INDEX (0xF9)
  119. #define MAC_LIMIT_REACHED (0xFA)
  120. #define MAC_READ_ONLY (0xFB)
  121. #define MAC_SCAN_IN_PROGRESS (0xFC)
  122. #define MAC_SUPERFRAME_OVERLAP (0xFD)
  123. #define MAC_SYSTEM_ERROR (0xFF)
  124. /* HWME attribute IDs */
  125. #define HWME_EDTHRESHOLD (0x04)
  126. #define HWME_EDVALUE (0x06)
  127. #define HWME_SYSCLKOUT (0x0F)
  128. #define HWME_LQILIMIT (0x11)
  129. /* TDME attribute IDs */
  130. #define TDME_CHANNEL (0x00)
  131. #define TDME_ATM_CONFIG (0x06)
  132. #define MAX_HWME_ATTRIBUTE_SIZE 16
  133. #define MAX_TDME_ATTRIBUTE_SIZE 2
  134. /* PHY/MAC PIB Attribute Enumerations */
  135. #define PHY_CURRENT_CHANNEL (0x00)
  136. #define PHY_TRANSMIT_POWER (0x02)
  137. #define PHY_CCA_MODE (0x03)
  138. #define MAC_ASSOCIATION_PERMIT (0x41)
  139. #define MAC_AUTO_REQUEST (0x42)
  140. #define MAC_BATT_LIFE_EXT (0x43)
  141. #define MAC_BATT_LIFE_EXT_PERIODS (0x44)
  142. #define MAC_BEACON_PAYLOAD (0x45)
  143. #define MAC_BEACON_PAYLOAD_LENGTH (0x46)
  144. #define MAC_BEACON_ORDER (0x47)
  145. #define MAC_GTS_PERMIT (0x4d)
  146. #define MAC_MAX_CSMA_BACKOFFS (0x4e)
  147. #define MAC_MIN_BE (0x4f)
  148. #define MAC_PAN_ID (0x50)
  149. #define MAC_PROMISCUOUS_MODE (0x51)
  150. #define MAC_RX_ON_WHEN_IDLE (0x52)
  151. #define MAC_SHORT_ADDRESS (0x53)
  152. #define MAC_SUPERFRAME_ORDER (0x54)
  153. #define MAC_ASSOCIATED_PAN_COORD (0x56)
  154. #define MAC_MAX_BE (0x57)
  155. #define MAC_MAX_FRAME_RETRIES (0x59)
  156. #define MAC_RESPONSE_WAIT_TIME (0x5A)
  157. #define MAC_SECURITY_ENABLED (0x5D)
  158. #define MAC_AUTO_REQUEST_SECURITY_LEVEL (0x78)
  159. #define MAC_AUTO_REQUEST_KEY_ID_MODE (0x79)
  160. #define NS_IEEE_ADDRESS (0xFF) /* Non-standard IEEE address */
  161. /* MAC Address Mode Definitions */
  162. #define MAC_MODE_NO_ADDR (0x00)
  163. #define MAC_MODE_SHORT_ADDR (0x02)
  164. #define MAC_MODE_LONG_ADDR (0x03)
  165. /* MAC constants */
  166. #define MAX_BEACON_OVERHEAD (75)
  167. #define MAX_BEACON_PAYLOAD_LENGTH (IEEE802154_MTU - MAX_BEACON_OVERHEAD)
  168. #define MAX_ATTRIBUTE_SIZE (122)
  169. #define MAX_DATA_SIZE (114)
  170. #define CA8210_VALID_CHANNELS (0x07FFF800)
  171. /* MAC workarounds for V1.1 and MPW silicon (V0.x) */
  172. #define CA8210_MAC_WORKAROUNDS (0)
  173. #define CA8210_MAC_MPW (0)
  174. /* memory manipulation macros */
  175. #define LS_BYTE(x) ((u8)((x) & 0xFF))
  176. #define MS_BYTE(x) ((u8)(((x) >> 8) & 0xFF))
  177. /* message ID codes in SPI commands */
  178. /* downstream */
  179. #define MCPS_DATA_REQUEST (0x00)
  180. #define MLME_ASSOCIATE_REQUEST (0x02)
  181. #define MLME_ASSOCIATE_RESPONSE (0x03)
  182. #define MLME_DISASSOCIATE_REQUEST (0x04)
  183. #define MLME_GET_REQUEST (0x05)
  184. #define MLME_ORPHAN_RESPONSE (0x06)
  185. #define MLME_RESET_REQUEST (0x07)
  186. #define MLME_RX_ENABLE_REQUEST (0x08)
  187. #define MLME_SCAN_REQUEST (0x09)
  188. #define MLME_SET_REQUEST (0x0A)
  189. #define MLME_START_REQUEST (0x0B)
  190. #define MLME_POLL_REQUEST (0x0D)
  191. #define HWME_SET_REQUEST (0x0E)
  192. #define HWME_GET_REQUEST (0x0F)
  193. #define TDME_SETSFR_REQUEST (0x11)
  194. #define TDME_GETSFR_REQUEST (0x12)
  195. #define TDME_SET_REQUEST (0x14)
  196. /* upstream */
  197. #define MCPS_DATA_INDICATION (0x00)
  198. #define MCPS_DATA_CONFIRM (0x01)
  199. #define MLME_RESET_CONFIRM (0x0A)
  200. #define MLME_SET_CONFIRM (0x0E)
  201. #define MLME_START_CONFIRM (0x0F)
  202. #define HWME_SET_CONFIRM (0x12)
  203. #define HWME_GET_CONFIRM (0x13)
  204. #define HWME_WAKEUP_INDICATION (0x15)
  205. #define TDME_SETSFR_CONFIRM (0x17)
  206. /* SPI command IDs */
  207. /* bit indicating a confirm or indication from slave to master */
  208. #define SPI_S2M (0x20)
  209. /* bit indicating a synchronous message */
  210. #define SPI_SYN (0x40)
  211. /* SPI command definitions */
  212. #define SPI_IDLE (0xFF)
  213. #define SPI_NACK (0xF0)
  214. #define SPI_MCPS_DATA_REQUEST (MCPS_DATA_REQUEST)
  215. #define SPI_MCPS_DATA_INDICATION (MCPS_DATA_INDICATION + SPI_S2M)
  216. #define SPI_MCPS_DATA_CONFIRM (MCPS_DATA_CONFIRM + SPI_S2M)
  217. #define SPI_MLME_ASSOCIATE_REQUEST (MLME_ASSOCIATE_REQUEST)
  218. #define SPI_MLME_RESET_REQUEST (MLME_RESET_REQUEST + SPI_SYN)
  219. #define SPI_MLME_SET_REQUEST (MLME_SET_REQUEST + SPI_SYN)
  220. #define SPI_MLME_START_REQUEST (MLME_START_REQUEST + SPI_SYN)
  221. #define SPI_MLME_RESET_CONFIRM (MLME_RESET_CONFIRM + SPI_S2M + SPI_SYN)
  222. #define SPI_MLME_SET_CONFIRM (MLME_SET_CONFIRM + SPI_S2M + SPI_SYN)
  223. #define SPI_MLME_START_CONFIRM (MLME_START_CONFIRM + SPI_S2M + SPI_SYN)
  224. #define SPI_HWME_SET_REQUEST (HWME_SET_REQUEST + SPI_SYN)
  225. #define SPI_HWME_GET_REQUEST (HWME_GET_REQUEST + SPI_SYN)
  226. #define SPI_HWME_SET_CONFIRM (HWME_SET_CONFIRM + SPI_S2M + SPI_SYN)
  227. #define SPI_HWME_GET_CONFIRM (HWME_GET_CONFIRM + SPI_S2M + SPI_SYN)
  228. #define SPI_HWME_WAKEUP_INDICATION (HWME_WAKEUP_INDICATION + SPI_S2M)
  229. #define SPI_TDME_SETSFR_REQUEST (TDME_SETSFR_REQUEST + SPI_SYN)
  230. #define SPI_TDME_SET_REQUEST (TDME_SET_REQUEST + SPI_SYN)
  231. #define SPI_TDME_SETSFR_CONFIRM (TDME_SETSFR_CONFIRM + SPI_S2M + SPI_SYN)
  232. /* TDME SFR addresses */
  233. /* Page 0 */
  234. #define CA8210_SFR_PACFG (0xB1)
  235. #define CA8210_SFR_MACCON (0xD8)
  236. #define CA8210_SFR_PACFGIB (0xFE)
  237. /* Page 1 */
  238. #define CA8210_SFR_LOTXCAL (0xBF)
  239. #define CA8210_SFR_PTHRH (0xD1)
  240. #define CA8210_SFR_PRECFG (0xD3)
  241. #define CA8210_SFR_LNAGX40 (0xE1)
  242. #define CA8210_SFR_LNAGX41 (0xE2)
  243. #define CA8210_SFR_LNAGX42 (0xE3)
  244. #define CA8210_SFR_LNAGX43 (0xE4)
  245. #define CA8210_SFR_LNAGX44 (0xE5)
  246. #define CA8210_SFR_LNAGX45 (0xE6)
  247. #define CA8210_SFR_LNAGX46 (0xE7)
  248. #define CA8210_SFR_LNAGX47 (0xE9)
  249. #define PACFGIB_DEFAULT_CURRENT (0x3F)
  250. #define PTHRH_DEFAULT_THRESHOLD (0x5A)
  251. #define LNAGX40_DEFAULT_GAIN (0x29) /* 10dB */
  252. #define LNAGX41_DEFAULT_GAIN (0x54) /* 21dB */
  253. #define LNAGX42_DEFAULT_GAIN (0x6C) /* 27dB */
  254. #define LNAGX43_DEFAULT_GAIN (0x7A) /* 30dB */
  255. #define LNAGX44_DEFAULT_GAIN (0x84) /* 33dB */
  256. #define LNAGX45_DEFAULT_GAIN (0x8B) /* 34dB */
  257. #define LNAGX46_DEFAULT_GAIN (0x92) /* 36dB */
  258. #define LNAGX47_DEFAULT_GAIN (0x96) /* 37dB */
  259. #define CA8210_IOCTL_HARD_RESET (0x00)
  260. /* Structs/Enums */
  261. /**
  262. * struct cas_control - spi transfer structure
  263. * @msg: spi_message for each exchange
  264. * @transfer: spi_transfer for each exchange
  265. * @tx_buf: source array for transmission
  266. * @tx_in_buf: array storing bytes received during transmission
  267. * @priv: pointer to private data
  268. *
  269. * This structure stores all the necessary data passed around during a single
  270. * spi exchange.
  271. */
  272. struct cas_control {
  273. struct spi_message msg;
  274. struct spi_transfer transfer;
  275. u8 tx_buf[CA8210_SPI_BUF_SIZE];
  276. u8 tx_in_buf[CA8210_SPI_BUF_SIZE];
  277. struct ca8210_priv *priv;
  278. };
  279. /**
  280. * struct ca8210_test - ca8210 test interface structure
  281. * @ca8210_dfs_spi_int: pointer to the entry in the debug fs for this device
  282. * @up_fifo: fifo for upstream messages
  283. *
  284. * This structure stores all the data pertaining to the debug interface
  285. */
  286. struct ca8210_test {
  287. struct dentry *ca8210_dfs_spi_int;
  288. struct kfifo up_fifo;
  289. wait_queue_head_t readq;
  290. };
  291. /**
  292. * struct ca8210_priv - ca8210 private data structure
  293. * @spi: pointer to the ca8210 spi device object
  294. * @hw: pointer to the ca8210 ieee802154_hw object
  295. * @hw_registered: true if hw has been registered with ieee802154
  296. * @lock: spinlock protecting the private data area
  297. * @mlme_workqueue: workqueue for triggering MLME Reset
  298. * @irq_workqueue: workqueue for irq processing
  299. * @tx_skb: current socket buffer to transmit
  300. * @nextmsduhandle: msdu handle to pass to the 15.4 MAC layer for the
  301. * next transmission
  302. * @clk: external clock provided by the ca8210
  303. * @last_dsn: sequence number of last data packet received, for
  304. * resend detection
  305. * @test: test interface data section for this instance
  306. * @async_tx_pending: true if an asynchronous transmission was started and
  307. * is not complete
  308. * @sync_command_response: pointer to buffer to fill with sync response
  309. * @ca8210_is_awake: nonzero if ca8210 is initialised, ready for comms
  310. * @sync_down: counts number of downstream synchronous commands
  311. * @sync_up: counts number of upstream synchronous commands
  312. * @spi_transfer_complete completion object for a single spi_transfer
  313. * @sync_exchange_complete completion object for a complete synchronous API
  314. * exchange
  315. * @promiscuous whether the ca8210 is in promiscuous mode or not
  316. * @retries: records how many times the current pending spi
  317. * transfer has been retried
  318. */
  319. struct ca8210_priv {
  320. struct spi_device *spi;
  321. struct ieee802154_hw *hw;
  322. bool hw_registered;
  323. spinlock_t lock;
  324. struct workqueue_struct *mlme_workqueue;
  325. struct workqueue_struct *irq_workqueue;
  326. struct sk_buff *tx_skb;
  327. u8 nextmsduhandle;
  328. struct clk *clk;
  329. int last_dsn;
  330. struct ca8210_test test;
  331. bool async_tx_pending;
  332. u8 *sync_command_response;
  333. struct completion ca8210_is_awake;
  334. int sync_down, sync_up;
  335. struct completion spi_transfer_complete, sync_exchange_complete;
  336. bool promiscuous;
  337. int retries;
  338. };
  339. /**
  340. * struct work_priv_container - link between a work object and the relevant
  341. * device's private data
  342. * @work: work object being executed
  343. * @priv: device's private data section
  344. *
  345. */
  346. struct work_priv_container {
  347. struct work_struct work;
  348. struct ca8210_priv *priv;
  349. };
  350. /**
  351. * struct ca8210_platform_data - ca8210 platform data structure
  352. * @extclockenable: true if the external clock is to be enabled
  353. * @extclockfreq: frequency of the external clock
  354. * @extclockgpio: ca8210 output gpio of the external clock
  355. * @gpio_reset: gpio number of ca8210 reset line
  356. * @gpio_irq: gpio number of ca8210 interrupt line
  357. * @irq_id: identifier for the ca8210 irq
  358. *
  359. */
  360. struct ca8210_platform_data {
  361. bool extclockenable;
  362. unsigned int extclockfreq;
  363. unsigned int extclockgpio;
  364. int gpio_reset;
  365. int gpio_irq;
  366. int irq_id;
  367. };
  368. /**
  369. * struct fulladdr - full MAC addressing information structure
  370. * @mode: address mode (none, short, extended)
  371. * @pan_id: 16-bit LE pan id
  372. * @address: LE address, variable length as specified by mode
  373. *
  374. */
  375. struct fulladdr {
  376. u8 mode;
  377. u8 pan_id[2];
  378. u8 address[8];
  379. };
  380. /**
  381. * union macaddr: generic MAC address container
  382. * @short_addr: 16-bit short address
  383. * @ieee_address: 64-bit extended address as LE byte array
  384. *
  385. */
  386. union macaddr {
  387. u16 short_address;
  388. u8 ieee_address[8];
  389. };
  390. /**
  391. * struct secspec: security specification for SAP commands
  392. * @security_level: 0-7, controls level of authentication & encryption
  393. * @key_id_mode: 0-3, specifies how to obtain key
  394. * @key_source: extended key retrieval data
  395. * @key_index: single-byte key identifier
  396. *
  397. */
  398. struct secspec {
  399. u8 security_level;
  400. u8 key_id_mode;
  401. u8 key_source[8];
  402. u8 key_index;
  403. };
  404. /* downlink functions parameter set definitions */
  405. struct mcps_data_request_pset {
  406. u8 src_addr_mode;
  407. struct fulladdr dst;
  408. u8 msdu_length;
  409. u8 msdu_handle;
  410. u8 tx_options;
  411. u8 msdu[MAX_DATA_SIZE];
  412. };
  413. struct mlme_set_request_pset {
  414. u8 pib_attribute;
  415. u8 pib_attribute_index;
  416. u8 pib_attribute_length;
  417. u8 pib_attribute_value[MAX_ATTRIBUTE_SIZE];
  418. };
  419. struct hwme_set_request_pset {
  420. u8 hw_attribute;
  421. u8 hw_attribute_length;
  422. u8 hw_attribute_value[MAX_HWME_ATTRIBUTE_SIZE];
  423. };
  424. struct hwme_get_request_pset {
  425. u8 hw_attribute;
  426. };
  427. struct tdme_setsfr_request_pset {
  428. u8 sfr_page;
  429. u8 sfr_address;
  430. u8 sfr_value;
  431. };
  432. /* uplink functions parameter set definitions */
  433. struct hwme_set_confirm_pset {
  434. u8 status;
  435. u8 hw_attribute;
  436. };
  437. struct hwme_get_confirm_pset {
  438. u8 status;
  439. u8 hw_attribute;
  440. u8 hw_attribute_length;
  441. u8 hw_attribute_value[MAX_HWME_ATTRIBUTE_SIZE];
  442. };
  443. struct tdme_setsfr_confirm_pset {
  444. u8 status;
  445. u8 sfr_page;
  446. u8 sfr_address;
  447. };
  448. struct mac_message {
  449. u8 command_id;
  450. u8 length;
  451. union {
  452. struct mcps_data_request_pset data_req;
  453. struct mlme_set_request_pset set_req;
  454. struct hwme_set_request_pset hwme_set_req;
  455. struct hwme_get_request_pset hwme_get_req;
  456. struct tdme_setsfr_request_pset tdme_set_sfr_req;
  457. struct hwme_set_confirm_pset hwme_set_cnf;
  458. struct hwme_get_confirm_pset hwme_get_cnf;
  459. struct tdme_setsfr_confirm_pset tdme_set_sfr_cnf;
  460. u8 u8param;
  461. u8 status;
  462. u8 payload[148];
  463. } pdata;
  464. };
  465. union pa_cfg_sfr {
  466. struct {
  467. u8 bias_current_trim : 3;
  468. u8 /* reserved */ : 1;
  469. u8 buffer_capacitor_trim : 3;
  470. u8 boost : 1;
  471. };
  472. u8 paib;
  473. };
  474. struct preamble_cfg_sfr {
  475. u8 timeout_symbols : 3;
  476. u8 acquisition_symbols : 3;
  477. u8 search_symbols : 2;
  478. };
  479. static int (*cascoda_api_upstream)(
  480. const u8 *buf,
  481. size_t len,
  482. void *device_ref
  483. );
  484. /**
  485. * link_to_linux_err() - Translates an 802.15.4 return code into the closest
  486. * linux error
  487. * @link_status: 802.15.4 status code
  488. *
  489. * Return: 0 or Linux error code
  490. */
  491. static int link_to_linux_err(int link_status)
  492. {
  493. if (link_status < 0) {
  494. /* status is already a Linux code */
  495. return link_status;
  496. }
  497. switch (link_status) {
  498. case MAC_SUCCESS:
  499. case MAC_REALIGNMENT:
  500. return 0;
  501. case MAC_IMPROPER_KEY_TYPE:
  502. return -EKEYREJECTED;
  503. case MAC_IMPROPER_SECURITY_LEVEL:
  504. case MAC_UNSUPPORTED_LEGACY:
  505. case MAC_DENIED:
  506. return -EACCES;
  507. case MAC_BEACON_LOST:
  508. case MAC_NO_ACK:
  509. case MAC_NO_BEACON:
  510. return -ENETUNREACH;
  511. case MAC_CHANNEL_ACCESS_FAILURE:
  512. case MAC_TX_ACTIVE:
  513. case MAC_SCAN_IN_PROGRESS:
  514. return -EBUSY;
  515. case MAC_DISABLE_TRX_FAILURE:
  516. case MAC_OUT_OF_CAP:
  517. return -EAGAIN;
  518. case MAC_FRAME_TOO_LONG:
  519. return -EMSGSIZE;
  520. case MAC_INVALID_GTS:
  521. case MAC_PAST_TIME:
  522. return -EBADSLT;
  523. case MAC_INVALID_HANDLE:
  524. return -EBADMSG;
  525. case MAC_INVALID_PARAMETER:
  526. case MAC_UNSUPPORTED_ATTRIBUTE:
  527. case MAC_ON_TIME_TOO_LONG:
  528. case MAC_INVALID_INDEX:
  529. return -EINVAL;
  530. case MAC_NO_DATA:
  531. return -ENODATA;
  532. case MAC_NO_SHORT_ADDRESS:
  533. return -EFAULT;
  534. case MAC_PAN_ID_CONFLICT:
  535. return -EADDRINUSE;
  536. case MAC_TRANSACTION_EXPIRED:
  537. return -ETIME;
  538. case MAC_TRANSACTION_OVERFLOW:
  539. return -ENOBUFS;
  540. case MAC_UNAVAILABLE_KEY:
  541. return -ENOKEY;
  542. case MAC_INVALID_ADDRESS:
  543. return -ENXIO;
  544. case MAC_TRACKING_OFF:
  545. case MAC_SUPERFRAME_OVERLAP:
  546. return -EREMOTEIO;
  547. case MAC_LIMIT_REACHED:
  548. return -EDQUOT;
  549. case MAC_READ_ONLY:
  550. return -EROFS;
  551. default:
  552. return -EPROTO;
  553. }
  554. }
  555. /**
  556. * ca8210_test_int_driver_write() - Writes a message to the test interface to be
  557. * read by the userspace
  558. * @buf: Buffer containing upstream message
  559. * @len: length of message to write
  560. * @spi: SPI device of message originator
  561. *
  562. * Return: 0 or linux error code
  563. */
  564. static int ca8210_test_int_driver_write(
  565. const u8 *buf,
  566. size_t len,
  567. void *spi
  568. )
  569. {
  570. struct ca8210_priv *priv = spi_get_drvdata(spi);
  571. struct ca8210_test *test = &priv->test;
  572. char *fifo_buffer;
  573. int i;
  574. dev_dbg(
  575. &priv->spi->dev,
  576. "test_interface: Buffering upstream message:\n"
  577. );
  578. for (i = 0; i < len; i++)
  579. dev_dbg(&priv->spi->dev, "%#03x\n", buf[i]);
  580. fifo_buffer = kmalloc(len, GFP_KERNEL);
  581. if (!fifo_buffer)
  582. return -ENOMEM;
  583. memcpy(fifo_buffer, buf, len);
  584. kfifo_in(&test->up_fifo, &fifo_buffer, 4);
  585. wake_up_interruptible(&priv->test.readq);
  586. return 0;
  587. }
  588. /* SPI Operation */
  589. static int ca8210_net_rx(
  590. struct ieee802154_hw *hw,
  591. u8 *command,
  592. size_t len
  593. );
  594. static u8 mlme_reset_request_sync(
  595. u8 set_default_pib,
  596. void *device_ref
  597. );
  598. static int ca8210_spi_transfer(
  599. struct spi_device *spi,
  600. const u8 *buf,
  601. size_t len
  602. );
  603. /**
  604. * ca8210_reset_send() - Hard resets the ca8210 for a given time
  605. * @spi: Pointer to target ca8210 spi device
  606. * @ms: Milliseconds to hold the reset line low for
  607. */
  608. static void ca8210_reset_send(struct spi_device *spi, unsigned int ms)
  609. {
  610. struct ca8210_platform_data *pdata = spi->dev.platform_data;
  611. struct ca8210_priv *priv = spi_get_drvdata(spi);
  612. long status;
  613. gpio_set_value(pdata->gpio_reset, 0);
  614. reinit_completion(&priv->ca8210_is_awake);
  615. msleep(ms);
  616. gpio_set_value(pdata->gpio_reset, 1);
  617. priv->promiscuous = false;
  618. /* Wait until wakeup indication seen */
  619. status = wait_for_completion_interruptible_timeout(
  620. &priv->ca8210_is_awake,
  621. msecs_to_jiffies(CA8210_SYNC_TIMEOUT)
  622. );
  623. if (status == 0) {
  624. dev_crit(
  625. &spi->dev,
  626. "Fatal: No wakeup from ca8210 after reset!\n"
  627. );
  628. }
  629. dev_dbg(&spi->dev, "Reset the device\n");
  630. }
  631. /**
  632. * ca8210_mlme_reset_worker() - Resets the MLME, Called when the MAC OVERFLOW
  633. * condition happens.
  634. * @work: Pointer to work being executed
  635. */
  636. static void ca8210_mlme_reset_worker(struct work_struct *work)
  637. {
  638. struct work_priv_container *wpc = container_of(
  639. work,
  640. struct work_priv_container,
  641. work
  642. );
  643. struct ca8210_priv *priv = wpc->priv;
  644. mlme_reset_request_sync(0, priv->spi);
  645. kfree(wpc);
  646. }
  647. /**
  648. * ca8210_rx_done() - Calls various message dispatches responding to a received
  649. * command
  650. * @arg: Pointer to the cas_control object for the relevant spi transfer
  651. *
  652. * Presents a received SAP command from the ca8210 to the Cascoda EVBME, test
  653. * interface and network driver.
  654. */
  655. static void ca8210_rx_done(struct cas_control *cas_ctl)
  656. {
  657. u8 *buf;
  658. u8 len;
  659. struct work_priv_container *mlme_reset_wpc;
  660. struct ca8210_priv *priv = cas_ctl->priv;
  661. buf = cas_ctl->tx_in_buf;
  662. len = buf[1] + 2;
  663. if (len > CA8210_SPI_BUF_SIZE) {
  664. dev_crit(
  665. &priv->spi->dev,
  666. "Received packet len (%d) erroneously long\n",
  667. len
  668. );
  669. goto finish;
  670. }
  671. if (buf[0] & SPI_SYN) {
  672. if (priv->sync_command_response) {
  673. memcpy(priv->sync_command_response, buf, len);
  674. complete(&priv->sync_exchange_complete);
  675. } else {
  676. if (cascoda_api_upstream)
  677. cascoda_api_upstream(buf, len, priv->spi);
  678. priv->sync_up++;
  679. }
  680. } else {
  681. if (cascoda_api_upstream)
  682. cascoda_api_upstream(buf, len, priv->spi);
  683. }
  684. ca8210_net_rx(priv->hw, buf, len);
  685. if (buf[0] == SPI_MCPS_DATA_CONFIRM) {
  686. if (buf[3] == MAC_TRANSACTION_OVERFLOW) {
  687. dev_info(
  688. &priv->spi->dev,
  689. "Waiting for transaction overflow to stabilise...\n");
  690. msleep(2000);
  691. dev_info(
  692. &priv->spi->dev,
  693. "Resetting MAC...\n");
  694. mlme_reset_wpc = kmalloc(sizeof(*mlme_reset_wpc),
  695. GFP_KERNEL);
  696. if (!mlme_reset_wpc)
  697. goto finish;
  698. INIT_WORK(
  699. &mlme_reset_wpc->work,
  700. ca8210_mlme_reset_worker
  701. );
  702. mlme_reset_wpc->priv = priv;
  703. queue_work(priv->mlme_workqueue, &mlme_reset_wpc->work);
  704. }
  705. } else if (buf[0] == SPI_HWME_WAKEUP_INDICATION) {
  706. dev_notice(
  707. &priv->spi->dev,
  708. "Wakeup indication received, reason:\n"
  709. );
  710. switch (buf[2]) {
  711. case 0:
  712. dev_notice(
  713. &priv->spi->dev,
  714. "Transceiver woken up from Power Up / System Reset\n"
  715. );
  716. break;
  717. case 1:
  718. dev_notice(
  719. &priv->spi->dev,
  720. "Watchdog Timer Time-Out\n"
  721. );
  722. break;
  723. case 2:
  724. dev_notice(
  725. &priv->spi->dev,
  726. "Transceiver woken up from Power-Off by Sleep Timer Time-Out\n");
  727. break;
  728. case 3:
  729. dev_notice(
  730. &priv->spi->dev,
  731. "Transceiver woken up from Power-Off by GPIO Activity\n"
  732. );
  733. break;
  734. case 4:
  735. dev_notice(
  736. &priv->spi->dev,
  737. "Transceiver woken up from Standby by Sleep Timer Time-Out\n"
  738. );
  739. break;
  740. case 5:
  741. dev_notice(
  742. &priv->spi->dev,
  743. "Transceiver woken up from Standby by GPIO Activity\n"
  744. );
  745. break;
  746. case 6:
  747. dev_notice(
  748. &priv->spi->dev,
  749. "Sleep-Timer Time-Out in Active Mode\n"
  750. );
  751. break;
  752. default:
  753. dev_warn(&priv->spi->dev, "Wakeup reason unknown\n");
  754. break;
  755. }
  756. complete(&priv->ca8210_is_awake);
  757. }
  758. finish:;
  759. }
  760. static int ca8210_remove(struct spi_device *spi_device);
  761. /**
  762. * ca8210_spi_transfer_complete() - Called when a single spi transfer has
  763. * completed
  764. * @context: Pointer to the cas_control object for the finished transfer
  765. */
  766. static void ca8210_spi_transfer_complete(void *context)
  767. {
  768. struct cas_control *cas_ctl = context;
  769. struct ca8210_priv *priv = cas_ctl->priv;
  770. bool duplex_rx = false;
  771. int i;
  772. u8 retry_buffer[CA8210_SPI_BUF_SIZE];
  773. if (
  774. cas_ctl->tx_in_buf[0] == SPI_NACK ||
  775. (cas_ctl->tx_in_buf[0] == SPI_IDLE &&
  776. cas_ctl->tx_in_buf[1] == SPI_NACK)
  777. ) {
  778. /* ca8210 is busy */
  779. dev_info(&priv->spi->dev, "ca8210 was busy during attempted write\n");
  780. if (cas_ctl->tx_buf[0] == SPI_IDLE) {
  781. dev_warn(
  782. &priv->spi->dev,
  783. "IRQ servicing NACKd, dropping transfer\n"
  784. );
  785. kfree(cas_ctl);
  786. return;
  787. }
  788. if (priv->retries > 3) {
  789. dev_err(&priv->spi->dev, "too many retries!\n");
  790. kfree(cas_ctl);
  791. ca8210_remove(priv->spi);
  792. return;
  793. }
  794. memcpy(retry_buffer, cas_ctl->tx_buf, CA8210_SPI_BUF_SIZE);
  795. kfree(cas_ctl);
  796. ca8210_spi_transfer(
  797. priv->spi,
  798. retry_buffer,
  799. CA8210_SPI_BUF_SIZE
  800. );
  801. priv->retries++;
  802. dev_info(&priv->spi->dev, "retried spi write\n");
  803. return;
  804. } else if (
  805. cas_ctl->tx_in_buf[0] != SPI_IDLE &&
  806. cas_ctl->tx_in_buf[0] != SPI_NACK
  807. ) {
  808. duplex_rx = true;
  809. }
  810. if (duplex_rx) {
  811. dev_dbg(&priv->spi->dev, "READ CMD DURING TX\n");
  812. for (i = 0; i < cas_ctl->tx_in_buf[1] + 2; i++)
  813. dev_dbg(
  814. &priv->spi->dev,
  815. "%#03x\n",
  816. cas_ctl->tx_in_buf[i]
  817. );
  818. ca8210_rx_done(cas_ctl);
  819. }
  820. complete(&priv->spi_transfer_complete);
  821. kfree(cas_ctl);
  822. priv->retries = 0;
  823. }
  824. /**
  825. * ca8210_spi_transfer() - Initiate duplex spi transfer with ca8210
  826. * @spi: Pointer to spi device for transfer
  827. * @buf: Octet array to send
  828. * @len: length of the buffer being sent
  829. *
  830. * Return: 0 or linux error code
  831. */
  832. static int ca8210_spi_transfer(
  833. struct spi_device *spi,
  834. const u8 *buf,
  835. size_t len
  836. )
  837. {
  838. int i, status = 0;
  839. struct ca8210_priv *priv = spi_get_drvdata(spi);
  840. struct cas_control *cas_ctl;
  841. if (!spi) {
  842. dev_crit(
  843. &spi->dev,
  844. "NULL spi device passed to ca8210_spi_transfer\n"
  845. );
  846. return -ENODEV;
  847. }
  848. reinit_completion(&priv->spi_transfer_complete);
  849. dev_dbg(&spi->dev, "ca8210_spi_transfer called\n");
  850. cas_ctl = kmalloc(sizeof(*cas_ctl), GFP_ATOMIC);
  851. if (!cas_ctl)
  852. return -ENOMEM;
  853. cas_ctl->priv = priv;
  854. memset(cas_ctl->tx_buf, SPI_IDLE, CA8210_SPI_BUF_SIZE);
  855. memset(cas_ctl->tx_in_buf, SPI_IDLE, CA8210_SPI_BUF_SIZE);
  856. memcpy(cas_ctl->tx_buf, buf, len);
  857. for (i = 0; i < len; i++)
  858. dev_dbg(&spi->dev, "%#03x\n", cas_ctl->tx_buf[i]);
  859. spi_message_init(&cas_ctl->msg);
  860. cas_ctl->transfer.tx_nbits = 1; /* 1 MOSI line */
  861. cas_ctl->transfer.rx_nbits = 1; /* 1 MISO line */
  862. cas_ctl->transfer.speed_hz = 0; /* Use device setting */
  863. cas_ctl->transfer.bits_per_word = 0; /* Use device setting */
  864. cas_ctl->transfer.tx_buf = cas_ctl->tx_buf;
  865. cas_ctl->transfer.rx_buf = cas_ctl->tx_in_buf;
  866. cas_ctl->transfer.delay_usecs = 0;
  867. cas_ctl->transfer.cs_change = 0;
  868. cas_ctl->transfer.len = sizeof(struct mac_message);
  869. cas_ctl->msg.complete = ca8210_spi_transfer_complete;
  870. cas_ctl->msg.context = cas_ctl;
  871. spi_message_add_tail(
  872. &cas_ctl->transfer,
  873. &cas_ctl->msg
  874. );
  875. status = spi_async(spi, &cas_ctl->msg);
  876. if (status < 0) {
  877. dev_crit(
  878. &spi->dev,
  879. "status %d from spi_sync in write\n",
  880. status
  881. );
  882. }
  883. return status;
  884. }
  885. /**
  886. * ca8210_spi_exchange() - Exchange API/SAP commands with the radio
  887. * @buf: Octet array of command being sent downstream
  888. * @len: length of buf
  889. * @response: buffer for storing synchronous response
  890. * @device_ref: spi_device pointer for ca8210
  891. *
  892. * Effectively calls ca8210_spi_transfer to write buf[] to the spi, then for
  893. * synchronous commands waits for the corresponding response to be read from
  894. * the spi before returning. The response is written to the response parameter.
  895. *
  896. * Return: 0 or linux error code
  897. */
  898. static int ca8210_spi_exchange(
  899. const u8 *buf,
  900. size_t len,
  901. u8 *response,
  902. void *device_ref
  903. )
  904. {
  905. int status = 0;
  906. struct spi_device *spi = device_ref;
  907. struct ca8210_priv *priv = spi->dev.driver_data;
  908. long wait_remaining;
  909. if ((buf[0] & SPI_SYN) && response) { /* if sync wait for confirm */
  910. reinit_completion(&priv->sync_exchange_complete);
  911. priv->sync_command_response = response;
  912. }
  913. do {
  914. reinit_completion(&priv->spi_transfer_complete);
  915. status = ca8210_spi_transfer(priv->spi, buf, len);
  916. if (status) {
  917. dev_warn(
  918. &spi->dev,
  919. "spi write failed, returned %d\n",
  920. status
  921. );
  922. if (status == -EBUSY)
  923. continue;
  924. if (((buf[0] & SPI_SYN) && response))
  925. complete(&priv->sync_exchange_complete);
  926. goto cleanup;
  927. }
  928. wait_remaining = wait_for_completion_interruptible_timeout(
  929. &priv->spi_transfer_complete,
  930. msecs_to_jiffies(1000)
  931. );
  932. if (wait_remaining == -ERESTARTSYS) {
  933. status = -ERESTARTSYS;
  934. } else if (wait_remaining == 0) {
  935. dev_err(
  936. &spi->dev,
  937. "SPI downstream transfer timed out!\n"
  938. );
  939. status = -ETIME;
  940. goto cleanup;
  941. }
  942. } while (status < 0);
  943. if (!((buf[0] & SPI_SYN) && response))
  944. goto cleanup;
  945. wait_remaining = wait_for_completion_interruptible_timeout(
  946. &priv->sync_exchange_complete,
  947. msecs_to_jiffies(CA8210_SYNC_TIMEOUT)
  948. );
  949. if (wait_remaining == -ERESTARTSYS) {
  950. status = -ERESTARTSYS;
  951. } else if (wait_remaining == 0) {
  952. dev_err(
  953. &spi->dev,
  954. "Synchronous confirm timeout\n"
  955. );
  956. status = -ETIME;
  957. }
  958. cleanup:
  959. priv->sync_command_response = NULL;
  960. return status;
  961. }
  962. /**
  963. * ca8210_interrupt_handler() - Called when an irq is received from the ca8210
  964. * @irq: Id of the irq being handled
  965. * @dev_id: Pointer passed by the system, pointing to the ca8210's private data
  966. *
  967. * This function is called when the irq line from the ca8210 is asserted,
  968. * signifying that the ca8210 has a message to send upstream to us. Starts the
  969. * asynchronous spi read.
  970. *
  971. * Return: irq return code
  972. */
  973. static irqreturn_t ca8210_interrupt_handler(int irq, void *dev_id)
  974. {
  975. struct ca8210_priv *priv = dev_id;
  976. int status;
  977. dev_dbg(&priv->spi->dev, "irq: Interrupt occurred\n");
  978. do {
  979. status = ca8210_spi_transfer(priv->spi, NULL, 0);
  980. if (status && (status != -EBUSY)) {
  981. dev_warn(
  982. &priv->spi->dev,
  983. "spi read failed, returned %d\n",
  984. status
  985. );
  986. }
  987. } while (status == -EBUSY);
  988. return IRQ_HANDLED;
  989. }
  990. static int (*cascoda_api_downstream)(
  991. const u8 *buf,
  992. size_t len,
  993. u8 *response,
  994. void *device_ref
  995. ) = ca8210_spi_exchange;
  996. /* Cascoda API / 15.4 SAP Primitives */
  997. /**
  998. * tdme_setsfr_request_sync() - TDME_SETSFR_request/confirm according to API
  999. * @sfr_page: SFR Page
  1000. * @sfr_address: SFR Address
  1001. * @sfr_value: SFR Value
  1002. * @device_ref: Nondescript pointer to target device
  1003. *
  1004. * Return: 802.15.4 status code of TDME-SETSFR.confirm
  1005. */
  1006. static u8 tdme_setsfr_request_sync(
  1007. u8 sfr_page,
  1008. u8 sfr_address,
  1009. u8 sfr_value,
  1010. void *device_ref
  1011. )
  1012. {
  1013. int ret;
  1014. struct mac_message command, response;
  1015. struct spi_device *spi = device_ref;
  1016. command.command_id = SPI_TDME_SETSFR_REQUEST;
  1017. command.length = 3;
  1018. command.pdata.tdme_set_sfr_req.sfr_page = sfr_page;
  1019. command.pdata.tdme_set_sfr_req.sfr_address = sfr_address;
  1020. command.pdata.tdme_set_sfr_req.sfr_value = sfr_value;
  1021. response.command_id = SPI_IDLE;
  1022. ret = cascoda_api_downstream(
  1023. &command.command_id,
  1024. command.length + 2,
  1025. &response.command_id,
  1026. device_ref
  1027. );
  1028. if (ret) {
  1029. dev_crit(&spi->dev, "cascoda_api_downstream returned %d", ret);
  1030. return MAC_SYSTEM_ERROR;
  1031. }
  1032. if (response.command_id != SPI_TDME_SETSFR_CONFIRM) {
  1033. dev_crit(
  1034. &spi->dev,
  1035. "sync response to SPI_TDME_SETSFR_REQUEST was not SPI_TDME_SETSFR_CONFIRM, it was %d\n",
  1036. response.command_id
  1037. );
  1038. return MAC_SYSTEM_ERROR;
  1039. }
  1040. return response.pdata.tdme_set_sfr_cnf.status;
  1041. }
  1042. /**
  1043. * tdme_chipinit() - TDME Chip Register Default Initialisation Macro
  1044. * @device_ref: Nondescript pointer to target device
  1045. *
  1046. * Return: 802.15.4 status code of API calls
  1047. */
  1048. static u8 tdme_chipinit(void *device_ref)
  1049. {
  1050. u8 status = MAC_SUCCESS;
  1051. u8 sfr_address;
  1052. struct spi_device *spi = device_ref;
  1053. struct preamble_cfg_sfr pre_cfg_value = {
  1054. .timeout_symbols = 3,
  1055. .acquisition_symbols = 3,
  1056. .search_symbols = 1,
  1057. };
  1058. /* LNA Gain Settings */
  1059. status = tdme_setsfr_request_sync(
  1060. 1, (sfr_address = CA8210_SFR_LNAGX40),
  1061. LNAGX40_DEFAULT_GAIN, device_ref);
  1062. if (status)
  1063. goto finish;
  1064. status = tdme_setsfr_request_sync(
  1065. 1, (sfr_address = CA8210_SFR_LNAGX41),
  1066. LNAGX41_DEFAULT_GAIN, device_ref);
  1067. if (status)
  1068. goto finish;
  1069. status = tdme_setsfr_request_sync(
  1070. 1, (sfr_address = CA8210_SFR_LNAGX42),
  1071. LNAGX42_DEFAULT_GAIN, device_ref);
  1072. if (status)
  1073. goto finish;
  1074. status = tdme_setsfr_request_sync(
  1075. 1, (sfr_address = CA8210_SFR_LNAGX43),
  1076. LNAGX43_DEFAULT_GAIN, device_ref);
  1077. if (status)
  1078. goto finish;
  1079. status = tdme_setsfr_request_sync(
  1080. 1, (sfr_address = CA8210_SFR_LNAGX44),
  1081. LNAGX44_DEFAULT_GAIN, device_ref);
  1082. if (status)
  1083. goto finish;
  1084. status = tdme_setsfr_request_sync(
  1085. 1, (sfr_address = CA8210_SFR_LNAGX45),
  1086. LNAGX45_DEFAULT_GAIN, device_ref);
  1087. if (status)
  1088. goto finish;
  1089. status = tdme_setsfr_request_sync(
  1090. 1, (sfr_address = CA8210_SFR_LNAGX46),
  1091. LNAGX46_DEFAULT_GAIN, device_ref);
  1092. if (status)
  1093. goto finish;
  1094. status = tdme_setsfr_request_sync(
  1095. 1, (sfr_address = CA8210_SFR_LNAGX47),
  1096. LNAGX47_DEFAULT_GAIN, device_ref);
  1097. if (status)
  1098. goto finish;
  1099. /* Preamble Timing Config */
  1100. status = tdme_setsfr_request_sync(
  1101. 1, (sfr_address = CA8210_SFR_PRECFG),
  1102. *((u8 *)&pre_cfg_value), device_ref);
  1103. if (status)
  1104. goto finish;
  1105. /* Preamble Threshold High */
  1106. status = tdme_setsfr_request_sync(
  1107. 1, (sfr_address = CA8210_SFR_PTHRH),
  1108. PTHRH_DEFAULT_THRESHOLD, device_ref);
  1109. if (status)
  1110. goto finish;
  1111. /* Tx Output Power 8 dBm */
  1112. status = tdme_setsfr_request_sync(
  1113. 0, (sfr_address = CA8210_SFR_PACFGIB),
  1114. PACFGIB_DEFAULT_CURRENT, device_ref);
  1115. if (status)
  1116. goto finish;
  1117. finish:
  1118. if (status != MAC_SUCCESS) {
  1119. dev_err(
  1120. &spi->dev,
  1121. "failed to set sfr at %#03x, status = %#03x\n",
  1122. sfr_address,
  1123. status
  1124. );
  1125. }
  1126. return status;
  1127. }
  1128. /**
  1129. * tdme_channelinit() - TDME Channel Register Default Initialisation Macro (Tx)
  1130. * @channel: 802.15.4 channel to initialise chip for
  1131. * @device_ref: Nondescript pointer to target device
  1132. *
  1133. * Return: 802.15.4 status code of API calls
  1134. */
  1135. static u8 tdme_channelinit(u8 channel, void *device_ref)
  1136. {
  1137. /* Transceiver front-end local oscillator tx two-point calibration
  1138. * value. Tuned for the hardware.
  1139. */
  1140. u8 txcalval;
  1141. if (channel >= 25)
  1142. txcalval = 0xA7;
  1143. else if (channel >= 23)
  1144. txcalval = 0xA8;
  1145. else if (channel >= 22)
  1146. txcalval = 0xA9;
  1147. else if (channel >= 20)
  1148. txcalval = 0xAA;
  1149. else if (channel >= 17)
  1150. txcalval = 0xAB;
  1151. else if (channel >= 16)
  1152. txcalval = 0xAC;
  1153. else if (channel >= 14)
  1154. txcalval = 0xAD;
  1155. else if (channel >= 12)
  1156. txcalval = 0xAE;
  1157. else
  1158. txcalval = 0xAF;
  1159. return tdme_setsfr_request_sync(
  1160. 1,
  1161. CA8210_SFR_LOTXCAL,
  1162. txcalval,
  1163. device_ref
  1164. ); /* LO Tx Cal */
  1165. }
  1166. /**
  1167. * tdme_checkpibattribute() - Checks Attribute Values that are not checked in
  1168. * MAC
  1169. * @pib_attribute: Attribute Number
  1170. * @pib_attribute_length: Attribute length
  1171. * @pib_attribute_value: Pointer to Attribute Value
  1172. * @device_ref: Nondescript pointer to target device
  1173. *
  1174. * Return: 802.15.4 status code of checks
  1175. */
  1176. static u8 tdme_checkpibattribute(
  1177. u8 pib_attribute,
  1178. u8 pib_attribute_length,
  1179. const void *pib_attribute_value
  1180. )
  1181. {
  1182. u8 status = MAC_SUCCESS;
  1183. u8 value;
  1184. value = *((u8 *)pib_attribute_value);
  1185. switch (pib_attribute) {
  1186. /* PHY */
  1187. case PHY_TRANSMIT_POWER:
  1188. if (value > 0x3F)
  1189. status = MAC_INVALID_PARAMETER;
  1190. break;
  1191. case PHY_CCA_MODE:
  1192. if (value > 0x03)
  1193. status = MAC_INVALID_PARAMETER;
  1194. break;
  1195. /* MAC */
  1196. case MAC_BATT_LIFE_EXT_PERIODS:
  1197. if ((value < 6) || (value > 41))
  1198. status = MAC_INVALID_PARAMETER;
  1199. break;
  1200. case MAC_BEACON_PAYLOAD:
  1201. if (pib_attribute_length > MAX_BEACON_PAYLOAD_LENGTH)
  1202. status = MAC_INVALID_PARAMETER;
  1203. break;
  1204. case MAC_BEACON_PAYLOAD_LENGTH:
  1205. if (value > MAX_BEACON_PAYLOAD_LENGTH)
  1206. status = MAC_INVALID_PARAMETER;
  1207. break;
  1208. case MAC_BEACON_ORDER:
  1209. if (value > 15)
  1210. status = MAC_INVALID_PARAMETER;
  1211. break;
  1212. case MAC_MAX_BE:
  1213. if ((value < 3) || (value > 8))
  1214. status = MAC_INVALID_PARAMETER;
  1215. break;
  1216. case MAC_MAX_CSMA_BACKOFFS:
  1217. if (value > 5)
  1218. status = MAC_INVALID_PARAMETER;
  1219. break;
  1220. case MAC_MAX_FRAME_RETRIES:
  1221. if (value > 7)
  1222. status = MAC_INVALID_PARAMETER;
  1223. break;
  1224. case MAC_MIN_BE:
  1225. if (value > 8)
  1226. status = MAC_INVALID_PARAMETER;
  1227. break;
  1228. case MAC_RESPONSE_WAIT_TIME:
  1229. if ((value < 2) || (value > 64))
  1230. status = MAC_INVALID_PARAMETER;
  1231. break;
  1232. case MAC_SUPERFRAME_ORDER:
  1233. if (value > 15)
  1234. status = MAC_INVALID_PARAMETER;
  1235. break;
  1236. /* boolean */
  1237. case MAC_ASSOCIATED_PAN_COORD:
  1238. case MAC_ASSOCIATION_PERMIT:
  1239. case MAC_AUTO_REQUEST:
  1240. case MAC_BATT_LIFE_EXT:
  1241. case MAC_GTS_PERMIT:
  1242. case MAC_PROMISCUOUS_MODE:
  1243. case MAC_RX_ON_WHEN_IDLE:
  1244. case MAC_SECURITY_ENABLED:
  1245. if (value > 1)
  1246. status = MAC_INVALID_PARAMETER;
  1247. break;
  1248. /* MAC SEC */
  1249. case MAC_AUTO_REQUEST_SECURITY_LEVEL:
  1250. if (value > 7)
  1251. status = MAC_INVALID_PARAMETER;
  1252. break;
  1253. case MAC_AUTO_REQUEST_KEY_ID_MODE:
  1254. if (value > 3)
  1255. status = MAC_INVALID_PARAMETER;
  1256. break;
  1257. default:
  1258. break;
  1259. }
  1260. return status;
  1261. }
  1262. /**
  1263. * tdme_settxpower() - Sets the tx power for MLME_SET phyTransmitPower
  1264. * @txp: Transmit Power
  1265. * @device_ref: Nondescript pointer to target device
  1266. *
  1267. * Normalised to 802.15.4 Definition (6-bit, signed):
  1268. * Bit 7-6: not used
  1269. * Bit 5-0: tx power (-32 - +31 dB)
  1270. *
  1271. * Return: 802.15.4 status code of api calls
  1272. */
  1273. static u8 tdme_settxpower(u8 txp, void *device_ref)
  1274. {
  1275. u8 status;
  1276. s8 txp_val;
  1277. u8 txp_ext;
  1278. union pa_cfg_sfr pa_cfg_val;
  1279. /* extend from 6 to 8 bit */
  1280. txp_ext = 0x3F & txp;
  1281. if (txp_ext & 0x20)
  1282. txp_ext += 0xC0;
  1283. txp_val = (s8)txp_ext;
  1284. if (CA8210_MAC_MPW) {
  1285. if (txp_val > 0) {
  1286. /* 8 dBm: ptrim = 5, itrim = +3 => +4 dBm */
  1287. pa_cfg_val.bias_current_trim = 3;
  1288. pa_cfg_val.buffer_capacitor_trim = 5;
  1289. pa_cfg_val.boost = 1;
  1290. } else {
  1291. /* 0 dBm: ptrim = 7, itrim = +3 => -6 dBm */
  1292. pa_cfg_val.bias_current_trim = 3;
  1293. pa_cfg_val.buffer_capacitor_trim = 7;
  1294. pa_cfg_val.boost = 0;
  1295. }
  1296. /* write PACFG */
  1297. status = tdme_setsfr_request_sync(
  1298. 0,
  1299. CA8210_SFR_PACFG,
  1300. pa_cfg_val.paib,
  1301. device_ref
  1302. );
  1303. } else {
  1304. /* Look-Up Table for Setting Current and Frequency Trim values
  1305. * for desired Output Power
  1306. */
  1307. if (txp_val > 8) {
  1308. pa_cfg_val.paib = 0x3F;
  1309. } else if (txp_val == 8) {
  1310. pa_cfg_val.paib = 0x32;
  1311. } else if (txp_val == 7) {
  1312. pa_cfg_val.paib = 0x22;
  1313. } else if (txp_val == 6) {
  1314. pa_cfg_val.paib = 0x18;
  1315. } else if (txp_val == 5) {
  1316. pa_cfg_val.paib = 0x10;
  1317. } else if (txp_val == 4) {
  1318. pa_cfg_val.paib = 0x0C;
  1319. } else if (txp_val == 3) {
  1320. pa_cfg_val.paib = 0x08;
  1321. } else if (txp_val == 2) {
  1322. pa_cfg_val.paib = 0x05;
  1323. } else if (txp_val == 1) {
  1324. pa_cfg_val.paib = 0x03;
  1325. } else if (txp_val == 0) {
  1326. pa_cfg_val.paib = 0x01;
  1327. } else { /* < 0 */
  1328. pa_cfg_val.paib = 0x00;
  1329. }
  1330. /* write PACFGIB */
  1331. status = tdme_setsfr_request_sync(
  1332. 0,
  1333. CA8210_SFR_PACFGIB,
  1334. pa_cfg_val.paib,
  1335. device_ref
  1336. );
  1337. }
  1338. return status;
  1339. }
  1340. /**
  1341. * mcps_data_request() - mcps_data_request (Send Data) according to API Spec
  1342. * @src_addr_mode: Source Addressing Mode
  1343. * @dst_address_mode: Destination Addressing Mode
  1344. * @dst_pan_id: Destination PAN ID
  1345. * @dst_addr: Pointer to Destination Address
  1346. * @msdu_length: length of Data
  1347. * @msdu: Pointer to Data
  1348. * @msdu_handle: Handle of Data
  1349. * @tx_options: Tx Options Bit Field
  1350. * @security: Pointer to Security Structure or NULL
  1351. * @device_ref: Nondescript pointer to target device
  1352. *
  1353. * Return: 802.15.4 status code of action
  1354. */
  1355. static u8 mcps_data_request(
  1356. u8 src_addr_mode,
  1357. u8 dst_address_mode,
  1358. u16 dst_pan_id,
  1359. union macaddr *dst_addr,
  1360. u8 msdu_length,
  1361. u8 *msdu,
  1362. u8 msdu_handle,
  1363. u8 tx_options,
  1364. struct secspec *security,
  1365. void *device_ref
  1366. )
  1367. {
  1368. struct secspec *psec;
  1369. struct mac_message command;
  1370. command.command_id = SPI_MCPS_DATA_REQUEST;
  1371. command.pdata.data_req.src_addr_mode = src_addr_mode;
  1372. command.pdata.data_req.dst.mode = dst_address_mode;
  1373. if (dst_address_mode != MAC_MODE_NO_ADDR) {
  1374. command.pdata.data_req.dst.pan_id[0] = LS_BYTE(dst_pan_id);
  1375. command.pdata.data_req.dst.pan_id[1] = MS_BYTE(dst_pan_id);
  1376. if (dst_address_mode == MAC_MODE_SHORT_ADDR) {
  1377. command.pdata.data_req.dst.address[0] = LS_BYTE(
  1378. dst_addr->short_address
  1379. );
  1380. command.pdata.data_req.dst.address[1] = MS_BYTE(
  1381. dst_addr->short_address
  1382. );
  1383. } else { /* MAC_MODE_LONG_ADDR*/
  1384. memcpy(
  1385. command.pdata.data_req.dst.address,
  1386. dst_addr->ieee_address,
  1387. 8
  1388. );
  1389. }
  1390. }
  1391. command.pdata.data_req.msdu_length = msdu_length;
  1392. command.pdata.data_req.msdu_handle = msdu_handle;
  1393. command.pdata.data_req.tx_options = tx_options;
  1394. memcpy(command.pdata.data_req.msdu, msdu, msdu_length);
  1395. psec = (struct secspec *)(command.pdata.data_req.msdu + msdu_length);
  1396. command.length = sizeof(struct mcps_data_request_pset) -
  1397. MAX_DATA_SIZE + msdu_length;
  1398. if (!security || (security->security_level == 0)) {
  1399. psec->security_level = 0;
  1400. command.length += 1;
  1401. } else {
  1402. *psec = *security;
  1403. command.length += sizeof(struct secspec);
  1404. }
  1405. if (ca8210_spi_transfer(device_ref, &command.command_id,
  1406. command.length + 2))
  1407. return MAC_SYSTEM_ERROR;
  1408. return MAC_SUCCESS;
  1409. }
  1410. /**
  1411. * mlme_reset_request_sync() - MLME_RESET_request/confirm according to API Spec
  1412. * @set_default_pib: Set defaults in PIB
  1413. * @device_ref: Nondescript pointer to target device
  1414. *
  1415. * Return: 802.15.4 status code of MLME-RESET.confirm
  1416. */
  1417. static u8 mlme_reset_request_sync(
  1418. u8 set_default_pib,
  1419. void *device_ref
  1420. )
  1421. {
  1422. u8 status;
  1423. struct mac_message command, response;
  1424. struct spi_device *spi = device_ref;
  1425. command.command_id = SPI_MLME_RESET_REQUEST;
  1426. command.length = 1;
  1427. command.pdata.u8param = set_default_pib;
  1428. if (cascoda_api_downstream(
  1429. &command.command_id,
  1430. command.length + 2,
  1431. &response.command_id,
  1432. device_ref)) {
  1433. dev_err(&spi->dev, "cascoda_api_downstream failed\n");
  1434. return MAC_SYSTEM_ERROR;
  1435. }
  1436. if (response.command_id != SPI_MLME_RESET_CONFIRM)
  1437. return MAC_SYSTEM_ERROR;
  1438. status = response.pdata.status;
  1439. /* reset COORD Bit for Channel Filtering as Coordinator */
  1440. if (CA8210_MAC_WORKAROUNDS && set_default_pib && (!status)) {
  1441. status = tdme_setsfr_request_sync(
  1442. 0,
  1443. CA8210_SFR_MACCON,
  1444. 0,
  1445. device_ref
  1446. );
  1447. }
  1448. return status;
  1449. }
  1450. /**
  1451. * mlme_set_request_sync() - MLME_SET_request/confirm according to API Spec
  1452. * @pib_attribute: Attribute Number
  1453. * @pib_attribute_index: Index within Attribute if an Array
  1454. * @pib_attribute_length: Attribute length
  1455. * @pib_attribute_value: Pointer to Attribute Value
  1456. * @device_ref: Nondescript pointer to target device
  1457. *
  1458. * Return: 802.15.4 status code of MLME-SET.confirm
  1459. */
  1460. static u8 mlme_set_request_sync(
  1461. u8 pib_attribute,
  1462. u8 pib_attribute_index,
  1463. u8 pib_attribute_length,
  1464. const void *pib_attribute_value,
  1465. void *device_ref
  1466. )
  1467. {
  1468. u8 status;
  1469. struct mac_message command, response;
  1470. /* pre-check the validity of pib_attribute values that are not checked
  1471. * in MAC
  1472. */
  1473. if (tdme_checkpibattribute(
  1474. pib_attribute, pib_attribute_length, pib_attribute_value)) {
  1475. return MAC_INVALID_PARAMETER;
  1476. }
  1477. if (pib_attribute == PHY_CURRENT_CHANNEL) {
  1478. status = tdme_channelinit(
  1479. *((u8 *)pib_attribute_value),
  1480. device_ref
  1481. );
  1482. if (status)
  1483. return status;
  1484. }
  1485. if (pib_attribute == PHY_TRANSMIT_POWER) {
  1486. return tdme_settxpower(
  1487. *((u8 *)pib_attribute_value),
  1488. device_ref
  1489. );
  1490. }
  1491. command.command_id = SPI_MLME_SET_REQUEST;
  1492. command.length = sizeof(struct mlme_set_request_pset) -
  1493. MAX_ATTRIBUTE_SIZE + pib_attribute_length;
  1494. command.pdata.set_req.pib_attribute = pib_attribute;
  1495. command.pdata.set_req.pib_attribute_index = pib_attribute_index;
  1496. command.pdata.set_req.pib_attribute_length = pib_attribute_length;
  1497. memcpy(
  1498. command.pdata.set_req.pib_attribute_value,
  1499. pib_attribute_value,
  1500. pib_attribute_length
  1501. );
  1502. if (cascoda_api_downstream(
  1503. &command.command_id,
  1504. command.length + 2,
  1505. &response.command_id,
  1506. device_ref)) {
  1507. return MAC_SYSTEM_ERROR;
  1508. }
  1509. if (response.command_id != SPI_MLME_SET_CONFIRM)
  1510. return MAC_SYSTEM_ERROR;
  1511. return response.pdata.status;
  1512. }
  1513. /**
  1514. * hwme_set_request_sync() - HWME_SET_request/confirm according to API Spec
  1515. * @hw_attribute: Attribute Number
  1516. * @hw_attribute_length: Attribute length
  1517. * @hw_attribute_value: Pointer to Attribute Value
  1518. * @device_ref: Nondescript pointer to target device
  1519. *
  1520. * Return: 802.15.4 status code of HWME-SET.confirm
  1521. */
  1522. static u8 hwme_set_request_sync(
  1523. u8 hw_attribute,
  1524. u8 hw_attribute_length,
  1525. u8 *hw_attribute_value,
  1526. void *device_ref
  1527. )
  1528. {
  1529. struct mac_message command, response;
  1530. command.command_id = SPI_HWME_SET_REQUEST;
  1531. command.length = 2 + hw_attribute_length;
  1532. command.pdata.hwme_set_req.hw_attribute = hw_attribute;
  1533. command.pdata.hwme_set_req.hw_attribute_length = hw_attribute_length;
  1534. memcpy(
  1535. command.pdata.hwme_set_req.hw_attribute_value,
  1536. hw_attribute_value,
  1537. hw_attribute_length
  1538. );
  1539. if (cascoda_api_downstream(
  1540. &command.command_id,
  1541. command.length + 2,
  1542. &response.command_id,
  1543. device_ref)) {
  1544. return MAC_SYSTEM_ERROR;
  1545. }
  1546. if (response.command_id != SPI_HWME_SET_CONFIRM)
  1547. return MAC_SYSTEM_ERROR;
  1548. return response.pdata.hwme_set_cnf.status;
  1549. }
  1550. /**
  1551. * hwme_get_request_sync() - HWME_GET_request/confirm according to API Spec
  1552. * @hw_attribute: Attribute Number
  1553. * @hw_attribute_length: Attribute length
  1554. * @hw_attribute_value: Pointer to Attribute Value
  1555. * @device_ref: Nondescript pointer to target device
  1556. *
  1557. * Return: 802.15.4 status code of HWME-GET.confirm
  1558. */
  1559. static u8 hwme_get_request_sync(
  1560. u8 hw_attribute,
  1561. u8 *hw_attribute_length,
  1562. u8 *hw_attribute_value,
  1563. void *device_ref
  1564. )
  1565. {
  1566. struct mac_message command, response;
  1567. command.command_id = SPI_HWME_GET_REQUEST;
  1568. command.length = 1;
  1569. command.pdata.hwme_get_req.hw_attribute = hw_attribute;
  1570. if (cascoda_api_downstream(
  1571. &command.command_id,
  1572. command.length + 2,
  1573. &response.command_id,
  1574. device_ref)) {
  1575. return MAC_SYSTEM_ERROR;
  1576. }
  1577. if (response.command_id != SPI_HWME_GET_CONFIRM)
  1578. return MAC_SYSTEM_ERROR;
  1579. if (response.pdata.hwme_get_cnf.status == MAC_SUCCESS) {
  1580. *hw_attribute_length =
  1581. response.pdata.hwme_get_cnf.hw_attribute_length;
  1582. memcpy(
  1583. hw_attribute_value,
  1584. response.pdata.hwme_get_cnf.hw_attribute_value,
  1585. *hw_attribute_length
  1586. );
  1587. }
  1588. return response.pdata.hwme_get_cnf.status;
  1589. }
  1590. /* Network driver operation */
  1591. /**
  1592. * ca8210_async_xmit_complete() - Called to announce that an asynchronous
  1593. * transmission has finished
  1594. * @hw: ieee802154_hw of ca8210 that has finished exchange
  1595. * @msduhandle: Identifier of transmission that has completed
  1596. * @status: Returned 802.15.4 status code of the transmission
  1597. *
  1598. * Return: 0 or linux error code
  1599. */
  1600. static int ca8210_async_xmit_complete(
  1601. struct ieee802154_hw *hw,
  1602. u8 msduhandle,
  1603. u8 status)
  1604. {
  1605. struct ca8210_priv *priv = hw->priv;
  1606. if (priv->nextmsduhandle != msduhandle) {
  1607. dev_err(
  1608. &priv->spi->dev,
  1609. "Unexpected msdu_handle on data confirm, Expected %d, got %d\n",
  1610. priv->nextmsduhandle,
  1611. msduhandle
  1612. );
  1613. return -EIO;
  1614. }
  1615. priv->async_tx_pending = false;
  1616. priv->nextmsduhandle++;
  1617. if (status) {
  1618. dev_err(
  1619. &priv->spi->dev,
  1620. "Link transmission unsuccessful, status = %d\n",
  1621. status
  1622. );
  1623. if (status != MAC_TRANSACTION_OVERFLOW) {
  1624. ieee802154_wake_queue(priv->hw);
  1625. return 0;
  1626. }
  1627. }
  1628. ieee802154_xmit_complete(priv->hw, priv->tx_skb, true);
  1629. return 0;
  1630. }
  1631. /**
  1632. * ca8210_skb_rx() - Contructs a properly framed socket buffer from a received
  1633. * MCPS_DATA_indication
  1634. * @hw: ieee802154_hw that MCPS_DATA_indication was received by
  1635. * @len: length of MCPS_DATA_indication
  1636. * @data_ind: Octet array of MCPS_DATA_indication
  1637. *
  1638. * Called by the spi driver whenever a SAP command is received, this function
  1639. * will ascertain whether the command is of interest to the network driver and
  1640. * take necessary action.
  1641. *
  1642. * Return: 0 or linux error code
  1643. */
  1644. static int ca8210_skb_rx(
  1645. struct ieee802154_hw *hw,
  1646. size_t len,
  1647. u8 *data_ind
  1648. )
  1649. {
  1650. struct ieee802154_hdr hdr;
  1651. int msdulen;
  1652. int hlen;
  1653. u8 mpdulinkquality = data_ind[23];
  1654. struct sk_buff *skb;
  1655. struct ca8210_priv *priv = hw->priv;
  1656. /* Allocate mtu size buffer for every rx packet */
  1657. skb = dev_alloc_skb(IEEE802154_MTU + sizeof(hdr));
  1658. if (!skb) {
  1659. dev_crit(&priv->spi->dev, "dev_alloc_skb failed\n");
  1660. return -ENOMEM;
  1661. }
  1662. skb_reserve(skb, sizeof(hdr));
  1663. msdulen = data_ind[22]; /* msdu_length */
  1664. if (msdulen > IEEE802154_MTU) {
  1665. dev_err(
  1666. &priv->spi->dev,
  1667. "received erroneously large msdu length!\n"
  1668. );
  1669. kfree_skb(skb);
  1670. return -EMSGSIZE;
  1671. }
  1672. dev_dbg(&priv->spi->dev, "skb buffer length = %d\n", msdulen);
  1673. if (priv->promiscuous)
  1674. goto copy_payload;
  1675. /* Populate hdr */
  1676. hdr.sec.level = data_ind[29 + msdulen];
  1677. dev_dbg(&priv->spi->dev, "security level: %#03x\n", hdr.sec.level);
  1678. if (hdr.sec.level > 0) {
  1679. hdr.sec.key_id_mode = data_ind[30 + msdulen];
  1680. memcpy(&hdr.sec.extended_src, &data_ind[31 + msdulen], 8);
  1681. hdr.sec.key_id = data_ind[39 + msdulen];
  1682. }
  1683. hdr.source.mode = data_ind[0];
  1684. dev_dbg(&priv->spi->dev, "srcAddrMode: %#03x\n", hdr.source.mode);
  1685. hdr.source.pan_id = *(u16 *)&data_ind[1];
  1686. dev_dbg(&priv->spi->dev, "srcPanId: %#06x\n", hdr.source.pan_id);
  1687. memcpy(&hdr.source.extended_addr, &data_ind[3], 8);
  1688. hdr.dest.mode = data_ind[11];
  1689. dev_dbg(&priv->spi->dev, "dstAddrMode: %#03x\n", hdr.dest.mode);
  1690. hdr.dest.pan_id = *(u16 *)&data_ind[12];
  1691. dev_dbg(&priv->spi->dev, "dstPanId: %#06x\n", hdr.dest.pan_id);
  1692. memcpy(&hdr.dest.extended_addr, &data_ind[14], 8);
  1693. /* Fill in FC implicitly */
  1694. hdr.fc.type = 1; /* Data frame */
  1695. if (hdr.sec.level)
  1696. hdr.fc.security_enabled = 1;
  1697. else
  1698. hdr.fc.security_enabled = 0;
  1699. if (data_ind[1] != data_ind[12] || data_ind[2] != data_ind[13])
  1700. hdr.fc.intra_pan = 1;
  1701. else
  1702. hdr.fc.intra_pan = 0;
  1703. hdr.fc.dest_addr_mode = hdr.dest.mode;
  1704. hdr.fc.source_addr_mode = hdr.source.mode;
  1705. /* Add hdr to front of buffer */
  1706. hlen = ieee802154_hdr_push(skb, &hdr);
  1707. if (hlen < 0) {
  1708. dev_crit(&priv->spi->dev, "failed to push mac hdr onto skb!\n");
  1709. kfree_skb(skb);
  1710. return hlen;
  1711. }
  1712. skb_reset_mac_header(skb);
  1713. skb->mac_len = hlen;
  1714. copy_payload:
  1715. /* Add <msdulen> bytes of space to the back of the buffer */
  1716. /* Copy msdu to skb */
  1717. memcpy(skb_put(skb, msdulen), &data_ind[29], msdulen);
  1718. ieee802154_rx_irqsafe(hw, skb, mpdulinkquality);
  1719. return 0;
  1720. }
  1721. /**
  1722. * ca8210_net_rx() - Acts upon received SAP commands relevant to the network
  1723. * driver
  1724. * @hw: ieee802154_hw that command was received by
  1725. * @command: Octet array of received command
  1726. * @len: length of the received command
  1727. *
  1728. * Called by the spi driver whenever a SAP command is received, this function
  1729. * will ascertain whether the command is of interest to the network driver and
  1730. * take necessary action.
  1731. *
  1732. * Return: 0 or linux error code
  1733. */
  1734. static int ca8210_net_rx(struct ieee802154_hw *hw, u8 *command, size_t len)
  1735. {
  1736. struct ca8210_priv *priv = hw->priv;
  1737. unsigned long flags;
  1738. u8 status;
  1739. dev_dbg(&priv->spi->dev, "ca8210_net_rx(), CmdID = %d\n", command[0]);
  1740. if (command[0] == SPI_MCPS_DATA_INDICATION) {
  1741. /* Received data */
  1742. spin_lock_irqsave(&priv->lock, flags);
  1743. if (command[26] == priv->last_dsn) {
  1744. dev_dbg(
  1745. &priv->spi->dev,
  1746. "DSN %d resend received, ignoring...\n",
  1747. command[26]
  1748. );
  1749. spin_unlock_irqrestore(&priv->lock, flags);
  1750. return 0;
  1751. }
  1752. priv->last_dsn = command[26];
  1753. spin_unlock_irqrestore(&priv->lock, flags);
  1754. return ca8210_skb_rx(hw, len - 2, command + 2);
  1755. } else if (command[0] == SPI_MCPS_DATA_CONFIRM) {
  1756. status = command[3];
  1757. if (priv->async_tx_pending) {
  1758. return ca8210_async_xmit_complete(
  1759. hw,
  1760. command[2],
  1761. status
  1762. );
  1763. }
  1764. }
  1765. return 0;
  1766. }
  1767. /**
  1768. * ca8210_skb_tx() - Transmits a given socket buffer using the ca8210
  1769. * @skb: Socket buffer to transmit
  1770. * @msduhandle: Data identifier to pass to the 802.15.4 MAC
  1771. * @priv: Pointer to private data section of target ca8210
  1772. *
  1773. * Return: 0 or linux error code
  1774. */
  1775. static int ca8210_skb_tx(
  1776. struct sk_buff *skb,
  1777. u8 msduhandle,
  1778. struct ca8210_priv *priv
  1779. )
  1780. {
  1781. int status;
  1782. struct ieee802154_hdr header = { 0 };
  1783. struct secspec secspec;
  1784. unsigned int mac_len;
  1785. dev_dbg(&priv->spi->dev, "ca8210_skb_tx() called\n");
  1786. /* Get addressing info from skb - ieee802154 layer creates a full
  1787. * packet
  1788. */
  1789. mac_len = ieee802154_hdr_peek_addrs(skb, &header);
  1790. secspec.security_level = header.sec.level;
  1791. secspec.key_id_mode = header.sec.key_id_mode;
  1792. if (secspec.key_id_mode == 2)
  1793. memcpy(secspec.key_source, &header.sec.short_src, 4);
  1794. else if (secspec.key_id_mode == 3)
  1795. memcpy(secspec.key_source, &header.sec.extended_src, 8);
  1796. secspec.key_index = header.sec.key_id;
  1797. /* Pass to Cascoda API */
  1798. status = mcps_data_request(
  1799. header.source.mode,
  1800. header.dest.mode,
  1801. header.dest.pan_id,
  1802. (union macaddr *)&header.dest.extended_addr,
  1803. skb->len - mac_len,
  1804. &skb->data[mac_len],
  1805. msduhandle,
  1806. header.fc.ack_request,
  1807. &secspec,
  1808. priv->spi
  1809. );
  1810. return link_to_linux_err(status);
  1811. }
  1812. /**
  1813. * ca8210_start() - Starts the network driver
  1814. * @hw: ieee802154_hw of ca8210 being started
  1815. *
  1816. * Return: 0 or linux error code
  1817. */
  1818. static int ca8210_start(struct ieee802154_hw *hw)
  1819. {
  1820. int status;
  1821. u8 rx_on_when_idle;
  1822. u8 lqi_threshold = 0;
  1823. struct ca8210_priv *priv = hw->priv;
  1824. priv->last_dsn = -1;
  1825. /* Turn receiver on when idle for now just to test rx */
  1826. rx_on_when_idle = 1;
  1827. status = mlme_set_request_sync(
  1828. MAC_RX_ON_WHEN_IDLE,
  1829. 0,
  1830. 1,
  1831. &rx_on_when_idle,
  1832. priv->spi
  1833. );
  1834. if (status) {
  1835. dev_crit(
  1836. &priv->spi->dev,
  1837. "Setting rx_on_when_idle failed, status = %d\n",
  1838. status
  1839. );
  1840. return link_to_linux_err(status);
  1841. }
  1842. status = hwme_set_request_sync(
  1843. HWME_LQILIMIT,
  1844. 1,
  1845. &lqi_threshold,
  1846. priv->spi
  1847. );
  1848. if (status) {
  1849. dev_crit(
  1850. &priv->spi->dev,
  1851. "Setting lqilimit failed, status = %d\n",
  1852. status
  1853. );
  1854. return link_to_linux_err(status);
  1855. }
  1856. return 0;
  1857. }
  1858. /**
  1859. * ca8210_stop() - Stops the network driver
  1860. * @hw: ieee802154_hw of ca8210 being stopped
  1861. *
  1862. * Return: 0 or linux error code
  1863. */
  1864. static void ca8210_stop(struct ieee802154_hw *hw)
  1865. {
  1866. }
  1867. /**
  1868. * ca8210_xmit_async() - Asynchronously transmits a given socket buffer using
  1869. * the ca8210
  1870. * @hw: ieee802154_hw of ca8210 to transmit from
  1871. * @skb: Socket buffer to transmit
  1872. *
  1873. * Return: 0 or linux error code
  1874. */
  1875. static int ca8210_xmit_async(struct ieee802154_hw *hw, struct sk_buff *skb)
  1876. {
  1877. struct ca8210_priv *priv = hw->priv;
  1878. int status;
  1879. dev_dbg(&priv->spi->dev, "calling ca8210_xmit_async()\n");
  1880. priv->tx_skb = skb;
  1881. priv->async_tx_pending = true;
  1882. status = ca8210_skb_tx(skb, priv->nextmsduhandle, priv);
  1883. return status;
  1884. }
  1885. /**
  1886. * ca8210_get_ed() - Returns the measured energy on the current channel at this
  1887. * instant in time
  1888. * @hw: ieee802154_hw of target ca8210
  1889. * @level: Measured Energy Detect level
  1890. *
  1891. * Return: 0 or linux error code
  1892. */
  1893. static int ca8210_get_ed(struct ieee802154_hw *hw, u8 *level)
  1894. {
  1895. u8 lenvar;
  1896. struct ca8210_priv *priv = hw->priv;
  1897. return link_to_linux_err(
  1898. hwme_get_request_sync(HWME_EDVALUE, &lenvar, level, priv->spi)
  1899. );
  1900. }
  1901. /**
  1902. * ca8210_set_channel() - Sets the current operating 802.15.4 channel of the
  1903. * ca8210
  1904. * @hw: ieee802154_hw of target ca8210
  1905. * @page: Channel page to set
  1906. * @channel: Channel number to set
  1907. *
  1908. * Return: 0 or linux error code
  1909. */
  1910. static int ca8210_set_channel(
  1911. struct ieee802154_hw *hw,
  1912. u8 page,
  1913. u8 channel
  1914. )
  1915. {
  1916. u8 status;
  1917. struct ca8210_priv *priv = hw->priv;
  1918. status = mlme_set_request_sync(
  1919. PHY_CURRENT_CHANNEL,
  1920. 0,
  1921. 1,
  1922. &channel,
  1923. priv->spi
  1924. );
  1925. if (status) {
  1926. dev_err(
  1927. &priv->spi->dev,
  1928. "error setting channel, MLME-SET.confirm status = %d\n",
  1929. status
  1930. );
  1931. }
  1932. return link_to_linux_err(status);
  1933. }
  1934. /**
  1935. * ca8210_set_hw_addr_filt() - Sets the address filtering parameters of the
  1936. * ca8210
  1937. * @hw: ieee802154_hw of target ca8210
  1938. * @filt: Filtering parameters
  1939. * @changed: Bitmap representing which parameters to change
  1940. *
  1941. * Effectively just sets the actual addressing information identifying this node
  1942. * as all filtering is performed by the ca8210 as detailed in the IEEE 802.15.4
  1943. * 2006 specification.
  1944. *
  1945. * Return: 0 or linux error code
  1946. */
  1947. static int ca8210_set_hw_addr_filt(
  1948. struct ieee802154_hw *hw,
  1949. struct ieee802154_hw_addr_filt *filt,
  1950. unsigned long changed
  1951. )
  1952. {
  1953. u8 status = 0;
  1954. struct ca8210_priv *priv = hw->priv;
  1955. if (changed & IEEE802154_AFILT_PANID_CHANGED) {
  1956. status = mlme_set_request_sync(
  1957. MAC_PAN_ID,
  1958. 0,
  1959. 2,
  1960. &filt->pan_id, priv->spi
  1961. );
  1962. if (status) {
  1963. dev_err(
  1964. &priv->spi->dev,
  1965. "error setting pan id, MLME-SET.confirm status = %d",
  1966. status
  1967. );
  1968. return link_to_linux_err(status);
  1969. }
  1970. }
  1971. if (changed & IEEE802154_AFILT_SADDR_CHANGED) {
  1972. status = mlme_set_request_sync(
  1973. MAC_SHORT_ADDRESS,
  1974. 0,
  1975. 2,
  1976. &filt->short_addr, priv->spi
  1977. );
  1978. if (status) {
  1979. dev_err(
  1980. &priv->spi->dev,
  1981. "error setting short address, MLME-SET.confirm status = %d",
  1982. status
  1983. );
  1984. return link_to_linux_err(status);
  1985. }
  1986. }
  1987. if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) {
  1988. status = mlme_set_request_sync(
  1989. NS_IEEE_ADDRESS,
  1990. 0,
  1991. 8,
  1992. &filt->ieee_addr,
  1993. priv->spi
  1994. );
  1995. if (status) {
  1996. dev_err(
  1997. &priv->spi->dev,
  1998. "error setting ieee address, MLME-SET.confirm status = %d",
  1999. status
  2000. );
  2001. return link_to_linux_err(status);
  2002. }
  2003. }
  2004. /* TODO: Should use MLME_START to set coord bit? */
  2005. return 0;
  2006. }
  2007. /**
  2008. * ca8210_set_tx_power() - Sets the transmit power of the ca8210
  2009. * @hw: ieee802154_hw of target ca8210
  2010. * @mbm: Transmit power in mBm (dBm*100)
  2011. *
  2012. * Return: 0 or linux error code
  2013. */
  2014. static int ca8210_set_tx_power(struct ieee802154_hw *hw, s32 mbm)
  2015. {
  2016. struct ca8210_priv *priv = hw->priv;
  2017. mbm /= 100;
  2018. return link_to_linux_err(
  2019. mlme_set_request_sync(PHY_TRANSMIT_POWER, 0, 1, &mbm, priv->spi)
  2020. );
  2021. }
  2022. /**
  2023. * ca8210_set_cca_mode() - Sets the clear channel assessment mode of the ca8210
  2024. * @hw: ieee802154_hw of target ca8210
  2025. * @cca: CCA mode to set
  2026. *
  2027. * Return: 0 or linux error code
  2028. */
  2029. static int ca8210_set_cca_mode(
  2030. struct ieee802154_hw *hw,
  2031. const struct wpan_phy_cca *cca
  2032. )
  2033. {
  2034. u8 status;
  2035. u8 cca_mode;
  2036. struct ca8210_priv *priv = hw->priv;
  2037. cca_mode = cca->mode & 3;
  2038. if (cca_mode == 3 && cca->opt == NL802154_CCA_OPT_ENERGY_CARRIER_OR) {
  2039. /* cca_mode 0 == CS OR ED, 3 == CS AND ED */
  2040. cca_mode = 0;
  2041. }
  2042. status = mlme_set_request_sync(
  2043. PHY_CCA_MODE,
  2044. 0,
  2045. 1,
  2046. &cca_mode,
  2047. priv->spi
  2048. );
  2049. if (status) {
  2050. dev_err(
  2051. &priv->spi->dev,
  2052. "error setting cca mode, MLME-SET.confirm status = %d",
  2053. status
  2054. );
  2055. }
  2056. return link_to_linux_err(status);
  2057. }
  2058. /**
  2059. * ca8210_set_cca_ed_level() - Sets the CCA ED level of the ca8210
  2060. * @hw: ieee802154_hw of target ca8210
  2061. * @level: ED level to set (in mbm)
  2062. *
  2063. * Sets the minimum threshold of measured energy above which the ca8210 will
  2064. * back off and retry a transmission.
  2065. *
  2066. * Return: 0 or linux error code
  2067. */
  2068. static int ca8210_set_cca_ed_level(struct ieee802154_hw *hw, s32 level)
  2069. {
  2070. u8 status;
  2071. u8 ed_threshold = (level / 100) * 2 + 256;
  2072. struct ca8210_priv *priv = hw->priv;
  2073. status = hwme_set_request_sync(
  2074. HWME_EDTHRESHOLD,
  2075. 1,
  2076. &ed_threshold,
  2077. priv->spi
  2078. );
  2079. if (status) {
  2080. dev_err(
  2081. &priv->spi->dev,
  2082. "error setting ed threshold, HWME-SET.confirm status = %d",
  2083. status
  2084. );
  2085. }
  2086. return link_to_linux_err(status);
  2087. }
  2088. /**
  2089. * ca8210_set_csma_params() - Sets the CSMA parameters of the ca8210
  2090. * @hw: ieee802154_hw of target ca8210
  2091. * @min_be: Minimum backoff exponent when backing off a transmission
  2092. * @max_be: Maximum backoff exponent when backing off a transmission
  2093. * @retries: Number of times to retry after backing off
  2094. *
  2095. * Return: 0 or linux error code
  2096. */
  2097. static int ca8210_set_csma_params(
  2098. struct ieee802154_hw *hw,
  2099. u8 min_be,
  2100. u8 max_be,
  2101. u8 retries
  2102. )
  2103. {
  2104. u8 status;
  2105. struct ca8210_priv *priv = hw->priv;
  2106. status = mlme_set_request_sync(MAC_MIN_BE, 0, 1, &min_be, priv->spi);
  2107. if (status) {
  2108. dev_err(
  2109. &priv->spi->dev,
  2110. "error setting min be, MLME-SET.confirm status = %d",
  2111. status
  2112. );
  2113. return link_to_linux_err(status);
  2114. }
  2115. status = mlme_set_request_sync(MAC_MAX_BE, 0, 1, &max_be, priv->spi);
  2116. if (status) {
  2117. dev_err(
  2118. &priv->spi->dev,
  2119. "error setting max be, MLME-SET.confirm status = %d",
  2120. status
  2121. );
  2122. return link_to_linux_err(status);
  2123. }
  2124. status = mlme_set_request_sync(
  2125. MAC_MAX_CSMA_BACKOFFS,
  2126. 0,
  2127. 1,
  2128. &retries,
  2129. priv->spi
  2130. );
  2131. if (status) {
  2132. dev_err(
  2133. &priv->spi->dev,
  2134. "error setting max csma backoffs, MLME-SET.confirm status = %d",
  2135. status
  2136. );
  2137. }
  2138. return link_to_linux_err(status);
  2139. }
  2140. /**
  2141. * ca8210_set_frame_retries() - Sets the maximum frame retries of the ca8210
  2142. * @hw: ieee802154_hw of target ca8210
  2143. * @retries: Number of retries
  2144. *
  2145. * Sets the number of times to retry a transmission if no acknowledgment was
  2146. * was received from the other end when one was requested.
  2147. *
  2148. * Return: 0 or linux error code
  2149. */
  2150. static int ca8210_set_frame_retries(struct ieee802154_hw *hw, s8 retries)
  2151. {
  2152. u8 status;
  2153. struct ca8210_priv *priv = hw->priv;
  2154. status = mlme_set_request_sync(
  2155. MAC_MAX_FRAME_RETRIES,
  2156. 0,
  2157. 1,
  2158. &retries,
  2159. priv->spi
  2160. );
  2161. if (status) {
  2162. dev_err(
  2163. &priv->spi->dev,
  2164. "error setting frame retries, MLME-SET.confirm status = %d",
  2165. status
  2166. );
  2167. }
  2168. return link_to_linux_err(status);
  2169. }
  2170. static int ca8210_set_promiscuous_mode(struct ieee802154_hw *hw, const bool on)
  2171. {
  2172. u8 status;
  2173. struct ca8210_priv *priv = hw->priv;
  2174. status = mlme_set_request_sync(
  2175. MAC_PROMISCUOUS_MODE,
  2176. 0,
  2177. 1,
  2178. (const void*)&on,
  2179. priv->spi
  2180. );
  2181. if (status) {
  2182. dev_err(
  2183. &priv->spi->dev,
  2184. "error setting promiscuous mode, MLME-SET.confirm status = %d",
  2185. status
  2186. );
  2187. } else {
  2188. priv->promiscuous = on;
  2189. }
  2190. return link_to_linux_err(status);
  2191. }
  2192. static const struct ieee802154_ops ca8210_phy_ops = {
  2193. .start = ca8210_start,
  2194. .stop = ca8210_stop,
  2195. .xmit_async = ca8210_xmit_async,
  2196. .ed = ca8210_get_ed,
  2197. .set_channel = ca8210_set_channel,
  2198. .set_hw_addr_filt = ca8210_set_hw_addr_filt,
  2199. .set_txpower = ca8210_set_tx_power,
  2200. .set_cca_mode = ca8210_set_cca_mode,
  2201. .set_cca_ed_level = ca8210_set_cca_ed_level,
  2202. .set_csma_params = ca8210_set_csma_params,
  2203. .set_frame_retries = ca8210_set_frame_retries,
  2204. .set_promiscuous_mode = ca8210_set_promiscuous_mode
  2205. };
  2206. /* Test/EVBME Interface */
  2207. /**
  2208. * ca8210_test_int_open() - Opens the test interface to the userspace
  2209. * @inodp: inode representation of file interface
  2210. * @filp: file interface
  2211. *
  2212. * Return: 0 or linux error code
  2213. */
  2214. static int ca8210_test_int_open(struct inode *inodp, struct file *filp)
  2215. {
  2216. struct ca8210_priv *priv = inodp->i_private;
  2217. filp->private_data = priv;
  2218. return 0;
  2219. }
  2220. /**
  2221. * ca8210_test_check_upstream() - Checks a command received from the upstream
  2222. * testing interface for required action
  2223. * @buf: Buffer containing command to check
  2224. * @device_ref: Nondescript pointer to target device
  2225. *
  2226. * Return: 0 or linux error code
  2227. */
  2228. static int ca8210_test_check_upstream(u8 *buf, void *device_ref)
  2229. {
  2230. int ret;
  2231. u8 response[CA8210_SPI_BUF_SIZE];
  2232. if (buf[0] == SPI_MLME_SET_REQUEST) {
  2233. ret = tdme_checkpibattribute(buf[2], buf[4], buf + 5);
  2234. if (ret) {
  2235. response[0] = SPI_MLME_SET_CONFIRM;
  2236. response[1] = 3;
  2237. response[2] = MAC_INVALID_PARAMETER;
  2238. response[3] = buf[2];
  2239. response[4] = buf[3];
  2240. if (cascoda_api_upstream)
  2241. cascoda_api_upstream(response, 5, device_ref);
  2242. return ret;
  2243. }
  2244. }
  2245. if (buf[0] == SPI_MLME_ASSOCIATE_REQUEST) {
  2246. return tdme_channelinit(buf[2], device_ref);
  2247. } else if (buf[0] == SPI_MLME_START_REQUEST) {
  2248. return tdme_channelinit(buf[4], device_ref);
  2249. } else if (
  2250. (buf[0] == SPI_MLME_SET_REQUEST) &&
  2251. (buf[2] == PHY_CURRENT_CHANNEL)
  2252. ) {
  2253. return tdme_channelinit(buf[5], device_ref);
  2254. } else if (
  2255. (buf[0] == SPI_TDME_SET_REQUEST) &&
  2256. (buf[2] == TDME_CHANNEL)
  2257. ) {
  2258. return tdme_channelinit(buf[4], device_ref);
  2259. } else if (
  2260. (CA8210_MAC_WORKAROUNDS) &&
  2261. (buf[0] == SPI_MLME_RESET_REQUEST) &&
  2262. (buf[2] == 1)
  2263. ) {
  2264. /* reset COORD Bit for Channel Filtering as Coordinator */
  2265. return tdme_setsfr_request_sync(
  2266. 0,
  2267. CA8210_SFR_MACCON,
  2268. 0,
  2269. device_ref
  2270. );
  2271. }
  2272. return 0;
  2273. } /* End of EVBMECheckSerialCommand() */
  2274. /**
  2275. * ca8210_test_int_user_write() - Called by a process in userspace to send a
  2276. * message to the ca8210 drivers
  2277. * @filp: file interface
  2278. * @in_buf: Buffer containing message to write
  2279. * @len: length of message
  2280. * @off: file offset
  2281. *
  2282. * Return: 0 or linux error code
  2283. */
  2284. static ssize_t ca8210_test_int_user_write(
  2285. struct file *filp,
  2286. const char __user *in_buf,
  2287. size_t len,
  2288. loff_t *off
  2289. )
  2290. {
  2291. int ret;
  2292. struct ca8210_priv *priv = filp->private_data;
  2293. u8 command[CA8210_SPI_BUF_SIZE];
  2294. if (len > CA8210_SPI_BUF_SIZE) {
  2295. dev_warn(
  2296. &priv->spi->dev,
  2297. "userspace requested erroneously long write (%zu)\n",
  2298. len
  2299. );
  2300. return -EMSGSIZE;
  2301. }
  2302. ret = copy_from_user(command, in_buf, len);
  2303. if (ret) {
  2304. dev_err(
  2305. &priv->spi->dev,
  2306. "%d bytes could not be copied from userspace\n",
  2307. ret
  2308. );
  2309. return -EIO;
  2310. }
  2311. ret = ca8210_test_check_upstream(command, priv->spi);
  2312. if (ret == 0) {
  2313. ret = ca8210_spi_exchange(
  2314. command,
  2315. command[1] + 2,
  2316. NULL,
  2317. priv->spi
  2318. );
  2319. if (ret < 0) {
  2320. /* effectively 0 bytes were written successfully */
  2321. dev_err(
  2322. &priv->spi->dev,
  2323. "spi exchange failed\n"
  2324. );
  2325. return ret;
  2326. }
  2327. if (command[0] & SPI_SYN)
  2328. priv->sync_down++;
  2329. }
  2330. return len;
  2331. }
  2332. /**
  2333. * ca8210_test_int_user_read() - Called by a process in userspace to read a
  2334. * message from the ca8210 drivers
  2335. * @filp: file interface
  2336. * @buf: Buffer to write message to
  2337. * @len: length of message to read (ignored)
  2338. * @offp: file offset
  2339. *
  2340. * If the O_NONBLOCK flag was set when opening the file then this function will
  2341. * not block, i.e. it will return if the fifo is empty. Otherwise the function
  2342. * will block, i.e. wait until new data arrives.
  2343. *
  2344. * Return: number of bytes read
  2345. */
  2346. static ssize_t ca8210_test_int_user_read(
  2347. struct file *filp,
  2348. char __user *buf,
  2349. size_t len,
  2350. loff_t *offp
  2351. )
  2352. {
  2353. int i, cmdlen;
  2354. struct ca8210_priv *priv = filp->private_data;
  2355. unsigned char *fifo_buffer;
  2356. unsigned long bytes_not_copied;
  2357. if (filp->f_flags & O_NONBLOCK) {
  2358. /* Non-blocking mode */
  2359. if (kfifo_is_empty(&priv->test.up_fifo))
  2360. return 0;
  2361. } else {
  2362. /* Blocking mode */
  2363. wait_event_interruptible(
  2364. priv->test.readq,
  2365. !kfifo_is_empty(&priv->test.up_fifo)
  2366. );
  2367. }
  2368. if (kfifo_out(&priv->test.up_fifo, &fifo_buffer, 4) != 4) {
  2369. dev_err(
  2370. &priv->spi->dev,
  2371. "test_interface: Wrong number of elements popped from upstream fifo\n"
  2372. );
  2373. return 0;
  2374. }
  2375. cmdlen = fifo_buffer[1];
  2376. bytes_not_copied = cmdlen + 2;
  2377. bytes_not_copied = copy_to_user(buf, fifo_buffer, bytes_not_copied);
  2378. if (bytes_not_copied > 0) {
  2379. dev_err(
  2380. &priv->spi->dev,
  2381. "%lu bytes could not be copied to user space!\n",
  2382. bytes_not_copied
  2383. );
  2384. }
  2385. dev_dbg(&priv->spi->dev, "test_interface: Cmd len = %d\n", cmdlen);
  2386. dev_dbg(&priv->spi->dev, "test_interface: Read\n");
  2387. for (i = 0; i < cmdlen + 2; i++)
  2388. dev_dbg(&priv->spi->dev, "%#03x\n", fifo_buffer[i]);
  2389. kfree(fifo_buffer);
  2390. return cmdlen + 2;
  2391. }
  2392. /**
  2393. * ca8210_test_int_ioctl() - Called by a process in userspace to enact an
  2394. * arbitrary action
  2395. * @filp: file interface
  2396. * @ioctl_num: which action to enact
  2397. * @ioctl_param: arbitrary parameter for the action
  2398. *
  2399. * Return: status
  2400. */
  2401. static long ca8210_test_int_ioctl(
  2402. struct file *filp,
  2403. unsigned int ioctl_num,
  2404. unsigned long ioctl_param
  2405. )
  2406. {
  2407. struct ca8210_priv *priv = filp->private_data;
  2408. switch (ioctl_num) {
  2409. case CA8210_IOCTL_HARD_RESET:
  2410. ca8210_reset_send(priv->spi, ioctl_param);
  2411. break;
  2412. default:
  2413. break;
  2414. }
  2415. return 0;
  2416. }
  2417. /**
  2418. * ca8210_test_int_poll() - Called by a process in userspace to determine which
  2419. * actions are currently possible for the file
  2420. * @filp: file interface
  2421. * @ptable: poll table
  2422. *
  2423. * Return: set of poll return flags
  2424. */
  2425. static unsigned int ca8210_test_int_poll(
  2426. struct file *filp,
  2427. struct poll_table_struct *ptable
  2428. )
  2429. {
  2430. unsigned int return_flags = 0;
  2431. struct ca8210_priv *priv = filp->private_data;
  2432. poll_wait(filp, &priv->test.readq, ptable);
  2433. if (!kfifo_is_empty(&priv->test.up_fifo))
  2434. return_flags |= (POLLIN | POLLRDNORM);
  2435. if (wait_event_interruptible(
  2436. priv->test.readq,
  2437. !kfifo_is_empty(&priv->test.up_fifo))) {
  2438. return POLLERR;
  2439. }
  2440. return return_flags;
  2441. }
  2442. static const struct file_operations test_int_fops = {
  2443. .read = ca8210_test_int_user_read,
  2444. .write = ca8210_test_int_user_write,
  2445. .open = ca8210_test_int_open,
  2446. .release = NULL,
  2447. .unlocked_ioctl = ca8210_test_int_ioctl,
  2448. .poll = ca8210_test_int_poll
  2449. };
  2450. /* Init/Deinit */
  2451. /**
  2452. * ca8210_get_platform_data() - Populate a ca8210_platform_data object
  2453. * @spi_device: Pointer to ca8210 spi device object to get data for
  2454. * @pdata: Pointer to ca8210_platform_data object to populate
  2455. *
  2456. * Return: 0 or linux error code
  2457. */
  2458. static int ca8210_get_platform_data(
  2459. struct spi_device *spi_device,
  2460. struct ca8210_platform_data *pdata
  2461. )
  2462. {
  2463. int ret = 0;
  2464. if (!spi_device->dev.of_node)
  2465. return -EINVAL;
  2466. pdata->extclockenable = of_property_read_bool(
  2467. spi_device->dev.of_node,
  2468. "extclock-enable"
  2469. );
  2470. if (pdata->extclockenable) {
  2471. ret = of_property_read_u32(
  2472. spi_device->dev.of_node,
  2473. "extclock-freq",
  2474. &pdata->extclockfreq
  2475. );
  2476. if (ret < 0)
  2477. return ret;
  2478. ret = of_property_read_u32(
  2479. spi_device->dev.of_node,
  2480. "extclock-gpio",
  2481. &pdata->extclockgpio
  2482. );
  2483. }
  2484. return ret;
  2485. }
  2486. /**
  2487. * ca8210_config_extern_clk() - Configure the external clock provided by the
  2488. * ca8210
  2489. * @pdata: Pointer to ca8210_platform_data containing clock parameters
  2490. * @spi: Pointer to target ca8210 spi device
  2491. * @on: True to turn the clock on, false to turn off
  2492. *
  2493. * The external clock is configured with a frequency and output pin taken from
  2494. * the platform data.
  2495. *
  2496. * Return: 0 or linux error code
  2497. */
  2498. static int ca8210_config_extern_clk(
  2499. struct ca8210_platform_data *pdata,
  2500. struct spi_device *spi,
  2501. bool on
  2502. )
  2503. {
  2504. u8 clkparam[2];
  2505. if (on) {
  2506. dev_info(&spi->dev, "Switching external clock on\n");
  2507. switch (pdata->extclockfreq) {
  2508. case SIXTEEN_MHZ:
  2509. clkparam[0] = 1;
  2510. break;
  2511. case EIGHT_MHZ:
  2512. clkparam[0] = 2;
  2513. break;
  2514. case FOUR_MHZ:
  2515. clkparam[0] = 3;
  2516. break;
  2517. case TWO_MHZ:
  2518. clkparam[0] = 4;
  2519. break;
  2520. case ONE_MHZ:
  2521. clkparam[0] = 5;
  2522. break;
  2523. default:
  2524. dev_crit(&spi->dev, "Invalid extclock-freq\n");
  2525. return -EINVAL;
  2526. }
  2527. clkparam[1] = pdata->extclockgpio;
  2528. } else {
  2529. dev_info(&spi->dev, "Switching external clock off\n");
  2530. clkparam[0] = 0; /* off */
  2531. clkparam[1] = 0;
  2532. }
  2533. return link_to_linux_err(
  2534. hwme_set_request_sync(HWME_SYSCLKOUT, 2, clkparam, spi)
  2535. );
  2536. }
  2537. /**
  2538. * ca8210_register_ext_clock() - Register ca8210's external clock with kernel
  2539. * @spi: Pointer to target ca8210 spi device
  2540. *
  2541. * Return: 0 or linux error code
  2542. */
  2543. static int ca8210_register_ext_clock(struct spi_device *spi)
  2544. {
  2545. struct device_node *np = spi->dev.of_node;
  2546. struct ca8210_priv *priv = spi_get_drvdata(spi);
  2547. struct ca8210_platform_data *pdata = spi->dev.platform_data;
  2548. int ret = 0;
  2549. if (!np)
  2550. return -EFAULT;
  2551. priv->clk = clk_register_fixed_rate(
  2552. &spi->dev,
  2553. np->name,
  2554. NULL,
  2555. 0,
  2556. pdata->extclockfreq
  2557. );
  2558. if (IS_ERR(priv->clk)) {
  2559. dev_crit(&spi->dev, "Failed to register external clk\n");
  2560. return PTR_ERR(priv->clk);
  2561. }
  2562. ret = of_clk_add_provider(np, of_clk_src_simple_get, priv->clk);
  2563. if (ret) {
  2564. clk_unregister(priv->clk);
  2565. dev_crit(
  2566. &spi->dev,
  2567. "Failed to register external clock as clock provider\n"
  2568. );
  2569. } else {
  2570. dev_info(&spi->dev, "External clock set as clock provider\n");
  2571. }
  2572. return ret;
  2573. }
  2574. /**
  2575. * ca8210_unregister_ext_clock() - Unregister ca8210's external clock with
  2576. * kernel
  2577. * @spi: Pointer to target ca8210 spi device
  2578. */
  2579. static void ca8210_unregister_ext_clock(struct spi_device *spi)
  2580. {
  2581. struct ca8210_priv *priv = spi_get_drvdata(spi);
  2582. if (!priv->clk)
  2583. return
  2584. of_clk_del_provider(spi->dev.of_node);
  2585. clk_unregister(priv->clk);
  2586. dev_info(&spi->dev, "External clock unregistered\n");
  2587. }
  2588. /**
  2589. * ca8210_reset_init() - Initialise the reset input to the ca8210
  2590. * @spi: Pointer to target ca8210 spi device
  2591. *
  2592. * Return: 0 or linux error code
  2593. */
  2594. static int ca8210_reset_init(struct spi_device *spi)
  2595. {
  2596. int ret;
  2597. struct ca8210_platform_data *pdata = spi->dev.platform_data;
  2598. pdata->gpio_reset = of_get_named_gpio(
  2599. spi->dev.of_node,
  2600. "reset-gpio",
  2601. 0
  2602. );
  2603. ret = gpio_direction_output(pdata->gpio_reset, 1);
  2604. if (ret < 0) {
  2605. dev_crit(
  2606. &spi->dev,
  2607. "Reset GPIO %d did not set to output mode\n",
  2608. pdata->gpio_reset
  2609. );
  2610. }
  2611. return ret;
  2612. }
  2613. /**
  2614. * ca8210_interrupt_init() - Initialise the irq output from the ca8210
  2615. * @spi: Pointer to target ca8210 spi device
  2616. *
  2617. * Return: 0 or linux error code
  2618. */
  2619. static int ca8210_interrupt_init(struct spi_device *spi)
  2620. {
  2621. int ret;
  2622. struct ca8210_platform_data *pdata = spi->dev.platform_data;
  2623. pdata->gpio_irq = of_get_named_gpio(
  2624. spi->dev.of_node,
  2625. "irq-gpio",
  2626. 0
  2627. );
  2628. pdata->irq_id = gpio_to_irq(pdata->gpio_irq);
  2629. if (pdata->irq_id < 0) {
  2630. dev_crit(
  2631. &spi->dev,
  2632. "Could not get irq for gpio pin %d\n",
  2633. pdata->gpio_irq
  2634. );
  2635. gpio_free(pdata->gpio_irq);
  2636. return pdata->irq_id;
  2637. }
  2638. ret = request_irq(
  2639. pdata->irq_id,
  2640. ca8210_interrupt_handler,
  2641. IRQF_TRIGGER_FALLING,
  2642. "ca8210-irq",
  2643. spi_get_drvdata(spi)
  2644. );
  2645. if (ret) {
  2646. dev_crit(&spi->dev, "request_irq %d failed\n", pdata->irq_id);
  2647. gpio_unexport(pdata->gpio_irq);
  2648. gpio_free(pdata->gpio_irq);
  2649. }
  2650. return ret;
  2651. }
  2652. /**
  2653. * ca8210_dev_com_init() - Initialise the spi communication component
  2654. * @priv: Pointer to private data structure
  2655. *
  2656. * Return: 0 or linux error code
  2657. */
  2658. static int ca8210_dev_com_init(struct ca8210_priv *priv)
  2659. {
  2660. priv->mlme_workqueue = alloc_ordered_workqueue(
  2661. "MLME work queue",
  2662. WQ_UNBOUND
  2663. );
  2664. if (!priv->mlme_workqueue) {
  2665. dev_crit(&priv->spi->dev, "alloc of mlme_workqueue failed!\n");
  2666. return -ENOMEM;
  2667. }
  2668. priv->irq_workqueue = alloc_ordered_workqueue(
  2669. "ca8210 irq worker",
  2670. WQ_UNBOUND
  2671. );
  2672. if (!priv->irq_workqueue) {
  2673. dev_crit(&priv->spi->dev, "alloc of irq_workqueue failed!\n");
  2674. return -ENOMEM;
  2675. }
  2676. return 0;
  2677. }
  2678. /**
  2679. * ca8210_dev_com_clear() - Deinitialise the spi communication component
  2680. * @priv: Pointer to private data structure
  2681. */
  2682. static void ca8210_dev_com_clear(struct ca8210_priv *priv)
  2683. {
  2684. flush_workqueue(priv->mlme_workqueue);
  2685. destroy_workqueue(priv->mlme_workqueue);
  2686. flush_workqueue(priv->irq_workqueue);
  2687. destroy_workqueue(priv->irq_workqueue);
  2688. }
  2689. #define CA8210_MAX_TX_POWERS (9)
  2690. static const s32 ca8210_tx_powers[CA8210_MAX_TX_POWERS] = {
  2691. 800, 700, 600, 500, 400, 300, 200, 100, 0
  2692. };
  2693. #define CA8210_MAX_ED_LEVELS (21)
  2694. static const s32 ca8210_ed_levels[CA8210_MAX_ED_LEVELS] = {
  2695. -10300, -10250, -10200, -10150, -10100, -10050, -10000, -9950, -9900,
  2696. -9850, -9800, -9750, -9700, -9650, -9600, -9550, -9500, -9450, -9400,
  2697. -9350, -9300
  2698. };
  2699. /**
  2700. * ca8210_hw_setup() - Populate the ieee802154_hw phy attributes with the
  2701. * ca8210's defaults
  2702. * @ca8210_hw: Pointer to ieee802154_hw to populate
  2703. */
  2704. static void ca8210_hw_setup(struct ieee802154_hw *ca8210_hw)
  2705. {
  2706. /* Support channels 11-26 */
  2707. ca8210_hw->phy->supported.channels[0] = CA8210_VALID_CHANNELS;
  2708. ca8210_hw->phy->supported.tx_powers_size = CA8210_MAX_TX_POWERS;
  2709. ca8210_hw->phy->supported.tx_powers = ca8210_tx_powers;
  2710. ca8210_hw->phy->supported.cca_ed_levels_size = CA8210_MAX_ED_LEVELS;
  2711. ca8210_hw->phy->supported.cca_ed_levels = ca8210_ed_levels;
  2712. ca8210_hw->phy->current_channel = 18;
  2713. ca8210_hw->phy->current_page = 0;
  2714. ca8210_hw->phy->transmit_power = 800;
  2715. ca8210_hw->phy->cca.mode = NL802154_CCA_ENERGY_CARRIER;
  2716. ca8210_hw->phy->cca.opt = NL802154_CCA_OPT_ENERGY_CARRIER_AND;
  2717. ca8210_hw->phy->cca_ed_level = -9800;
  2718. ca8210_hw->phy->symbol_duration = 16;
  2719. ca8210_hw->phy->lifs_period = 40;
  2720. ca8210_hw->phy->sifs_period = 12;
  2721. ca8210_hw->flags =
  2722. IEEE802154_HW_AFILT |
  2723. IEEE802154_HW_OMIT_CKSUM |
  2724. IEEE802154_HW_FRAME_RETRIES |
  2725. IEEE802154_HW_PROMISCUOUS |
  2726. IEEE802154_HW_CSMA_PARAMS;
  2727. ca8210_hw->phy->flags =
  2728. WPAN_PHY_FLAG_TXPOWER |
  2729. WPAN_PHY_FLAG_CCA_ED_LEVEL |
  2730. WPAN_PHY_FLAG_CCA_MODE;
  2731. }
  2732. /**
  2733. * ca8210_test_interface_init() - Initialise the test file interface
  2734. * @priv: Pointer to private data structure
  2735. *
  2736. * Provided as an alternative to the standard linux network interface, the test
  2737. * interface exposes a file in the filesystem (ca8210_test) that allows
  2738. * 802.15.4 SAP Commands and Cascoda EVBME commands to be sent directly to
  2739. * the stack.
  2740. *
  2741. * Return: 0 or linux error code
  2742. */
  2743. static int ca8210_test_interface_init(struct ca8210_priv *priv)
  2744. {
  2745. struct ca8210_test *test = &priv->test;
  2746. char node_name[32];
  2747. snprintf(
  2748. node_name,
  2749. sizeof(node_name),
  2750. "ca8210@%d_%d",
  2751. priv->spi->master->bus_num,
  2752. priv->spi->chip_select
  2753. );
  2754. test->ca8210_dfs_spi_int = debugfs_create_file(
  2755. node_name,
  2756. 0600, /* S_IRUSR | S_IWUSR */
  2757. NULL,
  2758. priv,
  2759. &test_int_fops
  2760. );
  2761. if (IS_ERR(test->ca8210_dfs_spi_int)) {
  2762. dev_err(
  2763. &priv->spi->dev,
  2764. "Error %ld when creating debugfs node\n",
  2765. PTR_ERR(test->ca8210_dfs_spi_int)
  2766. );
  2767. return PTR_ERR(test->ca8210_dfs_spi_int);
  2768. }
  2769. debugfs_create_symlink("ca8210", NULL, node_name);
  2770. init_waitqueue_head(&test->readq);
  2771. return kfifo_alloc(
  2772. &test->up_fifo,
  2773. CA8210_TEST_INT_FIFO_SIZE,
  2774. GFP_KERNEL
  2775. );
  2776. }
  2777. /**
  2778. * ca8210_test_interface_clear() - Deinitialise the test file interface
  2779. * @priv: Pointer to private data structure
  2780. */
  2781. static void ca8210_test_interface_clear(struct ca8210_priv *priv)
  2782. {
  2783. struct ca8210_test *test = &priv->test;
  2784. if (!IS_ERR(test->ca8210_dfs_spi_int))
  2785. debugfs_remove(test->ca8210_dfs_spi_int);
  2786. kfifo_free(&test->up_fifo);
  2787. dev_info(&priv->spi->dev, "Test interface removed\n");
  2788. }
  2789. /**
  2790. * ca8210_remove() - Shut down a ca8210 upon being disconnected
  2791. * @priv: Pointer to private data structure
  2792. *
  2793. * Return: 0 or linux error code
  2794. */
  2795. static int ca8210_remove(struct spi_device *spi_device)
  2796. {
  2797. struct ca8210_priv *priv;
  2798. struct ca8210_platform_data *pdata;
  2799. dev_info(&spi_device->dev, "Removing ca8210\n");
  2800. pdata = spi_device->dev.platform_data;
  2801. if (pdata) {
  2802. if (pdata->extclockenable) {
  2803. ca8210_unregister_ext_clock(spi_device);
  2804. ca8210_config_extern_clk(pdata, spi_device, 0);
  2805. }
  2806. free_irq(pdata->irq_id, spi_device->dev.driver_data);
  2807. kfree(pdata);
  2808. spi_device->dev.platform_data = NULL;
  2809. }
  2810. /* get spi_device private data */
  2811. priv = spi_get_drvdata(spi_device);
  2812. if (priv) {
  2813. dev_info(
  2814. &spi_device->dev,
  2815. "sync_down = %d, sync_up = %d\n",
  2816. priv->sync_down,
  2817. priv->sync_up
  2818. );
  2819. ca8210_dev_com_clear(spi_device->dev.driver_data);
  2820. if (priv->hw) {
  2821. if (priv->hw_registered)
  2822. ieee802154_unregister_hw(priv->hw);
  2823. ieee802154_free_hw(priv->hw);
  2824. priv->hw = NULL;
  2825. dev_info(
  2826. &spi_device->dev,
  2827. "Unregistered & freed ieee802154_hw.\n"
  2828. );
  2829. }
  2830. if (IS_ENABLED(CONFIG_IEEE802154_CA8210_DEBUGFS))
  2831. ca8210_test_interface_clear(priv);
  2832. }
  2833. return 0;
  2834. }
  2835. /**
  2836. * ca8210_probe() - Set up a connected ca8210 upon being detected by the system
  2837. * @priv: Pointer to private data structure
  2838. *
  2839. * Return: 0 or linux error code
  2840. */
  2841. static int ca8210_probe(struct spi_device *spi_device)
  2842. {
  2843. struct ca8210_priv *priv;
  2844. struct ieee802154_hw *hw;
  2845. struct ca8210_platform_data *pdata;
  2846. int ret;
  2847. dev_info(&spi_device->dev, "Inserting ca8210\n");
  2848. /* allocate ieee802154_hw and private data */
  2849. hw = ieee802154_alloc_hw(sizeof(struct ca8210_priv), &ca8210_phy_ops);
  2850. if (!hw) {
  2851. dev_crit(&spi_device->dev, "ieee802154_alloc_hw failed\n");
  2852. ret = -ENOMEM;
  2853. goto error;
  2854. }
  2855. priv = hw->priv;
  2856. priv->hw = hw;
  2857. priv->spi = spi_device;
  2858. hw->parent = &spi_device->dev;
  2859. spin_lock_init(&priv->lock);
  2860. priv->async_tx_pending = false;
  2861. priv->hw_registered = false;
  2862. priv->sync_up = 0;
  2863. priv->sync_down = 0;
  2864. priv->promiscuous = false;
  2865. priv->retries = 0;
  2866. init_completion(&priv->ca8210_is_awake);
  2867. init_completion(&priv->spi_transfer_complete);
  2868. init_completion(&priv->sync_exchange_complete);
  2869. spi_set_drvdata(priv->spi, priv);
  2870. if (IS_ENABLED(CONFIG_IEEE802154_CA8210_DEBUGFS)) {
  2871. cascoda_api_upstream = ca8210_test_int_driver_write;
  2872. ca8210_test_interface_init(priv);
  2873. } else {
  2874. cascoda_api_upstream = NULL;
  2875. }
  2876. ca8210_hw_setup(hw);
  2877. ieee802154_random_extended_addr(&hw->phy->perm_extended_addr);
  2878. pdata = kmalloc(sizeof(*pdata), GFP_KERNEL);
  2879. if (!pdata) {
  2880. dev_crit(
  2881. &spi_device->dev,
  2882. "Could not allocate platform data\n"
  2883. );
  2884. ret = -ENOMEM;
  2885. goto error;
  2886. }
  2887. ret = ca8210_get_platform_data(priv->spi, pdata);
  2888. if (ret) {
  2889. dev_crit(&spi_device->dev, "ca8210_get_platform_data failed\n");
  2890. goto error;
  2891. }
  2892. priv->spi->dev.platform_data = pdata;
  2893. ret = ca8210_dev_com_init(priv);
  2894. if (ret) {
  2895. dev_crit(&spi_device->dev, "ca8210_dev_com_init failed\n");
  2896. goto error;
  2897. }
  2898. ret = ca8210_reset_init(priv->spi);
  2899. if (ret) {
  2900. dev_crit(&spi_device->dev, "ca8210_reset_init failed\n");
  2901. goto error;
  2902. }
  2903. ret = ca8210_interrupt_init(priv->spi);
  2904. if (ret) {
  2905. dev_crit(&spi_device->dev, "ca8210_interrupt_init failed\n");
  2906. goto error;
  2907. }
  2908. msleep(100);
  2909. ca8210_reset_send(priv->spi, 1);
  2910. ret = tdme_chipinit(priv->spi);
  2911. if (ret) {
  2912. dev_crit(&spi_device->dev, "tdme_chipinit failed\n");
  2913. goto error;
  2914. }
  2915. if (pdata->extclockenable) {
  2916. ret = ca8210_config_extern_clk(pdata, priv->spi, 1);
  2917. if (ret) {
  2918. dev_crit(
  2919. &spi_device->dev,
  2920. "ca8210_config_extern_clk failed\n"
  2921. );
  2922. goto error;
  2923. }
  2924. ret = ca8210_register_ext_clock(priv->spi);
  2925. if (ret) {
  2926. dev_crit(
  2927. &spi_device->dev,
  2928. "ca8210_register_ext_clock failed\n"
  2929. );
  2930. goto error;
  2931. }
  2932. }
  2933. ret = ieee802154_register_hw(hw);
  2934. if (ret) {
  2935. dev_crit(&spi_device->dev, "ieee802154_register_hw failed\n");
  2936. goto error;
  2937. }
  2938. priv->hw_registered = true;
  2939. return 0;
  2940. error:
  2941. msleep(100); /* wait for pending spi transfers to complete */
  2942. ca8210_remove(spi_device);
  2943. return link_to_linux_err(ret);
  2944. }
  2945. static const struct of_device_id ca8210_of_ids[] = {
  2946. {.compatible = "cascoda,ca8210", },
  2947. {},
  2948. };
  2949. MODULE_DEVICE_TABLE(of, ca8210_of_ids);
  2950. static struct spi_driver ca8210_spi_driver = {
  2951. .driver = {
  2952. .name = DRIVER_NAME,
  2953. .owner = THIS_MODULE,
  2954. .of_match_table = of_match_ptr(ca8210_of_ids),
  2955. },
  2956. .probe = ca8210_probe,
  2957. .remove = ca8210_remove
  2958. };
  2959. module_spi_driver(ca8210_spi_driver);
  2960. MODULE_AUTHOR("Harry Morris <h.morris@cascoda.com>");
  2961. MODULE_DESCRIPTION("CA-8210 SoftMAC driver");
  2962. MODULE_LICENSE("Dual BSD/GPL");
  2963. MODULE_VERSION("1.0");