r8169.c 210 KB

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  1. /*
  2. * r8169.c: RealTek 8169/8168/8101 ethernet driver.
  3. *
  4. * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
  5. * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
  6. * Copyright (c) a lot of people too. Please respect their work.
  7. *
  8. * See MAINTAINERS file for support contact information.
  9. */
  10. #include <linux/module.h>
  11. #include <linux/moduleparam.h>
  12. #include <linux/pci.h>
  13. #include <linux/netdevice.h>
  14. #include <linux/etherdevice.h>
  15. #include <linux/delay.h>
  16. #include <linux/ethtool.h>
  17. #include <linux/mii.h>
  18. #include <linux/if_vlan.h>
  19. #include <linux/crc32.h>
  20. #include <linux/in.h>
  21. #include <linux/ip.h>
  22. #include <linux/tcp.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/dma-mapping.h>
  25. #include <linux/pm_runtime.h>
  26. #include <linux/firmware.h>
  27. #include <linux/pci-aspm.h>
  28. #include <linux/prefetch.h>
  29. #include <linux/ipv6.h>
  30. #include <net/ip6_checksum.h>
  31. #include <asm/io.h>
  32. #include <asm/irq.h>
  33. #define RTL8169_VERSION "2.3LK-NAPI"
  34. #define MODULENAME "r8169"
  35. #define PFX MODULENAME ": "
  36. #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
  37. #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
  38. #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
  39. #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
  40. #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
  41. #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
  42. #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
  43. #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
  44. #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
  45. #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
  46. #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
  47. #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
  48. #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
  49. #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
  50. #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
  51. #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
  52. #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
  53. #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
  54. #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
  55. #ifdef RTL8169_DEBUG
  56. #define assert(expr) \
  57. if (!(expr)) { \
  58. printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  59. #expr,__FILE__,__func__,__LINE__); \
  60. }
  61. #define dprintk(fmt, args...) \
  62. do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  63. #else
  64. #define assert(expr) do {} while (0)
  65. #define dprintk(fmt, args...) do {} while (0)
  66. #endif /* RTL8169_DEBUG */
  67. #define R8169_MSG_DEFAULT \
  68. (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  69. #define TX_SLOTS_AVAIL(tp) \
  70. (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  71. /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  72. #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  73. (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  74. /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  75. The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  76. static const int multicast_filter_limit = 32;
  77. #define MAX_READ_REQUEST_SHIFT 12
  78. #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
  79. #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
  80. #define R8169_REGS_SIZE 256
  81. #define R8169_NAPI_WEIGHT 64
  82. #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
  83. #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
  84. #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
  85. #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
  86. #define RTL8169_TX_TIMEOUT (6*HZ)
  87. #define RTL8169_PHY_TIMEOUT (10*HZ)
  88. /* write/read MMIO register */
  89. #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
  90. #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
  91. #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
  92. #define RTL_R8(reg) readb (ioaddr + (reg))
  93. #define RTL_R16(reg) readw (ioaddr + (reg))
  94. #define RTL_R32(reg) readl (ioaddr + (reg))
  95. enum mac_version {
  96. RTL_GIGA_MAC_VER_01 = 0,
  97. RTL_GIGA_MAC_VER_02,
  98. RTL_GIGA_MAC_VER_03,
  99. RTL_GIGA_MAC_VER_04,
  100. RTL_GIGA_MAC_VER_05,
  101. RTL_GIGA_MAC_VER_06,
  102. RTL_GIGA_MAC_VER_07,
  103. RTL_GIGA_MAC_VER_08,
  104. RTL_GIGA_MAC_VER_09,
  105. RTL_GIGA_MAC_VER_10,
  106. RTL_GIGA_MAC_VER_11,
  107. RTL_GIGA_MAC_VER_12,
  108. RTL_GIGA_MAC_VER_13,
  109. RTL_GIGA_MAC_VER_14,
  110. RTL_GIGA_MAC_VER_15,
  111. RTL_GIGA_MAC_VER_16,
  112. RTL_GIGA_MAC_VER_17,
  113. RTL_GIGA_MAC_VER_18,
  114. RTL_GIGA_MAC_VER_19,
  115. RTL_GIGA_MAC_VER_20,
  116. RTL_GIGA_MAC_VER_21,
  117. RTL_GIGA_MAC_VER_22,
  118. RTL_GIGA_MAC_VER_23,
  119. RTL_GIGA_MAC_VER_24,
  120. RTL_GIGA_MAC_VER_25,
  121. RTL_GIGA_MAC_VER_26,
  122. RTL_GIGA_MAC_VER_27,
  123. RTL_GIGA_MAC_VER_28,
  124. RTL_GIGA_MAC_VER_29,
  125. RTL_GIGA_MAC_VER_30,
  126. RTL_GIGA_MAC_VER_31,
  127. RTL_GIGA_MAC_VER_32,
  128. RTL_GIGA_MAC_VER_33,
  129. RTL_GIGA_MAC_VER_34,
  130. RTL_GIGA_MAC_VER_35,
  131. RTL_GIGA_MAC_VER_36,
  132. RTL_GIGA_MAC_VER_37,
  133. RTL_GIGA_MAC_VER_38,
  134. RTL_GIGA_MAC_VER_39,
  135. RTL_GIGA_MAC_VER_40,
  136. RTL_GIGA_MAC_VER_41,
  137. RTL_GIGA_MAC_VER_42,
  138. RTL_GIGA_MAC_VER_43,
  139. RTL_GIGA_MAC_VER_44,
  140. RTL_GIGA_MAC_VER_45,
  141. RTL_GIGA_MAC_VER_46,
  142. RTL_GIGA_MAC_VER_47,
  143. RTL_GIGA_MAC_VER_48,
  144. RTL_GIGA_MAC_VER_49,
  145. RTL_GIGA_MAC_VER_50,
  146. RTL_GIGA_MAC_VER_51,
  147. RTL_GIGA_MAC_NONE = 0xff,
  148. };
  149. enum rtl_tx_desc_version {
  150. RTL_TD_0 = 0,
  151. RTL_TD_1 = 1,
  152. };
  153. #define JUMBO_1K ETH_DATA_LEN
  154. #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
  155. #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
  156. #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
  157. #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
  158. #define _R(NAME,TD,FW,SZ,B) { \
  159. .name = NAME, \
  160. .txd_version = TD, \
  161. .fw_name = FW, \
  162. .jumbo_max = SZ, \
  163. .jumbo_tx_csum = B \
  164. }
  165. static const struct {
  166. const char *name;
  167. enum rtl_tx_desc_version txd_version;
  168. const char *fw_name;
  169. u16 jumbo_max;
  170. bool jumbo_tx_csum;
  171. } rtl_chip_infos[] = {
  172. /* PCI devices. */
  173. [RTL_GIGA_MAC_VER_01] =
  174. _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
  175. [RTL_GIGA_MAC_VER_02] =
  176. _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
  177. [RTL_GIGA_MAC_VER_03] =
  178. _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
  179. [RTL_GIGA_MAC_VER_04] =
  180. _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
  181. [RTL_GIGA_MAC_VER_05] =
  182. _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
  183. [RTL_GIGA_MAC_VER_06] =
  184. _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
  185. /* PCI-E devices. */
  186. [RTL_GIGA_MAC_VER_07] =
  187. _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
  188. [RTL_GIGA_MAC_VER_08] =
  189. _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
  190. [RTL_GIGA_MAC_VER_09] =
  191. _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
  192. [RTL_GIGA_MAC_VER_10] =
  193. _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
  194. [RTL_GIGA_MAC_VER_11] =
  195. _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
  196. [RTL_GIGA_MAC_VER_12] =
  197. _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
  198. [RTL_GIGA_MAC_VER_13] =
  199. _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
  200. [RTL_GIGA_MAC_VER_14] =
  201. _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
  202. [RTL_GIGA_MAC_VER_15] =
  203. _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
  204. [RTL_GIGA_MAC_VER_16] =
  205. _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
  206. [RTL_GIGA_MAC_VER_17] =
  207. _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
  208. [RTL_GIGA_MAC_VER_18] =
  209. _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
  210. [RTL_GIGA_MAC_VER_19] =
  211. _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
  212. [RTL_GIGA_MAC_VER_20] =
  213. _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
  214. [RTL_GIGA_MAC_VER_21] =
  215. _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
  216. [RTL_GIGA_MAC_VER_22] =
  217. _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
  218. [RTL_GIGA_MAC_VER_23] =
  219. _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
  220. [RTL_GIGA_MAC_VER_24] =
  221. _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
  222. [RTL_GIGA_MAC_VER_25] =
  223. _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
  224. JUMBO_9K, false),
  225. [RTL_GIGA_MAC_VER_26] =
  226. _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
  227. JUMBO_9K, false),
  228. [RTL_GIGA_MAC_VER_27] =
  229. _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
  230. [RTL_GIGA_MAC_VER_28] =
  231. _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
  232. [RTL_GIGA_MAC_VER_29] =
  233. _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
  234. JUMBO_1K, true),
  235. [RTL_GIGA_MAC_VER_30] =
  236. _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
  237. JUMBO_1K, true),
  238. [RTL_GIGA_MAC_VER_31] =
  239. _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
  240. [RTL_GIGA_MAC_VER_32] =
  241. _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
  242. JUMBO_9K, false),
  243. [RTL_GIGA_MAC_VER_33] =
  244. _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
  245. JUMBO_9K, false),
  246. [RTL_GIGA_MAC_VER_34] =
  247. _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
  248. JUMBO_9K, false),
  249. [RTL_GIGA_MAC_VER_35] =
  250. _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
  251. JUMBO_9K, false),
  252. [RTL_GIGA_MAC_VER_36] =
  253. _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
  254. JUMBO_9K, false),
  255. [RTL_GIGA_MAC_VER_37] =
  256. _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
  257. JUMBO_1K, true),
  258. [RTL_GIGA_MAC_VER_38] =
  259. _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
  260. JUMBO_9K, false),
  261. [RTL_GIGA_MAC_VER_39] =
  262. _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
  263. JUMBO_1K, true),
  264. [RTL_GIGA_MAC_VER_40] =
  265. _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
  266. JUMBO_9K, false),
  267. [RTL_GIGA_MAC_VER_41] =
  268. _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
  269. [RTL_GIGA_MAC_VER_42] =
  270. _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
  271. JUMBO_9K, false),
  272. [RTL_GIGA_MAC_VER_43] =
  273. _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
  274. JUMBO_1K, true),
  275. [RTL_GIGA_MAC_VER_44] =
  276. _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2,
  277. JUMBO_9K, false),
  278. [RTL_GIGA_MAC_VER_45] =
  279. _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1,
  280. JUMBO_9K, false),
  281. [RTL_GIGA_MAC_VER_46] =
  282. _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2,
  283. JUMBO_9K, false),
  284. [RTL_GIGA_MAC_VER_47] =
  285. _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1,
  286. JUMBO_1K, false),
  287. [RTL_GIGA_MAC_VER_48] =
  288. _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2,
  289. JUMBO_1K, false),
  290. [RTL_GIGA_MAC_VER_49] =
  291. _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
  292. JUMBO_9K, false),
  293. [RTL_GIGA_MAC_VER_50] =
  294. _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
  295. JUMBO_9K, false),
  296. [RTL_GIGA_MAC_VER_51] =
  297. _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
  298. JUMBO_9K, false),
  299. };
  300. #undef _R
  301. enum cfg_version {
  302. RTL_CFG_0 = 0x00,
  303. RTL_CFG_1,
  304. RTL_CFG_2
  305. };
  306. static const struct pci_device_id rtl8169_pci_tbl[] = {
  307. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
  308. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
  309. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161), 0, 0, RTL_CFG_1 },
  310. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
  311. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
  312. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
  313. { PCI_VENDOR_ID_DLINK, 0x4300,
  314. PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
  315. { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
  316. { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
  317. { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
  318. { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
  319. { PCI_VENDOR_ID_LINKSYS, 0x1032,
  320. PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
  321. { 0x0001, 0x8168,
  322. PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
  323. {0,},
  324. };
  325. MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
  326. static int rx_buf_sz = 16383;
  327. static int use_dac = -1;
  328. static struct {
  329. u32 msg_enable;
  330. } debug = { -1 };
  331. enum rtl_registers {
  332. MAC0 = 0, /* Ethernet hardware address. */
  333. MAC4 = 4,
  334. MAR0 = 8, /* Multicast filter. */
  335. CounterAddrLow = 0x10,
  336. CounterAddrHigh = 0x14,
  337. TxDescStartAddrLow = 0x20,
  338. TxDescStartAddrHigh = 0x24,
  339. TxHDescStartAddrLow = 0x28,
  340. TxHDescStartAddrHigh = 0x2c,
  341. FLASH = 0x30,
  342. ERSR = 0x36,
  343. ChipCmd = 0x37,
  344. TxPoll = 0x38,
  345. IntrMask = 0x3c,
  346. IntrStatus = 0x3e,
  347. TxConfig = 0x40,
  348. #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
  349. #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
  350. RxConfig = 0x44,
  351. #define RX128_INT_EN (1 << 15) /* 8111c and later */
  352. #define RX_MULTI_EN (1 << 14) /* 8111c only */
  353. #define RXCFG_FIFO_SHIFT 13
  354. /* No threshold before first PCI xfer */
  355. #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
  356. #define RX_EARLY_OFF (1 << 11)
  357. #define RXCFG_DMA_SHIFT 8
  358. /* Unlimited maximum PCI burst. */
  359. #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
  360. RxMissed = 0x4c,
  361. Cfg9346 = 0x50,
  362. Config0 = 0x51,
  363. Config1 = 0x52,
  364. Config2 = 0x53,
  365. #define PME_SIGNAL (1 << 5) /* 8168c and later */
  366. Config3 = 0x54,
  367. Config4 = 0x55,
  368. Config5 = 0x56,
  369. MultiIntr = 0x5c,
  370. PHYAR = 0x60,
  371. PHYstatus = 0x6c,
  372. RxMaxSize = 0xda,
  373. CPlusCmd = 0xe0,
  374. IntrMitigate = 0xe2,
  375. RxDescAddrLow = 0xe4,
  376. RxDescAddrHigh = 0xe8,
  377. EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
  378. #define NoEarlyTx 0x3f /* Max value : no early transmit. */
  379. MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
  380. #define TxPacketMax (8064 >> 7)
  381. #define EarlySize 0x27
  382. FuncEvent = 0xf0,
  383. FuncEventMask = 0xf4,
  384. FuncPresetState = 0xf8,
  385. IBCR0 = 0xf8,
  386. IBCR2 = 0xf9,
  387. IBIMR0 = 0xfa,
  388. IBISR0 = 0xfb,
  389. FuncForceEvent = 0xfc,
  390. };
  391. enum rtl8110_registers {
  392. TBICSR = 0x64,
  393. TBI_ANAR = 0x68,
  394. TBI_LPAR = 0x6a,
  395. };
  396. enum rtl8168_8101_registers {
  397. CSIDR = 0x64,
  398. CSIAR = 0x68,
  399. #define CSIAR_FLAG 0x80000000
  400. #define CSIAR_WRITE_CMD 0x80000000
  401. #define CSIAR_BYTE_ENABLE 0x0f
  402. #define CSIAR_BYTE_ENABLE_SHIFT 12
  403. #define CSIAR_ADDR_MASK 0x0fff
  404. #define CSIAR_FUNC_CARD 0x00000000
  405. #define CSIAR_FUNC_SDIO 0x00010000
  406. #define CSIAR_FUNC_NIC 0x00020000
  407. #define CSIAR_FUNC_NIC2 0x00010000
  408. PMCH = 0x6f,
  409. EPHYAR = 0x80,
  410. #define EPHYAR_FLAG 0x80000000
  411. #define EPHYAR_WRITE_CMD 0x80000000
  412. #define EPHYAR_REG_MASK 0x1f
  413. #define EPHYAR_REG_SHIFT 16
  414. #define EPHYAR_DATA_MASK 0xffff
  415. DLLPR = 0xd0,
  416. #define PFM_EN (1 << 6)
  417. #define TX_10M_PS_EN (1 << 7)
  418. DBG_REG = 0xd1,
  419. #define FIX_NAK_1 (1 << 4)
  420. #define FIX_NAK_2 (1 << 3)
  421. TWSI = 0xd2,
  422. MCU = 0xd3,
  423. #define NOW_IS_OOB (1 << 7)
  424. #define TX_EMPTY (1 << 5)
  425. #define RX_EMPTY (1 << 4)
  426. #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
  427. #define EN_NDP (1 << 3)
  428. #define EN_OOB_RESET (1 << 2)
  429. #define LINK_LIST_RDY (1 << 1)
  430. EFUSEAR = 0xdc,
  431. #define EFUSEAR_FLAG 0x80000000
  432. #define EFUSEAR_WRITE_CMD 0x80000000
  433. #define EFUSEAR_READ_CMD 0x00000000
  434. #define EFUSEAR_REG_MASK 0x03ff
  435. #define EFUSEAR_REG_SHIFT 8
  436. #define EFUSEAR_DATA_MASK 0xff
  437. MISC_1 = 0xf2,
  438. #define PFM_D3COLD_EN (1 << 6)
  439. };
  440. enum rtl8168_registers {
  441. LED_FREQ = 0x1a,
  442. EEE_LED = 0x1b,
  443. ERIDR = 0x70,
  444. ERIAR = 0x74,
  445. #define ERIAR_FLAG 0x80000000
  446. #define ERIAR_WRITE_CMD 0x80000000
  447. #define ERIAR_READ_CMD 0x00000000
  448. #define ERIAR_ADDR_BYTE_ALIGN 4
  449. #define ERIAR_TYPE_SHIFT 16
  450. #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
  451. #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
  452. #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
  453. #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
  454. #define ERIAR_MASK_SHIFT 12
  455. #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
  456. #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
  457. #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
  458. #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
  459. #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
  460. EPHY_RXER_NUM = 0x7c,
  461. OCPDR = 0xb0, /* OCP GPHY access */
  462. #define OCPDR_WRITE_CMD 0x80000000
  463. #define OCPDR_READ_CMD 0x00000000
  464. #define OCPDR_REG_MASK 0x7f
  465. #define OCPDR_GPHY_REG_SHIFT 16
  466. #define OCPDR_DATA_MASK 0xffff
  467. OCPAR = 0xb4,
  468. #define OCPAR_FLAG 0x80000000
  469. #define OCPAR_GPHY_WRITE_CMD 0x8000f060
  470. #define OCPAR_GPHY_READ_CMD 0x0000f060
  471. GPHY_OCP = 0xb8,
  472. RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
  473. MISC = 0xf0, /* 8168e only. */
  474. #define TXPLA_RST (1 << 29)
  475. #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
  476. #define PWM_EN (1 << 22)
  477. #define RXDV_GATED_EN (1 << 19)
  478. #define EARLY_TALLY_EN (1 << 16)
  479. };
  480. enum rtl_register_content {
  481. /* InterruptStatusBits */
  482. SYSErr = 0x8000,
  483. PCSTimeout = 0x4000,
  484. SWInt = 0x0100,
  485. TxDescUnavail = 0x0080,
  486. RxFIFOOver = 0x0040,
  487. LinkChg = 0x0020,
  488. RxOverflow = 0x0010,
  489. TxErr = 0x0008,
  490. TxOK = 0x0004,
  491. RxErr = 0x0002,
  492. RxOK = 0x0001,
  493. /* RxStatusDesc */
  494. RxBOVF = (1 << 24),
  495. RxFOVF = (1 << 23),
  496. RxRWT = (1 << 22),
  497. RxRES = (1 << 21),
  498. RxRUNT = (1 << 20),
  499. RxCRC = (1 << 19),
  500. /* ChipCmdBits */
  501. StopReq = 0x80,
  502. CmdReset = 0x10,
  503. CmdRxEnb = 0x08,
  504. CmdTxEnb = 0x04,
  505. RxBufEmpty = 0x01,
  506. /* TXPoll register p.5 */
  507. HPQ = 0x80, /* Poll cmd on the high prio queue */
  508. NPQ = 0x40, /* Poll cmd on the low prio queue */
  509. FSWInt = 0x01, /* Forced software interrupt */
  510. /* Cfg9346Bits */
  511. Cfg9346_Lock = 0x00,
  512. Cfg9346_Unlock = 0xc0,
  513. /* rx_mode_bits */
  514. AcceptErr = 0x20,
  515. AcceptRunt = 0x10,
  516. AcceptBroadcast = 0x08,
  517. AcceptMulticast = 0x04,
  518. AcceptMyPhys = 0x02,
  519. AcceptAllPhys = 0x01,
  520. #define RX_CONFIG_ACCEPT_MASK 0x3f
  521. /* TxConfigBits */
  522. TxInterFrameGapShift = 24,
  523. TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
  524. /* Config1 register p.24 */
  525. LEDS1 = (1 << 7),
  526. LEDS0 = (1 << 6),
  527. Speed_down = (1 << 4),
  528. MEMMAP = (1 << 3),
  529. IOMAP = (1 << 2),
  530. VPD = (1 << 1),
  531. PMEnable = (1 << 0), /* Power Management Enable */
  532. /* Config2 register p. 25 */
  533. ClkReqEn = (1 << 7), /* Clock Request Enable */
  534. MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
  535. PCI_Clock_66MHz = 0x01,
  536. PCI_Clock_33MHz = 0x00,
  537. /* Config3 register p.25 */
  538. MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
  539. LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
  540. Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
  541. Rdy_to_L23 = (1 << 1), /* L23 Enable */
  542. Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
  543. /* Config4 register */
  544. Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
  545. /* Config5 register p.27 */
  546. BWF = (1 << 6), /* Accept Broadcast wakeup frame */
  547. MWF = (1 << 5), /* Accept Multicast wakeup frame */
  548. UWF = (1 << 4), /* Accept Unicast wakeup frame */
  549. Spi_en = (1 << 3),
  550. LanWake = (1 << 1), /* LanWake enable/disable */
  551. PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
  552. ASPM_en = (1 << 0), /* ASPM enable */
  553. /* TBICSR p.28 */
  554. TBIReset = 0x80000000,
  555. TBILoopback = 0x40000000,
  556. TBINwEnable = 0x20000000,
  557. TBINwRestart = 0x10000000,
  558. TBILinkOk = 0x02000000,
  559. TBINwComplete = 0x01000000,
  560. /* CPlusCmd p.31 */
  561. EnableBist = (1 << 15), // 8168 8101
  562. Mac_dbgo_oe = (1 << 14), // 8168 8101
  563. Normal_mode = (1 << 13), // unused
  564. Force_half_dup = (1 << 12), // 8168 8101
  565. Force_rxflow_en = (1 << 11), // 8168 8101
  566. Force_txflow_en = (1 << 10), // 8168 8101
  567. Cxpl_dbg_sel = (1 << 9), // 8168 8101
  568. ASF = (1 << 8), // 8168 8101
  569. PktCntrDisable = (1 << 7), // 8168 8101
  570. Mac_dbgo_sel = 0x001c, // 8168
  571. RxVlan = (1 << 6),
  572. RxChkSum = (1 << 5),
  573. PCIDAC = (1 << 4),
  574. PCIMulRW = (1 << 3),
  575. INTT_0 = 0x0000, // 8168
  576. INTT_1 = 0x0001, // 8168
  577. INTT_2 = 0x0002, // 8168
  578. INTT_3 = 0x0003, // 8168
  579. /* rtl8169_PHYstatus */
  580. TBI_Enable = 0x80,
  581. TxFlowCtrl = 0x40,
  582. RxFlowCtrl = 0x20,
  583. _1000bpsF = 0x10,
  584. _100bps = 0x08,
  585. _10bps = 0x04,
  586. LinkStatus = 0x02,
  587. FullDup = 0x01,
  588. /* _TBICSRBit */
  589. TBILinkOK = 0x02000000,
  590. /* ResetCounterCommand */
  591. CounterReset = 0x1,
  592. /* DumpCounterCommand */
  593. CounterDump = 0x8,
  594. /* magic enable v2 */
  595. MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
  596. };
  597. enum rtl_desc_bit {
  598. /* First doubleword. */
  599. DescOwn = (1 << 31), /* Descriptor is owned by NIC */
  600. RingEnd = (1 << 30), /* End of descriptor ring */
  601. FirstFrag = (1 << 29), /* First segment of a packet */
  602. LastFrag = (1 << 28), /* Final segment of a packet */
  603. };
  604. /* Generic case. */
  605. enum rtl_tx_desc_bit {
  606. /* First doubleword. */
  607. TD_LSO = (1 << 27), /* Large Send Offload */
  608. #define TD_MSS_MAX 0x07ffu /* MSS value */
  609. /* Second doubleword. */
  610. TxVlanTag = (1 << 17), /* Add VLAN tag */
  611. };
  612. /* 8169, 8168b and 810x except 8102e. */
  613. enum rtl_tx_desc_bit_0 {
  614. /* First doubleword. */
  615. #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
  616. TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
  617. TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
  618. TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
  619. };
  620. /* 8102e, 8168c and beyond. */
  621. enum rtl_tx_desc_bit_1 {
  622. /* First doubleword. */
  623. TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
  624. TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
  625. #define GTTCPHO_SHIFT 18
  626. #define GTTCPHO_MAX 0x7fU
  627. /* Second doubleword. */
  628. #define TCPHO_SHIFT 18
  629. #define TCPHO_MAX 0x3ffU
  630. #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
  631. TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
  632. TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
  633. TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
  634. TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
  635. };
  636. enum rtl_rx_desc_bit {
  637. /* Rx private */
  638. PID1 = (1 << 18), /* Protocol ID bit 1/2 */
  639. PID0 = (1 << 17), /* Protocol ID bit 0/2 */
  640. #define RxProtoUDP (PID1)
  641. #define RxProtoTCP (PID0)
  642. #define RxProtoIP (PID1 | PID0)
  643. #define RxProtoMask RxProtoIP
  644. IPFail = (1 << 16), /* IP checksum failed */
  645. UDPFail = (1 << 15), /* UDP/IP checksum failed */
  646. TCPFail = (1 << 14), /* TCP/IP checksum failed */
  647. RxVlanTag = (1 << 16), /* VLAN tag available */
  648. };
  649. #define RsvdMask 0x3fffc000
  650. struct TxDesc {
  651. __le32 opts1;
  652. __le32 opts2;
  653. __le64 addr;
  654. };
  655. struct RxDesc {
  656. __le32 opts1;
  657. __le32 opts2;
  658. __le64 addr;
  659. };
  660. struct ring_info {
  661. struct sk_buff *skb;
  662. u32 len;
  663. u8 __pad[sizeof(void *) - sizeof(u32)];
  664. };
  665. enum features {
  666. RTL_FEATURE_WOL = (1 << 0),
  667. RTL_FEATURE_MSI = (1 << 1),
  668. RTL_FEATURE_GMII = (1 << 2),
  669. };
  670. struct rtl8169_counters {
  671. __le64 tx_packets;
  672. __le64 rx_packets;
  673. __le64 tx_errors;
  674. __le32 rx_errors;
  675. __le16 rx_missed;
  676. __le16 align_errors;
  677. __le32 tx_one_collision;
  678. __le32 tx_multi_collision;
  679. __le64 rx_unicast;
  680. __le64 rx_broadcast;
  681. __le32 rx_multicast;
  682. __le16 tx_aborted;
  683. __le16 tx_underun;
  684. };
  685. struct rtl8169_tc_offsets {
  686. bool inited;
  687. __le64 tx_errors;
  688. __le32 tx_multi_collision;
  689. __le16 tx_aborted;
  690. };
  691. enum rtl_flag {
  692. RTL_FLAG_TASK_ENABLED,
  693. RTL_FLAG_TASK_SLOW_PENDING,
  694. RTL_FLAG_TASK_RESET_PENDING,
  695. RTL_FLAG_TASK_PHY_PENDING,
  696. RTL_FLAG_MAX
  697. };
  698. struct rtl8169_stats {
  699. u64 packets;
  700. u64 bytes;
  701. struct u64_stats_sync syncp;
  702. };
  703. struct rtl8169_private {
  704. void __iomem *mmio_addr; /* memory map physical address */
  705. struct pci_dev *pci_dev;
  706. struct net_device *dev;
  707. struct napi_struct napi;
  708. u32 msg_enable;
  709. u16 txd_version;
  710. u16 mac_version;
  711. u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
  712. u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
  713. u32 dirty_tx;
  714. struct rtl8169_stats rx_stats;
  715. struct rtl8169_stats tx_stats;
  716. struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
  717. struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
  718. dma_addr_t TxPhyAddr;
  719. dma_addr_t RxPhyAddr;
  720. void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
  721. struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
  722. struct timer_list timer;
  723. u16 cp_cmd;
  724. u16 event_slow;
  725. struct mdio_ops {
  726. void (*write)(struct rtl8169_private *, int, int);
  727. int (*read)(struct rtl8169_private *, int);
  728. } mdio_ops;
  729. struct pll_power_ops {
  730. void (*down)(struct rtl8169_private *);
  731. void (*up)(struct rtl8169_private *);
  732. } pll_power_ops;
  733. struct jumbo_ops {
  734. void (*enable)(struct rtl8169_private *);
  735. void (*disable)(struct rtl8169_private *);
  736. } jumbo_ops;
  737. struct csi_ops {
  738. void (*write)(struct rtl8169_private *, int, int);
  739. u32 (*read)(struct rtl8169_private *, int);
  740. } csi_ops;
  741. int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
  742. int (*get_link_ksettings)(struct net_device *,
  743. struct ethtool_link_ksettings *);
  744. void (*phy_reset_enable)(struct rtl8169_private *tp);
  745. void (*hw_start)(struct net_device *);
  746. unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
  747. unsigned int (*link_ok)(void __iomem *);
  748. int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
  749. bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
  750. struct {
  751. DECLARE_BITMAP(flags, RTL_FLAG_MAX);
  752. struct mutex mutex;
  753. struct work_struct work;
  754. } wk;
  755. unsigned features;
  756. struct mii_if_info mii;
  757. dma_addr_t counters_phys_addr;
  758. struct rtl8169_counters *counters;
  759. struct rtl8169_tc_offsets tc_offset;
  760. u32 saved_wolopts;
  761. u32 opts1_mask;
  762. struct rtl_fw {
  763. const struct firmware *fw;
  764. #define RTL_VER_SIZE 32
  765. char version[RTL_VER_SIZE];
  766. struct rtl_fw_phy_action {
  767. __le32 *code;
  768. size_t size;
  769. } phy_action;
  770. } *rtl_fw;
  771. #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
  772. u32 ocp_base;
  773. };
  774. MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
  775. MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
  776. module_param(use_dac, int, 0);
  777. MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
  778. module_param_named(debug, debug.msg_enable, int, 0);
  779. MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
  780. MODULE_LICENSE("GPL");
  781. MODULE_VERSION(RTL8169_VERSION);
  782. MODULE_FIRMWARE(FIRMWARE_8168D_1);
  783. MODULE_FIRMWARE(FIRMWARE_8168D_2);
  784. MODULE_FIRMWARE(FIRMWARE_8168E_1);
  785. MODULE_FIRMWARE(FIRMWARE_8168E_2);
  786. MODULE_FIRMWARE(FIRMWARE_8168E_3);
  787. MODULE_FIRMWARE(FIRMWARE_8105E_1);
  788. MODULE_FIRMWARE(FIRMWARE_8168F_1);
  789. MODULE_FIRMWARE(FIRMWARE_8168F_2);
  790. MODULE_FIRMWARE(FIRMWARE_8402_1);
  791. MODULE_FIRMWARE(FIRMWARE_8411_1);
  792. MODULE_FIRMWARE(FIRMWARE_8411_2);
  793. MODULE_FIRMWARE(FIRMWARE_8106E_1);
  794. MODULE_FIRMWARE(FIRMWARE_8106E_2);
  795. MODULE_FIRMWARE(FIRMWARE_8168G_2);
  796. MODULE_FIRMWARE(FIRMWARE_8168G_3);
  797. MODULE_FIRMWARE(FIRMWARE_8168H_1);
  798. MODULE_FIRMWARE(FIRMWARE_8168H_2);
  799. MODULE_FIRMWARE(FIRMWARE_8107E_1);
  800. MODULE_FIRMWARE(FIRMWARE_8107E_2);
  801. static void rtl_lock_work(struct rtl8169_private *tp)
  802. {
  803. mutex_lock(&tp->wk.mutex);
  804. }
  805. static void rtl_unlock_work(struct rtl8169_private *tp)
  806. {
  807. mutex_unlock(&tp->wk.mutex);
  808. }
  809. static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
  810. {
  811. pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
  812. PCI_EXP_DEVCTL_READRQ, force);
  813. }
  814. struct rtl_cond {
  815. bool (*check)(struct rtl8169_private *);
  816. const char *msg;
  817. };
  818. static void rtl_udelay(unsigned int d)
  819. {
  820. udelay(d);
  821. }
  822. static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
  823. void (*delay)(unsigned int), unsigned int d, int n,
  824. bool high)
  825. {
  826. int i;
  827. for (i = 0; i < n; i++) {
  828. delay(d);
  829. if (c->check(tp) == high)
  830. return true;
  831. }
  832. netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
  833. c->msg, !high, n, d);
  834. return false;
  835. }
  836. static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
  837. const struct rtl_cond *c,
  838. unsigned int d, int n)
  839. {
  840. return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
  841. }
  842. static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
  843. const struct rtl_cond *c,
  844. unsigned int d, int n)
  845. {
  846. return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
  847. }
  848. static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
  849. const struct rtl_cond *c,
  850. unsigned int d, int n)
  851. {
  852. return rtl_loop_wait(tp, c, msleep, d, n, true);
  853. }
  854. static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
  855. const struct rtl_cond *c,
  856. unsigned int d, int n)
  857. {
  858. return rtl_loop_wait(tp, c, msleep, d, n, false);
  859. }
  860. #define DECLARE_RTL_COND(name) \
  861. static bool name ## _check(struct rtl8169_private *); \
  862. \
  863. static const struct rtl_cond name = { \
  864. .check = name ## _check, \
  865. .msg = #name \
  866. }; \
  867. \
  868. static bool name ## _check(struct rtl8169_private *tp)
  869. static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
  870. {
  871. if (reg & 0xffff0001) {
  872. netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
  873. return true;
  874. }
  875. return false;
  876. }
  877. DECLARE_RTL_COND(rtl_ocp_gphy_cond)
  878. {
  879. void __iomem *ioaddr = tp->mmio_addr;
  880. return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
  881. }
  882. static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
  883. {
  884. void __iomem *ioaddr = tp->mmio_addr;
  885. if (rtl_ocp_reg_failure(tp, reg))
  886. return;
  887. RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
  888. rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
  889. }
  890. static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
  891. {
  892. void __iomem *ioaddr = tp->mmio_addr;
  893. if (rtl_ocp_reg_failure(tp, reg))
  894. return 0;
  895. RTL_W32(GPHY_OCP, reg << 15);
  896. return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
  897. (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
  898. }
  899. static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
  900. {
  901. void __iomem *ioaddr = tp->mmio_addr;
  902. if (rtl_ocp_reg_failure(tp, reg))
  903. return;
  904. RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
  905. }
  906. static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
  907. {
  908. void __iomem *ioaddr = tp->mmio_addr;
  909. if (rtl_ocp_reg_failure(tp, reg))
  910. return 0;
  911. RTL_W32(OCPDR, reg << 15);
  912. return RTL_R32(OCPDR);
  913. }
  914. #define OCP_STD_PHY_BASE 0xa400
  915. static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
  916. {
  917. if (reg == 0x1f) {
  918. tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
  919. return;
  920. }
  921. if (tp->ocp_base != OCP_STD_PHY_BASE)
  922. reg -= 0x10;
  923. r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
  924. }
  925. static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
  926. {
  927. if (tp->ocp_base != OCP_STD_PHY_BASE)
  928. reg -= 0x10;
  929. return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
  930. }
  931. static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
  932. {
  933. if (reg == 0x1f) {
  934. tp->ocp_base = value << 4;
  935. return;
  936. }
  937. r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
  938. }
  939. static int mac_mcu_read(struct rtl8169_private *tp, int reg)
  940. {
  941. return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
  942. }
  943. DECLARE_RTL_COND(rtl_phyar_cond)
  944. {
  945. void __iomem *ioaddr = tp->mmio_addr;
  946. return RTL_R32(PHYAR) & 0x80000000;
  947. }
  948. static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
  949. {
  950. void __iomem *ioaddr = tp->mmio_addr;
  951. RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
  952. rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
  953. /*
  954. * According to hardware specs a 20us delay is required after write
  955. * complete indication, but before sending next command.
  956. */
  957. udelay(20);
  958. }
  959. static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
  960. {
  961. void __iomem *ioaddr = tp->mmio_addr;
  962. int value;
  963. RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
  964. value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
  965. RTL_R32(PHYAR) & 0xffff : ~0;
  966. /*
  967. * According to hardware specs a 20us delay is required after read
  968. * complete indication, but before sending next command.
  969. */
  970. udelay(20);
  971. return value;
  972. }
  973. DECLARE_RTL_COND(rtl_ocpar_cond)
  974. {
  975. void __iomem *ioaddr = tp->mmio_addr;
  976. return RTL_R32(OCPAR) & OCPAR_FLAG;
  977. }
  978. static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
  979. {
  980. void __iomem *ioaddr = tp->mmio_addr;
  981. RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
  982. RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
  983. RTL_W32(EPHY_RXER_NUM, 0);
  984. rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
  985. }
  986. static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
  987. {
  988. r8168dp_1_mdio_access(tp, reg,
  989. OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
  990. }
  991. static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
  992. {
  993. void __iomem *ioaddr = tp->mmio_addr;
  994. r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
  995. mdelay(1);
  996. RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
  997. RTL_W32(EPHY_RXER_NUM, 0);
  998. return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
  999. RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
  1000. }
  1001. #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
  1002. static void r8168dp_2_mdio_start(void __iomem *ioaddr)
  1003. {
  1004. RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
  1005. }
  1006. static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
  1007. {
  1008. RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
  1009. }
  1010. static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
  1011. {
  1012. void __iomem *ioaddr = tp->mmio_addr;
  1013. r8168dp_2_mdio_start(ioaddr);
  1014. r8169_mdio_write(tp, reg, value);
  1015. r8168dp_2_mdio_stop(ioaddr);
  1016. }
  1017. static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
  1018. {
  1019. void __iomem *ioaddr = tp->mmio_addr;
  1020. int value;
  1021. r8168dp_2_mdio_start(ioaddr);
  1022. value = r8169_mdio_read(tp, reg);
  1023. r8168dp_2_mdio_stop(ioaddr);
  1024. return value;
  1025. }
  1026. static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
  1027. {
  1028. tp->mdio_ops.write(tp, location, val);
  1029. }
  1030. static int rtl_readphy(struct rtl8169_private *tp, int location)
  1031. {
  1032. return tp->mdio_ops.read(tp, location);
  1033. }
  1034. static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
  1035. {
  1036. rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
  1037. }
  1038. static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
  1039. {
  1040. int val;
  1041. val = rtl_readphy(tp, reg_addr);
  1042. rtl_writephy(tp, reg_addr, (val & ~m) | p);
  1043. }
  1044. static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
  1045. int val)
  1046. {
  1047. struct rtl8169_private *tp = netdev_priv(dev);
  1048. rtl_writephy(tp, location, val);
  1049. }
  1050. static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
  1051. {
  1052. struct rtl8169_private *tp = netdev_priv(dev);
  1053. return rtl_readphy(tp, location);
  1054. }
  1055. DECLARE_RTL_COND(rtl_ephyar_cond)
  1056. {
  1057. void __iomem *ioaddr = tp->mmio_addr;
  1058. return RTL_R32(EPHYAR) & EPHYAR_FLAG;
  1059. }
  1060. static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
  1061. {
  1062. void __iomem *ioaddr = tp->mmio_addr;
  1063. RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
  1064. (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
  1065. rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
  1066. udelay(10);
  1067. }
  1068. static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
  1069. {
  1070. void __iomem *ioaddr = tp->mmio_addr;
  1071. RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
  1072. return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
  1073. RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
  1074. }
  1075. DECLARE_RTL_COND(rtl_eriar_cond)
  1076. {
  1077. void __iomem *ioaddr = tp->mmio_addr;
  1078. return RTL_R32(ERIAR) & ERIAR_FLAG;
  1079. }
  1080. static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
  1081. u32 val, int type)
  1082. {
  1083. void __iomem *ioaddr = tp->mmio_addr;
  1084. BUG_ON((addr & 3) || (mask == 0));
  1085. RTL_W32(ERIDR, val);
  1086. RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
  1087. rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
  1088. }
  1089. static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
  1090. {
  1091. void __iomem *ioaddr = tp->mmio_addr;
  1092. RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
  1093. return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
  1094. RTL_R32(ERIDR) : ~0;
  1095. }
  1096. static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
  1097. u32 m, int type)
  1098. {
  1099. u32 val;
  1100. val = rtl_eri_read(tp, addr, type);
  1101. rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
  1102. }
  1103. static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
  1104. {
  1105. void __iomem *ioaddr = tp->mmio_addr;
  1106. RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
  1107. return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
  1108. RTL_R32(OCPDR) : ~0;
  1109. }
  1110. static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
  1111. {
  1112. return rtl_eri_read(tp, reg, ERIAR_OOB);
  1113. }
  1114. static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
  1115. {
  1116. switch (tp->mac_version) {
  1117. case RTL_GIGA_MAC_VER_27:
  1118. case RTL_GIGA_MAC_VER_28:
  1119. case RTL_GIGA_MAC_VER_31:
  1120. return r8168dp_ocp_read(tp, mask, reg);
  1121. case RTL_GIGA_MAC_VER_49:
  1122. case RTL_GIGA_MAC_VER_50:
  1123. case RTL_GIGA_MAC_VER_51:
  1124. return r8168ep_ocp_read(tp, mask, reg);
  1125. default:
  1126. BUG();
  1127. return ~0;
  1128. }
  1129. }
  1130. static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
  1131. u32 data)
  1132. {
  1133. void __iomem *ioaddr = tp->mmio_addr;
  1134. RTL_W32(OCPDR, data);
  1135. RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
  1136. rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
  1137. }
  1138. static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
  1139. u32 data)
  1140. {
  1141. rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
  1142. data, ERIAR_OOB);
  1143. }
  1144. static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
  1145. {
  1146. switch (tp->mac_version) {
  1147. case RTL_GIGA_MAC_VER_27:
  1148. case RTL_GIGA_MAC_VER_28:
  1149. case RTL_GIGA_MAC_VER_31:
  1150. r8168dp_ocp_write(tp, mask, reg, data);
  1151. break;
  1152. case RTL_GIGA_MAC_VER_49:
  1153. case RTL_GIGA_MAC_VER_50:
  1154. case RTL_GIGA_MAC_VER_51:
  1155. r8168ep_ocp_write(tp, mask, reg, data);
  1156. break;
  1157. default:
  1158. BUG();
  1159. break;
  1160. }
  1161. }
  1162. static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
  1163. {
  1164. rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
  1165. ocp_write(tp, 0x1, 0x30, 0x00000001);
  1166. }
  1167. #define OOB_CMD_RESET 0x00
  1168. #define OOB_CMD_DRIVER_START 0x05
  1169. #define OOB_CMD_DRIVER_STOP 0x06
  1170. static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
  1171. {
  1172. return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
  1173. }
  1174. DECLARE_RTL_COND(rtl_ocp_read_cond)
  1175. {
  1176. u16 reg;
  1177. reg = rtl8168_get_ocp_reg(tp);
  1178. return ocp_read(tp, 0x0f, reg) & 0x00000800;
  1179. }
  1180. DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
  1181. {
  1182. return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
  1183. }
  1184. DECLARE_RTL_COND(rtl_ocp_tx_cond)
  1185. {
  1186. void __iomem *ioaddr = tp->mmio_addr;
  1187. return RTL_R8(IBISR0) & 0x02;
  1188. }
  1189. static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
  1190. {
  1191. void __iomem *ioaddr = tp->mmio_addr;
  1192. RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);
  1193. rtl_msleep_loop_wait_low(tp, &rtl_ocp_tx_cond, 50, 2000);
  1194. RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);
  1195. RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);
  1196. }
  1197. static void rtl8168dp_driver_start(struct rtl8169_private *tp)
  1198. {
  1199. rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
  1200. rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
  1201. }
  1202. static void rtl8168ep_driver_start(struct rtl8169_private *tp)
  1203. {
  1204. ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
  1205. ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
  1206. rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
  1207. }
  1208. static void rtl8168_driver_start(struct rtl8169_private *tp)
  1209. {
  1210. switch (tp->mac_version) {
  1211. case RTL_GIGA_MAC_VER_27:
  1212. case RTL_GIGA_MAC_VER_28:
  1213. case RTL_GIGA_MAC_VER_31:
  1214. rtl8168dp_driver_start(tp);
  1215. break;
  1216. case RTL_GIGA_MAC_VER_49:
  1217. case RTL_GIGA_MAC_VER_50:
  1218. case RTL_GIGA_MAC_VER_51:
  1219. rtl8168ep_driver_start(tp);
  1220. break;
  1221. default:
  1222. BUG();
  1223. break;
  1224. }
  1225. }
  1226. static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
  1227. {
  1228. rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
  1229. rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
  1230. }
  1231. static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
  1232. {
  1233. rtl8168ep_stop_cmac(tp);
  1234. ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
  1235. ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
  1236. rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
  1237. }
  1238. static void rtl8168_driver_stop(struct rtl8169_private *tp)
  1239. {
  1240. switch (tp->mac_version) {
  1241. case RTL_GIGA_MAC_VER_27:
  1242. case RTL_GIGA_MAC_VER_28:
  1243. case RTL_GIGA_MAC_VER_31:
  1244. rtl8168dp_driver_stop(tp);
  1245. break;
  1246. case RTL_GIGA_MAC_VER_49:
  1247. case RTL_GIGA_MAC_VER_50:
  1248. case RTL_GIGA_MAC_VER_51:
  1249. rtl8168ep_driver_stop(tp);
  1250. break;
  1251. default:
  1252. BUG();
  1253. break;
  1254. }
  1255. }
  1256. static int r8168dp_check_dash(struct rtl8169_private *tp)
  1257. {
  1258. u16 reg = rtl8168_get_ocp_reg(tp);
  1259. return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
  1260. }
  1261. static int r8168ep_check_dash(struct rtl8169_private *tp)
  1262. {
  1263. return (ocp_read(tp, 0x0f, 0x128) & 0x00000001) ? 1 : 0;
  1264. }
  1265. static int r8168_check_dash(struct rtl8169_private *tp)
  1266. {
  1267. switch (tp->mac_version) {
  1268. case RTL_GIGA_MAC_VER_27:
  1269. case RTL_GIGA_MAC_VER_28:
  1270. case RTL_GIGA_MAC_VER_31:
  1271. return r8168dp_check_dash(tp);
  1272. case RTL_GIGA_MAC_VER_49:
  1273. case RTL_GIGA_MAC_VER_50:
  1274. case RTL_GIGA_MAC_VER_51:
  1275. return r8168ep_check_dash(tp);
  1276. default:
  1277. return 0;
  1278. }
  1279. }
  1280. struct exgmac_reg {
  1281. u16 addr;
  1282. u16 mask;
  1283. u32 val;
  1284. };
  1285. static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
  1286. const struct exgmac_reg *r, int len)
  1287. {
  1288. while (len-- > 0) {
  1289. rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
  1290. r++;
  1291. }
  1292. }
  1293. DECLARE_RTL_COND(rtl_efusear_cond)
  1294. {
  1295. void __iomem *ioaddr = tp->mmio_addr;
  1296. return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
  1297. }
  1298. static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
  1299. {
  1300. void __iomem *ioaddr = tp->mmio_addr;
  1301. RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
  1302. return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
  1303. RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
  1304. }
  1305. static u16 rtl_get_events(struct rtl8169_private *tp)
  1306. {
  1307. void __iomem *ioaddr = tp->mmio_addr;
  1308. return RTL_R16(IntrStatus);
  1309. }
  1310. static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
  1311. {
  1312. void __iomem *ioaddr = tp->mmio_addr;
  1313. RTL_W16(IntrStatus, bits);
  1314. mmiowb();
  1315. }
  1316. static void rtl_irq_disable(struct rtl8169_private *tp)
  1317. {
  1318. void __iomem *ioaddr = tp->mmio_addr;
  1319. RTL_W16(IntrMask, 0);
  1320. mmiowb();
  1321. }
  1322. static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
  1323. {
  1324. void __iomem *ioaddr = tp->mmio_addr;
  1325. RTL_W16(IntrMask, bits);
  1326. }
  1327. #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
  1328. #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
  1329. #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
  1330. static void rtl_irq_enable_all(struct rtl8169_private *tp)
  1331. {
  1332. rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
  1333. }
  1334. static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
  1335. {
  1336. void __iomem *ioaddr = tp->mmio_addr;
  1337. rtl_irq_disable(tp);
  1338. rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
  1339. RTL_R8(ChipCmd);
  1340. }
  1341. static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
  1342. {
  1343. void __iomem *ioaddr = tp->mmio_addr;
  1344. return RTL_R32(TBICSR) & TBIReset;
  1345. }
  1346. static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
  1347. {
  1348. return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
  1349. }
  1350. static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
  1351. {
  1352. return RTL_R32(TBICSR) & TBILinkOk;
  1353. }
  1354. static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
  1355. {
  1356. return RTL_R8(PHYstatus) & LinkStatus;
  1357. }
  1358. static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
  1359. {
  1360. void __iomem *ioaddr = tp->mmio_addr;
  1361. RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
  1362. }
  1363. static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
  1364. {
  1365. unsigned int val;
  1366. val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
  1367. rtl_writephy(tp, MII_BMCR, val & 0xffff);
  1368. }
  1369. static void rtl_link_chg_patch(struct rtl8169_private *tp)
  1370. {
  1371. void __iomem *ioaddr = tp->mmio_addr;
  1372. struct net_device *dev = tp->dev;
  1373. if (!netif_running(dev))
  1374. return;
  1375. if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
  1376. tp->mac_version == RTL_GIGA_MAC_VER_38) {
  1377. if (RTL_R8(PHYstatus) & _1000bpsF) {
  1378. rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
  1379. ERIAR_EXGMAC);
  1380. rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
  1381. ERIAR_EXGMAC);
  1382. } else if (RTL_R8(PHYstatus) & _100bps) {
  1383. rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
  1384. ERIAR_EXGMAC);
  1385. rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
  1386. ERIAR_EXGMAC);
  1387. } else {
  1388. rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
  1389. ERIAR_EXGMAC);
  1390. rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
  1391. ERIAR_EXGMAC);
  1392. }
  1393. /* Reset packet filter */
  1394. rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
  1395. ERIAR_EXGMAC);
  1396. rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
  1397. ERIAR_EXGMAC);
  1398. } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
  1399. tp->mac_version == RTL_GIGA_MAC_VER_36) {
  1400. if (RTL_R8(PHYstatus) & _1000bpsF) {
  1401. rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
  1402. ERIAR_EXGMAC);
  1403. rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
  1404. ERIAR_EXGMAC);
  1405. } else {
  1406. rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
  1407. ERIAR_EXGMAC);
  1408. rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
  1409. ERIAR_EXGMAC);
  1410. }
  1411. } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
  1412. if (RTL_R8(PHYstatus) & _10bps) {
  1413. rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
  1414. ERIAR_EXGMAC);
  1415. rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
  1416. ERIAR_EXGMAC);
  1417. } else {
  1418. rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
  1419. ERIAR_EXGMAC);
  1420. }
  1421. }
  1422. }
  1423. static void __rtl8169_check_link_status(struct net_device *dev,
  1424. struct rtl8169_private *tp,
  1425. void __iomem *ioaddr, bool pm)
  1426. {
  1427. if (tp->link_ok(ioaddr)) {
  1428. rtl_link_chg_patch(tp);
  1429. /* This is to cancel a scheduled suspend if there's one. */
  1430. if (pm)
  1431. pm_request_resume(&tp->pci_dev->dev);
  1432. netif_carrier_on(dev);
  1433. if (net_ratelimit())
  1434. netif_info(tp, ifup, dev, "link up\n");
  1435. } else {
  1436. netif_carrier_off(dev);
  1437. netif_info(tp, ifdown, dev, "link down\n");
  1438. if (pm)
  1439. pm_schedule_suspend(&tp->pci_dev->dev, 5000);
  1440. }
  1441. }
  1442. static void rtl8169_check_link_status(struct net_device *dev,
  1443. struct rtl8169_private *tp,
  1444. void __iomem *ioaddr)
  1445. {
  1446. __rtl8169_check_link_status(dev, tp, ioaddr, false);
  1447. }
  1448. #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
  1449. static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
  1450. {
  1451. void __iomem *ioaddr = tp->mmio_addr;
  1452. u8 options;
  1453. u32 wolopts = 0;
  1454. options = RTL_R8(Config1);
  1455. if (!(options & PMEnable))
  1456. return 0;
  1457. options = RTL_R8(Config3);
  1458. if (options & LinkUp)
  1459. wolopts |= WAKE_PHY;
  1460. switch (tp->mac_version) {
  1461. case RTL_GIGA_MAC_VER_34:
  1462. case RTL_GIGA_MAC_VER_35:
  1463. case RTL_GIGA_MAC_VER_36:
  1464. case RTL_GIGA_MAC_VER_37:
  1465. case RTL_GIGA_MAC_VER_38:
  1466. case RTL_GIGA_MAC_VER_40:
  1467. case RTL_GIGA_MAC_VER_41:
  1468. case RTL_GIGA_MAC_VER_42:
  1469. case RTL_GIGA_MAC_VER_43:
  1470. case RTL_GIGA_MAC_VER_44:
  1471. case RTL_GIGA_MAC_VER_45:
  1472. case RTL_GIGA_MAC_VER_46:
  1473. case RTL_GIGA_MAC_VER_47:
  1474. case RTL_GIGA_MAC_VER_48:
  1475. case RTL_GIGA_MAC_VER_49:
  1476. case RTL_GIGA_MAC_VER_50:
  1477. case RTL_GIGA_MAC_VER_51:
  1478. if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
  1479. wolopts |= WAKE_MAGIC;
  1480. break;
  1481. default:
  1482. if (options & MagicPacket)
  1483. wolopts |= WAKE_MAGIC;
  1484. break;
  1485. }
  1486. options = RTL_R8(Config5);
  1487. if (options & UWF)
  1488. wolopts |= WAKE_UCAST;
  1489. if (options & BWF)
  1490. wolopts |= WAKE_BCAST;
  1491. if (options & MWF)
  1492. wolopts |= WAKE_MCAST;
  1493. return wolopts;
  1494. }
  1495. static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  1496. {
  1497. struct rtl8169_private *tp = netdev_priv(dev);
  1498. struct device *d = &tp->pci_dev->dev;
  1499. pm_runtime_get_noresume(d);
  1500. rtl_lock_work(tp);
  1501. wol->supported = WAKE_ANY;
  1502. if (pm_runtime_active(d))
  1503. wol->wolopts = __rtl8169_get_wol(tp);
  1504. else
  1505. wol->wolopts = tp->saved_wolopts;
  1506. rtl_unlock_work(tp);
  1507. pm_runtime_put_noidle(d);
  1508. }
  1509. static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
  1510. {
  1511. void __iomem *ioaddr = tp->mmio_addr;
  1512. unsigned int i, tmp;
  1513. static const struct {
  1514. u32 opt;
  1515. u16 reg;
  1516. u8 mask;
  1517. } cfg[] = {
  1518. { WAKE_PHY, Config3, LinkUp },
  1519. { WAKE_UCAST, Config5, UWF },
  1520. { WAKE_BCAST, Config5, BWF },
  1521. { WAKE_MCAST, Config5, MWF },
  1522. { WAKE_ANY, Config5, LanWake },
  1523. { WAKE_MAGIC, Config3, MagicPacket }
  1524. };
  1525. u8 options;
  1526. RTL_W8(Cfg9346, Cfg9346_Unlock);
  1527. switch (tp->mac_version) {
  1528. case RTL_GIGA_MAC_VER_34:
  1529. case RTL_GIGA_MAC_VER_35:
  1530. case RTL_GIGA_MAC_VER_36:
  1531. case RTL_GIGA_MAC_VER_37:
  1532. case RTL_GIGA_MAC_VER_38:
  1533. case RTL_GIGA_MAC_VER_40:
  1534. case RTL_GIGA_MAC_VER_41:
  1535. case RTL_GIGA_MAC_VER_42:
  1536. case RTL_GIGA_MAC_VER_43:
  1537. case RTL_GIGA_MAC_VER_44:
  1538. case RTL_GIGA_MAC_VER_45:
  1539. case RTL_GIGA_MAC_VER_46:
  1540. case RTL_GIGA_MAC_VER_47:
  1541. case RTL_GIGA_MAC_VER_48:
  1542. case RTL_GIGA_MAC_VER_49:
  1543. case RTL_GIGA_MAC_VER_50:
  1544. case RTL_GIGA_MAC_VER_51:
  1545. tmp = ARRAY_SIZE(cfg) - 1;
  1546. if (wolopts & WAKE_MAGIC)
  1547. rtl_w0w1_eri(tp,
  1548. 0x0dc,
  1549. ERIAR_MASK_0100,
  1550. MagicPacket_v2,
  1551. 0x0000,
  1552. ERIAR_EXGMAC);
  1553. else
  1554. rtl_w0w1_eri(tp,
  1555. 0x0dc,
  1556. ERIAR_MASK_0100,
  1557. 0x0000,
  1558. MagicPacket_v2,
  1559. ERIAR_EXGMAC);
  1560. break;
  1561. default:
  1562. tmp = ARRAY_SIZE(cfg);
  1563. break;
  1564. }
  1565. for (i = 0; i < tmp; i++) {
  1566. options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
  1567. if (wolopts & cfg[i].opt)
  1568. options |= cfg[i].mask;
  1569. RTL_W8(cfg[i].reg, options);
  1570. }
  1571. switch (tp->mac_version) {
  1572. case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
  1573. options = RTL_R8(Config1) & ~PMEnable;
  1574. if (wolopts)
  1575. options |= PMEnable;
  1576. RTL_W8(Config1, options);
  1577. break;
  1578. default:
  1579. options = RTL_R8(Config2) & ~PME_SIGNAL;
  1580. if (wolopts)
  1581. options |= PME_SIGNAL;
  1582. RTL_W8(Config2, options);
  1583. break;
  1584. }
  1585. RTL_W8(Cfg9346, Cfg9346_Lock);
  1586. }
  1587. static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  1588. {
  1589. struct rtl8169_private *tp = netdev_priv(dev);
  1590. struct device *d = &tp->pci_dev->dev;
  1591. pm_runtime_get_noresume(d);
  1592. rtl_lock_work(tp);
  1593. if (wol->wolopts)
  1594. tp->features |= RTL_FEATURE_WOL;
  1595. else
  1596. tp->features &= ~RTL_FEATURE_WOL;
  1597. if (pm_runtime_active(d))
  1598. __rtl8169_set_wol(tp, wol->wolopts);
  1599. else
  1600. tp->saved_wolopts = wol->wolopts;
  1601. rtl_unlock_work(tp);
  1602. device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
  1603. pm_runtime_put_noidle(d);
  1604. return 0;
  1605. }
  1606. static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
  1607. {
  1608. return rtl_chip_infos[tp->mac_version].fw_name;
  1609. }
  1610. static void rtl8169_get_drvinfo(struct net_device *dev,
  1611. struct ethtool_drvinfo *info)
  1612. {
  1613. struct rtl8169_private *tp = netdev_priv(dev);
  1614. struct rtl_fw *rtl_fw = tp->rtl_fw;
  1615. strlcpy(info->driver, MODULENAME, sizeof(info->driver));
  1616. strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
  1617. strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
  1618. BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
  1619. if (!IS_ERR_OR_NULL(rtl_fw))
  1620. strlcpy(info->fw_version, rtl_fw->version,
  1621. sizeof(info->fw_version));
  1622. }
  1623. static int rtl8169_get_regs_len(struct net_device *dev)
  1624. {
  1625. return R8169_REGS_SIZE;
  1626. }
  1627. static int rtl8169_set_speed_tbi(struct net_device *dev,
  1628. u8 autoneg, u16 speed, u8 duplex, u32 ignored)
  1629. {
  1630. struct rtl8169_private *tp = netdev_priv(dev);
  1631. void __iomem *ioaddr = tp->mmio_addr;
  1632. int ret = 0;
  1633. u32 reg;
  1634. reg = RTL_R32(TBICSR);
  1635. if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
  1636. (duplex == DUPLEX_FULL)) {
  1637. RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
  1638. } else if (autoneg == AUTONEG_ENABLE)
  1639. RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
  1640. else {
  1641. netif_warn(tp, link, dev,
  1642. "incorrect speed setting refused in TBI mode\n");
  1643. ret = -EOPNOTSUPP;
  1644. }
  1645. return ret;
  1646. }
  1647. static int rtl8169_set_speed_xmii(struct net_device *dev,
  1648. u8 autoneg, u16 speed, u8 duplex, u32 adv)
  1649. {
  1650. struct rtl8169_private *tp = netdev_priv(dev);
  1651. int giga_ctrl, bmcr;
  1652. int rc = -EINVAL;
  1653. rtl_writephy(tp, 0x1f, 0x0000);
  1654. if (autoneg == AUTONEG_ENABLE) {
  1655. int auto_nego;
  1656. auto_nego = rtl_readphy(tp, MII_ADVERTISE);
  1657. auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
  1658. ADVERTISE_100HALF | ADVERTISE_100FULL);
  1659. if (adv & ADVERTISED_10baseT_Half)
  1660. auto_nego |= ADVERTISE_10HALF;
  1661. if (adv & ADVERTISED_10baseT_Full)
  1662. auto_nego |= ADVERTISE_10FULL;
  1663. if (adv & ADVERTISED_100baseT_Half)
  1664. auto_nego |= ADVERTISE_100HALF;
  1665. if (adv & ADVERTISED_100baseT_Full)
  1666. auto_nego |= ADVERTISE_100FULL;
  1667. auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  1668. giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
  1669. giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
  1670. /* The 8100e/8101e/8102e do Fast Ethernet only. */
  1671. if (tp->mii.supports_gmii) {
  1672. if (adv & ADVERTISED_1000baseT_Half)
  1673. giga_ctrl |= ADVERTISE_1000HALF;
  1674. if (adv & ADVERTISED_1000baseT_Full)
  1675. giga_ctrl |= ADVERTISE_1000FULL;
  1676. } else if (adv & (ADVERTISED_1000baseT_Half |
  1677. ADVERTISED_1000baseT_Full)) {
  1678. netif_info(tp, link, dev,
  1679. "PHY does not support 1000Mbps\n");
  1680. goto out;
  1681. }
  1682. bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
  1683. rtl_writephy(tp, MII_ADVERTISE, auto_nego);
  1684. rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
  1685. } else {
  1686. giga_ctrl = 0;
  1687. if (speed == SPEED_10)
  1688. bmcr = 0;
  1689. else if (speed == SPEED_100)
  1690. bmcr = BMCR_SPEED100;
  1691. else
  1692. goto out;
  1693. if (duplex == DUPLEX_FULL)
  1694. bmcr |= BMCR_FULLDPLX;
  1695. }
  1696. rtl_writephy(tp, MII_BMCR, bmcr);
  1697. if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
  1698. tp->mac_version == RTL_GIGA_MAC_VER_03) {
  1699. if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
  1700. rtl_writephy(tp, 0x17, 0x2138);
  1701. rtl_writephy(tp, 0x0e, 0x0260);
  1702. } else {
  1703. rtl_writephy(tp, 0x17, 0x2108);
  1704. rtl_writephy(tp, 0x0e, 0x0000);
  1705. }
  1706. }
  1707. rc = 0;
  1708. out:
  1709. return rc;
  1710. }
  1711. static int rtl8169_set_speed(struct net_device *dev,
  1712. u8 autoneg, u16 speed, u8 duplex, u32 advertising)
  1713. {
  1714. struct rtl8169_private *tp = netdev_priv(dev);
  1715. int ret;
  1716. ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
  1717. if (ret < 0)
  1718. goto out;
  1719. if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
  1720. (advertising & ADVERTISED_1000baseT_Full) &&
  1721. !pci_is_pcie(tp->pci_dev)) {
  1722. mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
  1723. }
  1724. out:
  1725. return ret;
  1726. }
  1727. static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1728. {
  1729. struct rtl8169_private *tp = netdev_priv(dev);
  1730. int ret;
  1731. del_timer_sync(&tp->timer);
  1732. rtl_lock_work(tp);
  1733. ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
  1734. cmd->duplex, cmd->advertising);
  1735. rtl_unlock_work(tp);
  1736. return ret;
  1737. }
  1738. static netdev_features_t rtl8169_fix_features(struct net_device *dev,
  1739. netdev_features_t features)
  1740. {
  1741. struct rtl8169_private *tp = netdev_priv(dev);
  1742. if (dev->mtu > TD_MSS_MAX)
  1743. features &= ~NETIF_F_ALL_TSO;
  1744. if (dev->mtu > JUMBO_1K &&
  1745. !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
  1746. features &= ~NETIF_F_IP_CSUM;
  1747. return features;
  1748. }
  1749. static void __rtl8169_set_features(struct net_device *dev,
  1750. netdev_features_t features)
  1751. {
  1752. struct rtl8169_private *tp = netdev_priv(dev);
  1753. void __iomem *ioaddr = tp->mmio_addr;
  1754. u32 rx_config;
  1755. rx_config = RTL_R32(RxConfig);
  1756. if (features & NETIF_F_RXALL)
  1757. rx_config |= (AcceptErr | AcceptRunt);
  1758. else
  1759. rx_config &= ~(AcceptErr | AcceptRunt);
  1760. RTL_W32(RxConfig, rx_config);
  1761. if (features & NETIF_F_RXCSUM)
  1762. tp->cp_cmd |= RxChkSum;
  1763. else
  1764. tp->cp_cmd &= ~RxChkSum;
  1765. if (features & NETIF_F_HW_VLAN_CTAG_RX)
  1766. tp->cp_cmd |= RxVlan;
  1767. else
  1768. tp->cp_cmd &= ~RxVlan;
  1769. tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
  1770. RTL_W16(CPlusCmd, tp->cp_cmd);
  1771. RTL_R16(CPlusCmd);
  1772. }
  1773. static int rtl8169_set_features(struct net_device *dev,
  1774. netdev_features_t features)
  1775. {
  1776. struct rtl8169_private *tp = netdev_priv(dev);
  1777. features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
  1778. rtl_lock_work(tp);
  1779. if (features ^ dev->features)
  1780. __rtl8169_set_features(dev, features);
  1781. rtl_unlock_work(tp);
  1782. return 0;
  1783. }
  1784. static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
  1785. {
  1786. return (skb_vlan_tag_present(skb)) ?
  1787. TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
  1788. }
  1789. static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
  1790. {
  1791. u32 opts2 = le32_to_cpu(desc->opts2);
  1792. if (opts2 & RxVlanTag)
  1793. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
  1794. }
  1795. static int rtl8169_get_link_ksettings_tbi(struct net_device *dev,
  1796. struct ethtool_link_ksettings *cmd)
  1797. {
  1798. struct rtl8169_private *tp = netdev_priv(dev);
  1799. void __iomem *ioaddr = tp->mmio_addr;
  1800. u32 status;
  1801. u32 supported, advertising;
  1802. supported =
  1803. SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
  1804. cmd->base.port = PORT_FIBRE;
  1805. status = RTL_R32(TBICSR);
  1806. advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
  1807. cmd->base.autoneg = !!(status & TBINwEnable);
  1808. cmd->base.speed = SPEED_1000;
  1809. cmd->base.duplex = DUPLEX_FULL; /* Always set */
  1810. ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
  1811. supported);
  1812. ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
  1813. advertising);
  1814. return 0;
  1815. }
  1816. static int rtl8169_get_link_ksettings_xmii(struct net_device *dev,
  1817. struct ethtool_link_ksettings *cmd)
  1818. {
  1819. struct rtl8169_private *tp = netdev_priv(dev);
  1820. return mii_ethtool_get_link_ksettings(&tp->mii, cmd);
  1821. }
  1822. static int rtl8169_get_link_ksettings(struct net_device *dev,
  1823. struct ethtool_link_ksettings *cmd)
  1824. {
  1825. struct rtl8169_private *tp = netdev_priv(dev);
  1826. int rc;
  1827. rtl_lock_work(tp);
  1828. rc = tp->get_link_ksettings(dev, cmd);
  1829. rtl_unlock_work(tp);
  1830. return rc;
  1831. }
  1832. static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
  1833. void *p)
  1834. {
  1835. struct rtl8169_private *tp = netdev_priv(dev);
  1836. u32 __iomem *data = tp->mmio_addr;
  1837. u32 *dw = p;
  1838. int i;
  1839. rtl_lock_work(tp);
  1840. for (i = 0; i < R8169_REGS_SIZE; i += 4)
  1841. memcpy_fromio(dw++, data++, 4);
  1842. rtl_unlock_work(tp);
  1843. }
  1844. static u32 rtl8169_get_msglevel(struct net_device *dev)
  1845. {
  1846. struct rtl8169_private *tp = netdev_priv(dev);
  1847. return tp->msg_enable;
  1848. }
  1849. static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
  1850. {
  1851. struct rtl8169_private *tp = netdev_priv(dev);
  1852. tp->msg_enable = value;
  1853. }
  1854. static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
  1855. "tx_packets",
  1856. "rx_packets",
  1857. "tx_errors",
  1858. "rx_errors",
  1859. "rx_missed",
  1860. "align_errors",
  1861. "tx_single_collisions",
  1862. "tx_multi_collisions",
  1863. "unicast",
  1864. "broadcast",
  1865. "multicast",
  1866. "tx_aborted",
  1867. "tx_underrun",
  1868. };
  1869. static int rtl8169_get_sset_count(struct net_device *dev, int sset)
  1870. {
  1871. switch (sset) {
  1872. case ETH_SS_STATS:
  1873. return ARRAY_SIZE(rtl8169_gstrings);
  1874. default:
  1875. return -EOPNOTSUPP;
  1876. }
  1877. }
  1878. DECLARE_RTL_COND(rtl_counters_cond)
  1879. {
  1880. void __iomem *ioaddr = tp->mmio_addr;
  1881. return RTL_R32(CounterAddrLow) & (CounterReset | CounterDump);
  1882. }
  1883. static bool rtl8169_do_counters(struct net_device *dev, u32 counter_cmd)
  1884. {
  1885. struct rtl8169_private *tp = netdev_priv(dev);
  1886. void __iomem *ioaddr = tp->mmio_addr;
  1887. dma_addr_t paddr = tp->counters_phys_addr;
  1888. u32 cmd;
  1889. bool ret;
  1890. RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
  1891. cmd = (u64)paddr & DMA_BIT_MASK(32);
  1892. RTL_W32(CounterAddrLow, cmd);
  1893. RTL_W32(CounterAddrLow, cmd | counter_cmd);
  1894. ret = rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
  1895. RTL_W32(CounterAddrLow, 0);
  1896. RTL_W32(CounterAddrHigh, 0);
  1897. return ret;
  1898. }
  1899. static bool rtl8169_reset_counters(struct net_device *dev)
  1900. {
  1901. struct rtl8169_private *tp = netdev_priv(dev);
  1902. /*
  1903. * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
  1904. * tally counters.
  1905. */
  1906. if (tp->mac_version < RTL_GIGA_MAC_VER_19)
  1907. return true;
  1908. return rtl8169_do_counters(dev, CounterReset);
  1909. }
  1910. static bool rtl8169_update_counters(struct net_device *dev)
  1911. {
  1912. struct rtl8169_private *tp = netdev_priv(dev);
  1913. void __iomem *ioaddr = tp->mmio_addr;
  1914. /*
  1915. * Some chips are unable to dump tally counters when the receiver
  1916. * is disabled.
  1917. */
  1918. if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
  1919. return true;
  1920. return rtl8169_do_counters(dev, CounterDump);
  1921. }
  1922. static bool rtl8169_init_counter_offsets(struct net_device *dev)
  1923. {
  1924. struct rtl8169_private *tp = netdev_priv(dev);
  1925. struct rtl8169_counters *counters = tp->counters;
  1926. bool ret = false;
  1927. /*
  1928. * rtl8169_init_counter_offsets is called from rtl_open. On chip
  1929. * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
  1930. * reset by a power cycle, while the counter values collected by the
  1931. * driver are reset at every driver unload/load cycle.
  1932. *
  1933. * To make sure the HW values returned by @get_stats64 match the SW
  1934. * values, we collect the initial values at first open(*) and use them
  1935. * as offsets to normalize the values returned by @get_stats64.
  1936. *
  1937. * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
  1938. * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
  1939. * set at open time by rtl_hw_start.
  1940. */
  1941. if (tp->tc_offset.inited)
  1942. return true;
  1943. /* If both, reset and update fail, propagate to caller. */
  1944. if (rtl8169_reset_counters(dev))
  1945. ret = true;
  1946. if (rtl8169_update_counters(dev))
  1947. ret = true;
  1948. tp->tc_offset.tx_errors = counters->tx_errors;
  1949. tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
  1950. tp->tc_offset.tx_aborted = counters->tx_aborted;
  1951. tp->tc_offset.inited = true;
  1952. return ret;
  1953. }
  1954. static void rtl8169_get_ethtool_stats(struct net_device *dev,
  1955. struct ethtool_stats *stats, u64 *data)
  1956. {
  1957. struct rtl8169_private *tp = netdev_priv(dev);
  1958. struct device *d = &tp->pci_dev->dev;
  1959. struct rtl8169_counters *counters = tp->counters;
  1960. ASSERT_RTNL();
  1961. pm_runtime_get_noresume(d);
  1962. if (pm_runtime_active(d))
  1963. rtl8169_update_counters(dev);
  1964. pm_runtime_put_noidle(d);
  1965. data[0] = le64_to_cpu(counters->tx_packets);
  1966. data[1] = le64_to_cpu(counters->rx_packets);
  1967. data[2] = le64_to_cpu(counters->tx_errors);
  1968. data[3] = le32_to_cpu(counters->rx_errors);
  1969. data[4] = le16_to_cpu(counters->rx_missed);
  1970. data[5] = le16_to_cpu(counters->align_errors);
  1971. data[6] = le32_to_cpu(counters->tx_one_collision);
  1972. data[7] = le32_to_cpu(counters->tx_multi_collision);
  1973. data[8] = le64_to_cpu(counters->rx_unicast);
  1974. data[9] = le64_to_cpu(counters->rx_broadcast);
  1975. data[10] = le32_to_cpu(counters->rx_multicast);
  1976. data[11] = le16_to_cpu(counters->tx_aborted);
  1977. data[12] = le16_to_cpu(counters->tx_underun);
  1978. }
  1979. static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  1980. {
  1981. switch(stringset) {
  1982. case ETH_SS_STATS:
  1983. memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
  1984. break;
  1985. }
  1986. }
  1987. static int rtl8169_nway_reset(struct net_device *dev)
  1988. {
  1989. struct rtl8169_private *tp = netdev_priv(dev);
  1990. return mii_nway_restart(&tp->mii);
  1991. }
  1992. static const struct ethtool_ops rtl8169_ethtool_ops = {
  1993. .get_drvinfo = rtl8169_get_drvinfo,
  1994. .get_regs_len = rtl8169_get_regs_len,
  1995. .get_link = ethtool_op_get_link,
  1996. .set_settings = rtl8169_set_settings,
  1997. .get_msglevel = rtl8169_get_msglevel,
  1998. .set_msglevel = rtl8169_set_msglevel,
  1999. .get_regs = rtl8169_get_regs,
  2000. .get_wol = rtl8169_get_wol,
  2001. .set_wol = rtl8169_set_wol,
  2002. .get_strings = rtl8169_get_strings,
  2003. .get_sset_count = rtl8169_get_sset_count,
  2004. .get_ethtool_stats = rtl8169_get_ethtool_stats,
  2005. .get_ts_info = ethtool_op_get_ts_info,
  2006. .nway_reset = rtl8169_nway_reset,
  2007. .get_link_ksettings = rtl8169_get_link_ksettings,
  2008. };
  2009. static void rtl8169_get_mac_version(struct rtl8169_private *tp,
  2010. struct net_device *dev, u8 default_version)
  2011. {
  2012. void __iomem *ioaddr = tp->mmio_addr;
  2013. /*
  2014. * The driver currently handles the 8168Bf and the 8168Be identically
  2015. * but they can be identified more specifically through the test below
  2016. * if needed:
  2017. *
  2018. * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
  2019. *
  2020. * Same thing for the 8101Eb and the 8101Ec:
  2021. *
  2022. * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
  2023. */
  2024. static const struct rtl_mac_info {
  2025. u32 mask;
  2026. u32 val;
  2027. int mac_version;
  2028. } mac_info[] = {
  2029. /* 8168EP family. */
  2030. { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
  2031. { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
  2032. { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
  2033. /* 8168H family. */
  2034. { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
  2035. { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
  2036. /* 8168G family. */
  2037. { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
  2038. { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
  2039. { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
  2040. { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
  2041. /* 8168F family. */
  2042. { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
  2043. { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
  2044. { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
  2045. /* 8168E family. */
  2046. { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
  2047. { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
  2048. { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
  2049. { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
  2050. /* 8168D family. */
  2051. { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
  2052. { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
  2053. { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
  2054. /* 8168DP family. */
  2055. { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
  2056. { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
  2057. { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
  2058. /* 8168C family. */
  2059. { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
  2060. { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
  2061. { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
  2062. { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
  2063. { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
  2064. { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
  2065. { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
  2066. { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
  2067. { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
  2068. /* 8168B family. */
  2069. { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
  2070. { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
  2071. { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
  2072. { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
  2073. /* 8101 family. */
  2074. { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
  2075. { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
  2076. { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
  2077. { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
  2078. { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
  2079. { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
  2080. { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
  2081. { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
  2082. { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
  2083. { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
  2084. { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
  2085. { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
  2086. { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
  2087. { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
  2088. { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
  2089. { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
  2090. { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
  2091. { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
  2092. { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
  2093. /* FIXME: where did these entries come from ? -- FR */
  2094. { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
  2095. { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
  2096. /* 8110 family. */
  2097. { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
  2098. { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
  2099. { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
  2100. { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
  2101. { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
  2102. { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
  2103. /* Catch-all */
  2104. { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
  2105. };
  2106. const struct rtl_mac_info *p = mac_info;
  2107. u32 reg;
  2108. reg = RTL_R32(TxConfig);
  2109. while ((reg & p->mask) != p->val)
  2110. p++;
  2111. tp->mac_version = p->mac_version;
  2112. if (tp->mac_version == RTL_GIGA_MAC_NONE) {
  2113. netif_notice(tp, probe, dev,
  2114. "unknown MAC, using family default\n");
  2115. tp->mac_version = default_version;
  2116. } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
  2117. tp->mac_version = tp->mii.supports_gmii ?
  2118. RTL_GIGA_MAC_VER_42 :
  2119. RTL_GIGA_MAC_VER_43;
  2120. } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
  2121. tp->mac_version = tp->mii.supports_gmii ?
  2122. RTL_GIGA_MAC_VER_45 :
  2123. RTL_GIGA_MAC_VER_47;
  2124. } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
  2125. tp->mac_version = tp->mii.supports_gmii ?
  2126. RTL_GIGA_MAC_VER_46 :
  2127. RTL_GIGA_MAC_VER_48;
  2128. }
  2129. }
  2130. static void rtl8169_print_mac_version(struct rtl8169_private *tp)
  2131. {
  2132. dprintk("mac_version = 0x%02x\n", tp->mac_version);
  2133. }
  2134. struct phy_reg {
  2135. u16 reg;
  2136. u16 val;
  2137. };
  2138. static void rtl_writephy_batch(struct rtl8169_private *tp,
  2139. const struct phy_reg *regs, int len)
  2140. {
  2141. while (len-- > 0) {
  2142. rtl_writephy(tp, regs->reg, regs->val);
  2143. regs++;
  2144. }
  2145. }
  2146. #define PHY_READ 0x00000000
  2147. #define PHY_DATA_OR 0x10000000
  2148. #define PHY_DATA_AND 0x20000000
  2149. #define PHY_BJMPN 0x30000000
  2150. #define PHY_MDIO_CHG 0x40000000
  2151. #define PHY_CLEAR_READCOUNT 0x70000000
  2152. #define PHY_WRITE 0x80000000
  2153. #define PHY_READCOUNT_EQ_SKIP 0x90000000
  2154. #define PHY_COMP_EQ_SKIPN 0xa0000000
  2155. #define PHY_COMP_NEQ_SKIPN 0xb0000000
  2156. #define PHY_WRITE_PREVIOUS 0xc0000000
  2157. #define PHY_SKIPN 0xd0000000
  2158. #define PHY_DELAY_MS 0xe0000000
  2159. struct fw_info {
  2160. u32 magic;
  2161. char version[RTL_VER_SIZE];
  2162. __le32 fw_start;
  2163. __le32 fw_len;
  2164. u8 chksum;
  2165. } __packed;
  2166. #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
  2167. static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
  2168. {
  2169. const struct firmware *fw = rtl_fw->fw;
  2170. struct fw_info *fw_info = (struct fw_info *)fw->data;
  2171. struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
  2172. char *version = rtl_fw->version;
  2173. bool rc = false;
  2174. if (fw->size < FW_OPCODE_SIZE)
  2175. goto out;
  2176. if (!fw_info->magic) {
  2177. size_t i, size, start;
  2178. u8 checksum = 0;
  2179. if (fw->size < sizeof(*fw_info))
  2180. goto out;
  2181. for (i = 0; i < fw->size; i++)
  2182. checksum += fw->data[i];
  2183. if (checksum != 0)
  2184. goto out;
  2185. start = le32_to_cpu(fw_info->fw_start);
  2186. if (start > fw->size)
  2187. goto out;
  2188. size = le32_to_cpu(fw_info->fw_len);
  2189. if (size > (fw->size - start) / FW_OPCODE_SIZE)
  2190. goto out;
  2191. memcpy(version, fw_info->version, RTL_VER_SIZE);
  2192. pa->code = (__le32 *)(fw->data + start);
  2193. pa->size = size;
  2194. } else {
  2195. if (fw->size % FW_OPCODE_SIZE)
  2196. goto out;
  2197. strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
  2198. pa->code = (__le32 *)fw->data;
  2199. pa->size = fw->size / FW_OPCODE_SIZE;
  2200. }
  2201. version[RTL_VER_SIZE - 1] = 0;
  2202. rc = true;
  2203. out:
  2204. return rc;
  2205. }
  2206. static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
  2207. struct rtl_fw_phy_action *pa)
  2208. {
  2209. bool rc = false;
  2210. size_t index;
  2211. for (index = 0; index < pa->size; index++) {
  2212. u32 action = le32_to_cpu(pa->code[index]);
  2213. u32 regno = (action & 0x0fff0000) >> 16;
  2214. switch(action & 0xf0000000) {
  2215. case PHY_READ:
  2216. case PHY_DATA_OR:
  2217. case PHY_DATA_AND:
  2218. case PHY_MDIO_CHG:
  2219. case PHY_CLEAR_READCOUNT:
  2220. case PHY_WRITE:
  2221. case PHY_WRITE_PREVIOUS:
  2222. case PHY_DELAY_MS:
  2223. break;
  2224. case PHY_BJMPN:
  2225. if (regno > index) {
  2226. netif_err(tp, ifup, tp->dev,
  2227. "Out of range of firmware\n");
  2228. goto out;
  2229. }
  2230. break;
  2231. case PHY_READCOUNT_EQ_SKIP:
  2232. if (index + 2 >= pa->size) {
  2233. netif_err(tp, ifup, tp->dev,
  2234. "Out of range of firmware\n");
  2235. goto out;
  2236. }
  2237. break;
  2238. case PHY_COMP_EQ_SKIPN:
  2239. case PHY_COMP_NEQ_SKIPN:
  2240. case PHY_SKIPN:
  2241. if (index + 1 + regno >= pa->size) {
  2242. netif_err(tp, ifup, tp->dev,
  2243. "Out of range of firmware\n");
  2244. goto out;
  2245. }
  2246. break;
  2247. default:
  2248. netif_err(tp, ifup, tp->dev,
  2249. "Invalid action 0x%08x\n", action);
  2250. goto out;
  2251. }
  2252. }
  2253. rc = true;
  2254. out:
  2255. return rc;
  2256. }
  2257. static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
  2258. {
  2259. struct net_device *dev = tp->dev;
  2260. int rc = -EINVAL;
  2261. if (!rtl_fw_format_ok(tp, rtl_fw)) {
  2262. netif_err(tp, ifup, dev, "invalid firmware\n");
  2263. goto out;
  2264. }
  2265. if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
  2266. rc = 0;
  2267. out:
  2268. return rc;
  2269. }
  2270. static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
  2271. {
  2272. struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
  2273. struct mdio_ops org, *ops = &tp->mdio_ops;
  2274. u32 predata, count;
  2275. size_t index;
  2276. predata = count = 0;
  2277. org.write = ops->write;
  2278. org.read = ops->read;
  2279. for (index = 0; index < pa->size; ) {
  2280. u32 action = le32_to_cpu(pa->code[index]);
  2281. u32 data = action & 0x0000ffff;
  2282. u32 regno = (action & 0x0fff0000) >> 16;
  2283. if (!action)
  2284. break;
  2285. switch(action & 0xf0000000) {
  2286. case PHY_READ:
  2287. predata = rtl_readphy(tp, regno);
  2288. count++;
  2289. index++;
  2290. break;
  2291. case PHY_DATA_OR:
  2292. predata |= data;
  2293. index++;
  2294. break;
  2295. case PHY_DATA_AND:
  2296. predata &= data;
  2297. index++;
  2298. break;
  2299. case PHY_BJMPN:
  2300. index -= regno;
  2301. break;
  2302. case PHY_MDIO_CHG:
  2303. if (data == 0) {
  2304. ops->write = org.write;
  2305. ops->read = org.read;
  2306. } else if (data == 1) {
  2307. ops->write = mac_mcu_write;
  2308. ops->read = mac_mcu_read;
  2309. }
  2310. index++;
  2311. break;
  2312. case PHY_CLEAR_READCOUNT:
  2313. count = 0;
  2314. index++;
  2315. break;
  2316. case PHY_WRITE:
  2317. rtl_writephy(tp, regno, data);
  2318. index++;
  2319. break;
  2320. case PHY_READCOUNT_EQ_SKIP:
  2321. index += (count == data) ? 2 : 1;
  2322. break;
  2323. case PHY_COMP_EQ_SKIPN:
  2324. if (predata == data)
  2325. index += regno;
  2326. index++;
  2327. break;
  2328. case PHY_COMP_NEQ_SKIPN:
  2329. if (predata != data)
  2330. index += regno;
  2331. index++;
  2332. break;
  2333. case PHY_WRITE_PREVIOUS:
  2334. rtl_writephy(tp, regno, predata);
  2335. index++;
  2336. break;
  2337. case PHY_SKIPN:
  2338. index += regno + 1;
  2339. break;
  2340. case PHY_DELAY_MS:
  2341. mdelay(data);
  2342. index++;
  2343. break;
  2344. default:
  2345. BUG();
  2346. }
  2347. }
  2348. ops->write = org.write;
  2349. ops->read = org.read;
  2350. }
  2351. static void rtl_release_firmware(struct rtl8169_private *tp)
  2352. {
  2353. if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
  2354. release_firmware(tp->rtl_fw->fw);
  2355. kfree(tp->rtl_fw);
  2356. }
  2357. tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
  2358. }
  2359. static void rtl_apply_firmware(struct rtl8169_private *tp)
  2360. {
  2361. struct rtl_fw *rtl_fw = tp->rtl_fw;
  2362. /* TODO: release firmware once rtl_phy_write_fw signals failures. */
  2363. if (!IS_ERR_OR_NULL(rtl_fw))
  2364. rtl_phy_write_fw(tp, rtl_fw);
  2365. }
  2366. static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
  2367. {
  2368. if (rtl_readphy(tp, reg) != val)
  2369. netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
  2370. else
  2371. rtl_apply_firmware(tp);
  2372. }
  2373. static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
  2374. {
  2375. static const struct phy_reg phy_reg_init[] = {
  2376. { 0x1f, 0x0001 },
  2377. { 0x06, 0x006e },
  2378. { 0x08, 0x0708 },
  2379. { 0x15, 0x4000 },
  2380. { 0x18, 0x65c7 },
  2381. { 0x1f, 0x0001 },
  2382. { 0x03, 0x00a1 },
  2383. { 0x02, 0x0008 },
  2384. { 0x01, 0x0120 },
  2385. { 0x00, 0x1000 },
  2386. { 0x04, 0x0800 },
  2387. { 0x04, 0x0000 },
  2388. { 0x03, 0xff41 },
  2389. { 0x02, 0xdf60 },
  2390. { 0x01, 0x0140 },
  2391. { 0x00, 0x0077 },
  2392. { 0x04, 0x7800 },
  2393. { 0x04, 0x7000 },
  2394. { 0x03, 0x802f },
  2395. { 0x02, 0x4f02 },
  2396. { 0x01, 0x0409 },
  2397. { 0x00, 0xf0f9 },
  2398. { 0x04, 0x9800 },
  2399. { 0x04, 0x9000 },
  2400. { 0x03, 0xdf01 },
  2401. { 0x02, 0xdf20 },
  2402. { 0x01, 0xff95 },
  2403. { 0x00, 0xba00 },
  2404. { 0x04, 0xa800 },
  2405. { 0x04, 0xa000 },
  2406. { 0x03, 0xff41 },
  2407. { 0x02, 0xdf20 },
  2408. { 0x01, 0x0140 },
  2409. { 0x00, 0x00bb },
  2410. { 0x04, 0xb800 },
  2411. { 0x04, 0xb000 },
  2412. { 0x03, 0xdf41 },
  2413. { 0x02, 0xdc60 },
  2414. { 0x01, 0x6340 },
  2415. { 0x00, 0x007d },
  2416. { 0x04, 0xd800 },
  2417. { 0x04, 0xd000 },
  2418. { 0x03, 0xdf01 },
  2419. { 0x02, 0xdf20 },
  2420. { 0x01, 0x100a },
  2421. { 0x00, 0xa0ff },
  2422. { 0x04, 0xf800 },
  2423. { 0x04, 0xf000 },
  2424. { 0x1f, 0x0000 },
  2425. { 0x0b, 0x0000 },
  2426. { 0x00, 0x9200 }
  2427. };
  2428. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2429. }
  2430. static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
  2431. {
  2432. static const struct phy_reg phy_reg_init[] = {
  2433. { 0x1f, 0x0002 },
  2434. { 0x01, 0x90d0 },
  2435. { 0x1f, 0x0000 }
  2436. };
  2437. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2438. }
  2439. static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
  2440. {
  2441. struct pci_dev *pdev = tp->pci_dev;
  2442. if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
  2443. (pdev->subsystem_device != 0xe000))
  2444. return;
  2445. rtl_writephy(tp, 0x1f, 0x0001);
  2446. rtl_writephy(tp, 0x10, 0xf01b);
  2447. rtl_writephy(tp, 0x1f, 0x0000);
  2448. }
  2449. static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
  2450. {
  2451. static const struct phy_reg phy_reg_init[] = {
  2452. { 0x1f, 0x0001 },
  2453. { 0x04, 0x0000 },
  2454. { 0x03, 0x00a1 },
  2455. { 0x02, 0x0008 },
  2456. { 0x01, 0x0120 },
  2457. { 0x00, 0x1000 },
  2458. { 0x04, 0x0800 },
  2459. { 0x04, 0x9000 },
  2460. { 0x03, 0x802f },
  2461. { 0x02, 0x4f02 },
  2462. { 0x01, 0x0409 },
  2463. { 0x00, 0xf099 },
  2464. { 0x04, 0x9800 },
  2465. { 0x04, 0xa000 },
  2466. { 0x03, 0xdf01 },
  2467. { 0x02, 0xdf20 },
  2468. { 0x01, 0xff95 },
  2469. { 0x00, 0xba00 },
  2470. { 0x04, 0xa800 },
  2471. { 0x04, 0xf000 },
  2472. { 0x03, 0xdf01 },
  2473. { 0x02, 0xdf20 },
  2474. { 0x01, 0x101a },
  2475. { 0x00, 0xa0ff },
  2476. { 0x04, 0xf800 },
  2477. { 0x04, 0x0000 },
  2478. { 0x1f, 0x0000 },
  2479. { 0x1f, 0x0001 },
  2480. { 0x10, 0xf41b },
  2481. { 0x14, 0xfb54 },
  2482. { 0x18, 0xf5c7 },
  2483. { 0x1f, 0x0000 },
  2484. { 0x1f, 0x0001 },
  2485. { 0x17, 0x0cc0 },
  2486. { 0x1f, 0x0000 }
  2487. };
  2488. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2489. rtl8169scd_hw_phy_config_quirk(tp);
  2490. }
  2491. static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
  2492. {
  2493. static const struct phy_reg phy_reg_init[] = {
  2494. { 0x1f, 0x0001 },
  2495. { 0x04, 0x0000 },
  2496. { 0x03, 0x00a1 },
  2497. { 0x02, 0x0008 },
  2498. { 0x01, 0x0120 },
  2499. { 0x00, 0x1000 },
  2500. { 0x04, 0x0800 },
  2501. { 0x04, 0x9000 },
  2502. { 0x03, 0x802f },
  2503. { 0x02, 0x4f02 },
  2504. { 0x01, 0x0409 },
  2505. { 0x00, 0xf099 },
  2506. { 0x04, 0x9800 },
  2507. { 0x04, 0xa000 },
  2508. { 0x03, 0xdf01 },
  2509. { 0x02, 0xdf20 },
  2510. { 0x01, 0xff95 },
  2511. { 0x00, 0xba00 },
  2512. { 0x04, 0xa800 },
  2513. { 0x04, 0xf000 },
  2514. { 0x03, 0xdf01 },
  2515. { 0x02, 0xdf20 },
  2516. { 0x01, 0x101a },
  2517. { 0x00, 0xa0ff },
  2518. { 0x04, 0xf800 },
  2519. { 0x04, 0x0000 },
  2520. { 0x1f, 0x0000 },
  2521. { 0x1f, 0x0001 },
  2522. { 0x0b, 0x8480 },
  2523. { 0x1f, 0x0000 },
  2524. { 0x1f, 0x0001 },
  2525. { 0x18, 0x67c7 },
  2526. { 0x04, 0x2000 },
  2527. { 0x03, 0x002f },
  2528. { 0x02, 0x4360 },
  2529. { 0x01, 0x0109 },
  2530. { 0x00, 0x3022 },
  2531. { 0x04, 0x2800 },
  2532. { 0x1f, 0x0000 },
  2533. { 0x1f, 0x0001 },
  2534. { 0x17, 0x0cc0 },
  2535. { 0x1f, 0x0000 }
  2536. };
  2537. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2538. }
  2539. static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
  2540. {
  2541. static const struct phy_reg phy_reg_init[] = {
  2542. { 0x10, 0xf41b },
  2543. { 0x1f, 0x0000 }
  2544. };
  2545. rtl_writephy(tp, 0x1f, 0x0001);
  2546. rtl_patchphy(tp, 0x16, 1 << 0);
  2547. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2548. }
  2549. static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
  2550. {
  2551. static const struct phy_reg phy_reg_init[] = {
  2552. { 0x1f, 0x0001 },
  2553. { 0x10, 0xf41b },
  2554. { 0x1f, 0x0000 }
  2555. };
  2556. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2557. }
  2558. static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
  2559. {
  2560. static const struct phy_reg phy_reg_init[] = {
  2561. { 0x1f, 0x0000 },
  2562. { 0x1d, 0x0f00 },
  2563. { 0x1f, 0x0002 },
  2564. { 0x0c, 0x1ec8 },
  2565. { 0x1f, 0x0000 }
  2566. };
  2567. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2568. }
  2569. static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
  2570. {
  2571. static const struct phy_reg phy_reg_init[] = {
  2572. { 0x1f, 0x0001 },
  2573. { 0x1d, 0x3d98 },
  2574. { 0x1f, 0x0000 }
  2575. };
  2576. rtl_writephy(tp, 0x1f, 0x0000);
  2577. rtl_patchphy(tp, 0x14, 1 << 5);
  2578. rtl_patchphy(tp, 0x0d, 1 << 5);
  2579. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2580. }
  2581. static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
  2582. {
  2583. static const struct phy_reg phy_reg_init[] = {
  2584. { 0x1f, 0x0001 },
  2585. { 0x12, 0x2300 },
  2586. { 0x1f, 0x0002 },
  2587. { 0x00, 0x88d4 },
  2588. { 0x01, 0x82b1 },
  2589. { 0x03, 0x7002 },
  2590. { 0x08, 0x9e30 },
  2591. { 0x09, 0x01f0 },
  2592. { 0x0a, 0x5500 },
  2593. { 0x0c, 0x00c8 },
  2594. { 0x1f, 0x0003 },
  2595. { 0x12, 0xc096 },
  2596. { 0x16, 0x000a },
  2597. { 0x1f, 0x0000 },
  2598. { 0x1f, 0x0000 },
  2599. { 0x09, 0x2000 },
  2600. { 0x09, 0x0000 }
  2601. };
  2602. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2603. rtl_patchphy(tp, 0x14, 1 << 5);
  2604. rtl_patchphy(tp, 0x0d, 1 << 5);
  2605. rtl_writephy(tp, 0x1f, 0x0000);
  2606. }
  2607. static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
  2608. {
  2609. static const struct phy_reg phy_reg_init[] = {
  2610. { 0x1f, 0x0001 },
  2611. { 0x12, 0x2300 },
  2612. { 0x03, 0x802f },
  2613. { 0x02, 0x4f02 },
  2614. { 0x01, 0x0409 },
  2615. { 0x00, 0xf099 },
  2616. { 0x04, 0x9800 },
  2617. { 0x04, 0x9000 },
  2618. { 0x1d, 0x3d98 },
  2619. { 0x1f, 0x0002 },
  2620. { 0x0c, 0x7eb8 },
  2621. { 0x06, 0x0761 },
  2622. { 0x1f, 0x0003 },
  2623. { 0x16, 0x0f0a },
  2624. { 0x1f, 0x0000 }
  2625. };
  2626. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2627. rtl_patchphy(tp, 0x16, 1 << 0);
  2628. rtl_patchphy(tp, 0x14, 1 << 5);
  2629. rtl_patchphy(tp, 0x0d, 1 << 5);
  2630. rtl_writephy(tp, 0x1f, 0x0000);
  2631. }
  2632. static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
  2633. {
  2634. static const struct phy_reg phy_reg_init[] = {
  2635. { 0x1f, 0x0001 },
  2636. { 0x12, 0x2300 },
  2637. { 0x1d, 0x3d98 },
  2638. { 0x1f, 0x0002 },
  2639. { 0x0c, 0x7eb8 },
  2640. { 0x06, 0x5461 },
  2641. { 0x1f, 0x0003 },
  2642. { 0x16, 0x0f0a },
  2643. { 0x1f, 0x0000 }
  2644. };
  2645. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2646. rtl_patchphy(tp, 0x16, 1 << 0);
  2647. rtl_patchphy(tp, 0x14, 1 << 5);
  2648. rtl_patchphy(tp, 0x0d, 1 << 5);
  2649. rtl_writephy(tp, 0x1f, 0x0000);
  2650. }
  2651. static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
  2652. {
  2653. rtl8168c_3_hw_phy_config(tp);
  2654. }
  2655. static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
  2656. {
  2657. static const struct phy_reg phy_reg_init_0[] = {
  2658. /* Channel Estimation */
  2659. { 0x1f, 0x0001 },
  2660. { 0x06, 0x4064 },
  2661. { 0x07, 0x2863 },
  2662. { 0x08, 0x059c },
  2663. { 0x09, 0x26b4 },
  2664. { 0x0a, 0x6a19 },
  2665. { 0x0b, 0xdcc8 },
  2666. { 0x10, 0xf06d },
  2667. { 0x14, 0x7f68 },
  2668. { 0x18, 0x7fd9 },
  2669. { 0x1c, 0xf0ff },
  2670. { 0x1d, 0x3d9c },
  2671. { 0x1f, 0x0003 },
  2672. { 0x12, 0xf49f },
  2673. { 0x13, 0x070b },
  2674. { 0x1a, 0x05ad },
  2675. { 0x14, 0x94c0 },
  2676. /*
  2677. * Tx Error Issue
  2678. * Enhance line driver power
  2679. */
  2680. { 0x1f, 0x0002 },
  2681. { 0x06, 0x5561 },
  2682. { 0x1f, 0x0005 },
  2683. { 0x05, 0x8332 },
  2684. { 0x06, 0x5561 },
  2685. /*
  2686. * Can not link to 1Gbps with bad cable
  2687. * Decrease SNR threshold form 21.07dB to 19.04dB
  2688. */
  2689. { 0x1f, 0x0001 },
  2690. { 0x17, 0x0cc0 },
  2691. { 0x1f, 0x0000 },
  2692. { 0x0d, 0xf880 }
  2693. };
  2694. rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
  2695. /*
  2696. * Rx Error Issue
  2697. * Fine Tune Switching regulator parameter
  2698. */
  2699. rtl_writephy(tp, 0x1f, 0x0002);
  2700. rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
  2701. rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
  2702. if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
  2703. static const struct phy_reg phy_reg_init[] = {
  2704. { 0x1f, 0x0002 },
  2705. { 0x05, 0x669a },
  2706. { 0x1f, 0x0005 },
  2707. { 0x05, 0x8330 },
  2708. { 0x06, 0x669a },
  2709. { 0x1f, 0x0002 }
  2710. };
  2711. int val;
  2712. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2713. val = rtl_readphy(tp, 0x0d);
  2714. if ((val & 0x00ff) != 0x006c) {
  2715. static const u32 set[] = {
  2716. 0x0065, 0x0066, 0x0067, 0x0068,
  2717. 0x0069, 0x006a, 0x006b, 0x006c
  2718. };
  2719. int i;
  2720. rtl_writephy(tp, 0x1f, 0x0002);
  2721. val &= 0xff00;
  2722. for (i = 0; i < ARRAY_SIZE(set); i++)
  2723. rtl_writephy(tp, 0x0d, val | set[i]);
  2724. }
  2725. } else {
  2726. static const struct phy_reg phy_reg_init[] = {
  2727. { 0x1f, 0x0002 },
  2728. { 0x05, 0x6662 },
  2729. { 0x1f, 0x0005 },
  2730. { 0x05, 0x8330 },
  2731. { 0x06, 0x6662 }
  2732. };
  2733. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2734. }
  2735. /* RSET couple improve */
  2736. rtl_writephy(tp, 0x1f, 0x0002);
  2737. rtl_patchphy(tp, 0x0d, 0x0300);
  2738. rtl_patchphy(tp, 0x0f, 0x0010);
  2739. /* Fine tune PLL performance */
  2740. rtl_writephy(tp, 0x1f, 0x0002);
  2741. rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
  2742. rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
  2743. rtl_writephy(tp, 0x1f, 0x0005);
  2744. rtl_writephy(tp, 0x05, 0x001b);
  2745. rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
  2746. rtl_writephy(tp, 0x1f, 0x0000);
  2747. }
  2748. static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
  2749. {
  2750. static const struct phy_reg phy_reg_init_0[] = {
  2751. /* Channel Estimation */
  2752. { 0x1f, 0x0001 },
  2753. { 0x06, 0x4064 },
  2754. { 0x07, 0x2863 },
  2755. { 0x08, 0x059c },
  2756. { 0x09, 0x26b4 },
  2757. { 0x0a, 0x6a19 },
  2758. { 0x0b, 0xdcc8 },
  2759. { 0x10, 0xf06d },
  2760. { 0x14, 0x7f68 },
  2761. { 0x18, 0x7fd9 },
  2762. { 0x1c, 0xf0ff },
  2763. { 0x1d, 0x3d9c },
  2764. { 0x1f, 0x0003 },
  2765. { 0x12, 0xf49f },
  2766. { 0x13, 0x070b },
  2767. { 0x1a, 0x05ad },
  2768. { 0x14, 0x94c0 },
  2769. /*
  2770. * Tx Error Issue
  2771. * Enhance line driver power
  2772. */
  2773. { 0x1f, 0x0002 },
  2774. { 0x06, 0x5561 },
  2775. { 0x1f, 0x0005 },
  2776. { 0x05, 0x8332 },
  2777. { 0x06, 0x5561 },
  2778. /*
  2779. * Can not link to 1Gbps with bad cable
  2780. * Decrease SNR threshold form 21.07dB to 19.04dB
  2781. */
  2782. { 0x1f, 0x0001 },
  2783. { 0x17, 0x0cc0 },
  2784. { 0x1f, 0x0000 },
  2785. { 0x0d, 0xf880 }
  2786. };
  2787. rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
  2788. if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
  2789. static const struct phy_reg phy_reg_init[] = {
  2790. { 0x1f, 0x0002 },
  2791. { 0x05, 0x669a },
  2792. { 0x1f, 0x0005 },
  2793. { 0x05, 0x8330 },
  2794. { 0x06, 0x669a },
  2795. { 0x1f, 0x0002 }
  2796. };
  2797. int val;
  2798. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2799. val = rtl_readphy(tp, 0x0d);
  2800. if ((val & 0x00ff) != 0x006c) {
  2801. static const u32 set[] = {
  2802. 0x0065, 0x0066, 0x0067, 0x0068,
  2803. 0x0069, 0x006a, 0x006b, 0x006c
  2804. };
  2805. int i;
  2806. rtl_writephy(tp, 0x1f, 0x0002);
  2807. val &= 0xff00;
  2808. for (i = 0; i < ARRAY_SIZE(set); i++)
  2809. rtl_writephy(tp, 0x0d, val | set[i]);
  2810. }
  2811. } else {
  2812. static const struct phy_reg phy_reg_init[] = {
  2813. { 0x1f, 0x0002 },
  2814. { 0x05, 0x2642 },
  2815. { 0x1f, 0x0005 },
  2816. { 0x05, 0x8330 },
  2817. { 0x06, 0x2642 }
  2818. };
  2819. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2820. }
  2821. /* Fine tune PLL performance */
  2822. rtl_writephy(tp, 0x1f, 0x0002);
  2823. rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
  2824. rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
  2825. /* Switching regulator Slew rate */
  2826. rtl_writephy(tp, 0x1f, 0x0002);
  2827. rtl_patchphy(tp, 0x0f, 0x0017);
  2828. rtl_writephy(tp, 0x1f, 0x0005);
  2829. rtl_writephy(tp, 0x05, 0x001b);
  2830. rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
  2831. rtl_writephy(tp, 0x1f, 0x0000);
  2832. }
  2833. static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
  2834. {
  2835. static const struct phy_reg phy_reg_init[] = {
  2836. { 0x1f, 0x0002 },
  2837. { 0x10, 0x0008 },
  2838. { 0x0d, 0x006c },
  2839. { 0x1f, 0x0000 },
  2840. { 0x0d, 0xf880 },
  2841. { 0x1f, 0x0001 },
  2842. { 0x17, 0x0cc0 },
  2843. { 0x1f, 0x0001 },
  2844. { 0x0b, 0xa4d8 },
  2845. { 0x09, 0x281c },
  2846. { 0x07, 0x2883 },
  2847. { 0x0a, 0x6b35 },
  2848. { 0x1d, 0x3da4 },
  2849. { 0x1c, 0xeffd },
  2850. { 0x14, 0x7f52 },
  2851. { 0x18, 0x7fc6 },
  2852. { 0x08, 0x0601 },
  2853. { 0x06, 0x4063 },
  2854. { 0x10, 0xf074 },
  2855. { 0x1f, 0x0003 },
  2856. { 0x13, 0x0789 },
  2857. { 0x12, 0xf4bd },
  2858. { 0x1a, 0x04fd },
  2859. { 0x14, 0x84b0 },
  2860. { 0x1f, 0x0000 },
  2861. { 0x00, 0x9200 },
  2862. { 0x1f, 0x0005 },
  2863. { 0x01, 0x0340 },
  2864. { 0x1f, 0x0001 },
  2865. { 0x04, 0x4000 },
  2866. { 0x03, 0x1d21 },
  2867. { 0x02, 0x0c32 },
  2868. { 0x01, 0x0200 },
  2869. { 0x00, 0x5554 },
  2870. { 0x04, 0x4800 },
  2871. { 0x04, 0x4000 },
  2872. { 0x04, 0xf000 },
  2873. { 0x03, 0xdf01 },
  2874. { 0x02, 0xdf20 },
  2875. { 0x01, 0x101a },
  2876. { 0x00, 0xa0ff },
  2877. { 0x04, 0xf800 },
  2878. { 0x04, 0xf000 },
  2879. { 0x1f, 0x0000 },
  2880. { 0x1f, 0x0007 },
  2881. { 0x1e, 0x0023 },
  2882. { 0x16, 0x0000 },
  2883. { 0x1f, 0x0000 }
  2884. };
  2885. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2886. }
  2887. static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
  2888. {
  2889. static const struct phy_reg phy_reg_init[] = {
  2890. { 0x1f, 0x0001 },
  2891. { 0x17, 0x0cc0 },
  2892. { 0x1f, 0x0007 },
  2893. { 0x1e, 0x002d },
  2894. { 0x18, 0x0040 },
  2895. { 0x1f, 0x0000 }
  2896. };
  2897. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2898. rtl_patchphy(tp, 0x0d, 1 << 5);
  2899. }
  2900. static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
  2901. {
  2902. static const struct phy_reg phy_reg_init[] = {
  2903. /* Enable Delay cap */
  2904. { 0x1f, 0x0005 },
  2905. { 0x05, 0x8b80 },
  2906. { 0x06, 0xc896 },
  2907. { 0x1f, 0x0000 },
  2908. /* Channel estimation fine tune */
  2909. { 0x1f, 0x0001 },
  2910. { 0x0b, 0x6c20 },
  2911. { 0x07, 0x2872 },
  2912. { 0x1c, 0xefff },
  2913. { 0x1f, 0x0003 },
  2914. { 0x14, 0x6420 },
  2915. { 0x1f, 0x0000 },
  2916. /* Update PFM & 10M TX idle timer */
  2917. { 0x1f, 0x0007 },
  2918. { 0x1e, 0x002f },
  2919. { 0x15, 0x1919 },
  2920. { 0x1f, 0x0000 },
  2921. { 0x1f, 0x0007 },
  2922. { 0x1e, 0x00ac },
  2923. { 0x18, 0x0006 },
  2924. { 0x1f, 0x0000 }
  2925. };
  2926. rtl_apply_firmware(tp);
  2927. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2928. /* DCO enable for 10M IDLE Power */
  2929. rtl_writephy(tp, 0x1f, 0x0007);
  2930. rtl_writephy(tp, 0x1e, 0x0023);
  2931. rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
  2932. rtl_writephy(tp, 0x1f, 0x0000);
  2933. /* For impedance matching */
  2934. rtl_writephy(tp, 0x1f, 0x0002);
  2935. rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
  2936. rtl_writephy(tp, 0x1f, 0x0000);
  2937. /* PHY auto speed down */
  2938. rtl_writephy(tp, 0x1f, 0x0007);
  2939. rtl_writephy(tp, 0x1e, 0x002d);
  2940. rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
  2941. rtl_writephy(tp, 0x1f, 0x0000);
  2942. rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
  2943. rtl_writephy(tp, 0x1f, 0x0005);
  2944. rtl_writephy(tp, 0x05, 0x8b86);
  2945. rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
  2946. rtl_writephy(tp, 0x1f, 0x0000);
  2947. rtl_writephy(tp, 0x1f, 0x0005);
  2948. rtl_writephy(tp, 0x05, 0x8b85);
  2949. rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
  2950. rtl_writephy(tp, 0x1f, 0x0007);
  2951. rtl_writephy(tp, 0x1e, 0x0020);
  2952. rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
  2953. rtl_writephy(tp, 0x1f, 0x0006);
  2954. rtl_writephy(tp, 0x00, 0x5a00);
  2955. rtl_writephy(tp, 0x1f, 0x0000);
  2956. rtl_writephy(tp, 0x0d, 0x0007);
  2957. rtl_writephy(tp, 0x0e, 0x003c);
  2958. rtl_writephy(tp, 0x0d, 0x4007);
  2959. rtl_writephy(tp, 0x0e, 0x0000);
  2960. rtl_writephy(tp, 0x0d, 0x0000);
  2961. }
  2962. static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
  2963. {
  2964. const u16 w[] = {
  2965. addr[0] | (addr[1] << 8),
  2966. addr[2] | (addr[3] << 8),
  2967. addr[4] | (addr[5] << 8)
  2968. };
  2969. const struct exgmac_reg e[] = {
  2970. { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
  2971. { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
  2972. { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
  2973. { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
  2974. };
  2975. rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
  2976. }
  2977. static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
  2978. {
  2979. static const struct phy_reg phy_reg_init[] = {
  2980. /* Enable Delay cap */
  2981. { 0x1f, 0x0004 },
  2982. { 0x1f, 0x0007 },
  2983. { 0x1e, 0x00ac },
  2984. { 0x18, 0x0006 },
  2985. { 0x1f, 0x0002 },
  2986. { 0x1f, 0x0000 },
  2987. { 0x1f, 0x0000 },
  2988. /* Channel estimation fine tune */
  2989. { 0x1f, 0x0003 },
  2990. { 0x09, 0xa20f },
  2991. { 0x1f, 0x0000 },
  2992. { 0x1f, 0x0000 },
  2993. /* Green Setting */
  2994. { 0x1f, 0x0005 },
  2995. { 0x05, 0x8b5b },
  2996. { 0x06, 0x9222 },
  2997. { 0x05, 0x8b6d },
  2998. { 0x06, 0x8000 },
  2999. { 0x05, 0x8b76 },
  3000. { 0x06, 0x8000 },
  3001. { 0x1f, 0x0000 }
  3002. };
  3003. rtl_apply_firmware(tp);
  3004. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  3005. /* For 4-corner performance improve */
  3006. rtl_writephy(tp, 0x1f, 0x0005);
  3007. rtl_writephy(tp, 0x05, 0x8b80);
  3008. rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
  3009. rtl_writephy(tp, 0x1f, 0x0000);
  3010. /* PHY auto speed down */
  3011. rtl_writephy(tp, 0x1f, 0x0004);
  3012. rtl_writephy(tp, 0x1f, 0x0007);
  3013. rtl_writephy(tp, 0x1e, 0x002d);
  3014. rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
  3015. rtl_writephy(tp, 0x1f, 0x0002);
  3016. rtl_writephy(tp, 0x1f, 0x0000);
  3017. rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
  3018. /* improve 10M EEE waveform */
  3019. rtl_writephy(tp, 0x1f, 0x0005);
  3020. rtl_writephy(tp, 0x05, 0x8b86);
  3021. rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
  3022. rtl_writephy(tp, 0x1f, 0x0000);
  3023. /* Improve 2-pair detection performance */
  3024. rtl_writephy(tp, 0x1f, 0x0005);
  3025. rtl_writephy(tp, 0x05, 0x8b85);
  3026. rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
  3027. rtl_writephy(tp, 0x1f, 0x0000);
  3028. /* EEE setting */
  3029. rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
  3030. rtl_writephy(tp, 0x1f, 0x0005);
  3031. rtl_writephy(tp, 0x05, 0x8b85);
  3032. rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
  3033. rtl_writephy(tp, 0x1f, 0x0004);
  3034. rtl_writephy(tp, 0x1f, 0x0007);
  3035. rtl_writephy(tp, 0x1e, 0x0020);
  3036. rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
  3037. rtl_writephy(tp, 0x1f, 0x0002);
  3038. rtl_writephy(tp, 0x1f, 0x0000);
  3039. rtl_writephy(tp, 0x0d, 0x0007);
  3040. rtl_writephy(tp, 0x0e, 0x003c);
  3041. rtl_writephy(tp, 0x0d, 0x4007);
  3042. rtl_writephy(tp, 0x0e, 0x0000);
  3043. rtl_writephy(tp, 0x0d, 0x0000);
  3044. /* Green feature */
  3045. rtl_writephy(tp, 0x1f, 0x0003);
  3046. rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
  3047. rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
  3048. rtl_writephy(tp, 0x1f, 0x0000);
  3049. /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
  3050. rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
  3051. }
  3052. static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
  3053. {
  3054. /* For 4-corner performance improve */
  3055. rtl_writephy(tp, 0x1f, 0x0005);
  3056. rtl_writephy(tp, 0x05, 0x8b80);
  3057. rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
  3058. rtl_writephy(tp, 0x1f, 0x0000);
  3059. /* PHY auto speed down */
  3060. rtl_writephy(tp, 0x1f, 0x0007);
  3061. rtl_writephy(tp, 0x1e, 0x002d);
  3062. rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
  3063. rtl_writephy(tp, 0x1f, 0x0000);
  3064. rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
  3065. /* Improve 10M EEE waveform */
  3066. rtl_writephy(tp, 0x1f, 0x0005);
  3067. rtl_writephy(tp, 0x05, 0x8b86);
  3068. rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
  3069. rtl_writephy(tp, 0x1f, 0x0000);
  3070. }
  3071. static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
  3072. {
  3073. static const struct phy_reg phy_reg_init[] = {
  3074. /* Channel estimation fine tune */
  3075. { 0x1f, 0x0003 },
  3076. { 0x09, 0xa20f },
  3077. { 0x1f, 0x0000 },
  3078. /* Modify green table for giga & fnet */
  3079. { 0x1f, 0x0005 },
  3080. { 0x05, 0x8b55 },
  3081. { 0x06, 0x0000 },
  3082. { 0x05, 0x8b5e },
  3083. { 0x06, 0x0000 },
  3084. { 0x05, 0x8b67 },
  3085. { 0x06, 0x0000 },
  3086. { 0x05, 0x8b70 },
  3087. { 0x06, 0x0000 },
  3088. { 0x1f, 0x0000 },
  3089. { 0x1f, 0x0007 },
  3090. { 0x1e, 0x0078 },
  3091. { 0x17, 0x0000 },
  3092. { 0x19, 0x00fb },
  3093. { 0x1f, 0x0000 },
  3094. /* Modify green table for 10M */
  3095. { 0x1f, 0x0005 },
  3096. { 0x05, 0x8b79 },
  3097. { 0x06, 0xaa00 },
  3098. { 0x1f, 0x0000 },
  3099. /* Disable hiimpedance detection (RTCT) */
  3100. { 0x1f, 0x0003 },
  3101. { 0x01, 0x328a },
  3102. { 0x1f, 0x0000 }
  3103. };
  3104. rtl_apply_firmware(tp);
  3105. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  3106. rtl8168f_hw_phy_config(tp);
  3107. /* Improve 2-pair detection performance */
  3108. rtl_writephy(tp, 0x1f, 0x0005);
  3109. rtl_writephy(tp, 0x05, 0x8b85);
  3110. rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
  3111. rtl_writephy(tp, 0x1f, 0x0000);
  3112. }
  3113. static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
  3114. {
  3115. rtl_apply_firmware(tp);
  3116. rtl8168f_hw_phy_config(tp);
  3117. }
  3118. static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
  3119. {
  3120. static const struct phy_reg phy_reg_init[] = {
  3121. /* Channel estimation fine tune */
  3122. { 0x1f, 0x0003 },
  3123. { 0x09, 0xa20f },
  3124. { 0x1f, 0x0000 },
  3125. /* Modify green table for giga & fnet */
  3126. { 0x1f, 0x0005 },
  3127. { 0x05, 0x8b55 },
  3128. { 0x06, 0x0000 },
  3129. { 0x05, 0x8b5e },
  3130. { 0x06, 0x0000 },
  3131. { 0x05, 0x8b67 },
  3132. { 0x06, 0x0000 },
  3133. { 0x05, 0x8b70 },
  3134. { 0x06, 0x0000 },
  3135. { 0x1f, 0x0000 },
  3136. { 0x1f, 0x0007 },
  3137. { 0x1e, 0x0078 },
  3138. { 0x17, 0x0000 },
  3139. { 0x19, 0x00aa },
  3140. { 0x1f, 0x0000 },
  3141. /* Modify green table for 10M */
  3142. { 0x1f, 0x0005 },
  3143. { 0x05, 0x8b79 },
  3144. { 0x06, 0xaa00 },
  3145. { 0x1f, 0x0000 },
  3146. /* Disable hiimpedance detection (RTCT) */
  3147. { 0x1f, 0x0003 },
  3148. { 0x01, 0x328a },
  3149. { 0x1f, 0x0000 }
  3150. };
  3151. rtl_apply_firmware(tp);
  3152. rtl8168f_hw_phy_config(tp);
  3153. /* Improve 2-pair detection performance */
  3154. rtl_writephy(tp, 0x1f, 0x0005);
  3155. rtl_writephy(tp, 0x05, 0x8b85);
  3156. rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
  3157. rtl_writephy(tp, 0x1f, 0x0000);
  3158. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  3159. /* Modify green table for giga */
  3160. rtl_writephy(tp, 0x1f, 0x0005);
  3161. rtl_writephy(tp, 0x05, 0x8b54);
  3162. rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
  3163. rtl_writephy(tp, 0x05, 0x8b5d);
  3164. rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
  3165. rtl_writephy(tp, 0x05, 0x8a7c);
  3166. rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
  3167. rtl_writephy(tp, 0x05, 0x8a7f);
  3168. rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
  3169. rtl_writephy(tp, 0x05, 0x8a82);
  3170. rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
  3171. rtl_writephy(tp, 0x05, 0x8a85);
  3172. rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
  3173. rtl_writephy(tp, 0x05, 0x8a88);
  3174. rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
  3175. rtl_writephy(tp, 0x1f, 0x0000);
  3176. /* uc same-seed solution */
  3177. rtl_writephy(tp, 0x1f, 0x0005);
  3178. rtl_writephy(tp, 0x05, 0x8b85);
  3179. rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
  3180. rtl_writephy(tp, 0x1f, 0x0000);
  3181. /* eee setting */
  3182. rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
  3183. rtl_writephy(tp, 0x1f, 0x0005);
  3184. rtl_writephy(tp, 0x05, 0x8b85);
  3185. rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
  3186. rtl_writephy(tp, 0x1f, 0x0004);
  3187. rtl_writephy(tp, 0x1f, 0x0007);
  3188. rtl_writephy(tp, 0x1e, 0x0020);
  3189. rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
  3190. rtl_writephy(tp, 0x1f, 0x0000);
  3191. rtl_writephy(tp, 0x0d, 0x0007);
  3192. rtl_writephy(tp, 0x0e, 0x003c);
  3193. rtl_writephy(tp, 0x0d, 0x4007);
  3194. rtl_writephy(tp, 0x0e, 0x0000);
  3195. rtl_writephy(tp, 0x0d, 0x0000);
  3196. /* Green feature */
  3197. rtl_writephy(tp, 0x1f, 0x0003);
  3198. rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
  3199. rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
  3200. rtl_writephy(tp, 0x1f, 0x0000);
  3201. }
  3202. static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
  3203. {
  3204. rtl_apply_firmware(tp);
  3205. rtl_writephy(tp, 0x1f, 0x0a46);
  3206. if (rtl_readphy(tp, 0x10) & 0x0100) {
  3207. rtl_writephy(tp, 0x1f, 0x0bcc);
  3208. rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
  3209. } else {
  3210. rtl_writephy(tp, 0x1f, 0x0bcc);
  3211. rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
  3212. }
  3213. rtl_writephy(tp, 0x1f, 0x0a46);
  3214. if (rtl_readphy(tp, 0x13) & 0x0100) {
  3215. rtl_writephy(tp, 0x1f, 0x0c41);
  3216. rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
  3217. } else {
  3218. rtl_writephy(tp, 0x1f, 0x0c41);
  3219. rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
  3220. }
  3221. /* Enable PHY auto speed down */
  3222. rtl_writephy(tp, 0x1f, 0x0a44);
  3223. rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
  3224. rtl_writephy(tp, 0x1f, 0x0bcc);
  3225. rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
  3226. rtl_writephy(tp, 0x1f, 0x0a44);
  3227. rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
  3228. rtl_writephy(tp, 0x1f, 0x0a43);
  3229. rtl_writephy(tp, 0x13, 0x8084);
  3230. rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
  3231. rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
  3232. /* EEE auto-fallback function */
  3233. rtl_writephy(tp, 0x1f, 0x0a4b);
  3234. rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
  3235. /* Enable UC LPF tune function */
  3236. rtl_writephy(tp, 0x1f, 0x0a43);
  3237. rtl_writephy(tp, 0x13, 0x8012);
  3238. rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
  3239. rtl_writephy(tp, 0x1f, 0x0c42);
  3240. rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
  3241. /* Improve SWR Efficiency */
  3242. rtl_writephy(tp, 0x1f, 0x0bcd);
  3243. rtl_writephy(tp, 0x14, 0x5065);
  3244. rtl_writephy(tp, 0x14, 0xd065);
  3245. rtl_writephy(tp, 0x1f, 0x0bc8);
  3246. rtl_writephy(tp, 0x11, 0x5655);
  3247. rtl_writephy(tp, 0x1f, 0x0bcd);
  3248. rtl_writephy(tp, 0x14, 0x1065);
  3249. rtl_writephy(tp, 0x14, 0x9065);
  3250. rtl_writephy(tp, 0x14, 0x1065);
  3251. /* Check ALDPS bit, disable it if enabled */
  3252. rtl_writephy(tp, 0x1f, 0x0a43);
  3253. if (rtl_readphy(tp, 0x10) & 0x0004)
  3254. rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
  3255. rtl_writephy(tp, 0x1f, 0x0000);
  3256. }
  3257. static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
  3258. {
  3259. rtl_apply_firmware(tp);
  3260. }
  3261. static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
  3262. {
  3263. u16 dout_tapbin;
  3264. u32 data;
  3265. rtl_apply_firmware(tp);
  3266. /* CHN EST parameters adjust - giga master */
  3267. rtl_writephy(tp, 0x1f, 0x0a43);
  3268. rtl_writephy(tp, 0x13, 0x809b);
  3269. rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
  3270. rtl_writephy(tp, 0x13, 0x80a2);
  3271. rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
  3272. rtl_writephy(tp, 0x13, 0x80a4);
  3273. rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
  3274. rtl_writephy(tp, 0x13, 0x809c);
  3275. rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
  3276. rtl_writephy(tp, 0x1f, 0x0000);
  3277. /* CHN EST parameters adjust - giga slave */
  3278. rtl_writephy(tp, 0x1f, 0x0a43);
  3279. rtl_writephy(tp, 0x13, 0x80ad);
  3280. rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
  3281. rtl_writephy(tp, 0x13, 0x80b4);
  3282. rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
  3283. rtl_writephy(tp, 0x13, 0x80ac);
  3284. rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
  3285. rtl_writephy(tp, 0x1f, 0x0000);
  3286. /* CHN EST parameters adjust - fnet */
  3287. rtl_writephy(tp, 0x1f, 0x0a43);
  3288. rtl_writephy(tp, 0x13, 0x808e);
  3289. rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
  3290. rtl_writephy(tp, 0x13, 0x8090);
  3291. rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
  3292. rtl_writephy(tp, 0x13, 0x8092);
  3293. rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
  3294. rtl_writephy(tp, 0x1f, 0x0000);
  3295. /* enable R-tune & PGA-retune function */
  3296. dout_tapbin = 0;
  3297. rtl_writephy(tp, 0x1f, 0x0a46);
  3298. data = rtl_readphy(tp, 0x13);
  3299. data &= 3;
  3300. data <<= 2;
  3301. dout_tapbin |= data;
  3302. data = rtl_readphy(tp, 0x12);
  3303. data &= 0xc000;
  3304. data >>= 14;
  3305. dout_tapbin |= data;
  3306. dout_tapbin = ~(dout_tapbin^0x08);
  3307. dout_tapbin <<= 12;
  3308. dout_tapbin &= 0xf000;
  3309. rtl_writephy(tp, 0x1f, 0x0a43);
  3310. rtl_writephy(tp, 0x13, 0x827a);
  3311. rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
  3312. rtl_writephy(tp, 0x13, 0x827b);
  3313. rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
  3314. rtl_writephy(tp, 0x13, 0x827c);
  3315. rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
  3316. rtl_writephy(tp, 0x13, 0x827d);
  3317. rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
  3318. rtl_writephy(tp, 0x1f, 0x0a43);
  3319. rtl_writephy(tp, 0x13, 0x0811);
  3320. rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
  3321. rtl_writephy(tp, 0x1f, 0x0a42);
  3322. rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
  3323. rtl_writephy(tp, 0x1f, 0x0000);
  3324. /* enable GPHY 10M */
  3325. rtl_writephy(tp, 0x1f, 0x0a44);
  3326. rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
  3327. rtl_writephy(tp, 0x1f, 0x0000);
  3328. /* SAR ADC performance */
  3329. rtl_writephy(tp, 0x1f, 0x0bca);
  3330. rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
  3331. rtl_writephy(tp, 0x1f, 0x0000);
  3332. rtl_writephy(tp, 0x1f, 0x0a43);
  3333. rtl_writephy(tp, 0x13, 0x803f);
  3334. rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
  3335. rtl_writephy(tp, 0x13, 0x8047);
  3336. rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
  3337. rtl_writephy(tp, 0x13, 0x804f);
  3338. rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
  3339. rtl_writephy(tp, 0x13, 0x8057);
  3340. rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
  3341. rtl_writephy(tp, 0x13, 0x805f);
  3342. rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
  3343. rtl_writephy(tp, 0x13, 0x8067);
  3344. rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
  3345. rtl_writephy(tp, 0x13, 0x806f);
  3346. rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
  3347. rtl_writephy(tp, 0x1f, 0x0000);
  3348. /* disable phy pfm mode */
  3349. rtl_writephy(tp, 0x1f, 0x0a44);
  3350. rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
  3351. rtl_writephy(tp, 0x1f, 0x0000);
  3352. /* Check ALDPS bit, disable it if enabled */
  3353. rtl_writephy(tp, 0x1f, 0x0a43);
  3354. if (rtl_readphy(tp, 0x10) & 0x0004)
  3355. rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
  3356. rtl_writephy(tp, 0x1f, 0x0000);
  3357. }
  3358. static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
  3359. {
  3360. u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
  3361. u16 rlen;
  3362. u32 data;
  3363. rtl_apply_firmware(tp);
  3364. /* CHIN EST parameter update */
  3365. rtl_writephy(tp, 0x1f, 0x0a43);
  3366. rtl_writephy(tp, 0x13, 0x808a);
  3367. rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
  3368. rtl_writephy(tp, 0x1f, 0x0000);
  3369. /* enable R-tune & PGA-retune function */
  3370. rtl_writephy(tp, 0x1f, 0x0a43);
  3371. rtl_writephy(tp, 0x13, 0x0811);
  3372. rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
  3373. rtl_writephy(tp, 0x1f, 0x0a42);
  3374. rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
  3375. rtl_writephy(tp, 0x1f, 0x0000);
  3376. /* enable GPHY 10M */
  3377. rtl_writephy(tp, 0x1f, 0x0a44);
  3378. rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
  3379. rtl_writephy(tp, 0x1f, 0x0000);
  3380. r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
  3381. data = r8168_mac_ocp_read(tp, 0xdd02);
  3382. ioffset_p3 = ((data & 0x80)>>7);
  3383. ioffset_p3 <<= 3;
  3384. data = r8168_mac_ocp_read(tp, 0xdd00);
  3385. ioffset_p3 |= ((data & (0xe000))>>13);
  3386. ioffset_p2 = ((data & (0x1e00))>>9);
  3387. ioffset_p1 = ((data & (0x01e0))>>5);
  3388. ioffset_p0 = ((data & 0x0010)>>4);
  3389. ioffset_p0 <<= 3;
  3390. ioffset_p0 |= (data & (0x07));
  3391. data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
  3392. if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
  3393. (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
  3394. rtl_writephy(tp, 0x1f, 0x0bcf);
  3395. rtl_writephy(tp, 0x16, data);
  3396. rtl_writephy(tp, 0x1f, 0x0000);
  3397. }
  3398. /* Modify rlen (TX LPF corner frequency) level */
  3399. rtl_writephy(tp, 0x1f, 0x0bcd);
  3400. data = rtl_readphy(tp, 0x16);
  3401. data &= 0x000f;
  3402. rlen = 0;
  3403. if (data > 3)
  3404. rlen = data - 3;
  3405. data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
  3406. rtl_writephy(tp, 0x17, data);
  3407. rtl_writephy(tp, 0x1f, 0x0bcd);
  3408. rtl_writephy(tp, 0x1f, 0x0000);
  3409. /* disable phy pfm mode */
  3410. rtl_writephy(tp, 0x1f, 0x0a44);
  3411. rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
  3412. rtl_writephy(tp, 0x1f, 0x0000);
  3413. /* Check ALDPS bit, disable it if enabled */
  3414. rtl_writephy(tp, 0x1f, 0x0a43);
  3415. if (rtl_readphy(tp, 0x10) & 0x0004)
  3416. rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
  3417. rtl_writephy(tp, 0x1f, 0x0000);
  3418. }
  3419. static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
  3420. {
  3421. /* Enable PHY auto speed down */
  3422. rtl_writephy(tp, 0x1f, 0x0a44);
  3423. rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
  3424. rtl_writephy(tp, 0x1f, 0x0000);
  3425. /* patch 10M & ALDPS */
  3426. rtl_writephy(tp, 0x1f, 0x0bcc);
  3427. rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
  3428. rtl_writephy(tp, 0x1f, 0x0a44);
  3429. rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
  3430. rtl_writephy(tp, 0x1f, 0x0a43);
  3431. rtl_writephy(tp, 0x13, 0x8084);
  3432. rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
  3433. rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
  3434. rtl_writephy(tp, 0x1f, 0x0000);
  3435. /* Enable EEE auto-fallback function */
  3436. rtl_writephy(tp, 0x1f, 0x0a4b);
  3437. rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
  3438. rtl_writephy(tp, 0x1f, 0x0000);
  3439. /* Enable UC LPF tune function */
  3440. rtl_writephy(tp, 0x1f, 0x0a43);
  3441. rtl_writephy(tp, 0x13, 0x8012);
  3442. rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
  3443. rtl_writephy(tp, 0x1f, 0x0000);
  3444. /* set rg_sel_sdm_rate */
  3445. rtl_writephy(tp, 0x1f, 0x0c42);
  3446. rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
  3447. rtl_writephy(tp, 0x1f, 0x0000);
  3448. /* Check ALDPS bit, disable it if enabled */
  3449. rtl_writephy(tp, 0x1f, 0x0a43);
  3450. if (rtl_readphy(tp, 0x10) & 0x0004)
  3451. rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
  3452. rtl_writephy(tp, 0x1f, 0x0000);
  3453. }
  3454. static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
  3455. {
  3456. /* patch 10M & ALDPS */
  3457. rtl_writephy(tp, 0x1f, 0x0bcc);
  3458. rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
  3459. rtl_writephy(tp, 0x1f, 0x0a44);
  3460. rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
  3461. rtl_writephy(tp, 0x1f, 0x0a43);
  3462. rtl_writephy(tp, 0x13, 0x8084);
  3463. rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
  3464. rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
  3465. rtl_writephy(tp, 0x1f, 0x0000);
  3466. /* Enable UC LPF tune function */
  3467. rtl_writephy(tp, 0x1f, 0x0a43);
  3468. rtl_writephy(tp, 0x13, 0x8012);
  3469. rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
  3470. rtl_writephy(tp, 0x1f, 0x0000);
  3471. /* Set rg_sel_sdm_rate */
  3472. rtl_writephy(tp, 0x1f, 0x0c42);
  3473. rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
  3474. rtl_writephy(tp, 0x1f, 0x0000);
  3475. /* Channel estimation parameters */
  3476. rtl_writephy(tp, 0x1f, 0x0a43);
  3477. rtl_writephy(tp, 0x13, 0x80f3);
  3478. rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
  3479. rtl_writephy(tp, 0x13, 0x80f0);
  3480. rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
  3481. rtl_writephy(tp, 0x13, 0x80ef);
  3482. rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
  3483. rtl_writephy(tp, 0x13, 0x80f6);
  3484. rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
  3485. rtl_writephy(tp, 0x13, 0x80ec);
  3486. rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
  3487. rtl_writephy(tp, 0x13, 0x80ed);
  3488. rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
  3489. rtl_writephy(tp, 0x13, 0x80f2);
  3490. rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
  3491. rtl_writephy(tp, 0x13, 0x80f4);
  3492. rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
  3493. rtl_writephy(tp, 0x1f, 0x0a43);
  3494. rtl_writephy(tp, 0x13, 0x8110);
  3495. rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
  3496. rtl_writephy(tp, 0x13, 0x810f);
  3497. rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
  3498. rtl_writephy(tp, 0x13, 0x8111);
  3499. rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
  3500. rtl_writephy(tp, 0x13, 0x8113);
  3501. rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
  3502. rtl_writephy(tp, 0x13, 0x8115);
  3503. rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
  3504. rtl_writephy(tp, 0x13, 0x810e);
  3505. rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
  3506. rtl_writephy(tp, 0x13, 0x810c);
  3507. rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
  3508. rtl_writephy(tp, 0x13, 0x810b);
  3509. rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
  3510. rtl_writephy(tp, 0x1f, 0x0a43);
  3511. rtl_writephy(tp, 0x13, 0x80d1);
  3512. rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
  3513. rtl_writephy(tp, 0x13, 0x80cd);
  3514. rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
  3515. rtl_writephy(tp, 0x13, 0x80d3);
  3516. rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
  3517. rtl_writephy(tp, 0x13, 0x80d5);
  3518. rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
  3519. rtl_writephy(tp, 0x13, 0x80d7);
  3520. rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
  3521. /* Force PWM-mode */
  3522. rtl_writephy(tp, 0x1f, 0x0bcd);
  3523. rtl_writephy(tp, 0x14, 0x5065);
  3524. rtl_writephy(tp, 0x14, 0xd065);
  3525. rtl_writephy(tp, 0x1f, 0x0bc8);
  3526. rtl_writephy(tp, 0x12, 0x00ed);
  3527. rtl_writephy(tp, 0x1f, 0x0bcd);
  3528. rtl_writephy(tp, 0x14, 0x1065);
  3529. rtl_writephy(tp, 0x14, 0x9065);
  3530. rtl_writephy(tp, 0x14, 0x1065);
  3531. rtl_writephy(tp, 0x1f, 0x0000);
  3532. /* Check ALDPS bit, disable it if enabled */
  3533. rtl_writephy(tp, 0x1f, 0x0a43);
  3534. if (rtl_readphy(tp, 0x10) & 0x0004)
  3535. rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
  3536. rtl_writephy(tp, 0x1f, 0x0000);
  3537. }
  3538. static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
  3539. {
  3540. static const struct phy_reg phy_reg_init[] = {
  3541. { 0x1f, 0x0003 },
  3542. { 0x08, 0x441d },
  3543. { 0x01, 0x9100 },
  3544. { 0x1f, 0x0000 }
  3545. };
  3546. rtl_writephy(tp, 0x1f, 0x0000);
  3547. rtl_patchphy(tp, 0x11, 1 << 12);
  3548. rtl_patchphy(tp, 0x19, 1 << 13);
  3549. rtl_patchphy(tp, 0x10, 1 << 15);
  3550. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  3551. }
  3552. static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
  3553. {
  3554. static const struct phy_reg phy_reg_init[] = {
  3555. { 0x1f, 0x0005 },
  3556. { 0x1a, 0x0000 },
  3557. { 0x1f, 0x0000 },
  3558. { 0x1f, 0x0004 },
  3559. { 0x1c, 0x0000 },
  3560. { 0x1f, 0x0000 },
  3561. { 0x1f, 0x0001 },
  3562. { 0x15, 0x7701 },
  3563. { 0x1f, 0x0000 }
  3564. };
  3565. /* Disable ALDPS before ram code */
  3566. rtl_writephy(tp, 0x1f, 0x0000);
  3567. rtl_writephy(tp, 0x18, 0x0310);
  3568. msleep(100);
  3569. rtl_apply_firmware(tp);
  3570. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  3571. }
  3572. static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
  3573. {
  3574. /* Disable ALDPS before setting firmware */
  3575. rtl_writephy(tp, 0x1f, 0x0000);
  3576. rtl_writephy(tp, 0x18, 0x0310);
  3577. msleep(20);
  3578. rtl_apply_firmware(tp);
  3579. /* EEE setting */
  3580. rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  3581. rtl_writephy(tp, 0x1f, 0x0004);
  3582. rtl_writephy(tp, 0x10, 0x401f);
  3583. rtl_writephy(tp, 0x19, 0x7030);
  3584. rtl_writephy(tp, 0x1f, 0x0000);
  3585. }
  3586. static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
  3587. {
  3588. static const struct phy_reg phy_reg_init[] = {
  3589. { 0x1f, 0x0004 },
  3590. { 0x10, 0xc07f },
  3591. { 0x19, 0x7030 },
  3592. { 0x1f, 0x0000 }
  3593. };
  3594. /* Disable ALDPS before ram code */
  3595. rtl_writephy(tp, 0x1f, 0x0000);
  3596. rtl_writephy(tp, 0x18, 0x0310);
  3597. msleep(100);
  3598. rtl_apply_firmware(tp);
  3599. rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  3600. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  3601. rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  3602. }
  3603. static void rtl_hw_phy_config(struct net_device *dev)
  3604. {
  3605. struct rtl8169_private *tp = netdev_priv(dev);
  3606. rtl8169_print_mac_version(tp);
  3607. switch (tp->mac_version) {
  3608. case RTL_GIGA_MAC_VER_01:
  3609. break;
  3610. case RTL_GIGA_MAC_VER_02:
  3611. case RTL_GIGA_MAC_VER_03:
  3612. rtl8169s_hw_phy_config(tp);
  3613. break;
  3614. case RTL_GIGA_MAC_VER_04:
  3615. rtl8169sb_hw_phy_config(tp);
  3616. break;
  3617. case RTL_GIGA_MAC_VER_05:
  3618. rtl8169scd_hw_phy_config(tp);
  3619. break;
  3620. case RTL_GIGA_MAC_VER_06:
  3621. rtl8169sce_hw_phy_config(tp);
  3622. break;
  3623. case RTL_GIGA_MAC_VER_07:
  3624. case RTL_GIGA_MAC_VER_08:
  3625. case RTL_GIGA_MAC_VER_09:
  3626. rtl8102e_hw_phy_config(tp);
  3627. break;
  3628. case RTL_GIGA_MAC_VER_11:
  3629. rtl8168bb_hw_phy_config(tp);
  3630. break;
  3631. case RTL_GIGA_MAC_VER_12:
  3632. rtl8168bef_hw_phy_config(tp);
  3633. break;
  3634. case RTL_GIGA_MAC_VER_17:
  3635. rtl8168bef_hw_phy_config(tp);
  3636. break;
  3637. case RTL_GIGA_MAC_VER_18:
  3638. rtl8168cp_1_hw_phy_config(tp);
  3639. break;
  3640. case RTL_GIGA_MAC_VER_19:
  3641. rtl8168c_1_hw_phy_config(tp);
  3642. break;
  3643. case RTL_GIGA_MAC_VER_20:
  3644. rtl8168c_2_hw_phy_config(tp);
  3645. break;
  3646. case RTL_GIGA_MAC_VER_21:
  3647. rtl8168c_3_hw_phy_config(tp);
  3648. break;
  3649. case RTL_GIGA_MAC_VER_22:
  3650. rtl8168c_4_hw_phy_config(tp);
  3651. break;
  3652. case RTL_GIGA_MAC_VER_23:
  3653. case RTL_GIGA_MAC_VER_24:
  3654. rtl8168cp_2_hw_phy_config(tp);
  3655. break;
  3656. case RTL_GIGA_MAC_VER_25:
  3657. rtl8168d_1_hw_phy_config(tp);
  3658. break;
  3659. case RTL_GIGA_MAC_VER_26:
  3660. rtl8168d_2_hw_phy_config(tp);
  3661. break;
  3662. case RTL_GIGA_MAC_VER_27:
  3663. rtl8168d_3_hw_phy_config(tp);
  3664. break;
  3665. case RTL_GIGA_MAC_VER_28:
  3666. rtl8168d_4_hw_phy_config(tp);
  3667. break;
  3668. case RTL_GIGA_MAC_VER_29:
  3669. case RTL_GIGA_MAC_VER_30:
  3670. rtl8105e_hw_phy_config(tp);
  3671. break;
  3672. case RTL_GIGA_MAC_VER_31:
  3673. /* None. */
  3674. break;
  3675. case RTL_GIGA_MAC_VER_32:
  3676. case RTL_GIGA_MAC_VER_33:
  3677. rtl8168e_1_hw_phy_config(tp);
  3678. break;
  3679. case RTL_GIGA_MAC_VER_34:
  3680. rtl8168e_2_hw_phy_config(tp);
  3681. break;
  3682. case RTL_GIGA_MAC_VER_35:
  3683. rtl8168f_1_hw_phy_config(tp);
  3684. break;
  3685. case RTL_GIGA_MAC_VER_36:
  3686. rtl8168f_2_hw_phy_config(tp);
  3687. break;
  3688. case RTL_GIGA_MAC_VER_37:
  3689. rtl8402_hw_phy_config(tp);
  3690. break;
  3691. case RTL_GIGA_MAC_VER_38:
  3692. rtl8411_hw_phy_config(tp);
  3693. break;
  3694. case RTL_GIGA_MAC_VER_39:
  3695. rtl8106e_hw_phy_config(tp);
  3696. break;
  3697. case RTL_GIGA_MAC_VER_40:
  3698. rtl8168g_1_hw_phy_config(tp);
  3699. break;
  3700. case RTL_GIGA_MAC_VER_42:
  3701. case RTL_GIGA_MAC_VER_43:
  3702. case RTL_GIGA_MAC_VER_44:
  3703. rtl8168g_2_hw_phy_config(tp);
  3704. break;
  3705. case RTL_GIGA_MAC_VER_45:
  3706. case RTL_GIGA_MAC_VER_47:
  3707. rtl8168h_1_hw_phy_config(tp);
  3708. break;
  3709. case RTL_GIGA_MAC_VER_46:
  3710. case RTL_GIGA_MAC_VER_48:
  3711. rtl8168h_2_hw_phy_config(tp);
  3712. break;
  3713. case RTL_GIGA_MAC_VER_49:
  3714. rtl8168ep_1_hw_phy_config(tp);
  3715. break;
  3716. case RTL_GIGA_MAC_VER_50:
  3717. case RTL_GIGA_MAC_VER_51:
  3718. rtl8168ep_2_hw_phy_config(tp);
  3719. break;
  3720. case RTL_GIGA_MAC_VER_41:
  3721. default:
  3722. break;
  3723. }
  3724. }
  3725. static void rtl_phy_work(struct rtl8169_private *tp)
  3726. {
  3727. struct timer_list *timer = &tp->timer;
  3728. void __iomem *ioaddr = tp->mmio_addr;
  3729. unsigned long timeout = RTL8169_PHY_TIMEOUT;
  3730. assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
  3731. if (tp->phy_reset_pending(tp)) {
  3732. /*
  3733. * A busy loop could burn quite a few cycles on nowadays CPU.
  3734. * Let's delay the execution of the timer for a few ticks.
  3735. */
  3736. timeout = HZ/10;
  3737. goto out_mod_timer;
  3738. }
  3739. if (tp->link_ok(ioaddr))
  3740. return;
  3741. netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
  3742. tp->phy_reset_enable(tp);
  3743. out_mod_timer:
  3744. mod_timer(timer, jiffies + timeout);
  3745. }
  3746. static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
  3747. {
  3748. if (!test_and_set_bit(flag, tp->wk.flags))
  3749. schedule_work(&tp->wk.work);
  3750. }
  3751. static void rtl8169_phy_timer(unsigned long __opaque)
  3752. {
  3753. struct net_device *dev = (struct net_device *)__opaque;
  3754. struct rtl8169_private *tp = netdev_priv(dev);
  3755. rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
  3756. }
  3757. static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
  3758. void __iomem *ioaddr)
  3759. {
  3760. iounmap(ioaddr);
  3761. pci_release_regions(pdev);
  3762. pci_clear_mwi(pdev);
  3763. pci_disable_device(pdev);
  3764. free_netdev(dev);
  3765. }
  3766. DECLARE_RTL_COND(rtl_phy_reset_cond)
  3767. {
  3768. return tp->phy_reset_pending(tp);
  3769. }
  3770. static void rtl8169_phy_reset(struct net_device *dev,
  3771. struct rtl8169_private *tp)
  3772. {
  3773. tp->phy_reset_enable(tp);
  3774. rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
  3775. }
  3776. static bool rtl_tbi_enabled(struct rtl8169_private *tp)
  3777. {
  3778. void __iomem *ioaddr = tp->mmio_addr;
  3779. return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
  3780. (RTL_R8(PHYstatus) & TBI_Enable);
  3781. }
  3782. static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
  3783. {
  3784. void __iomem *ioaddr = tp->mmio_addr;
  3785. rtl_hw_phy_config(dev);
  3786. if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
  3787. dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
  3788. RTL_W8(0x82, 0x01);
  3789. }
  3790. pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
  3791. if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
  3792. pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
  3793. if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
  3794. dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
  3795. RTL_W8(0x82, 0x01);
  3796. dprintk("Set PHY Reg 0x0bh = 0x00h\n");
  3797. rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
  3798. }
  3799. rtl8169_phy_reset(dev, tp);
  3800. rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
  3801. ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
  3802. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
  3803. (tp->mii.supports_gmii ?
  3804. ADVERTISED_1000baseT_Half |
  3805. ADVERTISED_1000baseT_Full : 0));
  3806. if (rtl_tbi_enabled(tp))
  3807. netif_info(tp, link, dev, "TBI auto-negotiating\n");
  3808. }
  3809. static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
  3810. {
  3811. void __iomem *ioaddr = tp->mmio_addr;
  3812. rtl_lock_work(tp);
  3813. RTL_W8(Cfg9346, Cfg9346_Unlock);
  3814. RTL_W32(MAC4, addr[4] | addr[5] << 8);
  3815. RTL_R32(MAC4);
  3816. RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
  3817. RTL_R32(MAC0);
  3818. if (tp->mac_version == RTL_GIGA_MAC_VER_34)
  3819. rtl_rar_exgmac_set(tp, addr);
  3820. RTL_W8(Cfg9346, Cfg9346_Lock);
  3821. rtl_unlock_work(tp);
  3822. }
  3823. static int rtl_set_mac_address(struct net_device *dev, void *p)
  3824. {
  3825. struct rtl8169_private *tp = netdev_priv(dev);
  3826. struct device *d = &tp->pci_dev->dev;
  3827. struct sockaddr *addr = p;
  3828. if (!is_valid_ether_addr(addr->sa_data))
  3829. return -EADDRNOTAVAIL;
  3830. memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
  3831. pm_runtime_get_noresume(d);
  3832. if (pm_runtime_active(d))
  3833. rtl_rar_set(tp, dev->dev_addr);
  3834. pm_runtime_put_noidle(d);
  3835. return 0;
  3836. }
  3837. static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  3838. {
  3839. struct rtl8169_private *tp = netdev_priv(dev);
  3840. struct mii_ioctl_data *data = if_mii(ifr);
  3841. return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
  3842. }
  3843. static int rtl_xmii_ioctl(struct rtl8169_private *tp,
  3844. struct mii_ioctl_data *data, int cmd)
  3845. {
  3846. switch (cmd) {
  3847. case SIOCGMIIPHY:
  3848. data->phy_id = 32; /* Internal PHY */
  3849. return 0;
  3850. case SIOCGMIIREG:
  3851. data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
  3852. return 0;
  3853. case SIOCSMIIREG:
  3854. rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
  3855. return 0;
  3856. }
  3857. return -EOPNOTSUPP;
  3858. }
  3859. static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
  3860. {
  3861. return -EOPNOTSUPP;
  3862. }
  3863. static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
  3864. {
  3865. if (tp->features & RTL_FEATURE_MSI) {
  3866. pci_disable_msi(pdev);
  3867. tp->features &= ~RTL_FEATURE_MSI;
  3868. }
  3869. }
  3870. static void rtl_init_mdio_ops(struct rtl8169_private *tp)
  3871. {
  3872. struct mdio_ops *ops = &tp->mdio_ops;
  3873. switch (tp->mac_version) {
  3874. case RTL_GIGA_MAC_VER_27:
  3875. ops->write = r8168dp_1_mdio_write;
  3876. ops->read = r8168dp_1_mdio_read;
  3877. break;
  3878. case RTL_GIGA_MAC_VER_28:
  3879. case RTL_GIGA_MAC_VER_31:
  3880. ops->write = r8168dp_2_mdio_write;
  3881. ops->read = r8168dp_2_mdio_read;
  3882. break;
  3883. case RTL_GIGA_MAC_VER_40:
  3884. case RTL_GIGA_MAC_VER_41:
  3885. case RTL_GIGA_MAC_VER_42:
  3886. case RTL_GIGA_MAC_VER_43:
  3887. case RTL_GIGA_MAC_VER_44:
  3888. case RTL_GIGA_MAC_VER_45:
  3889. case RTL_GIGA_MAC_VER_46:
  3890. case RTL_GIGA_MAC_VER_47:
  3891. case RTL_GIGA_MAC_VER_48:
  3892. case RTL_GIGA_MAC_VER_49:
  3893. case RTL_GIGA_MAC_VER_50:
  3894. case RTL_GIGA_MAC_VER_51:
  3895. ops->write = r8168g_mdio_write;
  3896. ops->read = r8168g_mdio_read;
  3897. break;
  3898. default:
  3899. ops->write = r8169_mdio_write;
  3900. ops->read = r8169_mdio_read;
  3901. break;
  3902. }
  3903. }
  3904. static void rtl_speed_down(struct rtl8169_private *tp)
  3905. {
  3906. u32 adv;
  3907. int lpa;
  3908. rtl_writephy(tp, 0x1f, 0x0000);
  3909. lpa = rtl_readphy(tp, MII_LPA);
  3910. if (lpa & (LPA_10HALF | LPA_10FULL))
  3911. adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
  3912. else if (lpa & (LPA_100HALF | LPA_100FULL))
  3913. adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
  3914. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
  3915. else
  3916. adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
  3917. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
  3918. (tp->mii.supports_gmii ?
  3919. ADVERTISED_1000baseT_Half |
  3920. ADVERTISED_1000baseT_Full : 0);
  3921. rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
  3922. adv);
  3923. }
  3924. static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
  3925. {
  3926. void __iomem *ioaddr = tp->mmio_addr;
  3927. switch (tp->mac_version) {
  3928. case RTL_GIGA_MAC_VER_25:
  3929. case RTL_GIGA_MAC_VER_26:
  3930. case RTL_GIGA_MAC_VER_29:
  3931. case RTL_GIGA_MAC_VER_30:
  3932. case RTL_GIGA_MAC_VER_32:
  3933. case RTL_GIGA_MAC_VER_33:
  3934. case RTL_GIGA_MAC_VER_34:
  3935. case RTL_GIGA_MAC_VER_37:
  3936. case RTL_GIGA_MAC_VER_38:
  3937. case RTL_GIGA_MAC_VER_39:
  3938. case RTL_GIGA_MAC_VER_40:
  3939. case RTL_GIGA_MAC_VER_41:
  3940. case RTL_GIGA_MAC_VER_42:
  3941. case RTL_GIGA_MAC_VER_43:
  3942. case RTL_GIGA_MAC_VER_44:
  3943. case RTL_GIGA_MAC_VER_45:
  3944. case RTL_GIGA_MAC_VER_46:
  3945. case RTL_GIGA_MAC_VER_47:
  3946. case RTL_GIGA_MAC_VER_48:
  3947. case RTL_GIGA_MAC_VER_49:
  3948. case RTL_GIGA_MAC_VER_50:
  3949. case RTL_GIGA_MAC_VER_51:
  3950. RTL_W32(RxConfig, RTL_R32(RxConfig) |
  3951. AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
  3952. break;
  3953. default:
  3954. break;
  3955. }
  3956. }
  3957. static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
  3958. {
  3959. if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
  3960. return false;
  3961. rtl_speed_down(tp);
  3962. rtl_wol_suspend_quirk(tp);
  3963. return true;
  3964. }
  3965. static void r810x_phy_power_down(struct rtl8169_private *tp)
  3966. {
  3967. rtl_writephy(tp, 0x1f, 0x0000);
  3968. rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
  3969. }
  3970. static void r810x_phy_power_up(struct rtl8169_private *tp)
  3971. {
  3972. rtl_writephy(tp, 0x1f, 0x0000);
  3973. rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
  3974. }
  3975. static void r810x_pll_power_down(struct rtl8169_private *tp)
  3976. {
  3977. void __iomem *ioaddr = tp->mmio_addr;
  3978. if (rtl_wol_pll_power_down(tp))
  3979. return;
  3980. r810x_phy_power_down(tp);
  3981. switch (tp->mac_version) {
  3982. case RTL_GIGA_MAC_VER_07:
  3983. case RTL_GIGA_MAC_VER_08:
  3984. case RTL_GIGA_MAC_VER_09:
  3985. case RTL_GIGA_MAC_VER_10:
  3986. case RTL_GIGA_MAC_VER_13:
  3987. case RTL_GIGA_MAC_VER_16:
  3988. break;
  3989. default:
  3990. RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
  3991. break;
  3992. }
  3993. }
  3994. static void r810x_pll_power_up(struct rtl8169_private *tp)
  3995. {
  3996. void __iomem *ioaddr = tp->mmio_addr;
  3997. r810x_phy_power_up(tp);
  3998. switch (tp->mac_version) {
  3999. case RTL_GIGA_MAC_VER_07:
  4000. case RTL_GIGA_MAC_VER_08:
  4001. case RTL_GIGA_MAC_VER_09:
  4002. case RTL_GIGA_MAC_VER_10:
  4003. case RTL_GIGA_MAC_VER_13:
  4004. case RTL_GIGA_MAC_VER_16:
  4005. break;
  4006. case RTL_GIGA_MAC_VER_47:
  4007. case RTL_GIGA_MAC_VER_48:
  4008. RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
  4009. break;
  4010. default:
  4011. RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
  4012. break;
  4013. }
  4014. }
  4015. static void r8168_phy_power_up(struct rtl8169_private *tp)
  4016. {
  4017. rtl_writephy(tp, 0x1f, 0x0000);
  4018. switch (tp->mac_version) {
  4019. case RTL_GIGA_MAC_VER_11:
  4020. case RTL_GIGA_MAC_VER_12:
  4021. case RTL_GIGA_MAC_VER_17:
  4022. case RTL_GIGA_MAC_VER_18:
  4023. case RTL_GIGA_MAC_VER_19:
  4024. case RTL_GIGA_MAC_VER_20:
  4025. case RTL_GIGA_MAC_VER_21:
  4026. case RTL_GIGA_MAC_VER_22:
  4027. case RTL_GIGA_MAC_VER_23:
  4028. case RTL_GIGA_MAC_VER_24:
  4029. case RTL_GIGA_MAC_VER_25:
  4030. case RTL_GIGA_MAC_VER_26:
  4031. case RTL_GIGA_MAC_VER_27:
  4032. case RTL_GIGA_MAC_VER_28:
  4033. case RTL_GIGA_MAC_VER_31:
  4034. rtl_writephy(tp, 0x0e, 0x0000);
  4035. break;
  4036. default:
  4037. break;
  4038. }
  4039. rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
  4040. }
  4041. static void r8168_phy_power_down(struct rtl8169_private *tp)
  4042. {
  4043. rtl_writephy(tp, 0x1f, 0x0000);
  4044. switch (tp->mac_version) {
  4045. case RTL_GIGA_MAC_VER_32:
  4046. case RTL_GIGA_MAC_VER_33:
  4047. case RTL_GIGA_MAC_VER_40:
  4048. case RTL_GIGA_MAC_VER_41:
  4049. rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
  4050. break;
  4051. case RTL_GIGA_MAC_VER_11:
  4052. case RTL_GIGA_MAC_VER_12:
  4053. case RTL_GIGA_MAC_VER_17:
  4054. case RTL_GIGA_MAC_VER_18:
  4055. case RTL_GIGA_MAC_VER_19:
  4056. case RTL_GIGA_MAC_VER_20:
  4057. case RTL_GIGA_MAC_VER_21:
  4058. case RTL_GIGA_MAC_VER_22:
  4059. case RTL_GIGA_MAC_VER_23:
  4060. case RTL_GIGA_MAC_VER_24:
  4061. case RTL_GIGA_MAC_VER_25:
  4062. case RTL_GIGA_MAC_VER_26:
  4063. case RTL_GIGA_MAC_VER_27:
  4064. case RTL_GIGA_MAC_VER_28:
  4065. case RTL_GIGA_MAC_VER_31:
  4066. rtl_writephy(tp, 0x0e, 0x0200);
  4067. default:
  4068. rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
  4069. break;
  4070. }
  4071. }
  4072. static void r8168_pll_power_down(struct rtl8169_private *tp)
  4073. {
  4074. void __iomem *ioaddr = tp->mmio_addr;
  4075. if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
  4076. tp->mac_version == RTL_GIGA_MAC_VER_28 ||
  4077. tp->mac_version == RTL_GIGA_MAC_VER_31 ||
  4078. tp->mac_version == RTL_GIGA_MAC_VER_49 ||
  4079. tp->mac_version == RTL_GIGA_MAC_VER_50 ||
  4080. tp->mac_version == RTL_GIGA_MAC_VER_51) &&
  4081. r8168_check_dash(tp)) {
  4082. return;
  4083. }
  4084. if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
  4085. tp->mac_version == RTL_GIGA_MAC_VER_24) &&
  4086. (RTL_R16(CPlusCmd) & ASF)) {
  4087. return;
  4088. }
  4089. if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
  4090. tp->mac_version == RTL_GIGA_MAC_VER_33)
  4091. rtl_ephy_write(tp, 0x19, 0xff64);
  4092. if (rtl_wol_pll_power_down(tp))
  4093. return;
  4094. r8168_phy_power_down(tp);
  4095. switch (tp->mac_version) {
  4096. case RTL_GIGA_MAC_VER_25:
  4097. case RTL_GIGA_MAC_VER_26:
  4098. case RTL_GIGA_MAC_VER_27:
  4099. case RTL_GIGA_MAC_VER_28:
  4100. case RTL_GIGA_MAC_VER_31:
  4101. case RTL_GIGA_MAC_VER_32:
  4102. case RTL_GIGA_MAC_VER_33:
  4103. case RTL_GIGA_MAC_VER_44:
  4104. case RTL_GIGA_MAC_VER_45:
  4105. case RTL_GIGA_MAC_VER_46:
  4106. case RTL_GIGA_MAC_VER_50:
  4107. case RTL_GIGA_MAC_VER_51:
  4108. RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
  4109. break;
  4110. case RTL_GIGA_MAC_VER_40:
  4111. case RTL_GIGA_MAC_VER_41:
  4112. case RTL_GIGA_MAC_VER_49:
  4113. rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
  4114. 0xfc000000, ERIAR_EXGMAC);
  4115. RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
  4116. break;
  4117. }
  4118. }
  4119. static void r8168_pll_power_up(struct rtl8169_private *tp)
  4120. {
  4121. void __iomem *ioaddr = tp->mmio_addr;
  4122. switch (tp->mac_version) {
  4123. case RTL_GIGA_MAC_VER_25:
  4124. case RTL_GIGA_MAC_VER_26:
  4125. case RTL_GIGA_MAC_VER_27:
  4126. case RTL_GIGA_MAC_VER_28:
  4127. case RTL_GIGA_MAC_VER_31:
  4128. case RTL_GIGA_MAC_VER_32:
  4129. case RTL_GIGA_MAC_VER_33:
  4130. RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
  4131. break;
  4132. case RTL_GIGA_MAC_VER_44:
  4133. case RTL_GIGA_MAC_VER_45:
  4134. case RTL_GIGA_MAC_VER_46:
  4135. case RTL_GIGA_MAC_VER_50:
  4136. case RTL_GIGA_MAC_VER_51:
  4137. RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
  4138. break;
  4139. case RTL_GIGA_MAC_VER_40:
  4140. case RTL_GIGA_MAC_VER_41:
  4141. case RTL_GIGA_MAC_VER_49:
  4142. RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
  4143. rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
  4144. 0x00000000, ERIAR_EXGMAC);
  4145. break;
  4146. }
  4147. r8168_phy_power_up(tp);
  4148. }
  4149. static void rtl_generic_op(struct rtl8169_private *tp,
  4150. void (*op)(struct rtl8169_private *))
  4151. {
  4152. if (op)
  4153. op(tp);
  4154. }
  4155. static void rtl_pll_power_down(struct rtl8169_private *tp)
  4156. {
  4157. rtl_generic_op(tp, tp->pll_power_ops.down);
  4158. }
  4159. static void rtl_pll_power_up(struct rtl8169_private *tp)
  4160. {
  4161. rtl_generic_op(tp, tp->pll_power_ops.up);
  4162. }
  4163. static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
  4164. {
  4165. struct pll_power_ops *ops = &tp->pll_power_ops;
  4166. switch (tp->mac_version) {
  4167. case RTL_GIGA_MAC_VER_07:
  4168. case RTL_GIGA_MAC_VER_08:
  4169. case RTL_GIGA_MAC_VER_09:
  4170. case RTL_GIGA_MAC_VER_10:
  4171. case RTL_GIGA_MAC_VER_16:
  4172. case RTL_GIGA_MAC_VER_29:
  4173. case RTL_GIGA_MAC_VER_30:
  4174. case RTL_GIGA_MAC_VER_37:
  4175. case RTL_GIGA_MAC_VER_39:
  4176. case RTL_GIGA_MAC_VER_43:
  4177. case RTL_GIGA_MAC_VER_47:
  4178. case RTL_GIGA_MAC_VER_48:
  4179. ops->down = r810x_pll_power_down;
  4180. ops->up = r810x_pll_power_up;
  4181. break;
  4182. case RTL_GIGA_MAC_VER_11:
  4183. case RTL_GIGA_MAC_VER_12:
  4184. case RTL_GIGA_MAC_VER_17:
  4185. case RTL_GIGA_MAC_VER_18:
  4186. case RTL_GIGA_MAC_VER_19:
  4187. case RTL_GIGA_MAC_VER_20:
  4188. case RTL_GIGA_MAC_VER_21:
  4189. case RTL_GIGA_MAC_VER_22:
  4190. case RTL_GIGA_MAC_VER_23:
  4191. case RTL_GIGA_MAC_VER_24:
  4192. case RTL_GIGA_MAC_VER_25:
  4193. case RTL_GIGA_MAC_VER_26:
  4194. case RTL_GIGA_MAC_VER_27:
  4195. case RTL_GIGA_MAC_VER_28:
  4196. case RTL_GIGA_MAC_VER_31:
  4197. case RTL_GIGA_MAC_VER_32:
  4198. case RTL_GIGA_MAC_VER_33:
  4199. case RTL_GIGA_MAC_VER_34:
  4200. case RTL_GIGA_MAC_VER_35:
  4201. case RTL_GIGA_MAC_VER_36:
  4202. case RTL_GIGA_MAC_VER_38:
  4203. case RTL_GIGA_MAC_VER_40:
  4204. case RTL_GIGA_MAC_VER_41:
  4205. case RTL_GIGA_MAC_VER_42:
  4206. case RTL_GIGA_MAC_VER_44:
  4207. case RTL_GIGA_MAC_VER_45:
  4208. case RTL_GIGA_MAC_VER_46:
  4209. case RTL_GIGA_MAC_VER_49:
  4210. case RTL_GIGA_MAC_VER_50:
  4211. case RTL_GIGA_MAC_VER_51:
  4212. ops->down = r8168_pll_power_down;
  4213. ops->up = r8168_pll_power_up;
  4214. break;
  4215. default:
  4216. ops->down = NULL;
  4217. ops->up = NULL;
  4218. break;
  4219. }
  4220. }
  4221. static void rtl_init_rxcfg(struct rtl8169_private *tp)
  4222. {
  4223. void __iomem *ioaddr = tp->mmio_addr;
  4224. switch (tp->mac_version) {
  4225. case RTL_GIGA_MAC_VER_01:
  4226. case RTL_GIGA_MAC_VER_02:
  4227. case RTL_GIGA_MAC_VER_03:
  4228. case RTL_GIGA_MAC_VER_04:
  4229. case RTL_GIGA_MAC_VER_05:
  4230. case RTL_GIGA_MAC_VER_06:
  4231. case RTL_GIGA_MAC_VER_10:
  4232. case RTL_GIGA_MAC_VER_11:
  4233. case RTL_GIGA_MAC_VER_12:
  4234. case RTL_GIGA_MAC_VER_13:
  4235. case RTL_GIGA_MAC_VER_14:
  4236. case RTL_GIGA_MAC_VER_15:
  4237. case RTL_GIGA_MAC_VER_16:
  4238. case RTL_GIGA_MAC_VER_17:
  4239. RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
  4240. break;
  4241. case RTL_GIGA_MAC_VER_18:
  4242. case RTL_GIGA_MAC_VER_19:
  4243. case RTL_GIGA_MAC_VER_20:
  4244. case RTL_GIGA_MAC_VER_21:
  4245. case RTL_GIGA_MAC_VER_22:
  4246. case RTL_GIGA_MAC_VER_23:
  4247. case RTL_GIGA_MAC_VER_24:
  4248. case RTL_GIGA_MAC_VER_34:
  4249. case RTL_GIGA_MAC_VER_35:
  4250. RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
  4251. break;
  4252. case RTL_GIGA_MAC_VER_40:
  4253. case RTL_GIGA_MAC_VER_41:
  4254. case RTL_GIGA_MAC_VER_42:
  4255. case RTL_GIGA_MAC_VER_43:
  4256. case RTL_GIGA_MAC_VER_44:
  4257. case RTL_GIGA_MAC_VER_45:
  4258. case RTL_GIGA_MAC_VER_46:
  4259. case RTL_GIGA_MAC_VER_47:
  4260. case RTL_GIGA_MAC_VER_48:
  4261. case RTL_GIGA_MAC_VER_49:
  4262. case RTL_GIGA_MAC_VER_50:
  4263. case RTL_GIGA_MAC_VER_51:
  4264. RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
  4265. break;
  4266. default:
  4267. RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
  4268. break;
  4269. }
  4270. }
  4271. static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
  4272. {
  4273. tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
  4274. }
  4275. static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
  4276. {
  4277. void __iomem *ioaddr = tp->mmio_addr;
  4278. RTL_W8(Cfg9346, Cfg9346_Unlock);
  4279. rtl_generic_op(tp, tp->jumbo_ops.enable);
  4280. RTL_W8(Cfg9346, Cfg9346_Lock);
  4281. }
  4282. static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
  4283. {
  4284. void __iomem *ioaddr = tp->mmio_addr;
  4285. RTL_W8(Cfg9346, Cfg9346_Unlock);
  4286. rtl_generic_op(tp, tp->jumbo_ops.disable);
  4287. RTL_W8(Cfg9346, Cfg9346_Lock);
  4288. }
  4289. static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
  4290. {
  4291. void __iomem *ioaddr = tp->mmio_addr;
  4292. RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
  4293. RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
  4294. rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
  4295. }
  4296. static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
  4297. {
  4298. void __iomem *ioaddr = tp->mmio_addr;
  4299. RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
  4300. RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
  4301. rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4302. }
  4303. static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
  4304. {
  4305. void __iomem *ioaddr = tp->mmio_addr;
  4306. RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
  4307. }
  4308. static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
  4309. {
  4310. void __iomem *ioaddr = tp->mmio_addr;
  4311. RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
  4312. }
  4313. static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
  4314. {
  4315. void __iomem *ioaddr = tp->mmio_addr;
  4316. RTL_W8(MaxTxPacketSize, 0x3f);
  4317. RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
  4318. RTL_W8(Config4, RTL_R8(Config4) | 0x01);
  4319. rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
  4320. }
  4321. static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
  4322. {
  4323. void __iomem *ioaddr = tp->mmio_addr;
  4324. RTL_W8(MaxTxPacketSize, 0x0c);
  4325. RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
  4326. RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
  4327. rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4328. }
  4329. static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
  4330. {
  4331. rtl_tx_performance_tweak(tp->pci_dev,
  4332. PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
  4333. }
  4334. static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
  4335. {
  4336. rtl_tx_performance_tweak(tp->pci_dev,
  4337. (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
  4338. }
  4339. static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
  4340. {
  4341. void __iomem *ioaddr = tp->mmio_addr;
  4342. r8168b_0_hw_jumbo_enable(tp);
  4343. RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
  4344. }
  4345. static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
  4346. {
  4347. void __iomem *ioaddr = tp->mmio_addr;
  4348. r8168b_0_hw_jumbo_disable(tp);
  4349. RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
  4350. }
  4351. static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
  4352. {
  4353. struct jumbo_ops *ops = &tp->jumbo_ops;
  4354. switch (tp->mac_version) {
  4355. case RTL_GIGA_MAC_VER_11:
  4356. ops->disable = r8168b_0_hw_jumbo_disable;
  4357. ops->enable = r8168b_0_hw_jumbo_enable;
  4358. break;
  4359. case RTL_GIGA_MAC_VER_12:
  4360. case RTL_GIGA_MAC_VER_17:
  4361. ops->disable = r8168b_1_hw_jumbo_disable;
  4362. ops->enable = r8168b_1_hw_jumbo_enable;
  4363. break;
  4364. case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
  4365. case RTL_GIGA_MAC_VER_19:
  4366. case RTL_GIGA_MAC_VER_20:
  4367. case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
  4368. case RTL_GIGA_MAC_VER_22:
  4369. case RTL_GIGA_MAC_VER_23:
  4370. case RTL_GIGA_MAC_VER_24:
  4371. case RTL_GIGA_MAC_VER_25:
  4372. case RTL_GIGA_MAC_VER_26:
  4373. ops->disable = r8168c_hw_jumbo_disable;
  4374. ops->enable = r8168c_hw_jumbo_enable;
  4375. break;
  4376. case RTL_GIGA_MAC_VER_27:
  4377. case RTL_GIGA_MAC_VER_28:
  4378. ops->disable = r8168dp_hw_jumbo_disable;
  4379. ops->enable = r8168dp_hw_jumbo_enable;
  4380. break;
  4381. case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
  4382. case RTL_GIGA_MAC_VER_32:
  4383. case RTL_GIGA_MAC_VER_33:
  4384. case RTL_GIGA_MAC_VER_34:
  4385. ops->disable = r8168e_hw_jumbo_disable;
  4386. ops->enable = r8168e_hw_jumbo_enable;
  4387. break;
  4388. /*
  4389. * No action needed for jumbo frames with 8169.
  4390. * No jumbo for 810x at all.
  4391. */
  4392. case RTL_GIGA_MAC_VER_40:
  4393. case RTL_GIGA_MAC_VER_41:
  4394. case RTL_GIGA_MAC_VER_42:
  4395. case RTL_GIGA_MAC_VER_43:
  4396. case RTL_GIGA_MAC_VER_44:
  4397. case RTL_GIGA_MAC_VER_45:
  4398. case RTL_GIGA_MAC_VER_46:
  4399. case RTL_GIGA_MAC_VER_47:
  4400. case RTL_GIGA_MAC_VER_48:
  4401. case RTL_GIGA_MAC_VER_49:
  4402. case RTL_GIGA_MAC_VER_50:
  4403. case RTL_GIGA_MAC_VER_51:
  4404. default:
  4405. ops->disable = NULL;
  4406. ops->enable = NULL;
  4407. break;
  4408. }
  4409. }
  4410. DECLARE_RTL_COND(rtl_chipcmd_cond)
  4411. {
  4412. void __iomem *ioaddr = tp->mmio_addr;
  4413. return RTL_R8(ChipCmd) & CmdReset;
  4414. }
  4415. static void rtl_hw_reset(struct rtl8169_private *tp)
  4416. {
  4417. void __iomem *ioaddr = tp->mmio_addr;
  4418. RTL_W8(ChipCmd, CmdReset);
  4419. rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
  4420. }
  4421. static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
  4422. {
  4423. struct rtl_fw *rtl_fw;
  4424. const char *name;
  4425. int rc = -ENOMEM;
  4426. name = rtl_lookup_firmware_name(tp);
  4427. if (!name)
  4428. goto out_no_firmware;
  4429. rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
  4430. if (!rtl_fw)
  4431. goto err_warn;
  4432. rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
  4433. if (rc < 0)
  4434. goto err_free;
  4435. rc = rtl_check_firmware(tp, rtl_fw);
  4436. if (rc < 0)
  4437. goto err_release_firmware;
  4438. tp->rtl_fw = rtl_fw;
  4439. out:
  4440. return;
  4441. err_release_firmware:
  4442. release_firmware(rtl_fw->fw);
  4443. err_free:
  4444. kfree(rtl_fw);
  4445. err_warn:
  4446. netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
  4447. name, rc);
  4448. out_no_firmware:
  4449. tp->rtl_fw = NULL;
  4450. goto out;
  4451. }
  4452. static void rtl_request_firmware(struct rtl8169_private *tp)
  4453. {
  4454. if (IS_ERR(tp->rtl_fw))
  4455. rtl_request_uncached_firmware(tp);
  4456. }
  4457. static void rtl_rx_close(struct rtl8169_private *tp)
  4458. {
  4459. void __iomem *ioaddr = tp->mmio_addr;
  4460. RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
  4461. }
  4462. DECLARE_RTL_COND(rtl_npq_cond)
  4463. {
  4464. void __iomem *ioaddr = tp->mmio_addr;
  4465. return RTL_R8(TxPoll) & NPQ;
  4466. }
  4467. DECLARE_RTL_COND(rtl_txcfg_empty_cond)
  4468. {
  4469. void __iomem *ioaddr = tp->mmio_addr;
  4470. return RTL_R32(TxConfig) & TXCFG_EMPTY;
  4471. }
  4472. static void rtl8169_hw_reset(struct rtl8169_private *tp)
  4473. {
  4474. void __iomem *ioaddr = tp->mmio_addr;
  4475. /* Disable interrupts */
  4476. rtl8169_irq_mask_and_ack(tp);
  4477. rtl_rx_close(tp);
  4478. if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
  4479. tp->mac_version == RTL_GIGA_MAC_VER_28 ||
  4480. tp->mac_version == RTL_GIGA_MAC_VER_31) {
  4481. rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
  4482. } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
  4483. tp->mac_version == RTL_GIGA_MAC_VER_35 ||
  4484. tp->mac_version == RTL_GIGA_MAC_VER_36 ||
  4485. tp->mac_version == RTL_GIGA_MAC_VER_37 ||
  4486. tp->mac_version == RTL_GIGA_MAC_VER_38 ||
  4487. tp->mac_version == RTL_GIGA_MAC_VER_40 ||
  4488. tp->mac_version == RTL_GIGA_MAC_VER_41 ||
  4489. tp->mac_version == RTL_GIGA_MAC_VER_42 ||
  4490. tp->mac_version == RTL_GIGA_MAC_VER_43 ||
  4491. tp->mac_version == RTL_GIGA_MAC_VER_44 ||
  4492. tp->mac_version == RTL_GIGA_MAC_VER_45 ||
  4493. tp->mac_version == RTL_GIGA_MAC_VER_46 ||
  4494. tp->mac_version == RTL_GIGA_MAC_VER_47 ||
  4495. tp->mac_version == RTL_GIGA_MAC_VER_48 ||
  4496. tp->mac_version == RTL_GIGA_MAC_VER_49 ||
  4497. tp->mac_version == RTL_GIGA_MAC_VER_50 ||
  4498. tp->mac_version == RTL_GIGA_MAC_VER_51) {
  4499. RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
  4500. rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
  4501. } else {
  4502. RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
  4503. udelay(100);
  4504. }
  4505. rtl_hw_reset(tp);
  4506. }
  4507. static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
  4508. {
  4509. void __iomem *ioaddr = tp->mmio_addr;
  4510. /* Set DMA burst size and Interframe Gap Time */
  4511. RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
  4512. (InterFrameGap << TxInterFrameGapShift));
  4513. }
  4514. static void rtl_hw_start(struct net_device *dev)
  4515. {
  4516. struct rtl8169_private *tp = netdev_priv(dev);
  4517. tp->hw_start(dev);
  4518. rtl_irq_enable_all(tp);
  4519. }
  4520. static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
  4521. void __iomem *ioaddr)
  4522. {
  4523. /*
  4524. * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
  4525. * register to be written before TxDescAddrLow to work.
  4526. * Switching from MMIO to I/O access fixes the issue as well.
  4527. */
  4528. RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
  4529. RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
  4530. RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
  4531. RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
  4532. }
  4533. static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
  4534. {
  4535. u16 cmd;
  4536. cmd = RTL_R16(CPlusCmd);
  4537. RTL_W16(CPlusCmd, cmd);
  4538. return cmd;
  4539. }
  4540. static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
  4541. {
  4542. /* Low hurts. Let's disable the filtering. */
  4543. RTL_W16(RxMaxSize, rx_buf_sz + 1);
  4544. }
  4545. static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
  4546. {
  4547. static const struct rtl_cfg2_info {
  4548. u32 mac_version;
  4549. u32 clk;
  4550. u32 val;
  4551. } cfg2_info [] = {
  4552. { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
  4553. { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
  4554. { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
  4555. { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
  4556. };
  4557. const struct rtl_cfg2_info *p = cfg2_info;
  4558. unsigned int i;
  4559. u32 clk;
  4560. clk = RTL_R8(Config2) & PCI_Clock_66MHz;
  4561. for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
  4562. if ((p->mac_version == mac_version) && (p->clk == clk)) {
  4563. RTL_W32(0x7c, p->val);
  4564. break;
  4565. }
  4566. }
  4567. }
  4568. static void rtl_set_rx_mode(struct net_device *dev)
  4569. {
  4570. struct rtl8169_private *tp = netdev_priv(dev);
  4571. void __iomem *ioaddr = tp->mmio_addr;
  4572. u32 mc_filter[2]; /* Multicast hash filter */
  4573. int rx_mode;
  4574. u32 tmp = 0;
  4575. if (dev->flags & IFF_PROMISC) {
  4576. /* Unconditionally log net taps. */
  4577. netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
  4578. rx_mode =
  4579. AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
  4580. AcceptAllPhys;
  4581. mc_filter[1] = mc_filter[0] = 0xffffffff;
  4582. } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
  4583. (dev->flags & IFF_ALLMULTI)) {
  4584. /* Too many to filter perfectly -- accept all multicasts. */
  4585. rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
  4586. mc_filter[1] = mc_filter[0] = 0xffffffff;
  4587. } else {
  4588. struct netdev_hw_addr *ha;
  4589. rx_mode = AcceptBroadcast | AcceptMyPhys;
  4590. mc_filter[1] = mc_filter[0] = 0;
  4591. netdev_for_each_mc_addr(ha, dev) {
  4592. int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
  4593. mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  4594. rx_mode |= AcceptMulticast;
  4595. }
  4596. }
  4597. if (dev->features & NETIF_F_RXALL)
  4598. rx_mode |= (AcceptErr | AcceptRunt);
  4599. tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
  4600. if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
  4601. u32 data = mc_filter[0];
  4602. mc_filter[0] = swab32(mc_filter[1]);
  4603. mc_filter[1] = swab32(data);
  4604. }
  4605. if (tp->mac_version == RTL_GIGA_MAC_VER_35)
  4606. mc_filter[1] = mc_filter[0] = 0xffffffff;
  4607. RTL_W32(MAR0 + 4, mc_filter[1]);
  4608. RTL_W32(MAR0 + 0, mc_filter[0]);
  4609. RTL_W32(RxConfig, tmp);
  4610. }
  4611. static void rtl_hw_start_8169(struct net_device *dev)
  4612. {
  4613. struct rtl8169_private *tp = netdev_priv(dev);
  4614. void __iomem *ioaddr = tp->mmio_addr;
  4615. struct pci_dev *pdev = tp->pci_dev;
  4616. if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
  4617. RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
  4618. pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
  4619. }
  4620. RTL_W8(Cfg9346, Cfg9346_Unlock);
  4621. if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
  4622. tp->mac_version == RTL_GIGA_MAC_VER_02 ||
  4623. tp->mac_version == RTL_GIGA_MAC_VER_03 ||
  4624. tp->mac_version == RTL_GIGA_MAC_VER_04)
  4625. RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
  4626. rtl_init_rxcfg(tp);
  4627. RTL_W8(EarlyTxThres, NoEarlyTx);
  4628. rtl_set_rx_max_size(ioaddr, rx_buf_sz);
  4629. if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
  4630. tp->mac_version == RTL_GIGA_MAC_VER_02 ||
  4631. tp->mac_version == RTL_GIGA_MAC_VER_03 ||
  4632. tp->mac_version == RTL_GIGA_MAC_VER_04)
  4633. rtl_set_rx_tx_config_registers(tp);
  4634. tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
  4635. if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
  4636. tp->mac_version == RTL_GIGA_MAC_VER_03) {
  4637. dprintk("Set MAC Reg C+CR Offset 0xe0. "
  4638. "Bit-3 and bit-14 MUST be 1\n");
  4639. tp->cp_cmd |= (1 << 14);
  4640. }
  4641. RTL_W16(CPlusCmd, tp->cp_cmd);
  4642. rtl8169_set_magic_reg(ioaddr, tp->mac_version);
  4643. /*
  4644. * Undocumented corner. Supposedly:
  4645. * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
  4646. */
  4647. RTL_W16(IntrMitigate, 0x0000);
  4648. rtl_set_rx_tx_desc_registers(tp, ioaddr);
  4649. if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
  4650. tp->mac_version != RTL_GIGA_MAC_VER_02 &&
  4651. tp->mac_version != RTL_GIGA_MAC_VER_03 &&
  4652. tp->mac_version != RTL_GIGA_MAC_VER_04) {
  4653. RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
  4654. rtl_set_rx_tx_config_registers(tp);
  4655. }
  4656. RTL_W8(Cfg9346, Cfg9346_Lock);
  4657. /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
  4658. RTL_R8(IntrMask);
  4659. RTL_W32(RxMissed, 0);
  4660. rtl_set_rx_mode(dev);
  4661. /* no early-rx interrupts */
  4662. RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
  4663. }
  4664. static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
  4665. {
  4666. if (tp->csi_ops.write)
  4667. tp->csi_ops.write(tp, addr, value);
  4668. }
  4669. static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
  4670. {
  4671. return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
  4672. }
  4673. static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
  4674. {
  4675. u32 csi;
  4676. csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
  4677. rtl_csi_write(tp, 0x070c, csi | bits);
  4678. }
  4679. static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
  4680. {
  4681. rtl_csi_access_enable(tp, 0x17000000);
  4682. }
  4683. static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
  4684. {
  4685. rtl_csi_access_enable(tp, 0x27000000);
  4686. }
  4687. DECLARE_RTL_COND(rtl_csiar_cond)
  4688. {
  4689. void __iomem *ioaddr = tp->mmio_addr;
  4690. return RTL_R32(CSIAR) & CSIAR_FLAG;
  4691. }
  4692. static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
  4693. {
  4694. void __iomem *ioaddr = tp->mmio_addr;
  4695. RTL_W32(CSIDR, value);
  4696. RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
  4697. CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
  4698. rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
  4699. }
  4700. static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
  4701. {
  4702. void __iomem *ioaddr = tp->mmio_addr;
  4703. RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
  4704. CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
  4705. return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
  4706. RTL_R32(CSIDR) : ~0;
  4707. }
  4708. static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
  4709. {
  4710. void __iomem *ioaddr = tp->mmio_addr;
  4711. RTL_W32(CSIDR, value);
  4712. RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
  4713. CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
  4714. CSIAR_FUNC_NIC);
  4715. rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
  4716. }
  4717. static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
  4718. {
  4719. void __iomem *ioaddr = tp->mmio_addr;
  4720. RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
  4721. CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
  4722. return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
  4723. RTL_R32(CSIDR) : ~0;
  4724. }
  4725. static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
  4726. {
  4727. void __iomem *ioaddr = tp->mmio_addr;
  4728. RTL_W32(CSIDR, value);
  4729. RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
  4730. CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
  4731. CSIAR_FUNC_NIC2);
  4732. rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
  4733. }
  4734. static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
  4735. {
  4736. void __iomem *ioaddr = tp->mmio_addr;
  4737. RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
  4738. CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
  4739. return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
  4740. RTL_R32(CSIDR) : ~0;
  4741. }
  4742. static void rtl_init_csi_ops(struct rtl8169_private *tp)
  4743. {
  4744. struct csi_ops *ops = &tp->csi_ops;
  4745. switch (tp->mac_version) {
  4746. case RTL_GIGA_MAC_VER_01:
  4747. case RTL_GIGA_MAC_VER_02:
  4748. case RTL_GIGA_MAC_VER_03:
  4749. case RTL_GIGA_MAC_VER_04:
  4750. case RTL_GIGA_MAC_VER_05:
  4751. case RTL_GIGA_MAC_VER_06:
  4752. case RTL_GIGA_MAC_VER_10:
  4753. case RTL_GIGA_MAC_VER_11:
  4754. case RTL_GIGA_MAC_VER_12:
  4755. case RTL_GIGA_MAC_VER_13:
  4756. case RTL_GIGA_MAC_VER_14:
  4757. case RTL_GIGA_MAC_VER_15:
  4758. case RTL_GIGA_MAC_VER_16:
  4759. case RTL_GIGA_MAC_VER_17:
  4760. ops->write = NULL;
  4761. ops->read = NULL;
  4762. break;
  4763. case RTL_GIGA_MAC_VER_37:
  4764. case RTL_GIGA_MAC_VER_38:
  4765. ops->write = r8402_csi_write;
  4766. ops->read = r8402_csi_read;
  4767. break;
  4768. case RTL_GIGA_MAC_VER_44:
  4769. ops->write = r8411_csi_write;
  4770. ops->read = r8411_csi_read;
  4771. break;
  4772. default:
  4773. ops->write = r8169_csi_write;
  4774. ops->read = r8169_csi_read;
  4775. break;
  4776. }
  4777. }
  4778. struct ephy_info {
  4779. unsigned int offset;
  4780. u16 mask;
  4781. u16 bits;
  4782. };
  4783. static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
  4784. int len)
  4785. {
  4786. u16 w;
  4787. while (len-- > 0) {
  4788. w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
  4789. rtl_ephy_write(tp, e->offset, w);
  4790. e++;
  4791. }
  4792. }
  4793. static void rtl_disable_clock_request(struct pci_dev *pdev)
  4794. {
  4795. pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
  4796. PCI_EXP_LNKCTL_CLKREQ_EN);
  4797. }
  4798. static void rtl_enable_clock_request(struct pci_dev *pdev)
  4799. {
  4800. pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
  4801. PCI_EXP_LNKCTL_CLKREQ_EN);
  4802. }
  4803. static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
  4804. {
  4805. void __iomem *ioaddr = tp->mmio_addr;
  4806. u8 data;
  4807. data = RTL_R8(Config3);
  4808. if (enable)
  4809. data |= Rdy_to_L23;
  4810. else
  4811. data &= ~Rdy_to_L23;
  4812. RTL_W8(Config3, data);
  4813. }
  4814. #define R8168_CPCMD_QUIRK_MASK (\
  4815. EnableBist | \
  4816. Mac_dbgo_oe | \
  4817. Force_half_dup | \
  4818. Force_rxflow_en | \
  4819. Force_txflow_en | \
  4820. Cxpl_dbg_sel | \
  4821. ASF | \
  4822. PktCntrDisable | \
  4823. Mac_dbgo_sel)
  4824. static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
  4825. {
  4826. void __iomem *ioaddr = tp->mmio_addr;
  4827. struct pci_dev *pdev = tp->pci_dev;
  4828. RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
  4829. RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
  4830. if (tp->dev->mtu <= ETH_DATA_LEN) {
  4831. rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
  4832. PCI_EXP_DEVCTL_NOSNOOP_EN);
  4833. }
  4834. }
  4835. static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
  4836. {
  4837. void __iomem *ioaddr = tp->mmio_addr;
  4838. rtl_hw_start_8168bb(tp);
  4839. RTL_W8(MaxTxPacketSize, TxPacketMax);
  4840. RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
  4841. }
  4842. static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
  4843. {
  4844. void __iomem *ioaddr = tp->mmio_addr;
  4845. struct pci_dev *pdev = tp->pci_dev;
  4846. RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
  4847. RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
  4848. if (tp->dev->mtu <= ETH_DATA_LEN)
  4849. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4850. rtl_disable_clock_request(pdev);
  4851. RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
  4852. }
  4853. static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
  4854. {
  4855. static const struct ephy_info e_info_8168cp[] = {
  4856. { 0x01, 0, 0x0001 },
  4857. { 0x02, 0x0800, 0x1000 },
  4858. { 0x03, 0, 0x0042 },
  4859. { 0x06, 0x0080, 0x0000 },
  4860. { 0x07, 0, 0x2000 }
  4861. };
  4862. rtl_csi_access_enable_2(tp);
  4863. rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
  4864. __rtl_hw_start_8168cp(tp);
  4865. }
  4866. static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
  4867. {
  4868. void __iomem *ioaddr = tp->mmio_addr;
  4869. struct pci_dev *pdev = tp->pci_dev;
  4870. rtl_csi_access_enable_2(tp);
  4871. RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
  4872. if (tp->dev->mtu <= ETH_DATA_LEN)
  4873. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4874. RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
  4875. }
  4876. static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
  4877. {
  4878. void __iomem *ioaddr = tp->mmio_addr;
  4879. struct pci_dev *pdev = tp->pci_dev;
  4880. rtl_csi_access_enable_2(tp);
  4881. RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
  4882. /* Magic. */
  4883. RTL_W8(DBG_REG, 0x20);
  4884. RTL_W8(MaxTxPacketSize, TxPacketMax);
  4885. if (tp->dev->mtu <= ETH_DATA_LEN)
  4886. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4887. RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
  4888. }
  4889. static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
  4890. {
  4891. void __iomem *ioaddr = tp->mmio_addr;
  4892. static const struct ephy_info e_info_8168c_1[] = {
  4893. { 0x02, 0x0800, 0x1000 },
  4894. { 0x03, 0, 0x0002 },
  4895. { 0x06, 0x0080, 0x0000 }
  4896. };
  4897. rtl_csi_access_enable_2(tp);
  4898. RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
  4899. rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
  4900. __rtl_hw_start_8168cp(tp);
  4901. }
  4902. static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
  4903. {
  4904. static const struct ephy_info e_info_8168c_2[] = {
  4905. { 0x01, 0, 0x0001 },
  4906. { 0x03, 0x0400, 0x0220 }
  4907. };
  4908. rtl_csi_access_enable_2(tp);
  4909. rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
  4910. __rtl_hw_start_8168cp(tp);
  4911. }
  4912. static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
  4913. {
  4914. rtl_hw_start_8168c_2(tp);
  4915. }
  4916. static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
  4917. {
  4918. rtl_csi_access_enable_2(tp);
  4919. __rtl_hw_start_8168cp(tp);
  4920. }
  4921. static void rtl_hw_start_8168d(struct rtl8169_private *tp)
  4922. {
  4923. void __iomem *ioaddr = tp->mmio_addr;
  4924. struct pci_dev *pdev = tp->pci_dev;
  4925. rtl_csi_access_enable_2(tp);
  4926. rtl_disable_clock_request(pdev);
  4927. RTL_W8(MaxTxPacketSize, TxPacketMax);
  4928. if (tp->dev->mtu <= ETH_DATA_LEN)
  4929. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4930. RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
  4931. }
  4932. static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
  4933. {
  4934. void __iomem *ioaddr = tp->mmio_addr;
  4935. struct pci_dev *pdev = tp->pci_dev;
  4936. rtl_csi_access_enable_1(tp);
  4937. if (tp->dev->mtu <= ETH_DATA_LEN)
  4938. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4939. RTL_W8(MaxTxPacketSize, TxPacketMax);
  4940. rtl_disable_clock_request(pdev);
  4941. }
  4942. static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
  4943. {
  4944. void __iomem *ioaddr = tp->mmio_addr;
  4945. struct pci_dev *pdev = tp->pci_dev;
  4946. static const struct ephy_info e_info_8168d_4[] = {
  4947. { 0x0b, 0x0000, 0x0048 },
  4948. { 0x19, 0x0020, 0x0050 },
  4949. { 0x0c, 0x0100, 0x0020 }
  4950. };
  4951. rtl_csi_access_enable_1(tp);
  4952. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4953. RTL_W8(MaxTxPacketSize, TxPacketMax);
  4954. rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
  4955. rtl_enable_clock_request(pdev);
  4956. }
  4957. static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
  4958. {
  4959. void __iomem *ioaddr = tp->mmio_addr;
  4960. struct pci_dev *pdev = tp->pci_dev;
  4961. static const struct ephy_info e_info_8168e_1[] = {
  4962. { 0x00, 0x0200, 0x0100 },
  4963. { 0x00, 0x0000, 0x0004 },
  4964. { 0x06, 0x0002, 0x0001 },
  4965. { 0x06, 0x0000, 0x0030 },
  4966. { 0x07, 0x0000, 0x2000 },
  4967. { 0x00, 0x0000, 0x0020 },
  4968. { 0x03, 0x5800, 0x2000 },
  4969. { 0x03, 0x0000, 0x0001 },
  4970. { 0x01, 0x0800, 0x1000 },
  4971. { 0x07, 0x0000, 0x4000 },
  4972. { 0x1e, 0x0000, 0x2000 },
  4973. { 0x19, 0xffff, 0xfe6c },
  4974. { 0x0a, 0x0000, 0x0040 }
  4975. };
  4976. rtl_csi_access_enable_2(tp);
  4977. rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
  4978. if (tp->dev->mtu <= ETH_DATA_LEN)
  4979. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4980. RTL_W8(MaxTxPacketSize, TxPacketMax);
  4981. rtl_disable_clock_request(pdev);
  4982. /* Reset tx FIFO pointer */
  4983. RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
  4984. RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
  4985. RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
  4986. }
  4987. static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
  4988. {
  4989. void __iomem *ioaddr = tp->mmio_addr;
  4990. struct pci_dev *pdev = tp->pci_dev;
  4991. static const struct ephy_info e_info_8168e_2[] = {
  4992. { 0x09, 0x0000, 0x0080 },
  4993. { 0x19, 0x0000, 0x0224 }
  4994. };
  4995. rtl_csi_access_enable_1(tp);
  4996. rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
  4997. if (tp->dev->mtu <= ETH_DATA_LEN)
  4998. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4999. rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  5000. rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  5001. rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
  5002. rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
  5003. rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
  5004. rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
  5005. rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
  5006. rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
  5007. RTL_W8(MaxTxPacketSize, EarlySize);
  5008. rtl_disable_clock_request(pdev);
  5009. RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
  5010. RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
  5011. /* Adjust EEE LED frequency */
  5012. RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
  5013. RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
  5014. RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
  5015. RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
  5016. }
  5017. static void rtl_hw_start_8168f(struct rtl8169_private *tp)
  5018. {
  5019. void __iomem *ioaddr = tp->mmio_addr;
  5020. struct pci_dev *pdev = tp->pci_dev;
  5021. rtl_csi_access_enable_2(tp);
  5022. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  5023. rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  5024. rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  5025. rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
  5026. rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
  5027. rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
  5028. rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
  5029. rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
  5030. rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
  5031. rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
  5032. rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
  5033. RTL_W8(MaxTxPacketSize, EarlySize);
  5034. rtl_disable_clock_request(pdev);
  5035. RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
  5036. RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
  5037. RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
  5038. RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
  5039. RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
  5040. }
  5041. static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
  5042. {
  5043. void __iomem *ioaddr = tp->mmio_addr;
  5044. static const struct ephy_info e_info_8168f_1[] = {
  5045. { 0x06, 0x00c0, 0x0020 },
  5046. { 0x08, 0x0001, 0x0002 },
  5047. { 0x09, 0x0000, 0x0080 },
  5048. { 0x19, 0x0000, 0x0224 }
  5049. };
  5050. rtl_hw_start_8168f(tp);
  5051. rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
  5052. rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
  5053. /* Adjust EEE LED frequency */
  5054. RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
  5055. }
  5056. static void rtl_hw_start_8411(struct rtl8169_private *tp)
  5057. {
  5058. static const struct ephy_info e_info_8168f_1[] = {
  5059. { 0x06, 0x00c0, 0x0020 },
  5060. { 0x0f, 0xffff, 0x5200 },
  5061. { 0x1e, 0x0000, 0x4000 },
  5062. { 0x19, 0x0000, 0x0224 }
  5063. };
  5064. rtl_hw_start_8168f(tp);
  5065. rtl_pcie_state_l2l3_enable(tp, false);
  5066. rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
  5067. rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
  5068. }
  5069. static void rtl_hw_start_8168g(struct rtl8169_private *tp)
  5070. {
  5071. void __iomem *ioaddr = tp->mmio_addr;
  5072. struct pci_dev *pdev = tp->pci_dev;
  5073. RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
  5074. rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
  5075. rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
  5076. rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
  5077. rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
  5078. rtl_csi_access_enable_1(tp);
  5079. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  5080. rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
  5081. rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
  5082. rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
  5083. RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
  5084. RTL_W8(MaxTxPacketSize, EarlySize);
  5085. rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  5086. rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  5087. /* Adjust EEE LED frequency */
  5088. RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
  5089. rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
  5090. rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
  5091. rtl_pcie_state_l2l3_enable(tp, false);
  5092. }
  5093. static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
  5094. {
  5095. void __iomem *ioaddr = tp->mmio_addr;
  5096. static const struct ephy_info e_info_8168g_1[] = {
  5097. { 0x00, 0x0000, 0x0008 },
  5098. { 0x0c, 0x37d0, 0x0820 },
  5099. { 0x1e, 0x0000, 0x0001 },
  5100. { 0x19, 0x8000, 0x0000 }
  5101. };
  5102. rtl_hw_start_8168g(tp);
  5103. /* disable aspm and clock request before access ephy */
  5104. RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
  5105. RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
  5106. rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
  5107. }
  5108. static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
  5109. {
  5110. void __iomem *ioaddr = tp->mmio_addr;
  5111. static const struct ephy_info e_info_8168g_2[] = {
  5112. { 0x00, 0x0000, 0x0008 },
  5113. { 0x0c, 0x3df0, 0x0200 },
  5114. { 0x19, 0xffff, 0xfc00 },
  5115. { 0x1e, 0xffff, 0x20eb }
  5116. };
  5117. rtl_hw_start_8168g(tp);
  5118. /* disable aspm and clock request before access ephy */
  5119. RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
  5120. RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
  5121. rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
  5122. }
  5123. static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
  5124. {
  5125. void __iomem *ioaddr = tp->mmio_addr;
  5126. static const struct ephy_info e_info_8411_2[] = {
  5127. { 0x00, 0x0000, 0x0008 },
  5128. { 0x0c, 0x3df0, 0x0200 },
  5129. { 0x0f, 0xffff, 0x5200 },
  5130. { 0x19, 0x0020, 0x0000 },
  5131. { 0x1e, 0x0000, 0x2000 }
  5132. };
  5133. rtl_hw_start_8168g(tp);
  5134. /* disable aspm and clock request before access ephy */
  5135. RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
  5136. RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
  5137. rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
  5138. }
  5139. static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
  5140. {
  5141. void __iomem *ioaddr = tp->mmio_addr;
  5142. struct pci_dev *pdev = tp->pci_dev;
  5143. int rg_saw_cnt;
  5144. u32 data;
  5145. static const struct ephy_info e_info_8168h_1[] = {
  5146. { 0x1e, 0x0800, 0x0001 },
  5147. { 0x1d, 0x0000, 0x0800 },
  5148. { 0x05, 0xffff, 0x2089 },
  5149. { 0x06, 0xffff, 0x5881 },
  5150. { 0x04, 0xffff, 0x154a },
  5151. { 0x01, 0xffff, 0x068b }
  5152. };
  5153. /* disable aspm and clock request before access ephy */
  5154. RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
  5155. RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
  5156. rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
  5157. RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
  5158. rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
  5159. rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
  5160. rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
  5161. rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
  5162. rtl_csi_access_enable_1(tp);
  5163. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  5164. rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
  5165. rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
  5166. rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
  5167. rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
  5168. rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
  5169. RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
  5170. RTL_W8(MaxTxPacketSize, EarlySize);
  5171. rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  5172. rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  5173. /* Adjust EEE LED frequency */
  5174. RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
  5175. RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
  5176. RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
  5177. RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
  5178. rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
  5179. rtl_pcie_state_l2l3_enable(tp, false);
  5180. rtl_writephy(tp, 0x1f, 0x0c42);
  5181. rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
  5182. rtl_writephy(tp, 0x1f, 0x0000);
  5183. if (rg_saw_cnt > 0) {
  5184. u16 sw_cnt_1ms_ini;
  5185. sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
  5186. sw_cnt_1ms_ini &= 0x0fff;
  5187. data = r8168_mac_ocp_read(tp, 0xd412);
  5188. data &= ~0x0fff;
  5189. data |= sw_cnt_1ms_ini;
  5190. r8168_mac_ocp_write(tp, 0xd412, data);
  5191. }
  5192. data = r8168_mac_ocp_read(tp, 0xe056);
  5193. data &= ~0xf0;
  5194. data |= 0x70;
  5195. r8168_mac_ocp_write(tp, 0xe056, data);
  5196. data = r8168_mac_ocp_read(tp, 0xe052);
  5197. data &= ~0x6000;
  5198. data |= 0x8008;
  5199. r8168_mac_ocp_write(tp, 0xe052, data);
  5200. data = r8168_mac_ocp_read(tp, 0xe0d6);
  5201. data &= ~0x01ff;
  5202. data |= 0x017f;
  5203. r8168_mac_ocp_write(tp, 0xe0d6, data);
  5204. data = r8168_mac_ocp_read(tp, 0xd420);
  5205. data &= ~0x0fff;
  5206. data |= 0x047f;
  5207. r8168_mac_ocp_write(tp, 0xd420, data);
  5208. r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
  5209. r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
  5210. r8168_mac_ocp_write(tp, 0xc094, 0x0000);
  5211. r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
  5212. }
  5213. static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
  5214. {
  5215. void __iomem *ioaddr = tp->mmio_addr;
  5216. struct pci_dev *pdev = tp->pci_dev;
  5217. rtl8168ep_stop_cmac(tp);
  5218. RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
  5219. rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
  5220. rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
  5221. rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
  5222. rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
  5223. rtl_csi_access_enable_1(tp);
  5224. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  5225. rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
  5226. rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
  5227. rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
  5228. rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
  5229. RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
  5230. RTL_W8(MaxTxPacketSize, EarlySize);
  5231. rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  5232. rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  5233. /* Adjust EEE LED frequency */
  5234. RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
  5235. rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
  5236. RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
  5237. rtl_pcie_state_l2l3_enable(tp, false);
  5238. }
  5239. static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
  5240. {
  5241. void __iomem *ioaddr = tp->mmio_addr;
  5242. static const struct ephy_info e_info_8168ep_1[] = {
  5243. { 0x00, 0xffff, 0x10ab },
  5244. { 0x06, 0xffff, 0xf030 },
  5245. { 0x08, 0xffff, 0x2006 },
  5246. { 0x0d, 0xffff, 0x1666 },
  5247. { 0x0c, 0x3ff0, 0x0000 }
  5248. };
  5249. /* disable aspm and clock request before access ephy */
  5250. RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
  5251. RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
  5252. rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
  5253. rtl_hw_start_8168ep(tp);
  5254. }
  5255. static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
  5256. {
  5257. void __iomem *ioaddr = tp->mmio_addr;
  5258. static const struct ephy_info e_info_8168ep_2[] = {
  5259. { 0x00, 0xffff, 0x10a3 },
  5260. { 0x19, 0xffff, 0xfc00 },
  5261. { 0x1e, 0xffff, 0x20ea }
  5262. };
  5263. /* disable aspm and clock request before access ephy */
  5264. RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
  5265. RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
  5266. rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
  5267. rtl_hw_start_8168ep(tp);
  5268. RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
  5269. RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
  5270. }
  5271. static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
  5272. {
  5273. void __iomem *ioaddr = tp->mmio_addr;
  5274. u32 data;
  5275. static const struct ephy_info e_info_8168ep_3[] = {
  5276. { 0x00, 0xffff, 0x10a3 },
  5277. { 0x19, 0xffff, 0x7c00 },
  5278. { 0x1e, 0xffff, 0x20eb },
  5279. { 0x0d, 0xffff, 0x1666 }
  5280. };
  5281. /* disable aspm and clock request before access ephy */
  5282. RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
  5283. RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
  5284. rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
  5285. rtl_hw_start_8168ep(tp);
  5286. RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
  5287. RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
  5288. data = r8168_mac_ocp_read(tp, 0xd3e2);
  5289. data &= 0xf000;
  5290. data |= 0x0271;
  5291. r8168_mac_ocp_write(tp, 0xd3e2, data);
  5292. data = r8168_mac_ocp_read(tp, 0xd3e4);
  5293. data &= 0xff00;
  5294. r8168_mac_ocp_write(tp, 0xd3e4, data);
  5295. data = r8168_mac_ocp_read(tp, 0xe860);
  5296. data |= 0x0080;
  5297. r8168_mac_ocp_write(tp, 0xe860, data);
  5298. }
  5299. static void rtl_hw_start_8168(struct net_device *dev)
  5300. {
  5301. struct rtl8169_private *tp = netdev_priv(dev);
  5302. void __iomem *ioaddr = tp->mmio_addr;
  5303. RTL_W8(Cfg9346, Cfg9346_Unlock);
  5304. RTL_W8(MaxTxPacketSize, TxPacketMax);
  5305. rtl_set_rx_max_size(ioaddr, rx_buf_sz);
  5306. tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
  5307. RTL_W16(CPlusCmd, tp->cp_cmd);
  5308. RTL_W16(IntrMitigate, 0x5151);
  5309. /* Work around for RxFIFO overflow. */
  5310. if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
  5311. tp->event_slow |= RxFIFOOver | PCSTimeout;
  5312. tp->event_slow &= ~RxOverflow;
  5313. }
  5314. rtl_set_rx_tx_desc_registers(tp, ioaddr);
  5315. rtl_set_rx_tx_config_registers(tp);
  5316. RTL_R8(IntrMask);
  5317. switch (tp->mac_version) {
  5318. case RTL_GIGA_MAC_VER_11:
  5319. rtl_hw_start_8168bb(tp);
  5320. break;
  5321. case RTL_GIGA_MAC_VER_12:
  5322. case RTL_GIGA_MAC_VER_17:
  5323. rtl_hw_start_8168bef(tp);
  5324. break;
  5325. case RTL_GIGA_MAC_VER_18:
  5326. rtl_hw_start_8168cp_1(tp);
  5327. break;
  5328. case RTL_GIGA_MAC_VER_19:
  5329. rtl_hw_start_8168c_1(tp);
  5330. break;
  5331. case RTL_GIGA_MAC_VER_20:
  5332. rtl_hw_start_8168c_2(tp);
  5333. break;
  5334. case RTL_GIGA_MAC_VER_21:
  5335. rtl_hw_start_8168c_3(tp);
  5336. break;
  5337. case RTL_GIGA_MAC_VER_22:
  5338. rtl_hw_start_8168c_4(tp);
  5339. break;
  5340. case RTL_GIGA_MAC_VER_23:
  5341. rtl_hw_start_8168cp_2(tp);
  5342. break;
  5343. case RTL_GIGA_MAC_VER_24:
  5344. rtl_hw_start_8168cp_3(tp);
  5345. break;
  5346. case RTL_GIGA_MAC_VER_25:
  5347. case RTL_GIGA_MAC_VER_26:
  5348. case RTL_GIGA_MAC_VER_27:
  5349. rtl_hw_start_8168d(tp);
  5350. break;
  5351. case RTL_GIGA_MAC_VER_28:
  5352. rtl_hw_start_8168d_4(tp);
  5353. break;
  5354. case RTL_GIGA_MAC_VER_31:
  5355. rtl_hw_start_8168dp(tp);
  5356. break;
  5357. case RTL_GIGA_MAC_VER_32:
  5358. case RTL_GIGA_MAC_VER_33:
  5359. rtl_hw_start_8168e_1(tp);
  5360. break;
  5361. case RTL_GIGA_MAC_VER_34:
  5362. rtl_hw_start_8168e_2(tp);
  5363. break;
  5364. case RTL_GIGA_MAC_VER_35:
  5365. case RTL_GIGA_MAC_VER_36:
  5366. rtl_hw_start_8168f_1(tp);
  5367. break;
  5368. case RTL_GIGA_MAC_VER_38:
  5369. rtl_hw_start_8411(tp);
  5370. break;
  5371. case RTL_GIGA_MAC_VER_40:
  5372. case RTL_GIGA_MAC_VER_41:
  5373. rtl_hw_start_8168g_1(tp);
  5374. break;
  5375. case RTL_GIGA_MAC_VER_42:
  5376. rtl_hw_start_8168g_2(tp);
  5377. break;
  5378. case RTL_GIGA_MAC_VER_44:
  5379. rtl_hw_start_8411_2(tp);
  5380. break;
  5381. case RTL_GIGA_MAC_VER_45:
  5382. case RTL_GIGA_MAC_VER_46:
  5383. rtl_hw_start_8168h_1(tp);
  5384. break;
  5385. case RTL_GIGA_MAC_VER_49:
  5386. rtl_hw_start_8168ep_1(tp);
  5387. break;
  5388. case RTL_GIGA_MAC_VER_50:
  5389. rtl_hw_start_8168ep_2(tp);
  5390. break;
  5391. case RTL_GIGA_MAC_VER_51:
  5392. rtl_hw_start_8168ep_3(tp);
  5393. break;
  5394. default:
  5395. printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
  5396. dev->name, tp->mac_version);
  5397. break;
  5398. }
  5399. RTL_W8(Cfg9346, Cfg9346_Lock);
  5400. RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
  5401. rtl_set_rx_mode(dev);
  5402. RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
  5403. }
  5404. #define R810X_CPCMD_QUIRK_MASK (\
  5405. EnableBist | \
  5406. Mac_dbgo_oe | \
  5407. Force_half_dup | \
  5408. Force_rxflow_en | \
  5409. Force_txflow_en | \
  5410. Cxpl_dbg_sel | \
  5411. ASF | \
  5412. PktCntrDisable | \
  5413. Mac_dbgo_sel)
  5414. static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
  5415. {
  5416. void __iomem *ioaddr = tp->mmio_addr;
  5417. struct pci_dev *pdev = tp->pci_dev;
  5418. static const struct ephy_info e_info_8102e_1[] = {
  5419. { 0x01, 0, 0x6e65 },
  5420. { 0x02, 0, 0x091f },
  5421. { 0x03, 0, 0xc2f9 },
  5422. { 0x06, 0, 0xafb5 },
  5423. { 0x07, 0, 0x0e00 },
  5424. { 0x19, 0, 0xec80 },
  5425. { 0x01, 0, 0x2e65 },
  5426. { 0x01, 0, 0x6e65 }
  5427. };
  5428. u8 cfg1;
  5429. rtl_csi_access_enable_2(tp);
  5430. RTL_W8(DBG_REG, FIX_NAK_1);
  5431. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  5432. RTL_W8(Config1,
  5433. LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
  5434. RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
  5435. cfg1 = RTL_R8(Config1);
  5436. if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
  5437. RTL_W8(Config1, cfg1 & ~LEDS0);
  5438. rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
  5439. }
  5440. static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
  5441. {
  5442. void __iomem *ioaddr = tp->mmio_addr;
  5443. struct pci_dev *pdev = tp->pci_dev;
  5444. rtl_csi_access_enable_2(tp);
  5445. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  5446. RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
  5447. RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
  5448. }
  5449. static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
  5450. {
  5451. rtl_hw_start_8102e_2(tp);
  5452. rtl_ephy_write(tp, 0x03, 0xc2f9);
  5453. }
  5454. static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
  5455. {
  5456. void __iomem *ioaddr = tp->mmio_addr;
  5457. static const struct ephy_info e_info_8105e_1[] = {
  5458. { 0x07, 0, 0x4000 },
  5459. { 0x19, 0, 0x0200 },
  5460. { 0x19, 0, 0x0020 },
  5461. { 0x1e, 0, 0x2000 },
  5462. { 0x03, 0, 0x0001 },
  5463. { 0x19, 0, 0x0100 },
  5464. { 0x19, 0, 0x0004 },
  5465. { 0x0a, 0, 0x0020 }
  5466. };
  5467. /* Force LAN exit from ASPM if Rx/Tx are not idle */
  5468. RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
  5469. /* Disable Early Tally Counter */
  5470. RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
  5471. RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
  5472. RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
  5473. rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
  5474. rtl_pcie_state_l2l3_enable(tp, false);
  5475. }
  5476. static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
  5477. {
  5478. rtl_hw_start_8105e_1(tp);
  5479. rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
  5480. }
  5481. static void rtl_hw_start_8402(struct rtl8169_private *tp)
  5482. {
  5483. void __iomem *ioaddr = tp->mmio_addr;
  5484. static const struct ephy_info e_info_8402[] = {
  5485. { 0x19, 0xffff, 0xff64 },
  5486. { 0x1e, 0, 0x4000 }
  5487. };
  5488. rtl_csi_access_enable_2(tp);
  5489. /* Force LAN exit from ASPM if Rx/Tx are not idle */
  5490. RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
  5491. RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
  5492. RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
  5493. rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
  5494. rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
  5495. rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
  5496. rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
  5497. rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
  5498. rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
  5499. rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  5500. rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  5501. rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
  5502. rtl_pcie_state_l2l3_enable(tp, false);
  5503. }
  5504. static void rtl_hw_start_8106(struct rtl8169_private *tp)
  5505. {
  5506. void __iomem *ioaddr = tp->mmio_addr;
  5507. /* Force LAN exit from ASPM if Rx/Tx are not idle */
  5508. RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
  5509. RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
  5510. RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
  5511. RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
  5512. rtl_pcie_state_l2l3_enable(tp, false);
  5513. }
  5514. static void rtl_hw_start_8101(struct net_device *dev)
  5515. {
  5516. struct rtl8169_private *tp = netdev_priv(dev);
  5517. void __iomem *ioaddr = tp->mmio_addr;
  5518. struct pci_dev *pdev = tp->pci_dev;
  5519. if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
  5520. tp->event_slow &= ~RxFIFOOver;
  5521. if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
  5522. tp->mac_version == RTL_GIGA_MAC_VER_16)
  5523. pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
  5524. PCI_EXP_DEVCTL_NOSNOOP_EN);
  5525. RTL_W8(Cfg9346, Cfg9346_Unlock);
  5526. RTL_W8(MaxTxPacketSize, TxPacketMax);
  5527. rtl_set_rx_max_size(ioaddr, rx_buf_sz);
  5528. tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
  5529. RTL_W16(CPlusCmd, tp->cp_cmd);
  5530. rtl_set_rx_tx_desc_registers(tp, ioaddr);
  5531. rtl_set_rx_tx_config_registers(tp);
  5532. switch (tp->mac_version) {
  5533. case RTL_GIGA_MAC_VER_07:
  5534. rtl_hw_start_8102e_1(tp);
  5535. break;
  5536. case RTL_GIGA_MAC_VER_08:
  5537. rtl_hw_start_8102e_3(tp);
  5538. break;
  5539. case RTL_GIGA_MAC_VER_09:
  5540. rtl_hw_start_8102e_2(tp);
  5541. break;
  5542. case RTL_GIGA_MAC_VER_29:
  5543. rtl_hw_start_8105e_1(tp);
  5544. break;
  5545. case RTL_GIGA_MAC_VER_30:
  5546. rtl_hw_start_8105e_2(tp);
  5547. break;
  5548. case RTL_GIGA_MAC_VER_37:
  5549. rtl_hw_start_8402(tp);
  5550. break;
  5551. case RTL_GIGA_MAC_VER_39:
  5552. rtl_hw_start_8106(tp);
  5553. break;
  5554. case RTL_GIGA_MAC_VER_43:
  5555. rtl_hw_start_8168g_2(tp);
  5556. break;
  5557. case RTL_GIGA_MAC_VER_47:
  5558. case RTL_GIGA_MAC_VER_48:
  5559. rtl_hw_start_8168h_1(tp);
  5560. break;
  5561. }
  5562. RTL_W8(Cfg9346, Cfg9346_Lock);
  5563. RTL_W16(IntrMitigate, 0x0000);
  5564. RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
  5565. rtl_set_rx_mode(dev);
  5566. RTL_R8(IntrMask);
  5567. RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
  5568. }
  5569. static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
  5570. {
  5571. struct rtl8169_private *tp = netdev_priv(dev);
  5572. if (new_mtu > ETH_DATA_LEN)
  5573. rtl_hw_jumbo_enable(tp);
  5574. else
  5575. rtl_hw_jumbo_disable(tp);
  5576. dev->mtu = new_mtu;
  5577. netdev_update_features(dev);
  5578. return 0;
  5579. }
  5580. static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
  5581. {
  5582. desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
  5583. desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
  5584. }
  5585. static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
  5586. void **data_buff, struct RxDesc *desc)
  5587. {
  5588. dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
  5589. DMA_FROM_DEVICE);
  5590. kfree(*data_buff);
  5591. *data_buff = NULL;
  5592. rtl8169_make_unusable_by_asic(desc);
  5593. }
  5594. static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
  5595. {
  5596. u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
  5597. /* Force memory writes to complete before releasing descriptor */
  5598. dma_wmb();
  5599. desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
  5600. }
  5601. static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
  5602. u32 rx_buf_sz)
  5603. {
  5604. desc->addr = cpu_to_le64(mapping);
  5605. rtl8169_mark_to_asic(desc, rx_buf_sz);
  5606. }
  5607. static inline void *rtl8169_align(void *data)
  5608. {
  5609. return (void *)ALIGN((long)data, 16);
  5610. }
  5611. static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
  5612. struct RxDesc *desc)
  5613. {
  5614. void *data;
  5615. dma_addr_t mapping;
  5616. struct device *d = &tp->pci_dev->dev;
  5617. struct net_device *dev = tp->dev;
  5618. int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
  5619. data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
  5620. if (!data)
  5621. return NULL;
  5622. if (rtl8169_align(data) != data) {
  5623. kfree(data);
  5624. data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
  5625. if (!data)
  5626. return NULL;
  5627. }
  5628. mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
  5629. DMA_FROM_DEVICE);
  5630. if (unlikely(dma_mapping_error(d, mapping))) {
  5631. if (net_ratelimit())
  5632. netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
  5633. goto err_out;
  5634. }
  5635. rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
  5636. return data;
  5637. err_out:
  5638. kfree(data);
  5639. return NULL;
  5640. }
  5641. static void rtl8169_rx_clear(struct rtl8169_private *tp)
  5642. {
  5643. unsigned int i;
  5644. for (i = 0; i < NUM_RX_DESC; i++) {
  5645. if (tp->Rx_databuff[i]) {
  5646. rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
  5647. tp->RxDescArray + i);
  5648. }
  5649. }
  5650. }
  5651. static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
  5652. {
  5653. desc->opts1 |= cpu_to_le32(RingEnd);
  5654. }
  5655. static int rtl8169_rx_fill(struct rtl8169_private *tp)
  5656. {
  5657. unsigned int i;
  5658. for (i = 0; i < NUM_RX_DESC; i++) {
  5659. void *data;
  5660. if (tp->Rx_databuff[i])
  5661. continue;
  5662. data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
  5663. if (!data) {
  5664. rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
  5665. goto err_out;
  5666. }
  5667. tp->Rx_databuff[i] = data;
  5668. }
  5669. rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
  5670. return 0;
  5671. err_out:
  5672. rtl8169_rx_clear(tp);
  5673. return -ENOMEM;
  5674. }
  5675. static int rtl8169_init_ring(struct net_device *dev)
  5676. {
  5677. struct rtl8169_private *tp = netdev_priv(dev);
  5678. rtl8169_init_ring_indexes(tp);
  5679. memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
  5680. memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
  5681. return rtl8169_rx_fill(tp);
  5682. }
  5683. static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
  5684. struct TxDesc *desc)
  5685. {
  5686. unsigned int len = tx_skb->len;
  5687. dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
  5688. desc->opts1 = 0x00;
  5689. desc->opts2 = 0x00;
  5690. desc->addr = 0x00;
  5691. tx_skb->len = 0;
  5692. }
  5693. static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
  5694. unsigned int n)
  5695. {
  5696. unsigned int i;
  5697. for (i = 0; i < n; i++) {
  5698. unsigned int entry = (start + i) % NUM_TX_DESC;
  5699. struct ring_info *tx_skb = tp->tx_skb + entry;
  5700. unsigned int len = tx_skb->len;
  5701. if (len) {
  5702. struct sk_buff *skb = tx_skb->skb;
  5703. rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
  5704. tp->TxDescArray + entry);
  5705. if (skb) {
  5706. tp->dev->stats.tx_dropped++;
  5707. dev_kfree_skb_any(skb);
  5708. tx_skb->skb = NULL;
  5709. }
  5710. }
  5711. }
  5712. }
  5713. static void rtl8169_tx_clear(struct rtl8169_private *tp)
  5714. {
  5715. rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
  5716. tp->cur_tx = tp->dirty_tx = 0;
  5717. }
  5718. static void rtl_reset_work(struct rtl8169_private *tp)
  5719. {
  5720. struct net_device *dev = tp->dev;
  5721. int i;
  5722. napi_disable(&tp->napi);
  5723. netif_stop_queue(dev);
  5724. synchronize_sched();
  5725. rtl8169_hw_reset(tp);
  5726. for (i = 0; i < NUM_RX_DESC; i++)
  5727. rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
  5728. rtl8169_tx_clear(tp);
  5729. rtl8169_init_ring_indexes(tp);
  5730. napi_enable(&tp->napi);
  5731. rtl_hw_start(dev);
  5732. netif_wake_queue(dev);
  5733. rtl8169_check_link_status(dev, tp, tp->mmio_addr);
  5734. }
  5735. static void rtl8169_tx_timeout(struct net_device *dev)
  5736. {
  5737. struct rtl8169_private *tp = netdev_priv(dev);
  5738. rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
  5739. }
  5740. static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
  5741. u32 *opts)
  5742. {
  5743. struct skb_shared_info *info = skb_shinfo(skb);
  5744. unsigned int cur_frag, entry;
  5745. struct TxDesc *uninitialized_var(txd);
  5746. struct device *d = &tp->pci_dev->dev;
  5747. entry = tp->cur_tx;
  5748. for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
  5749. const skb_frag_t *frag = info->frags + cur_frag;
  5750. dma_addr_t mapping;
  5751. u32 status, len;
  5752. void *addr;
  5753. entry = (entry + 1) % NUM_TX_DESC;
  5754. txd = tp->TxDescArray + entry;
  5755. len = skb_frag_size(frag);
  5756. addr = skb_frag_address(frag);
  5757. mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
  5758. if (unlikely(dma_mapping_error(d, mapping))) {
  5759. if (net_ratelimit())
  5760. netif_err(tp, drv, tp->dev,
  5761. "Failed to map TX fragments DMA!\n");
  5762. goto err_out;
  5763. }
  5764. /* Anti gcc 2.95.3 bugware (sic) */
  5765. status = opts[0] | len |
  5766. (RingEnd * !((entry + 1) % NUM_TX_DESC));
  5767. txd->opts1 = cpu_to_le32(status);
  5768. txd->opts2 = cpu_to_le32(opts[1]);
  5769. txd->addr = cpu_to_le64(mapping);
  5770. tp->tx_skb[entry].len = len;
  5771. }
  5772. if (cur_frag) {
  5773. tp->tx_skb[entry].skb = skb;
  5774. txd->opts1 |= cpu_to_le32(LastFrag);
  5775. }
  5776. return cur_frag;
  5777. err_out:
  5778. rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
  5779. return -EIO;
  5780. }
  5781. static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
  5782. {
  5783. return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
  5784. }
  5785. static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
  5786. struct net_device *dev);
  5787. /* r8169_csum_workaround()
  5788. * The hw limites the value the transport offset. When the offset is out of the
  5789. * range, calculate the checksum by sw.
  5790. */
  5791. static void r8169_csum_workaround(struct rtl8169_private *tp,
  5792. struct sk_buff *skb)
  5793. {
  5794. if (skb_shinfo(skb)->gso_size) {
  5795. netdev_features_t features = tp->dev->features;
  5796. struct sk_buff *segs, *nskb;
  5797. features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
  5798. segs = skb_gso_segment(skb, features);
  5799. if (IS_ERR(segs) || !segs)
  5800. goto drop;
  5801. do {
  5802. nskb = segs;
  5803. segs = segs->next;
  5804. nskb->next = NULL;
  5805. rtl8169_start_xmit(nskb, tp->dev);
  5806. } while (segs);
  5807. dev_consume_skb_any(skb);
  5808. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  5809. if (skb_checksum_help(skb) < 0)
  5810. goto drop;
  5811. rtl8169_start_xmit(skb, tp->dev);
  5812. } else {
  5813. struct net_device_stats *stats;
  5814. drop:
  5815. stats = &tp->dev->stats;
  5816. stats->tx_dropped++;
  5817. dev_kfree_skb_any(skb);
  5818. }
  5819. }
  5820. /* msdn_giant_send_check()
  5821. * According to the document of microsoft, the TCP Pseudo Header excludes the
  5822. * packet length for IPv6 TCP large packets.
  5823. */
  5824. static int msdn_giant_send_check(struct sk_buff *skb)
  5825. {
  5826. const struct ipv6hdr *ipv6h;
  5827. struct tcphdr *th;
  5828. int ret;
  5829. ret = skb_cow_head(skb, 0);
  5830. if (ret)
  5831. return ret;
  5832. ipv6h = ipv6_hdr(skb);
  5833. th = tcp_hdr(skb);
  5834. th->check = 0;
  5835. th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
  5836. return ret;
  5837. }
  5838. static inline __be16 get_protocol(struct sk_buff *skb)
  5839. {
  5840. __be16 protocol;
  5841. if (skb->protocol == htons(ETH_P_8021Q))
  5842. protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
  5843. else
  5844. protocol = skb->protocol;
  5845. return protocol;
  5846. }
  5847. static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
  5848. struct sk_buff *skb, u32 *opts)
  5849. {
  5850. u32 mss = skb_shinfo(skb)->gso_size;
  5851. if (mss) {
  5852. opts[0] |= TD_LSO;
  5853. opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
  5854. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  5855. const struct iphdr *ip = ip_hdr(skb);
  5856. if (ip->protocol == IPPROTO_TCP)
  5857. opts[0] |= TD0_IP_CS | TD0_TCP_CS;
  5858. else if (ip->protocol == IPPROTO_UDP)
  5859. opts[0] |= TD0_IP_CS | TD0_UDP_CS;
  5860. else
  5861. WARN_ON_ONCE(1);
  5862. }
  5863. return true;
  5864. }
  5865. static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
  5866. struct sk_buff *skb, u32 *opts)
  5867. {
  5868. u32 transport_offset = (u32)skb_transport_offset(skb);
  5869. u32 mss = skb_shinfo(skb)->gso_size;
  5870. if (mss) {
  5871. if (transport_offset > GTTCPHO_MAX) {
  5872. netif_warn(tp, tx_err, tp->dev,
  5873. "Invalid transport offset 0x%x for TSO\n",
  5874. transport_offset);
  5875. return false;
  5876. }
  5877. switch (get_protocol(skb)) {
  5878. case htons(ETH_P_IP):
  5879. opts[0] |= TD1_GTSENV4;
  5880. break;
  5881. case htons(ETH_P_IPV6):
  5882. if (msdn_giant_send_check(skb))
  5883. return false;
  5884. opts[0] |= TD1_GTSENV6;
  5885. break;
  5886. default:
  5887. WARN_ON_ONCE(1);
  5888. break;
  5889. }
  5890. opts[0] |= transport_offset << GTTCPHO_SHIFT;
  5891. opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
  5892. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  5893. u8 ip_protocol;
  5894. if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
  5895. return !(skb_checksum_help(skb) || eth_skb_pad(skb));
  5896. if (transport_offset > TCPHO_MAX) {
  5897. netif_warn(tp, tx_err, tp->dev,
  5898. "Invalid transport offset 0x%x\n",
  5899. transport_offset);
  5900. return false;
  5901. }
  5902. switch (get_protocol(skb)) {
  5903. case htons(ETH_P_IP):
  5904. opts[1] |= TD1_IPv4_CS;
  5905. ip_protocol = ip_hdr(skb)->protocol;
  5906. break;
  5907. case htons(ETH_P_IPV6):
  5908. opts[1] |= TD1_IPv6_CS;
  5909. ip_protocol = ipv6_hdr(skb)->nexthdr;
  5910. break;
  5911. default:
  5912. ip_protocol = IPPROTO_RAW;
  5913. break;
  5914. }
  5915. if (ip_protocol == IPPROTO_TCP)
  5916. opts[1] |= TD1_TCP_CS;
  5917. else if (ip_protocol == IPPROTO_UDP)
  5918. opts[1] |= TD1_UDP_CS;
  5919. else
  5920. WARN_ON_ONCE(1);
  5921. opts[1] |= transport_offset << TCPHO_SHIFT;
  5922. } else {
  5923. if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
  5924. return !eth_skb_pad(skb);
  5925. }
  5926. return true;
  5927. }
  5928. static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
  5929. struct net_device *dev)
  5930. {
  5931. struct rtl8169_private *tp = netdev_priv(dev);
  5932. unsigned int entry = tp->cur_tx % NUM_TX_DESC;
  5933. struct TxDesc *txd = tp->TxDescArray + entry;
  5934. void __iomem *ioaddr = tp->mmio_addr;
  5935. struct device *d = &tp->pci_dev->dev;
  5936. dma_addr_t mapping;
  5937. u32 status, len;
  5938. u32 opts[2];
  5939. int frags;
  5940. if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
  5941. netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
  5942. goto err_stop_0;
  5943. }
  5944. if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
  5945. goto err_stop_0;
  5946. opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
  5947. opts[0] = DescOwn;
  5948. if (!tp->tso_csum(tp, skb, opts)) {
  5949. r8169_csum_workaround(tp, skb);
  5950. return NETDEV_TX_OK;
  5951. }
  5952. len = skb_headlen(skb);
  5953. mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
  5954. if (unlikely(dma_mapping_error(d, mapping))) {
  5955. if (net_ratelimit())
  5956. netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
  5957. goto err_dma_0;
  5958. }
  5959. tp->tx_skb[entry].len = len;
  5960. txd->addr = cpu_to_le64(mapping);
  5961. frags = rtl8169_xmit_frags(tp, skb, opts);
  5962. if (frags < 0)
  5963. goto err_dma_1;
  5964. else if (frags)
  5965. opts[0] |= FirstFrag;
  5966. else {
  5967. opts[0] |= FirstFrag | LastFrag;
  5968. tp->tx_skb[entry].skb = skb;
  5969. }
  5970. txd->opts2 = cpu_to_le32(opts[1]);
  5971. skb_tx_timestamp(skb);
  5972. /* Force memory writes to complete before releasing descriptor */
  5973. dma_wmb();
  5974. /* Anti gcc 2.95.3 bugware (sic) */
  5975. status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
  5976. txd->opts1 = cpu_to_le32(status);
  5977. /* Force all memory writes to complete before notifying device */
  5978. wmb();
  5979. tp->cur_tx += frags + 1;
  5980. RTL_W8(TxPoll, NPQ);
  5981. mmiowb();
  5982. if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
  5983. /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
  5984. * not miss a ring update when it notices a stopped queue.
  5985. */
  5986. smp_wmb();
  5987. netif_stop_queue(dev);
  5988. /* Sync with rtl_tx:
  5989. * - publish queue status and cur_tx ring index (write barrier)
  5990. * - refresh dirty_tx ring index (read barrier).
  5991. * May the current thread have a pessimistic view of the ring
  5992. * status and forget to wake up queue, a racing rtl_tx thread
  5993. * can't.
  5994. */
  5995. smp_mb();
  5996. if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
  5997. netif_wake_queue(dev);
  5998. }
  5999. return NETDEV_TX_OK;
  6000. err_dma_1:
  6001. rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
  6002. err_dma_0:
  6003. dev_kfree_skb_any(skb);
  6004. dev->stats.tx_dropped++;
  6005. return NETDEV_TX_OK;
  6006. err_stop_0:
  6007. netif_stop_queue(dev);
  6008. dev->stats.tx_dropped++;
  6009. return NETDEV_TX_BUSY;
  6010. }
  6011. static void rtl8169_pcierr_interrupt(struct net_device *dev)
  6012. {
  6013. struct rtl8169_private *tp = netdev_priv(dev);
  6014. struct pci_dev *pdev = tp->pci_dev;
  6015. u16 pci_status, pci_cmd;
  6016. pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
  6017. pci_read_config_word(pdev, PCI_STATUS, &pci_status);
  6018. netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
  6019. pci_cmd, pci_status);
  6020. /*
  6021. * The recovery sequence below admits a very elaborated explanation:
  6022. * - it seems to work;
  6023. * - I did not see what else could be done;
  6024. * - it makes iop3xx happy.
  6025. *
  6026. * Feel free to adjust to your needs.
  6027. */
  6028. if (pdev->broken_parity_status)
  6029. pci_cmd &= ~PCI_COMMAND_PARITY;
  6030. else
  6031. pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
  6032. pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
  6033. pci_write_config_word(pdev, PCI_STATUS,
  6034. pci_status & (PCI_STATUS_DETECTED_PARITY |
  6035. PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
  6036. PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
  6037. /* The infamous DAC f*ckup only happens at boot time */
  6038. if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
  6039. void __iomem *ioaddr = tp->mmio_addr;
  6040. netif_info(tp, intr, dev, "disabling PCI DAC\n");
  6041. tp->cp_cmd &= ~PCIDAC;
  6042. RTL_W16(CPlusCmd, tp->cp_cmd);
  6043. dev->features &= ~NETIF_F_HIGHDMA;
  6044. }
  6045. rtl8169_hw_reset(tp);
  6046. rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
  6047. }
  6048. static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
  6049. {
  6050. unsigned int dirty_tx, tx_left;
  6051. dirty_tx = tp->dirty_tx;
  6052. smp_rmb();
  6053. tx_left = tp->cur_tx - dirty_tx;
  6054. while (tx_left > 0) {
  6055. unsigned int entry = dirty_tx % NUM_TX_DESC;
  6056. struct ring_info *tx_skb = tp->tx_skb + entry;
  6057. u32 status;
  6058. status = le32_to_cpu(tp->TxDescArray[entry].opts1);
  6059. if (status & DescOwn)
  6060. break;
  6061. /* This barrier is needed to keep us from reading
  6062. * any other fields out of the Tx descriptor until
  6063. * we know the status of DescOwn
  6064. */
  6065. dma_rmb();
  6066. rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
  6067. tp->TxDescArray + entry);
  6068. if (status & LastFrag) {
  6069. u64_stats_update_begin(&tp->tx_stats.syncp);
  6070. tp->tx_stats.packets++;
  6071. tp->tx_stats.bytes += tx_skb->skb->len;
  6072. u64_stats_update_end(&tp->tx_stats.syncp);
  6073. dev_kfree_skb_any(tx_skb->skb);
  6074. tx_skb->skb = NULL;
  6075. }
  6076. dirty_tx++;
  6077. tx_left--;
  6078. }
  6079. if (tp->dirty_tx != dirty_tx) {
  6080. tp->dirty_tx = dirty_tx;
  6081. /* Sync with rtl8169_start_xmit:
  6082. * - publish dirty_tx ring index (write barrier)
  6083. * - refresh cur_tx ring index and queue status (read barrier)
  6084. * May the current thread miss the stopped queue condition,
  6085. * a racing xmit thread can only have a right view of the
  6086. * ring status.
  6087. */
  6088. smp_mb();
  6089. if (netif_queue_stopped(dev) &&
  6090. TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
  6091. netif_wake_queue(dev);
  6092. }
  6093. /*
  6094. * 8168 hack: TxPoll requests are lost when the Tx packets are
  6095. * too close. Let's kick an extra TxPoll request when a burst
  6096. * of start_xmit activity is detected (if it is not detected,
  6097. * it is slow enough). -- FR
  6098. */
  6099. if (tp->cur_tx != dirty_tx) {
  6100. void __iomem *ioaddr = tp->mmio_addr;
  6101. RTL_W8(TxPoll, NPQ);
  6102. }
  6103. }
  6104. }
  6105. static inline int rtl8169_fragmented_frame(u32 status)
  6106. {
  6107. return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
  6108. }
  6109. static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
  6110. {
  6111. u32 status = opts1 & RxProtoMask;
  6112. if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
  6113. ((status == RxProtoUDP) && !(opts1 & UDPFail)))
  6114. skb->ip_summed = CHECKSUM_UNNECESSARY;
  6115. else
  6116. skb_checksum_none_assert(skb);
  6117. }
  6118. static struct sk_buff *rtl8169_try_rx_copy(void *data,
  6119. struct rtl8169_private *tp,
  6120. int pkt_size,
  6121. dma_addr_t addr)
  6122. {
  6123. struct sk_buff *skb;
  6124. struct device *d = &tp->pci_dev->dev;
  6125. data = rtl8169_align(data);
  6126. dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
  6127. prefetch(data);
  6128. skb = napi_alloc_skb(&tp->napi, pkt_size);
  6129. if (skb)
  6130. memcpy(skb->data, data, pkt_size);
  6131. dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
  6132. return skb;
  6133. }
  6134. static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
  6135. {
  6136. unsigned int cur_rx, rx_left;
  6137. unsigned int count;
  6138. cur_rx = tp->cur_rx;
  6139. for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
  6140. unsigned int entry = cur_rx % NUM_RX_DESC;
  6141. struct RxDesc *desc = tp->RxDescArray + entry;
  6142. u32 status;
  6143. status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
  6144. if (status & DescOwn)
  6145. break;
  6146. /* This barrier is needed to keep us from reading
  6147. * any other fields out of the Rx descriptor until
  6148. * we know the status of DescOwn
  6149. */
  6150. dma_rmb();
  6151. if (unlikely(status & RxRES)) {
  6152. netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
  6153. status);
  6154. dev->stats.rx_errors++;
  6155. if (status & (RxRWT | RxRUNT))
  6156. dev->stats.rx_length_errors++;
  6157. if (status & RxCRC)
  6158. dev->stats.rx_crc_errors++;
  6159. if (status & RxFOVF) {
  6160. rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
  6161. dev->stats.rx_fifo_errors++;
  6162. }
  6163. if ((status & (RxRUNT | RxCRC)) &&
  6164. !(status & (RxRWT | RxFOVF)) &&
  6165. (dev->features & NETIF_F_RXALL))
  6166. goto process_pkt;
  6167. } else {
  6168. struct sk_buff *skb;
  6169. dma_addr_t addr;
  6170. int pkt_size;
  6171. process_pkt:
  6172. addr = le64_to_cpu(desc->addr);
  6173. if (likely(!(dev->features & NETIF_F_RXFCS)))
  6174. pkt_size = (status & 0x00003fff) - 4;
  6175. else
  6176. pkt_size = status & 0x00003fff;
  6177. /*
  6178. * The driver does not support incoming fragmented
  6179. * frames. They are seen as a symptom of over-mtu
  6180. * sized frames.
  6181. */
  6182. if (unlikely(rtl8169_fragmented_frame(status))) {
  6183. dev->stats.rx_dropped++;
  6184. dev->stats.rx_length_errors++;
  6185. goto release_descriptor;
  6186. }
  6187. skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
  6188. tp, pkt_size, addr);
  6189. if (!skb) {
  6190. dev->stats.rx_dropped++;
  6191. goto release_descriptor;
  6192. }
  6193. rtl8169_rx_csum(skb, status);
  6194. skb_put(skb, pkt_size);
  6195. skb->protocol = eth_type_trans(skb, dev);
  6196. rtl8169_rx_vlan_tag(desc, skb);
  6197. if (skb->pkt_type == PACKET_MULTICAST)
  6198. dev->stats.multicast++;
  6199. napi_gro_receive(&tp->napi, skb);
  6200. u64_stats_update_begin(&tp->rx_stats.syncp);
  6201. tp->rx_stats.packets++;
  6202. tp->rx_stats.bytes += pkt_size;
  6203. u64_stats_update_end(&tp->rx_stats.syncp);
  6204. }
  6205. release_descriptor:
  6206. desc->opts2 = 0;
  6207. rtl8169_mark_to_asic(desc, rx_buf_sz);
  6208. }
  6209. count = cur_rx - tp->cur_rx;
  6210. tp->cur_rx = cur_rx;
  6211. return count;
  6212. }
  6213. static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
  6214. {
  6215. struct net_device *dev = dev_instance;
  6216. struct rtl8169_private *tp = netdev_priv(dev);
  6217. int handled = 0;
  6218. u16 status;
  6219. status = rtl_get_events(tp);
  6220. if (status && status != 0xffff) {
  6221. status &= RTL_EVENT_NAPI | tp->event_slow;
  6222. if (status) {
  6223. handled = 1;
  6224. rtl_irq_disable(tp);
  6225. napi_schedule(&tp->napi);
  6226. }
  6227. }
  6228. return IRQ_RETVAL(handled);
  6229. }
  6230. /*
  6231. * Workqueue context.
  6232. */
  6233. static void rtl_slow_event_work(struct rtl8169_private *tp)
  6234. {
  6235. struct net_device *dev = tp->dev;
  6236. u16 status;
  6237. status = rtl_get_events(tp) & tp->event_slow;
  6238. rtl_ack_events(tp, status);
  6239. if (unlikely(status & RxFIFOOver)) {
  6240. switch (tp->mac_version) {
  6241. /* Work around for rx fifo overflow */
  6242. case RTL_GIGA_MAC_VER_11:
  6243. netif_stop_queue(dev);
  6244. /* XXX - Hack alert. See rtl_task(). */
  6245. set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
  6246. default:
  6247. break;
  6248. }
  6249. }
  6250. if (unlikely(status & SYSErr))
  6251. rtl8169_pcierr_interrupt(dev);
  6252. if (status & LinkChg)
  6253. __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
  6254. rtl_irq_enable_all(tp);
  6255. }
  6256. static void rtl_task(struct work_struct *work)
  6257. {
  6258. static const struct {
  6259. int bitnr;
  6260. void (*action)(struct rtl8169_private *);
  6261. } rtl_work[] = {
  6262. /* XXX - keep rtl_slow_event_work() as first element. */
  6263. { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
  6264. { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
  6265. { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
  6266. };
  6267. struct rtl8169_private *tp =
  6268. container_of(work, struct rtl8169_private, wk.work);
  6269. struct net_device *dev = tp->dev;
  6270. int i;
  6271. rtl_lock_work(tp);
  6272. if (!netif_running(dev) ||
  6273. !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
  6274. goto out_unlock;
  6275. for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
  6276. bool pending;
  6277. pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
  6278. if (pending)
  6279. rtl_work[i].action(tp);
  6280. }
  6281. out_unlock:
  6282. rtl_unlock_work(tp);
  6283. }
  6284. static int rtl8169_poll(struct napi_struct *napi, int budget)
  6285. {
  6286. struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
  6287. struct net_device *dev = tp->dev;
  6288. u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
  6289. int work_done= 0;
  6290. u16 status;
  6291. status = rtl_get_events(tp);
  6292. rtl_ack_events(tp, status & ~tp->event_slow);
  6293. if (status & RTL_EVENT_NAPI_RX)
  6294. work_done = rtl_rx(dev, tp, (u32) budget);
  6295. if (status & RTL_EVENT_NAPI_TX)
  6296. rtl_tx(dev, tp);
  6297. if (status & tp->event_slow) {
  6298. enable_mask &= ~tp->event_slow;
  6299. rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
  6300. }
  6301. if (work_done < budget) {
  6302. napi_complete_done(napi, work_done);
  6303. rtl_irq_enable(tp, enable_mask);
  6304. mmiowb();
  6305. }
  6306. return work_done;
  6307. }
  6308. static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
  6309. {
  6310. struct rtl8169_private *tp = netdev_priv(dev);
  6311. if (tp->mac_version > RTL_GIGA_MAC_VER_06)
  6312. return;
  6313. dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
  6314. RTL_W32(RxMissed, 0);
  6315. }
  6316. static void rtl8169_down(struct net_device *dev)
  6317. {
  6318. struct rtl8169_private *tp = netdev_priv(dev);
  6319. void __iomem *ioaddr = tp->mmio_addr;
  6320. del_timer_sync(&tp->timer);
  6321. napi_disable(&tp->napi);
  6322. netif_stop_queue(dev);
  6323. rtl8169_hw_reset(tp);
  6324. /*
  6325. * At this point device interrupts can not be enabled in any function,
  6326. * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
  6327. * and napi is disabled (rtl8169_poll).
  6328. */
  6329. rtl8169_rx_missed(dev, ioaddr);
  6330. /* Give a racing hard_start_xmit a few cycles to complete. */
  6331. synchronize_sched();
  6332. rtl8169_tx_clear(tp);
  6333. rtl8169_rx_clear(tp);
  6334. rtl_pll_power_down(tp);
  6335. }
  6336. static int rtl8169_close(struct net_device *dev)
  6337. {
  6338. struct rtl8169_private *tp = netdev_priv(dev);
  6339. struct pci_dev *pdev = tp->pci_dev;
  6340. pm_runtime_get_sync(&pdev->dev);
  6341. /* Update counters before going down */
  6342. rtl8169_update_counters(dev);
  6343. rtl_lock_work(tp);
  6344. clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
  6345. rtl8169_down(dev);
  6346. rtl_unlock_work(tp);
  6347. cancel_work_sync(&tp->wk.work);
  6348. free_irq(pdev->irq, dev);
  6349. dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
  6350. tp->RxPhyAddr);
  6351. dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
  6352. tp->TxPhyAddr);
  6353. tp->TxDescArray = NULL;
  6354. tp->RxDescArray = NULL;
  6355. pm_runtime_put_sync(&pdev->dev);
  6356. return 0;
  6357. }
  6358. #ifdef CONFIG_NET_POLL_CONTROLLER
  6359. static void rtl8169_netpoll(struct net_device *dev)
  6360. {
  6361. struct rtl8169_private *tp = netdev_priv(dev);
  6362. rtl8169_interrupt(tp->pci_dev->irq, dev);
  6363. }
  6364. #endif
  6365. static int rtl_open(struct net_device *dev)
  6366. {
  6367. struct rtl8169_private *tp = netdev_priv(dev);
  6368. void __iomem *ioaddr = tp->mmio_addr;
  6369. struct pci_dev *pdev = tp->pci_dev;
  6370. int retval = -ENOMEM;
  6371. pm_runtime_get_sync(&pdev->dev);
  6372. /*
  6373. * Rx and Tx descriptors needs 256 bytes alignment.
  6374. * dma_alloc_coherent provides more.
  6375. */
  6376. tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
  6377. &tp->TxPhyAddr, GFP_KERNEL);
  6378. if (!tp->TxDescArray)
  6379. goto err_pm_runtime_put;
  6380. tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
  6381. &tp->RxPhyAddr, GFP_KERNEL);
  6382. if (!tp->RxDescArray)
  6383. goto err_free_tx_0;
  6384. retval = rtl8169_init_ring(dev);
  6385. if (retval < 0)
  6386. goto err_free_rx_1;
  6387. INIT_WORK(&tp->wk.work, rtl_task);
  6388. smp_mb();
  6389. rtl_request_firmware(tp);
  6390. retval = request_irq(pdev->irq, rtl8169_interrupt,
  6391. (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
  6392. dev->name, dev);
  6393. if (retval < 0)
  6394. goto err_release_fw_2;
  6395. rtl_lock_work(tp);
  6396. set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
  6397. napi_enable(&tp->napi);
  6398. rtl8169_init_phy(dev, tp);
  6399. __rtl8169_set_features(dev, dev->features);
  6400. rtl_pll_power_up(tp);
  6401. rtl_hw_start(dev);
  6402. if (!rtl8169_init_counter_offsets(dev))
  6403. netif_warn(tp, hw, dev, "counter reset/update failed\n");
  6404. netif_start_queue(dev);
  6405. rtl_unlock_work(tp);
  6406. tp->saved_wolopts = 0;
  6407. pm_runtime_put_noidle(&pdev->dev);
  6408. rtl8169_check_link_status(dev, tp, ioaddr);
  6409. out:
  6410. return retval;
  6411. err_release_fw_2:
  6412. rtl_release_firmware(tp);
  6413. rtl8169_rx_clear(tp);
  6414. err_free_rx_1:
  6415. dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
  6416. tp->RxPhyAddr);
  6417. tp->RxDescArray = NULL;
  6418. err_free_tx_0:
  6419. dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
  6420. tp->TxPhyAddr);
  6421. tp->TxDescArray = NULL;
  6422. err_pm_runtime_put:
  6423. pm_runtime_put_noidle(&pdev->dev);
  6424. goto out;
  6425. }
  6426. static void
  6427. rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
  6428. {
  6429. struct rtl8169_private *tp = netdev_priv(dev);
  6430. void __iomem *ioaddr = tp->mmio_addr;
  6431. struct pci_dev *pdev = tp->pci_dev;
  6432. struct rtl8169_counters *counters = tp->counters;
  6433. unsigned int start;
  6434. pm_runtime_get_noresume(&pdev->dev);
  6435. if (netif_running(dev) && pm_runtime_active(&pdev->dev))
  6436. rtl8169_rx_missed(dev, ioaddr);
  6437. do {
  6438. start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
  6439. stats->rx_packets = tp->rx_stats.packets;
  6440. stats->rx_bytes = tp->rx_stats.bytes;
  6441. } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
  6442. do {
  6443. start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
  6444. stats->tx_packets = tp->tx_stats.packets;
  6445. stats->tx_bytes = tp->tx_stats.bytes;
  6446. } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
  6447. stats->rx_dropped = dev->stats.rx_dropped;
  6448. stats->tx_dropped = dev->stats.tx_dropped;
  6449. stats->rx_length_errors = dev->stats.rx_length_errors;
  6450. stats->rx_errors = dev->stats.rx_errors;
  6451. stats->rx_crc_errors = dev->stats.rx_crc_errors;
  6452. stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
  6453. stats->rx_missed_errors = dev->stats.rx_missed_errors;
  6454. stats->multicast = dev->stats.multicast;
  6455. /*
  6456. * Fetch additonal counter values missing in stats collected by driver
  6457. * from tally counters.
  6458. */
  6459. if (pm_runtime_active(&pdev->dev))
  6460. rtl8169_update_counters(dev);
  6461. /*
  6462. * Subtract values fetched during initalization.
  6463. * See rtl8169_init_counter_offsets for a description why we do that.
  6464. */
  6465. stats->tx_errors = le64_to_cpu(counters->tx_errors) -
  6466. le64_to_cpu(tp->tc_offset.tx_errors);
  6467. stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
  6468. le32_to_cpu(tp->tc_offset.tx_multi_collision);
  6469. stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
  6470. le16_to_cpu(tp->tc_offset.tx_aborted);
  6471. pm_runtime_put_noidle(&pdev->dev);
  6472. }
  6473. static void rtl8169_net_suspend(struct net_device *dev)
  6474. {
  6475. struct rtl8169_private *tp = netdev_priv(dev);
  6476. if (!netif_running(dev))
  6477. return;
  6478. netif_device_detach(dev);
  6479. netif_stop_queue(dev);
  6480. rtl_lock_work(tp);
  6481. napi_disable(&tp->napi);
  6482. clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
  6483. rtl_unlock_work(tp);
  6484. rtl_pll_power_down(tp);
  6485. }
  6486. #ifdef CONFIG_PM
  6487. static int rtl8169_suspend(struct device *device)
  6488. {
  6489. struct pci_dev *pdev = to_pci_dev(device);
  6490. struct net_device *dev = pci_get_drvdata(pdev);
  6491. rtl8169_net_suspend(dev);
  6492. return 0;
  6493. }
  6494. static void __rtl8169_resume(struct net_device *dev)
  6495. {
  6496. struct rtl8169_private *tp = netdev_priv(dev);
  6497. netif_device_attach(dev);
  6498. rtl_pll_power_up(tp);
  6499. rtl_lock_work(tp);
  6500. napi_enable(&tp->napi);
  6501. set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
  6502. rtl_unlock_work(tp);
  6503. rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
  6504. }
  6505. static int rtl8169_resume(struct device *device)
  6506. {
  6507. struct pci_dev *pdev = to_pci_dev(device);
  6508. struct net_device *dev = pci_get_drvdata(pdev);
  6509. struct rtl8169_private *tp = netdev_priv(dev);
  6510. rtl8169_init_phy(dev, tp);
  6511. if (netif_running(dev))
  6512. __rtl8169_resume(dev);
  6513. return 0;
  6514. }
  6515. static int rtl8169_runtime_suspend(struct device *device)
  6516. {
  6517. struct pci_dev *pdev = to_pci_dev(device);
  6518. struct net_device *dev = pci_get_drvdata(pdev);
  6519. struct rtl8169_private *tp = netdev_priv(dev);
  6520. if (!tp->TxDescArray)
  6521. return 0;
  6522. rtl_lock_work(tp);
  6523. tp->saved_wolopts = __rtl8169_get_wol(tp);
  6524. __rtl8169_set_wol(tp, WAKE_ANY);
  6525. rtl_unlock_work(tp);
  6526. rtl8169_net_suspend(dev);
  6527. /* Update counters before going runtime suspend */
  6528. rtl8169_rx_missed(dev, tp->mmio_addr);
  6529. rtl8169_update_counters(dev);
  6530. return 0;
  6531. }
  6532. static int rtl8169_runtime_resume(struct device *device)
  6533. {
  6534. struct pci_dev *pdev = to_pci_dev(device);
  6535. struct net_device *dev = pci_get_drvdata(pdev);
  6536. struct rtl8169_private *tp = netdev_priv(dev);
  6537. rtl_rar_set(tp, dev->dev_addr);
  6538. if (!tp->TxDescArray)
  6539. return 0;
  6540. rtl_lock_work(tp);
  6541. __rtl8169_set_wol(tp, tp->saved_wolopts);
  6542. tp->saved_wolopts = 0;
  6543. rtl_unlock_work(tp);
  6544. rtl8169_init_phy(dev, tp);
  6545. __rtl8169_resume(dev);
  6546. return 0;
  6547. }
  6548. static int rtl8169_runtime_idle(struct device *device)
  6549. {
  6550. struct pci_dev *pdev = to_pci_dev(device);
  6551. struct net_device *dev = pci_get_drvdata(pdev);
  6552. struct rtl8169_private *tp = netdev_priv(dev);
  6553. return tp->TxDescArray ? -EBUSY : 0;
  6554. }
  6555. static const struct dev_pm_ops rtl8169_pm_ops = {
  6556. .suspend = rtl8169_suspend,
  6557. .resume = rtl8169_resume,
  6558. .freeze = rtl8169_suspend,
  6559. .thaw = rtl8169_resume,
  6560. .poweroff = rtl8169_suspend,
  6561. .restore = rtl8169_resume,
  6562. .runtime_suspend = rtl8169_runtime_suspend,
  6563. .runtime_resume = rtl8169_runtime_resume,
  6564. .runtime_idle = rtl8169_runtime_idle,
  6565. };
  6566. #define RTL8169_PM_OPS (&rtl8169_pm_ops)
  6567. #else /* !CONFIG_PM */
  6568. #define RTL8169_PM_OPS NULL
  6569. #endif /* !CONFIG_PM */
  6570. static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
  6571. {
  6572. void __iomem *ioaddr = tp->mmio_addr;
  6573. /* WoL fails with 8168b when the receiver is disabled. */
  6574. switch (tp->mac_version) {
  6575. case RTL_GIGA_MAC_VER_11:
  6576. case RTL_GIGA_MAC_VER_12:
  6577. case RTL_GIGA_MAC_VER_17:
  6578. pci_clear_master(tp->pci_dev);
  6579. RTL_W8(ChipCmd, CmdRxEnb);
  6580. /* PCI commit */
  6581. RTL_R8(ChipCmd);
  6582. break;
  6583. default:
  6584. break;
  6585. }
  6586. }
  6587. static void rtl_shutdown(struct pci_dev *pdev)
  6588. {
  6589. struct net_device *dev = pci_get_drvdata(pdev);
  6590. struct rtl8169_private *tp = netdev_priv(dev);
  6591. struct device *d = &pdev->dev;
  6592. pm_runtime_get_sync(d);
  6593. rtl8169_net_suspend(dev);
  6594. /* Restore original MAC address */
  6595. rtl_rar_set(tp, dev->perm_addr);
  6596. rtl8169_hw_reset(tp);
  6597. if (system_state == SYSTEM_POWER_OFF) {
  6598. if (__rtl8169_get_wol(tp) & WAKE_ANY) {
  6599. rtl_wol_suspend_quirk(tp);
  6600. rtl_wol_shutdown_quirk(tp);
  6601. }
  6602. pci_wake_from_d3(pdev, true);
  6603. pci_set_power_state(pdev, PCI_D3hot);
  6604. }
  6605. pm_runtime_put_noidle(d);
  6606. }
  6607. static void rtl_remove_one(struct pci_dev *pdev)
  6608. {
  6609. struct net_device *dev = pci_get_drvdata(pdev);
  6610. struct rtl8169_private *tp = netdev_priv(dev);
  6611. if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
  6612. tp->mac_version == RTL_GIGA_MAC_VER_28 ||
  6613. tp->mac_version == RTL_GIGA_MAC_VER_31 ||
  6614. tp->mac_version == RTL_GIGA_MAC_VER_49 ||
  6615. tp->mac_version == RTL_GIGA_MAC_VER_50 ||
  6616. tp->mac_version == RTL_GIGA_MAC_VER_51) &&
  6617. r8168_check_dash(tp)) {
  6618. rtl8168_driver_stop(tp);
  6619. }
  6620. netif_napi_del(&tp->napi);
  6621. unregister_netdev(dev);
  6622. dma_free_coherent(&tp->pci_dev->dev, sizeof(*tp->counters),
  6623. tp->counters, tp->counters_phys_addr);
  6624. rtl_release_firmware(tp);
  6625. if (pci_dev_run_wake(pdev))
  6626. pm_runtime_get_noresume(&pdev->dev);
  6627. /* restore original MAC address */
  6628. rtl_rar_set(tp, dev->perm_addr);
  6629. rtl_disable_msi(pdev, tp);
  6630. rtl8169_release_board(pdev, dev, tp->mmio_addr);
  6631. }
  6632. static const struct net_device_ops rtl_netdev_ops = {
  6633. .ndo_open = rtl_open,
  6634. .ndo_stop = rtl8169_close,
  6635. .ndo_get_stats64 = rtl8169_get_stats64,
  6636. .ndo_start_xmit = rtl8169_start_xmit,
  6637. .ndo_tx_timeout = rtl8169_tx_timeout,
  6638. .ndo_validate_addr = eth_validate_addr,
  6639. .ndo_change_mtu = rtl8169_change_mtu,
  6640. .ndo_fix_features = rtl8169_fix_features,
  6641. .ndo_set_features = rtl8169_set_features,
  6642. .ndo_set_mac_address = rtl_set_mac_address,
  6643. .ndo_do_ioctl = rtl8169_ioctl,
  6644. .ndo_set_rx_mode = rtl_set_rx_mode,
  6645. #ifdef CONFIG_NET_POLL_CONTROLLER
  6646. .ndo_poll_controller = rtl8169_netpoll,
  6647. #endif
  6648. };
  6649. static const struct rtl_cfg_info {
  6650. void (*hw_start)(struct net_device *);
  6651. unsigned int region;
  6652. unsigned int align;
  6653. u16 event_slow;
  6654. unsigned features;
  6655. u8 default_ver;
  6656. } rtl_cfg_infos [] = {
  6657. [RTL_CFG_0] = {
  6658. .hw_start = rtl_hw_start_8169,
  6659. .region = 1,
  6660. .align = 0,
  6661. .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
  6662. .features = RTL_FEATURE_GMII,
  6663. .default_ver = RTL_GIGA_MAC_VER_01,
  6664. },
  6665. [RTL_CFG_1] = {
  6666. .hw_start = rtl_hw_start_8168,
  6667. .region = 2,
  6668. .align = 8,
  6669. .event_slow = SYSErr | LinkChg | RxOverflow,
  6670. .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
  6671. .default_ver = RTL_GIGA_MAC_VER_11,
  6672. },
  6673. [RTL_CFG_2] = {
  6674. .hw_start = rtl_hw_start_8101,
  6675. .region = 2,
  6676. .align = 8,
  6677. .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
  6678. PCSTimeout,
  6679. .features = RTL_FEATURE_MSI,
  6680. .default_ver = RTL_GIGA_MAC_VER_13,
  6681. }
  6682. };
  6683. /* Cfg9346_Unlock assumed. */
  6684. static unsigned rtl_try_msi(struct rtl8169_private *tp,
  6685. const struct rtl_cfg_info *cfg)
  6686. {
  6687. void __iomem *ioaddr = tp->mmio_addr;
  6688. unsigned msi = 0;
  6689. u8 cfg2;
  6690. cfg2 = RTL_R8(Config2) & ~MSIEnable;
  6691. if (cfg->features & RTL_FEATURE_MSI) {
  6692. if (pci_enable_msi(tp->pci_dev)) {
  6693. netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
  6694. } else {
  6695. cfg2 |= MSIEnable;
  6696. msi = RTL_FEATURE_MSI;
  6697. }
  6698. }
  6699. if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
  6700. RTL_W8(Config2, cfg2);
  6701. return msi;
  6702. }
  6703. DECLARE_RTL_COND(rtl_link_list_ready_cond)
  6704. {
  6705. void __iomem *ioaddr = tp->mmio_addr;
  6706. return RTL_R8(MCU) & LINK_LIST_RDY;
  6707. }
  6708. DECLARE_RTL_COND(rtl_rxtx_empty_cond)
  6709. {
  6710. void __iomem *ioaddr = tp->mmio_addr;
  6711. return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
  6712. }
  6713. static void rtl_hw_init_8168g(struct rtl8169_private *tp)
  6714. {
  6715. void __iomem *ioaddr = tp->mmio_addr;
  6716. u32 data;
  6717. tp->ocp_base = OCP_STD_PHY_BASE;
  6718. RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
  6719. if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
  6720. return;
  6721. if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
  6722. return;
  6723. RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
  6724. msleep(1);
  6725. RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
  6726. data = r8168_mac_ocp_read(tp, 0xe8de);
  6727. data &= ~(1 << 14);
  6728. r8168_mac_ocp_write(tp, 0xe8de, data);
  6729. if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
  6730. return;
  6731. data = r8168_mac_ocp_read(tp, 0xe8de);
  6732. data |= (1 << 15);
  6733. r8168_mac_ocp_write(tp, 0xe8de, data);
  6734. if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
  6735. return;
  6736. }
  6737. static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
  6738. {
  6739. rtl8168ep_stop_cmac(tp);
  6740. rtl_hw_init_8168g(tp);
  6741. }
  6742. static void rtl_hw_initialize(struct rtl8169_private *tp)
  6743. {
  6744. switch (tp->mac_version) {
  6745. case RTL_GIGA_MAC_VER_40:
  6746. case RTL_GIGA_MAC_VER_41:
  6747. case RTL_GIGA_MAC_VER_42:
  6748. case RTL_GIGA_MAC_VER_43:
  6749. case RTL_GIGA_MAC_VER_44:
  6750. case RTL_GIGA_MAC_VER_45:
  6751. case RTL_GIGA_MAC_VER_46:
  6752. case RTL_GIGA_MAC_VER_47:
  6753. case RTL_GIGA_MAC_VER_48:
  6754. rtl_hw_init_8168g(tp);
  6755. break;
  6756. case RTL_GIGA_MAC_VER_49:
  6757. case RTL_GIGA_MAC_VER_50:
  6758. case RTL_GIGA_MAC_VER_51:
  6759. rtl_hw_init_8168ep(tp);
  6760. break;
  6761. default:
  6762. break;
  6763. }
  6764. }
  6765. static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  6766. {
  6767. const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
  6768. const unsigned int region = cfg->region;
  6769. struct rtl8169_private *tp;
  6770. struct mii_if_info *mii;
  6771. struct net_device *dev;
  6772. void __iomem *ioaddr;
  6773. int chipset, i;
  6774. int rc;
  6775. if (netif_msg_drv(&debug)) {
  6776. printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
  6777. MODULENAME, RTL8169_VERSION);
  6778. }
  6779. dev = alloc_etherdev(sizeof (*tp));
  6780. if (!dev) {
  6781. rc = -ENOMEM;
  6782. goto out;
  6783. }
  6784. SET_NETDEV_DEV(dev, &pdev->dev);
  6785. dev->netdev_ops = &rtl_netdev_ops;
  6786. tp = netdev_priv(dev);
  6787. tp->dev = dev;
  6788. tp->pci_dev = pdev;
  6789. tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
  6790. mii = &tp->mii;
  6791. mii->dev = dev;
  6792. mii->mdio_read = rtl_mdio_read;
  6793. mii->mdio_write = rtl_mdio_write;
  6794. mii->phy_id_mask = 0x1f;
  6795. mii->reg_num_mask = 0x1f;
  6796. mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
  6797. /* disable ASPM completely as that cause random device stop working
  6798. * problems as well as full system hangs for some PCIe devices users */
  6799. pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
  6800. PCIE_LINK_STATE_CLKPM);
  6801. /* enable device (incl. PCI PM wakeup and hotplug setup) */
  6802. rc = pci_enable_device(pdev);
  6803. if (rc < 0) {
  6804. netif_err(tp, probe, dev, "enable failure\n");
  6805. goto err_out_free_dev_1;
  6806. }
  6807. if (pci_set_mwi(pdev) < 0)
  6808. netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
  6809. /* make sure PCI base addr 1 is MMIO */
  6810. if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
  6811. netif_err(tp, probe, dev,
  6812. "region #%d not an MMIO resource, aborting\n",
  6813. region);
  6814. rc = -ENODEV;
  6815. goto err_out_mwi_2;
  6816. }
  6817. /* check for weird/broken PCI region reporting */
  6818. if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
  6819. netif_err(tp, probe, dev,
  6820. "Invalid PCI region size(s), aborting\n");
  6821. rc = -ENODEV;
  6822. goto err_out_mwi_2;
  6823. }
  6824. rc = pci_request_regions(pdev, MODULENAME);
  6825. if (rc < 0) {
  6826. netif_err(tp, probe, dev, "could not request regions\n");
  6827. goto err_out_mwi_2;
  6828. }
  6829. /* ioremap MMIO region */
  6830. ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
  6831. if (!ioaddr) {
  6832. netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
  6833. rc = -EIO;
  6834. goto err_out_free_res_3;
  6835. }
  6836. tp->mmio_addr = ioaddr;
  6837. if (!pci_is_pcie(pdev))
  6838. netif_info(tp, probe, dev, "not PCI Express\n");
  6839. /* Identify chip attached to board */
  6840. rtl8169_get_mac_version(tp, dev, cfg->default_ver);
  6841. tp->cp_cmd = 0;
  6842. if ((sizeof(dma_addr_t) > 4) &&
  6843. (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
  6844. tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
  6845. !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
  6846. !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
  6847. /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
  6848. if (!pci_is_pcie(pdev))
  6849. tp->cp_cmd |= PCIDAC;
  6850. dev->features |= NETIF_F_HIGHDMA;
  6851. } else {
  6852. rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  6853. if (rc < 0) {
  6854. netif_err(tp, probe, dev, "DMA configuration failed\n");
  6855. goto err_out_unmap_4;
  6856. }
  6857. }
  6858. rtl_init_rxcfg(tp);
  6859. rtl_irq_disable(tp);
  6860. rtl_hw_initialize(tp);
  6861. rtl_hw_reset(tp);
  6862. rtl_ack_events(tp, 0xffff);
  6863. pci_set_master(pdev);
  6864. rtl_init_mdio_ops(tp);
  6865. rtl_init_pll_power_ops(tp);
  6866. rtl_init_jumbo_ops(tp);
  6867. rtl_init_csi_ops(tp);
  6868. rtl8169_print_mac_version(tp);
  6869. chipset = tp->mac_version;
  6870. tp->txd_version = rtl_chip_infos[chipset].txd_version;
  6871. RTL_W8(Cfg9346, Cfg9346_Unlock);
  6872. RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
  6873. RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
  6874. switch (tp->mac_version) {
  6875. case RTL_GIGA_MAC_VER_34:
  6876. case RTL_GIGA_MAC_VER_35:
  6877. case RTL_GIGA_MAC_VER_36:
  6878. case RTL_GIGA_MAC_VER_37:
  6879. case RTL_GIGA_MAC_VER_38:
  6880. case RTL_GIGA_MAC_VER_40:
  6881. case RTL_GIGA_MAC_VER_41:
  6882. case RTL_GIGA_MAC_VER_42:
  6883. case RTL_GIGA_MAC_VER_43:
  6884. case RTL_GIGA_MAC_VER_44:
  6885. case RTL_GIGA_MAC_VER_45:
  6886. case RTL_GIGA_MAC_VER_46:
  6887. case RTL_GIGA_MAC_VER_47:
  6888. case RTL_GIGA_MAC_VER_48:
  6889. case RTL_GIGA_MAC_VER_49:
  6890. case RTL_GIGA_MAC_VER_50:
  6891. case RTL_GIGA_MAC_VER_51:
  6892. if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
  6893. tp->features |= RTL_FEATURE_WOL;
  6894. if ((RTL_R8(Config3) & LinkUp) != 0)
  6895. tp->features |= RTL_FEATURE_WOL;
  6896. break;
  6897. default:
  6898. if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
  6899. tp->features |= RTL_FEATURE_WOL;
  6900. break;
  6901. }
  6902. if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
  6903. tp->features |= RTL_FEATURE_WOL;
  6904. tp->features |= rtl_try_msi(tp, cfg);
  6905. RTL_W8(Cfg9346, Cfg9346_Lock);
  6906. if (rtl_tbi_enabled(tp)) {
  6907. tp->set_speed = rtl8169_set_speed_tbi;
  6908. tp->get_link_ksettings = rtl8169_get_link_ksettings_tbi;
  6909. tp->phy_reset_enable = rtl8169_tbi_reset_enable;
  6910. tp->phy_reset_pending = rtl8169_tbi_reset_pending;
  6911. tp->link_ok = rtl8169_tbi_link_ok;
  6912. tp->do_ioctl = rtl_tbi_ioctl;
  6913. } else {
  6914. tp->set_speed = rtl8169_set_speed_xmii;
  6915. tp->get_link_ksettings = rtl8169_get_link_ksettings_xmii;
  6916. tp->phy_reset_enable = rtl8169_xmii_reset_enable;
  6917. tp->phy_reset_pending = rtl8169_xmii_reset_pending;
  6918. tp->link_ok = rtl8169_xmii_link_ok;
  6919. tp->do_ioctl = rtl_xmii_ioctl;
  6920. }
  6921. mutex_init(&tp->wk.mutex);
  6922. u64_stats_init(&tp->rx_stats.syncp);
  6923. u64_stats_init(&tp->tx_stats.syncp);
  6924. /* Get MAC address */
  6925. if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
  6926. tp->mac_version == RTL_GIGA_MAC_VER_36 ||
  6927. tp->mac_version == RTL_GIGA_MAC_VER_37 ||
  6928. tp->mac_version == RTL_GIGA_MAC_VER_38 ||
  6929. tp->mac_version == RTL_GIGA_MAC_VER_40 ||
  6930. tp->mac_version == RTL_GIGA_MAC_VER_41 ||
  6931. tp->mac_version == RTL_GIGA_MAC_VER_42 ||
  6932. tp->mac_version == RTL_GIGA_MAC_VER_43 ||
  6933. tp->mac_version == RTL_GIGA_MAC_VER_44 ||
  6934. tp->mac_version == RTL_GIGA_MAC_VER_45 ||
  6935. tp->mac_version == RTL_GIGA_MAC_VER_46 ||
  6936. tp->mac_version == RTL_GIGA_MAC_VER_47 ||
  6937. tp->mac_version == RTL_GIGA_MAC_VER_48 ||
  6938. tp->mac_version == RTL_GIGA_MAC_VER_49 ||
  6939. tp->mac_version == RTL_GIGA_MAC_VER_50 ||
  6940. tp->mac_version == RTL_GIGA_MAC_VER_51) {
  6941. u16 mac_addr[3];
  6942. *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
  6943. *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
  6944. if (is_valid_ether_addr((u8 *)mac_addr))
  6945. rtl_rar_set(tp, (u8 *)mac_addr);
  6946. }
  6947. for (i = 0; i < ETH_ALEN; i++)
  6948. dev->dev_addr[i] = RTL_R8(MAC0 + i);
  6949. dev->ethtool_ops = &rtl8169_ethtool_ops;
  6950. dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
  6951. netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
  6952. /* don't enable SG, IP_CSUM and TSO by default - it might not work
  6953. * properly for all devices */
  6954. dev->features |= NETIF_F_RXCSUM |
  6955. NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
  6956. dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
  6957. NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
  6958. NETIF_F_HW_VLAN_CTAG_RX;
  6959. dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
  6960. NETIF_F_HIGHDMA;
  6961. tp->cp_cmd |= RxChkSum | RxVlan;
  6962. /*
  6963. * Pretend we are using VLANs; This bypasses a nasty bug where
  6964. * Interrupts stop flowing on high load on 8110SCd controllers.
  6965. */
  6966. if (tp->mac_version == RTL_GIGA_MAC_VER_05)
  6967. /* Disallow toggling */
  6968. dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
  6969. if (tp->txd_version == RTL_TD_0)
  6970. tp->tso_csum = rtl8169_tso_csum_v1;
  6971. else if (tp->txd_version == RTL_TD_1) {
  6972. tp->tso_csum = rtl8169_tso_csum_v2;
  6973. dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
  6974. } else
  6975. WARN_ON_ONCE(1);
  6976. dev->hw_features |= NETIF_F_RXALL;
  6977. dev->hw_features |= NETIF_F_RXFCS;
  6978. /* MTU range: 60 - hw-specific max */
  6979. dev->min_mtu = ETH_ZLEN;
  6980. dev->max_mtu = rtl_chip_infos[chipset].jumbo_max;
  6981. tp->hw_start = cfg->hw_start;
  6982. tp->event_slow = cfg->event_slow;
  6983. tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
  6984. ~(RxBOVF | RxFOVF) : ~0;
  6985. setup_timer(&tp->timer, rtl8169_phy_timer, (unsigned long)dev);
  6986. tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
  6987. tp->counters = dma_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
  6988. &tp->counters_phys_addr, GFP_KERNEL);
  6989. if (!tp->counters) {
  6990. rc = -ENOMEM;
  6991. goto err_out_msi_5;
  6992. }
  6993. rc = register_netdev(dev);
  6994. if (rc < 0)
  6995. goto err_out_cnt_6;
  6996. pci_set_drvdata(pdev, dev);
  6997. netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
  6998. rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
  6999. (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
  7000. if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
  7001. netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
  7002. "tx checksumming: %s]\n",
  7003. rtl_chip_infos[chipset].jumbo_max,
  7004. rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
  7005. }
  7006. if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
  7007. tp->mac_version == RTL_GIGA_MAC_VER_28 ||
  7008. tp->mac_version == RTL_GIGA_MAC_VER_31 ||
  7009. tp->mac_version == RTL_GIGA_MAC_VER_49 ||
  7010. tp->mac_version == RTL_GIGA_MAC_VER_50 ||
  7011. tp->mac_version == RTL_GIGA_MAC_VER_51) &&
  7012. r8168_check_dash(tp)) {
  7013. rtl8168_driver_start(tp);
  7014. }
  7015. device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
  7016. if (pci_dev_run_wake(pdev))
  7017. pm_runtime_put_noidle(&pdev->dev);
  7018. netif_carrier_off(dev);
  7019. out:
  7020. return rc;
  7021. err_out_cnt_6:
  7022. dma_free_coherent(&pdev->dev, sizeof(*tp->counters), tp->counters,
  7023. tp->counters_phys_addr);
  7024. err_out_msi_5:
  7025. netif_napi_del(&tp->napi);
  7026. rtl_disable_msi(pdev, tp);
  7027. err_out_unmap_4:
  7028. iounmap(ioaddr);
  7029. err_out_free_res_3:
  7030. pci_release_regions(pdev);
  7031. err_out_mwi_2:
  7032. pci_clear_mwi(pdev);
  7033. pci_disable_device(pdev);
  7034. err_out_free_dev_1:
  7035. free_netdev(dev);
  7036. goto out;
  7037. }
  7038. static struct pci_driver rtl8169_pci_driver = {
  7039. .name = MODULENAME,
  7040. .id_table = rtl8169_pci_tbl,
  7041. .probe = rtl_init_one,
  7042. .remove = rtl_remove_one,
  7043. .shutdown = rtl_shutdown,
  7044. .driver.pm = RTL8169_PM_OPS,
  7045. };
  7046. module_pci_driver(rtl8169_pci_driver);