qed_ll2.c 64 KB

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  1. /* QLogic qed NIC Driver
  2. * Copyright (c) 2015-2017 QLogic Corporation
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and /or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/types.h>
  33. #include <asm/byteorder.h>
  34. #include <linux/dma-mapping.h>
  35. #include <linux/if_vlan.h>
  36. #include <linux/kernel.h>
  37. #include <linux/pci.h>
  38. #include <linux/slab.h>
  39. #include <linux/stddef.h>
  40. #include <linux/version.h>
  41. #include <linux/workqueue.h>
  42. #include <net/ipv6.h>
  43. #include <linux/bitops.h>
  44. #include <linux/delay.h>
  45. #include <linux/errno.h>
  46. #include <linux/etherdevice.h>
  47. #include <linux/io.h>
  48. #include <linux/list.h>
  49. #include <linux/mutex.h>
  50. #include <linux/spinlock.h>
  51. #include <linux/string.h>
  52. #include <linux/qed/qed_ll2_if.h>
  53. #include "qed.h"
  54. #include "qed_cxt.h"
  55. #include "qed_dev_api.h"
  56. #include "qed_hsi.h"
  57. #include "qed_hw.h"
  58. #include "qed_int.h"
  59. #include "qed_ll2.h"
  60. #include "qed_mcp.h"
  61. #include "qed_ooo.h"
  62. #include "qed_reg_addr.h"
  63. #include "qed_sp.h"
  64. #include "qed_roce.h"
  65. #define QED_LL2_RX_REGISTERED(ll2) ((ll2)->rx_queue.b_cb_registred)
  66. #define QED_LL2_TX_REGISTERED(ll2) ((ll2)->tx_queue.b_cb_registred)
  67. #define QED_LL2_TX_SIZE (256)
  68. #define QED_LL2_RX_SIZE (4096)
  69. struct qed_cb_ll2_info {
  70. int rx_cnt;
  71. u32 rx_size;
  72. u8 handle;
  73. bool frags_mapped;
  74. /* Lock protecting LL2 buffer lists in sleepless context */
  75. spinlock_t lock;
  76. struct list_head list;
  77. const struct qed_ll2_cb_ops *cbs;
  78. void *cb_cookie;
  79. };
  80. struct qed_ll2_buffer {
  81. struct list_head list;
  82. void *data;
  83. dma_addr_t phys_addr;
  84. };
  85. static void qed_ll2b_complete_tx_packet(struct qed_hwfn *p_hwfn,
  86. u8 connection_handle,
  87. void *cookie,
  88. dma_addr_t first_frag_addr,
  89. bool b_last_fragment,
  90. bool b_last_packet)
  91. {
  92. struct qed_dev *cdev = p_hwfn->cdev;
  93. struct sk_buff *skb = cookie;
  94. /* All we need to do is release the mapping */
  95. dma_unmap_single(&p_hwfn->cdev->pdev->dev, first_frag_addr,
  96. skb_headlen(skb), DMA_TO_DEVICE);
  97. if (cdev->ll2->cbs && cdev->ll2->cbs->tx_cb)
  98. cdev->ll2->cbs->tx_cb(cdev->ll2->cb_cookie, skb,
  99. b_last_fragment);
  100. if (cdev->ll2->frags_mapped)
  101. /* Case where mapped frags were received, need to
  102. * free skb with nr_frags marked as 0
  103. */
  104. skb_shinfo(skb)->nr_frags = 0;
  105. dev_kfree_skb_any(skb);
  106. }
  107. static int qed_ll2_alloc_buffer(struct qed_dev *cdev,
  108. u8 **data, dma_addr_t *phys_addr)
  109. {
  110. *data = kmalloc(cdev->ll2->rx_size, GFP_ATOMIC);
  111. if (!(*data)) {
  112. DP_INFO(cdev, "Failed to allocate LL2 buffer data\n");
  113. return -ENOMEM;
  114. }
  115. *phys_addr = dma_map_single(&cdev->pdev->dev,
  116. ((*data) + NET_SKB_PAD),
  117. cdev->ll2->rx_size, DMA_FROM_DEVICE);
  118. if (dma_mapping_error(&cdev->pdev->dev, *phys_addr)) {
  119. DP_INFO(cdev, "Failed to map LL2 buffer data\n");
  120. kfree((*data));
  121. return -ENOMEM;
  122. }
  123. return 0;
  124. }
  125. static int qed_ll2_dealloc_buffer(struct qed_dev *cdev,
  126. struct qed_ll2_buffer *buffer)
  127. {
  128. spin_lock_bh(&cdev->ll2->lock);
  129. dma_unmap_single(&cdev->pdev->dev, buffer->phys_addr,
  130. cdev->ll2->rx_size, DMA_FROM_DEVICE);
  131. kfree(buffer->data);
  132. list_del(&buffer->list);
  133. cdev->ll2->rx_cnt--;
  134. if (!cdev->ll2->rx_cnt)
  135. DP_INFO(cdev, "All LL2 entries were removed\n");
  136. spin_unlock_bh(&cdev->ll2->lock);
  137. return 0;
  138. }
  139. static void qed_ll2_kill_buffers(struct qed_dev *cdev)
  140. {
  141. struct qed_ll2_buffer *buffer, *tmp_buffer;
  142. list_for_each_entry_safe(buffer, tmp_buffer, &cdev->ll2->list, list)
  143. qed_ll2_dealloc_buffer(cdev, buffer);
  144. }
  145. static void qed_ll2b_complete_rx_packet(struct qed_hwfn *p_hwfn,
  146. u8 connection_handle,
  147. struct qed_ll2_rx_packet *p_pkt,
  148. struct core_rx_fast_path_cqe *p_cqe,
  149. bool b_last_packet)
  150. {
  151. u16 packet_length = le16_to_cpu(p_cqe->packet_length);
  152. struct qed_ll2_buffer *buffer = p_pkt->cookie;
  153. struct qed_dev *cdev = p_hwfn->cdev;
  154. u16 vlan = le16_to_cpu(p_cqe->vlan);
  155. u32 opaque_data_0, opaque_data_1;
  156. u8 pad = p_cqe->placement_offset;
  157. dma_addr_t new_phys_addr;
  158. struct sk_buff *skb;
  159. bool reuse = false;
  160. int rc = -EINVAL;
  161. u8 *new_data;
  162. opaque_data_0 = le32_to_cpu(p_cqe->opaque_data.data[0]);
  163. opaque_data_1 = le32_to_cpu(p_cqe->opaque_data.data[1]);
  164. DP_VERBOSE(p_hwfn,
  165. (NETIF_MSG_RX_STATUS | QED_MSG_STORAGE | NETIF_MSG_PKTDATA),
  166. "Got an LL2 Rx completion: [Buffer at phys 0x%llx, offset 0x%02x] Length 0x%04x Parse_flags 0x%04x vlan 0x%04x Opaque data [0x%08x:0x%08x]\n",
  167. (u64)p_pkt->rx_buf_addr, pad, packet_length,
  168. le16_to_cpu(p_cqe->parse_flags.flags), vlan,
  169. opaque_data_0, opaque_data_1);
  170. if ((cdev->dp_module & NETIF_MSG_PKTDATA) && buffer->data) {
  171. print_hex_dump(KERN_INFO, "",
  172. DUMP_PREFIX_OFFSET, 16, 1,
  173. buffer->data, packet_length, false);
  174. }
  175. /* Determine if data is valid */
  176. if (packet_length < ETH_HLEN)
  177. reuse = true;
  178. /* Allocate a replacement for buffer; Reuse upon failure */
  179. if (!reuse)
  180. rc = qed_ll2_alloc_buffer(p_hwfn->cdev, &new_data,
  181. &new_phys_addr);
  182. /* If need to reuse or there's no replacement buffer, repost this */
  183. if (rc)
  184. goto out_post;
  185. dma_unmap_single(&cdev->pdev->dev, buffer->phys_addr,
  186. cdev->ll2->rx_size, DMA_FROM_DEVICE);
  187. skb = build_skb(buffer->data, 0);
  188. if (!skb) {
  189. rc = -ENOMEM;
  190. goto out_post;
  191. }
  192. pad += NET_SKB_PAD;
  193. skb_reserve(skb, pad);
  194. skb_put(skb, packet_length);
  195. skb_checksum_none_assert(skb);
  196. /* Get parital ethernet information instead of eth_type_trans(),
  197. * Since we don't have an associated net_device.
  198. */
  199. skb_reset_mac_header(skb);
  200. skb->protocol = eth_hdr(skb)->h_proto;
  201. /* Pass SKB onward */
  202. if (cdev->ll2->cbs && cdev->ll2->cbs->rx_cb) {
  203. if (vlan)
  204. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan);
  205. cdev->ll2->cbs->rx_cb(cdev->ll2->cb_cookie, skb,
  206. opaque_data_0, opaque_data_1);
  207. }
  208. /* Update Buffer information and update FW producer */
  209. buffer->data = new_data;
  210. buffer->phys_addr = new_phys_addr;
  211. out_post:
  212. rc = qed_ll2_post_rx_buffer(QED_LEADING_HWFN(cdev), cdev->ll2->handle,
  213. buffer->phys_addr, 0, buffer, 1);
  214. if (rc)
  215. qed_ll2_dealloc_buffer(cdev, buffer);
  216. }
  217. static struct qed_ll2_info *__qed_ll2_handle_sanity(struct qed_hwfn *p_hwfn,
  218. u8 connection_handle,
  219. bool b_lock,
  220. bool b_only_active)
  221. {
  222. struct qed_ll2_info *p_ll2_conn, *p_ret = NULL;
  223. if (connection_handle >= QED_MAX_NUM_OF_LL2_CONNECTIONS)
  224. return NULL;
  225. if (!p_hwfn->p_ll2_info)
  226. return NULL;
  227. p_ll2_conn = &p_hwfn->p_ll2_info[connection_handle];
  228. if (b_only_active) {
  229. if (b_lock)
  230. mutex_lock(&p_ll2_conn->mutex);
  231. if (p_ll2_conn->b_active)
  232. p_ret = p_ll2_conn;
  233. if (b_lock)
  234. mutex_unlock(&p_ll2_conn->mutex);
  235. } else {
  236. p_ret = p_ll2_conn;
  237. }
  238. return p_ret;
  239. }
  240. static struct qed_ll2_info *qed_ll2_handle_sanity(struct qed_hwfn *p_hwfn,
  241. u8 connection_handle)
  242. {
  243. return __qed_ll2_handle_sanity(p_hwfn, connection_handle, false, true);
  244. }
  245. static struct qed_ll2_info *qed_ll2_handle_sanity_lock(struct qed_hwfn *p_hwfn,
  246. u8 connection_handle)
  247. {
  248. return __qed_ll2_handle_sanity(p_hwfn, connection_handle, true, true);
  249. }
  250. static struct qed_ll2_info *qed_ll2_handle_sanity_inactive(struct qed_hwfn
  251. *p_hwfn,
  252. u8 connection_handle)
  253. {
  254. return __qed_ll2_handle_sanity(p_hwfn, connection_handle, false, false);
  255. }
  256. static void qed_ll2_txq_flush(struct qed_hwfn *p_hwfn, u8 connection_handle)
  257. {
  258. bool b_last_packet = false, b_last_frag = false;
  259. struct qed_ll2_tx_packet *p_pkt = NULL;
  260. struct qed_ll2_info *p_ll2_conn;
  261. struct qed_ll2_tx_queue *p_tx;
  262. dma_addr_t tx_frag;
  263. p_ll2_conn = qed_ll2_handle_sanity_inactive(p_hwfn, connection_handle);
  264. if (!p_ll2_conn)
  265. return;
  266. p_tx = &p_ll2_conn->tx_queue;
  267. while (!list_empty(&p_tx->active_descq)) {
  268. p_pkt = list_first_entry(&p_tx->active_descq,
  269. struct qed_ll2_tx_packet, list_entry);
  270. if (!p_pkt)
  271. break;
  272. list_del(&p_pkt->list_entry);
  273. b_last_packet = list_empty(&p_tx->active_descq);
  274. list_add_tail(&p_pkt->list_entry, &p_tx->free_descq);
  275. if (p_ll2_conn->conn.conn_type == QED_LL2_TYPE_ISCSI_OOO) {
  276. struct qed_ooo_buffer *p_buffer;
  277. p_buffer = (struct qed_ooo_buffer *)p_pkt->cookie;
  278. qed_ooo_put_free_buffer(p_hwfn, p_hwfn->p_ooo_info,
  279. p_buffer);
  280. } else {
  281. p_tx->cur_completing_packet = *p_pkt;
  282. p_tx->cur_completing_bd_idx = 1;
  283. b_last_frag =
  284. p_tx->cur_completing_bd_idx == p_pkt->bd_used;
  285. tx_frag = p_pkt->bds_set[0].tx_frag;
  286. if (p_ll2_conn->conn.gsi_enable)
  287. qed_ll2b_release_tx_gsi_packet(p_hwfn,
  288. p_ll2_conn->
  289. my_id,
  290. p_pkt->cookie,
  291. tx_frag,
  292. b_last_frag,
  293. b_last_packet);
  294. else
  295. qed_ll2b_complete_tx_packet(p_hwfn,
  296. p_ll2_conn->my_id,
  297. p_pkt->cookie,
  298. tx_frag,
  299. b_last_frag,
  300. b_last_packet);
  301. }
  302. }
  303. }
  304. static int qed_ll2_txq_completion(struct qed_hwfn *p_hwfn, void *p_cookie)
  305. {
  306. struct qed_ll2_info *p_ll2_conn = p_cookie;
  307. struct qed_ll2_tx_queue *p_tx = &p_ll2_conn->tx_queue;
  308. u16 new_idx = 0, num_bds = 0, num_bds_in_packet = 0;
  309. struct qed_ll2_tx_packet *p_pkt;
  310. bool b_last_frag = false;
  311. unsigned long flags;
  312. dma_addr_t tx_frag;
  313. int rc = -EINVAL;
  314. spin_lock_irqsave(&p_tx->lock, flags);
  315. if (p_tx->b_completing_packet) {
  316. rc = -EBUSY;
  317. goto out;
  318. }
  319. new_idx = le16_to_cpu(*p_tx->p_fw_cons);
  320. num_bds = ((s16)new_idx - (s16)p_tx->bds_idx);
  321. while (num_bds) {
  322. if (list_empty(&p_tx->active_descq))
  323. goto out;
  324. p_pkt = list_first_entry(&p_tx->active_descq,
  325. struct qed_ll2_tx_packet, list_entry);
  326. if (!p_pkt)
  327. goto out;
  328. p_tx->b_completing_packet = true;
  329. p_tx->cur_completing_packet = *p_pkt;
  330. num_bds_in_packet = p_pkt->bd_used;
  331. list_del(&p_pkt->list_entry);
  332. if (num_bds < num_bds_in_packet) {
  333. DP_NOTICE(p_hwfn,
  334. "Rest of BDs does not cover whole packet\n");
  335. goto out;
  336. }
  337. num_bds -= num_bds_in_packet;
  338. p_tx->bds_idx += num_bds_in_packet;
  339. while (num_bds_in_packet--)
  340. qed_chain_consume(&p_tx->txq_chain);
  341. p_tx->cur_completing_bd_idx = 1;
  342. b_last_frag = p_tx->cur_completing_bd_idx == p_pkt->bd_used;
  343. list_add_tail(&p_pkt->list_entry, &p_tx->free_descq);
  344. spin_unlock_irqrestore(&p_tx->lock, flags);
  345. tx_frag = p_pkt->bds_set[0].tx_frag;
  346. if (p_ll2_conn->conn.gsi_enable)
  347. qed_ll2b_complete_tx_gsi_packet(p_hwfn,
  348. p_ll2_conn->my_id,
  349. p_pkt->cookie,
  350. tx_frag,
  351. b_last_frag, !num_bds);
  352. else
  353. qed_ll2b_complete_tx_packet(p_hwfn,
  354. p_ll2_conn->my_id,
  355. p_pkt->cookie,
  356. tx_frag,
  357. b_last_frag, !num_bds);
  358. spin_lock_irqsave(&p_tx->lock, flags);
  359. }
  360. p_tx->b_completing_packet = false;
  361. rc = 0;
  362. out:
  363. spin_unlock_irqrestore(&p_tx->lock, flags);
  364. return rc;
  365. }
  366. static int
  367. qed_ll2_rxq_completion_gsi(struct qed_hwfn *p_hwfn,
  368. struct qed_ll2_info *p_ll2_info,
  369. union core_rx_cqe_union *p_cqe,
  370. unsigned long lock_flags, bool b_last_cqe)
  371. {
  372. struct qed_ll2_rx_queue *p_rx = &p_ll2_info->rx_queue;
  373. struct qed_ll2_rx_packet *p_pkt = NULL;
  374. u16 packet_length, parse_flags, vlan;
  375. u32 src_mac_addrhi;
  376. u16 src_mac_addrlo;
  377. if (!list_empty(&p_rx->active_descq))
  378. p_pkt = list_first_entry(&p_rx->active_descq,
  379. struct qed_ll2_rx_packet, list_entry);
  380. if (!p_pkt) {
  381. DP_NOTICE(p_hwfn,
  382. "GSI Rx completion but active_descq is empty\n");
  383. return -EIO;
  384. }
  385. list_del(&p_pkt->list_entry);
  386. parse_flags = le16_to_cpu(p_cqe->rx_cqe_gsi.parse_flags.flags);
  387. packet_length = le16_to_cpu(p_cqe->rx_cqe_gsi.data_length);
  388. vlan = le16_to_cpu(p_cqe->rx_cqe_gsi.vlan);
  389. src_mac_addrhi = le32_to_cpu(p_cqe->rx_cqe_gsi.src_mac_addrhi);
  390. src_mac_addrlo = le16_to_cpu(p_cqe->rx_cqe_gsi.src_mac_addrlo);
  391. if (qed_chain_consume(&p_rx->rxq_chain) != p_pkt->rxq_bd)
  392. DP_NOTICE(p_hwfn,
  393. "Mismatch between active_descq and the LL2 Rx chain\n");
  394. list_add_tail(&p_pkt->list_entry, &p_rx->free_descq);
  395. spin_unlock_irqrestore(&p_rx->lock, lock_flags);
  396. qed_ll2b_complete_rx_gsi_packet(p_hwfn,
  397. p_ll2_info->my_id,
  398. p_pkt->cookie,
  399. p_pkt->rx_buf_addr,
  400. packet_length,
  401. p_cqe->rx_cqe_gsi.data_length_error,
  402. parse_flags,
  403. vlan,
  404. src_mac_addrhi,
  405. src_mac_addrlo, b_last_cqe);
  406. spin_lock_irqsave(&p_rx->lock, lock_flags);
  407. return 0;
  408. }
  409. static int qed_ll2_rxq_completion_reg(struct qed_hwfn *p_hwfn,
  410. struct qed_ll2_info *p_ll2_conn,
  411. union core_rx_cqe_union *p_cqe,
  412. unsigned long *p_lock_flags,
  413. bool b_last_cqe)
  414. {
  415. struct qed_ll2_rx_queue *p_rx = &p_ll2_conn->rx_queue;
  416. struct qed_ll2_rx_packet *p_pkt = NULL;
  417. if (!list_empty(&p_rx->active_descq))
  418. p_pkt = list_first_entry(&p_rx->active_descq,
  419. struct qed_ll2_rx_packet, list_entry);
  420. if (!p_pkt) {
  421. DP_NOTICE(p_hwfn,
  422. "LL2 Rx completion but active_descq is empty\n");
  423. return -EIO;
  424. }
  425. list_del(&p_pkt->list_entry);
  426. if (qed_chain_consume(&p_rx->rxq_chain) != p_pkt->rxq_bd)
  427. DP_NOTICE(p_hwfn,
  428. "Mismatch between active_descq and the LL2 Rx chain\n");
  429. list_add_tail(&p_pkt->list_entry, &p_rx->free_descq);
  430. spin_unlock_irqrestore(&p_rx->lock, *p_lock_flags);
  431. qed_ll2b_complete_rx_packet(p_hwfn, p_ll2_conn->my_id,
  432. p_pkt, &p_cqe->rx_cqe_fp, b_last_cqe);
  433. spin_lock_irqsave(&p_rx->lock, *p_lock_flags);
  434. return 0;
  435. }
  436. static int qed_ll2_rxq_completion(struct qed_hwfn *p_hwfn, void *cookie)
  437. {
  438. struct qed_ll2_info *p_ll2_conn = cookie;
  439. struct qed_ll2_rx_queue *p_rx = &p_ll2_conn->rx_queue;
  440. union core_rx_cqe_union *cqe = NULL;
  441. u16 cq_new_idx = 0, cq_old_idx = 0;
  442. unsigned long flags = 0;
  443. int rc = 0;
  444. spin_lock_irqsave(&p_rx->lock, flags);
  445. cq_new_idx = le16_to_cpu(*p_rx->p_fw_cons);
  446. cq_old_idx = qed_chain_get_cons_idx(&p_rx->rcq_chain);
  447. while (cq_new_idx != cq_old_idx) {
  448. bool b_last_cqe = (cq_new_idx == cq_old_idx);
  449. cqe = qed_chain_consume(&p_rx->rcq_chain);
  450. cq_old_idx = qed_chain_get_cons_idx(&p_rx->rcq_chain);
  451. DP_VERBOSE(p_hwfn,
  452. QED_MSG_LL2,
  453. "LL2 [sw. cons %04x, fw. at %04x] - Got Packet of type %02x\n",
  454. cq_old_idx, cq_new_idx, cqe->rx_cqe_sp.type);
  455. switch (cqe->rx_cqe_sp.type) {
  456. case CORE_RX_CQE_TYPE_SLOW_PATH:
  457. DP_NOTICE(p_hwfn, "LL2 - unexpected Rx CQE slowpath\n");
  458. rc = -EINVAL;
  459. break;
  460. case CORE_RX_CQE_TYPE_GSI_OFFLOAD:
  461. rc = qed_ll2_rxq_completion_gsi(p_hwfn, p_ll2_conn,
  462. cqe, flags, b_last_cqe);
  463. break;
  464. case CORE_RX_CQE_TYPE_REGULAR:
  465. rc = qed_ll2_rxq_completion_reg(p_hwfn, p_ll2_conn,
  466. cqe, &flags,
  467. b_last_cqe);
  468. break;
  469. default:
  470. rc = -EIO;
  471. }
  472. }
  473. spin_unlock_irqrestore(&p_rx->lock, flags);
  474. return rc;
  475. }
  476. static void qed_ll2_rxq_flush(struct qed_hwfn *p_hwfn, u8 connection_handle)
  477. {
  478. struct qed_ll2_info *p_ll2_conn = NULL;
  479. struct qed_ll2_rx_packet *p_pkt = NULL;
  480. struct qed_ll2_rx_queue *p_rx;
  481. p_ll2_conn = qed_ll2_handle_sanity_inactive(p_hwfn, connection_handle);
  482. if (!p_ll2_conn)
  483. return;
  484. p_rx = &p_ll2_conn->rx_queue;
  485. while (!list_empty(&p_rx->active_descq)) {
  486. dma_addr_t rx_buf_addr;
  487. void *cookie;
  488. bool b_last;
  489. p_pkt = list_first_entry(&p_rx->active_descq,
  490. struct qed_ll2_rx_packet, list_entry);
  491. if (!p_pkt)
  492. break;
  493. list_move_tail(&p_pkt->list_entry, &p_rx->free_descq);
  494. if (p_ll2_conn->conn.conn_type == QED_LL2_TYPE_ISCSI_OOO) {
  495. struct qed_ooo_buffer *p_buffer;
  496. p_buffer = (struct qed_ooo_buffer *)p_pkt->cookie;
  497. qed_ooo_put_free_buffer(p_hwfn, p_hwfn->p_ooo_info,
  498. p_buffer);
  499. } else {
  500. rx_buf_addr = p_pkt->rx_buf_addr;
  501. cookie = p_pkt->cookie;
  502. b_last = list_empty(&p_rx->active_descq);
  503. }
  504. }
  505. }
  506. #if IS_ENABLED(CONFIG_QED_ISCSI)
  507. static u8 qed_ll2_convert_rx_parse_to_tx_flags(u16 parse_flags)
  508. {
  509. u8 bd_flags = 0;
  510. if (GET_FIELD(parse_flags, PARSING_AND_ERR_FLAGS_TAG8021QEXIST))
  511. SET_FIELD(bd_flags, CORE_TX_BD_DATA_VLAN_INSERTION, 1);
  512. return bd_flags;
  513. }
  514. static int qed_ll2_lb_rxq_handler(struct qed_hwfn *p_hwfn,
  515. struct qed_ll2_info *p_ll2_conn)
  516. {
  517. struct qed_ll2_rx_queue *p_rx = &p_ll2_conn->rx_queue;
  518. u16 packet_length = 0, parse_flags = 0, vlan = 0;
  519. struct qed_ll2_rx_packet *p_pkt = NULL;
  520. u32 num_ooo_add_to_peninsula = 0, cid;
  521. union core_rx_cqe_union *cqe = NULL;
  522. u16 cq_new_idx = 0, cq_old_idx = 0;
  523. struct qed_ooo_buffer *p_buffer;
  524. struct ooo_opaque *iscsi_ooo;
  525. u8 placement_offset = 0;
  526. u8 cqe_type;
  527. cq_new_idx = le16_to_cpu(*p_rx->p_fw_cons);
  528. cq_old_idx = qed_chain_get_cons_idx(&p_rx->rcq_chain);
  529. if (cq_new_idx == cq_old_idx)
  530. return 0;
  531. while (cq_new_idx != cq_old_idx) {
  532. struct core_rx_fast_path_cqe *p_cqe_fp;
  533. cqe = qed_chain_consume(&p_rx->rcq_chain);
  534. cq_old_idx = qed_chain_get_cons_idx(&p_rx->rcq_chain);
  535. cqe_type = cqe->rx_cqe_sp.type;
  536. if (cqe_type != CORE_RX_CQE_TYPE_REGULAR) {
  537. DP_NOTICE(p_hwfn,
  538. "Got a non-regular LB LL2 completion [type 0x%02x]\n",
  539. cqe_type);
  540. return -EINVAL;
  541. }
  542. p_cqe_fp = &cqe->rx_cqe_fp;
  543. placement_offset = p_cqe_fp->placement_offset;
  544. parse_flags = le16_to_cpu(p_cqe_fp->parse_flags.flags);
  545. packet_length = le16_to_cpu(p_cqe_fp->packet_length);
  546. vlan = le16_to_cpu(p_cqe_fp->vlan);
  547. iscsi_ooo = (struct ooo_opaque *)&p_cqe_fp->opaque_data;
  548. qed_ooo_save_history_entry(p_hwfn, p_hwfn->p_ooo_info,
  549. iscsi_ooo);
  550. cid = le32_to_cpu(iscsi_ooo->cid);
  551. /* Process delete isle first */
  552. if (iscsi_ooo->drop_size)
  553. qed_ooo_delete_isles(p_hwfn, p_hwfn->p_ooo_info, cid,
  554. iscsi_ooo->drop_isle,
  555. iscsi_ooo->drop_size);
  556. if (iscsi_ooo->ooo_opcode == TCP_EVENT_NOP)
  557. continue;
  558. /* Now process create/add/join isles */
  559. if (list_empty(&p_rx->active_descq)) {
  560. DP_NOTICE(p_hwfn,
  561. "LL2 OOO RX chain has no submitted buffers\n"
  562. );
  563. return -EIO;
  564. }
  565. p_pkt = list_first_entry(&p_rx->active_descq,
  566. struct qed_ll2_rx_packet, list_entry);
  567. if ((iscsi_ooo->ooo_opcode == TCP_EVENT_ADD_NEW_ISLE) ||
  568. (iscsi_ooo->ooo_opcode == TCP_EVENT_ADD_ISLE_RIGHT) ||
  569. (iscsi_ooo->ooo_opcode == TCP_EVENT_ADD_ISLE_LEFT) ||
  570. (iscsi_ooo->ooo_opcode == TCP_EVENT_ADD_PEN) ||
  571. (iscsi_ooo->ooo_opcode == TCP_EVENT_JOIN)) {
  572. if (!p_pkt) {
  573. DP_NOTICE(p_hwfn,
  574. "LL2 OOO RX packet is not valid\n");
  575. return -EIO;
  576. }
  577. list_del(&p_pkt->list_entry);
  578. p_buffer = (struct qed_ooo_buffer *)p_pkt->cookie;
  579. p_buffer->packet_length = packet_length;
  580. p_buffer->parse_flags = parse_flags;
  581. p_buffer->vlan = vlan;
  582. p_buffer->placement_offset = placement_offset;
  583. qed_chain_consume(&p_rx->rxq_chain);
  584. list_add_tail(&p_pkt->list_entry, &p_rx->free_descq);
  585. switch (iscsi_ooo->ooo_opcode) {
  586. case TCP_EVENT_ADD_NEW_ISLE:
  587. qed_ooo_add_new_isle(p_hwfn,
  588. p_hwfn->p_ooo_info,
  589. cid,
  590. iscsi_ooo->ooo_isle,
  591. p_buffer);
  592. break;
  593. case TCP_EVENT_ADD_ISLE_RIGHT:
  594. qed_ooo_add_new_buffer(p_hwfn,
  595. p_hwfn->p_ooo_info,
  596. cid,
  597. iscsi_ooo->ooo_isle,
  598. p_buffer,
  599. QED_OOO_RIGHT_BUF);
  600. break;
  601. case TCP_EVENT_ADD_ISLE_LEFT:
  602. qed_ooo_add_new_buffer(p_hwfn,
  603. p_hwfn->p_ooo_info,
  604. cid,
  605. iscsi_ooo->ooo_isle,
  606. p_buffer,
  607. QED_OOO_LEFT_BUF);
  608. break;
  609. case TCP_EVENT_JOIN:
  610. qed_ooo_add_new_buffer(p_hwfn,
  611. p_hwfn->p_ooo_info,
  612. cid,
  613. iscsi_ooo->ooo_isle +
  614. 1,
  615. p_buffer,
  616. QED_OOO_LEFT_BUF);
  617. qed_ooo_join_isles(p_hwfn,
  618. p_hwfn->p_ooo_info,
  619. cid, iscsi_ooo->ooo_isle);
  620. break;
  621. case TCP_EVENT_ADD_PEN:
  622. num_ooo_add_to_peninsula++;
  623. qed_ooo_put_ready_buffer(p_hwfn,
  624. p_hwfn->p_ooo_info,
  625. p_buffer, true);
  626. break;
  627. }
  628. } else {
  629. DP_NOTICE(p_hwfn,
  630. "Unexpected event (%d) TX OOO completion\n",
  631. iscsi_ooo->ooo_opcode);
  632. }
  633. }
  634. return 0;
  635. }
  636. static void
  637. qed_ooo_submit_tx_buffers(struct qed_hwfn *p_hwfn,
  638. struct qed_ll2_info *p_ll2_conn)
  639. {
  640. struct qed_ooo_buffer *p_buffer;
  641. int rc;
  642. u16 l4_hdr_offset_w;
  643. dma_addr_t first_frag;
  644. u16 parse_flags;
  645. u8 bd_flags;
  646. /* Submit Tx buffers here */
  647. while ((p_buffer = qed_ooo_get_ready_buffer(p_hwfn,
  648. p_hwfn->p_ooo_info))) {
  649. l4_hdr_offset_w = 0;
  650. bd_flags = 0;
  651. first_frag = p_buffer->rx_buffer_phys_addr +
  652. p_buffer->placement_offset;
  653. parse_flags = p_buffer->parse_flags;
  654. bd_flags = qed_ll2_convert_rx_parse_to_tx_flags(parse_flags);
  655. SET_FIELD(bd_flags, CORE_TX_BD_DATA_FORCE_VLAN_MODE, 1);
  656. SET_FIELD(bd_flags, CORE_TX_BD_DATA_L4_PROTOCOL, 1);
  657. rc = qed_ll2_prepare_tx_packet(p_hwfn, p_ll2_conn->my_id, 1,
  658. p_buffer->vlan, bd_flags,
  659. l4_hdr_offset_w,
  660. p_ll2_conn->conn.tx_dest, 0,
  661. first_frag,
  662. p_buffer->packet_length,
  663. p_buffer, true);
  664. if (rc) {
  665. qed_ooo_put_ready_buffer(p_hwfn, p_hwfn->p_ooo_info,
  666. p_buffer, false);
  667. break;
  668. }
  669. }
  670. }
  671. static void
  672. qed_ooo_submit_rx_buffers(struct qed_hwfn *p_hwfn,
  673. struct qed_ll2_info *p_ll2_conn)
  674. {
  675. struct qed_ooo_buffer *p_buffer;
  676. int rc;
  677. while ((p_buffer = qed_ooo_get_free_buffer(p_hwfn,
  678. p_hwfn->p_ooo_info))) {
  679. rc = qed_ll2_post_rx_buffer(p_hwfn,
  680. p_ll2_conn->my_id,
  681. p_buffer->rx_buffer_phys_addr,
  682. 0, p_buffer, true);
  683. if (rc) {
  684. qed_ooo_put_free_buffer(p_hwfn,
  685. p_hwfn->p_ooo_info, p_buffer);
  686. break;
  687. }
  688. }
  689. }
  690. static int qed_ll2_lb_rxq_completion(struct qed_hwfn *p_hwfn, void *p_cookie)
  691. {
  692. struct qed_ll2_info *p_ll2_conn = (struct qed_ll2_info *)p_cookie;
  693. int rc;
  694. rc = qed_ll2_lb_rxq_handler(p_hwfn, p_ll2_conn);
  695. if (rc)
  696. return rc;
  697. qed_ooo_submit_rx_buffers(p_hwfn, p_ll2_conn);
  698. qed_ooo_submit_tx_buffers(p_hwfn, p_ll2_conn);
  699. return 0;
  700. }
  701. static int qed_ll2_lb_txq_completion(struct qed_hwfn *p_hwfn, void *p_cookie)
  702. {
  703. struct qed_ll2_info *p_ll2_conn = (struct qed_ll2_info *)p_cookie;
  704. struct qed_ll2_tx_queue *p_tx = &p_ll2_conn->tx_queue;
  705. struct qed_ll2_tx_packet *p_pkt = NULL;
  706. struct qed_ooo_buffer *p_buffer;
  707. bool b_dont_submit_rx = false;
  708. u16 new_idx = 0, num_bds = 0;
  709. int rc;
  710. new_idx = le16_to_cpu(*p_tx->p_fw_cons);
  711. num_bds = ((s16)new_idx - (s16)p_tx->bds_idx);
  712. if (!num_bds)
  713. return 0;
  714. while (num_bds) {
  715. if (list_empty(&p_tx->active_descq))
  716. return -EINVAL;
  717. p_pkt = list_first_entry(&p_tx->active_descq,
  718. struct qed_ll2_tx_packet, list_entry);
  719. if (!p_pkt)
  720. return -EINVAL;
  721. if (p_pkt->bd_used != 1) {
  722. DP_NOTICE(p_hwfn,
  723. "Unexpectedly many BDs(%d) in TX OOO completion\n",
  724. p_pkt->bd_used);
  725. return -EINVAL;
  726. }
  727. list_del(&p_pkt->list_entry);
  728. num_bds--;
  729. p_tx->bds_idx++;
  730. qed_chain_consume(&p_tx->txq_chain);
  731. p_buffer = (struct qed_ooo_buffer *)p_pkt->cookie;
  732. list_add_tail(&p_pkt->list_entry, &p_tx->free_descq);
  733. if (b_dont_submit_rx) {
  734. qed_ooo_put_free_buffer(p_hwfn, p_hwfn->p_ooo_info,
  735. p_buffer);
  736. continue;
  737. }
  738. rc = qed_ll2_post_rx_buffer(p_hwfn, p_ll2_conn->my_id,
  739. p_buffer->rx_buffer_phys_addr, 0,
  740. p_buffer, true);
  741. if (rc != 0) {
  742. qed_ooo_put_free_buffer(p_hwfn,
  743. p_hwfn->p_ooo_info, p_buffer);
  744. b_dont_submit_rx = true;
  745. }
  746. }
  747. qed_ooo_submit_tx_buffers(p_hwfn, p_ll2_conn);
  748. return 0;
  749. }
  750. static int
  751. qed_ll2_acquire_connection_ooo(struct qed_hwfn *p_hwfn,
  752. struct qed_ll2_info *p_ll2_info,
  753. u16 rx_num_ooo_buffers, u16 mtu)
  754. {
  755. struct qed_ooo_buffer *p_buf = NULL;
  756. void *p_virt;
  757. u16 buf_idx;
  758. int rc = 0;
  759. if (p_ll2_info->conn.conn_type != QED_LL2_TYPE_ISCSI_OOO)
  760. return rc;
  761. if (!rx_num_ooo_buffers)
  762. return -EINVAL;
  763. for (buf_idx = 0; buf_idx < rx_num_ooo_buffers; buf_idx++) {
  764. p_buf = kzalloc(sizeof(*p_buf), GFP_KERNEL);
  765. if (!p_buf) {
  766. rc = -ENOMEM;
  767. goto out;
  768. }
  769. p_buf->rx_buffer_size = mtu + 26 + ETH_CACHE_LINE_SIZE;
  770. p_buf->rx_buffer_size = (p_buf->rx_buffer_size +
  771. ETH_CACHE_LINE_SIZE - 1) &
  772. ~(ETH_CACHE_LINE_SIZE - 1);
  773. p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
  774. p_buf->rx_buffer_size,
  775. &p_buf->rx_buffer_phys_addr,
  776. GFP_KERNEL);
  777. if (!p_virt) {
  778. kfree(p_buf);
  779. rc = -ENOMEM;
  780. goto out;
  781. }
  782. p_buf->rx_buffer_virt_addr = p_virt;
  783. qed_ooo_put_free_buffer(p_hwfn, p_hwfn->p_ooo_info, p_buf);
  784. }
  785. DP_VERBOSE(p_hwfn, QED_MSG_LL2,
  786. "Allocated [%04x] LL2 OOO buffers [each of size 0x%08x]\n",
  787. rx_num_ooo_buffers, p_buf->rx_buffer_size);
  788. out:
  789. return rc;
  790. }
  791. static void
  792. qed_ll2_establish_connection_ooo(struct qed_hwfn *p_hwfn,
  793. struct qed_ll2_info *p_ll2_conn)
  794. {
  795. if (p_ll2_conn->conn.conn_type != QED_LL2_TYPE_ISCSI_OOO)
  796. return;
  797. qed_ooo_release_all_isles(p_hwfn, p_hwfn->p_ooo_info);
  798. qed_ooo_submit_rx_buffers(p_hwfn, p_ll2_conn);
  799. }
  800. static void qed_ll2_release_connection_ooo(struct qed_hwfn *p_hwfn,
  801. struct qed_ll2_info *p_ll2_conn)
  802. {
  803. struct qed_ooo_buffer *p_buffer;
  804. if (p_ll2_conn->conn.conn_type != QED_LL2_TYPE_ISCSI_OOO)
  805. return;
  806. qed_ooo_release_all_isles(p_hwfn, p_hwfn->p_ooo_info);
  807. while ((p_buffer = qed_ooo_get_free_buffer(p_hwfn,
  808. p_hwfn->p_ooo_info))) {
  809. dma_free_coherent(&p_hwfn->cdev->pdev->dev,
  810. p_buffer->rx_buffer_size,
  811. p_buffer->rx_buffer_virt_addr,
  812. p_buffer->rx_buffer_phys_addr);
  813. kfree(p_buffer);
  814. }
  815. }
  816. static void qed_ll2_stop_ooo(struct qed_dev *cdev)
  817. {
  818. struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
  819. u8 *handle = &hwfn->pf_params.iscsi_pf_params.ll2_ooo_queue_id;
  820. DP_VERBOSE(cdev, QED_MSG_STORAGE, "Stopping LL2 OOO queue [%02x]\n",
  821. *handle);
  822. qed_ll2_terminate_connection(hwfn, *handle);
  823. qed_ll2_release_connection(hwfn, *handle);
  824. *handle = QED_LL2_UNUSED_HANDLE;
  825. }
  826. static int qed_ll2_start_ooo(struct qed_dev *cdev,
  827. struct qed_ll2_params *params)
  828. {
  829. struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
  830. u8 *handle = &hwfn->pf_params.iscsi_pf_params.ll2_ooo_queue_id;
  831. struct qed_ll2_conn ll2_info = { 0 };
  832. int rc;
  833. ll2_info.conn_type = QED_LL2_TYPE_ISCSI_OOO;
  834. ll2_info.mtu = params->mtu;
  835. ll2_info.rx_drop_ttl0_flg = params->drop_ttl0_packets;
  836. ll2_info.rx_vlan_removal_en = params->rx_vlan_stripping;
  837. ll2_info.tx_tc = OOO_LB_TC;
  838. ll2_info.tx_dest = CORE_TX_DEST_LB;
  839. rc = qed_ll2_acquire_connection(hwfn, &ll2_info,
  840. QED_LL2_RX_SIZE, QED_LL2_TX_SIZE,
  841. handle);
  842. if (rc) {
  843. DP_INFO(cdev, "Failed to acquire LL2 OOO connection\n");
  844. goto out;
  845. }
  846. rc = qed_ll2_establish_connection(hwfn, *handle);
  847. if (rc) {
  848. DP_INFO(cdev, "Failed to establist LL2 OOO connection\n");
  849. goto fail;
  850. }
  851. return 0;
  852. fail:
  853. qed_ll2_release_connection(hwfn, *handle);
  854. out:
  855. *handle = QED_LL2_UNUSED_HANDLE;
  856. return rc;
  857. }
  858. #else /* IS_ENABLED(CONFIG_QED_ISCSI) */
  859. static int qed_ll2_lb_rxq_completion(struct qed_hwfn *p_hwfn,
  860. void *p_cookie) { return -EINVAL; }
  861. static int qed_ll2_lb_txq_completion(struct qed_hwfn *p_hwfn,
  862. void *p_cookie) { return -EINVAL; }
  863. static inline int
  864. qed_ll2_acquire_connection_ooo(struct qed_hwfn *p_hwfn,
  865. struct qed_ll2_info *p_ll2_info,
  866. u16 rx_num_ooo_buffers, u16 mtu) { return 0; }
  867. static inline void
  868. qed_ll2_establish_connection_ooo(struct qed_hwfn *p_hwfn,
  869. struct qed_ll2_info *p_ll2_conn) { return; }
  870. static inline void
  871. qed_ll2_release_connection_ooo(struct qed_hwfn *p_hwfn,
  872. struct qed_ll2_info *p_ll2_conn) { return; }
  873. static inline void qed_ll2_stop_ooo(struct qed_dev *cdev) { return; }
  874. static inline int qed_ll2_start_ooo(struct qed_dev *cdev,
  875. struct qed_ll2_params *params)
  876. { return -EINVAL; }
  877. #endif /* IS_ENABLED(CONFIG_QED_ISCSI) */
  878. static int qed_sp_ll2_rx_queue_start(struct qed_hwfn *p_hwfn,
  879. struct qed_ll2_info *p_ll2_conn,
  880. u8 action_on_error)
  881. {
  882. enum qed_ll2_conn_type conn_type = p_ll2_conn->conn.conn_type;
  883. struct qed_ll2_rx_queue *p_rx = &p_ll2_conn->rx_queue;
  884. struct core_rx_start_ramrod_data *p_ramrod = NULL;
  885. struct qed_spq_entry *p_ent = NULL;
  886. struct qed_sp_init_data init_data;
  887. u16 cqe_pbl_size;
  888. int rc = 0;
  889. /* Get SPQ entry */
  890. memset(&init_data, 0, sizeof(init_data));
  891. init_data.cid = p_ll2_conn->cid;
  892. init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
  893. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  894. rc = qed_sp_init_request(p_hwfn, &p_ent,
  895. CORE_RAMROD_RX_QUEUE_START,
  896. PROTOCOLID_CORE, &init_data);
  897. if (rc)
  898. return rc;
  899. p_ramrod = &p_ent->ramrod.core_rx_queue_start;
  900. p_ramrod->sb_id = cpu_to_le16(qed_int_get_sp_sb_id(p_hwfn));
  901. p_ramrod->sb_index = p_rx->rx_sb_index;
  902. p_ramrod->complete_event_flg = 1;
  903. p_ramrod->mtu = cpu_to_le16(p_ll2_conn->conn.mtu);
  904. DMA_REGPAIR_LE(p_ramrod->bd_base,
  905. p_rx->rxq_chain.p_phys_addr);
  906. cqe_pbl_size = (u16)qed_chain_get_page_cnt(&p_rx->rcq_chain);
  907. p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size);
  908. DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr,
  909. qed_chain_get_pbl_phys(&p_rx->rcq_chain));
  910. p_ramrod->drop_ttl0_flg = p_ll2_conn->conn.rx_drop_ttl0_flg;
  911. p_ramrod->inner_vlan_removal_en = p_ll2_conn->conn.rx_vlan_removal_en;
  912. p_ramrod->queue_id = p_ll2_conn->queue_id;
  913. p_ramrod->main_func_queue = (conn_type == QED_LL2_TYPE_ISCSI_OOO) ? 0
  914. : 1;
  915. if ((IS_MF_DEFAULT(p_hwfn) || IS_MF_SI(p_hwfn)) &&
  916. p_ramrod->main_func_queue && (conn_type != QED_LL2_TYPE_ROCE)) {
  917. p_ramrod->mf_si_bcast_accept_all = 1;
  918. p_ramrod->mf_si_mcast_accept_all = 1;
  919. } else {
  920. p_ramrod->mf_si_bcast_accept_all = 0;
  921. p_ramrod->mf_si_mcast_accept_all = 0;
  922. }
  923. p_ramrod->action_on_error.error_type = action_on_error;
  924. p_ramrod->gsi_offload_flag = p_ll2_conn->conn.gsi_enable;
  925. return qed_spq_post(p_hwfn, p_ent, NULL);
  926. }
  927. static int qed_sp_ll2_tx_queue_start(struct qed_hwfn *p_hwfn,
  928. struct qed_ll2_info *p_ll2_conn)
  929. {
  930. enum qed_ll2_conn_type conn_type = p_ll2_conn->conn.conn_type;
  931. struct qed_ll2_tx_queue *p_tx = &p_ll2_conn->tx_queue;
  932. struct core_tx_start_ramrod_data *p_ramrod = NULL;
  933. struct qed_spq_entry *p_ent = NULL;
  934. struct qed_sp_init_data init_data;
  935. u16 pq_id = 0, pbl_size;
  936. int rc = -EINVAL;
  937. if (!QED_LL2_TX_REGISTERED(p_ll2_conn))
  938. return 0;
  939. if (p_ll2_conn->conn.conn_type == QED_LL2_TYPE_ISCSI_OOO)
  940. p_ll2_conn->tx_stats_en = 0;
  941. else
  942. p_ll2_conn->tx_stats_en = 1;
  943. /* Get SPQ entry */
  944. memset(&init_data, 0, sizeof(init_data));
  945. init_data.cid = p_ll2_conn->cid;
  946. init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
  947. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  948. rc = qed_sp_init_request(p_hwfn, &p_ent,
  949. CORE_RAMROD_TX_QUEUE_START,
  950. PROTOCOLID_CORE, &init_data);
  951. if (rc)
  952. return rc;
  953. p_ramrod = &p_ent->ramrod.core_tx_queue_start;
  954. p_ramrod->sb_id = cpu_to_le16(qed_int_get_sp_sb_id(p_hwfn));
  955. p_ramrod->sb_index = p_tx->tx_sb_index;
  956. p_ramrod->mtu = cpu_to_le16(p_ll2_conn->conn.mtu);
  957. p_ramrod->stats_en = p_ll2_conn->tx_stats_en;
  958. p_ramrod->stats_id = p_ll2_conn->tx_stats_id;
  959. DMA_REGPAIR_LE(p_ramrod->pbl_base_addr,
  960. qed_chain_get_pbl_phys(&p_tx->txq_chain));
  961. pbl_size = qed_chain_get_page_cnt(&p_tx->txq_chain);
  962. p_ramrod->pbl_size = cpu_to_le16(pbl_size);
  963. switch (p_ll2_conn->conn.tx_tc) {
  964. case LB_TC:
  965. pq_id = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB);
  966. break;
  967. case OOO_LB_TC:
  968. pq_id = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OOO);
  969. break;
  970. default:
  971. pq_id = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD);
  972. break;
  973. }
  974. p_ramrod->qm_pq_id = cpu_to_le16(pq_id);
  975. switch (conn_type) {
  976. case QED_LL2_TYPE_FCOE:
  977. p_ramrod->conn_type = PROTOCOLID_FCOE;
  978. break;
  979. case QED_LL2_TYPE_ISCSI:
  980. case QED_LL2_TYPE_ISCSI_OOO:
  981. p_ramrod->conn_type = PROTOCOLID_ISCSI;
  982. break;
  983. case QED_LL2_TYPE_ROCE:
  984. p_ramrod->conn_type = PROTOCOLID_ROCE;
  985. break;
  986. default:
  987. p_ramrod->conn_type = PROTOCOLID_ETH;
  988. DP_NOTICE(p_hwfn, "Unknown connection type: %d\n", conn_type);
  989. }
  990. p_ramrod->gsi_offload_flag = p_ll2_conn->conn.gsi_enable;
  991. return qed_spq_post(p_hwfn, p_ent, NULL);
  992. }
  993. static int qed_sp_ll2_rx_queue_stop(struct qed_hwfn *p_hwfn,
  994. struct qed_ll2_info *p_ll2_conn)
  995. {
  996. struct core_rx_stop_ramrod_data *p_ramrod = NULL;
  997. struct qed_spq_entry *p_ent = NULL;
  998. struct qed_sp_init_data init_data;
  999. int rc = -EINVAL;
  1000. /* Get SPQ entry */
  1001. memset(&init_data, 0, sizeof(init_data));
  1002. init_data.cid = p_ll2_conn->cid;
  1003. init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
  1004. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  1005. rc = qed_sp_init_request(p_hwfn, &p_ent,
  1006. CORE_RAMROD_RX_QUEUE_STOP,
  1007. PROTOCOLID_CORE, &init_data);
  1008. if (rc)
  1009. return rc;
  1010. p_ramrod = &p_ent->ramrod.core_rx_queue_stop;
  1011. p_ramrod->complete_event_flg = 1;
  1012. p_ramrod->queue_id = p_ll2_conn->queue_id;
  1013. return qed_spq_post(p_hwfn, p_ent, NULL);
  1014. }
  1015. static int qed_sp_ll2_tx_queue_stop(struct qed_hwfn *p_hwfn,
  1016. struct qed_ll2_info *p_ll2_conn)
  1017. {
  1018. struct qed_spq_entry *p_ent = NULL;
  1019. struct qed_sp_init_data init_data;
  1020. int rc = -EINVAL;
  1021. /* Get SPQ entry */
  1022. memset(&init_data, 0, sizeof(init_data));
  1023. init_data.cid = p_ll2_conn->cid;
  1024. init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
  1025. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  1026. rc = qed_sp_init_request(p_hwfn, &p_ent,
  1027. CORE_RAMROD_TX_QUEUE_STOP,
  1028. PROTOCOLID_CORE, &init_data);
  1029. if (rc)
  1030. return rc;
  1031. return qed_spq_post(p_hwfn, p_ent, NULL);
  1032. }
  1033. static int
  1034. qed_ll2_acquire_connection_rx(struct qed_hwfn *p_hwfn,
  1035. struct qed_ll2_info *p_ll2_info, u16 rx_num_desc)
  1036. {
  1037. struct qed_ll2_rx_packet *p_descq;
  1038. u32 capacity;
  1039. int rc = 0;
  1040. if (!rx_num_desc)
  1041. goto out;
  1042. rc = qed_chain_alloc(p_hwfn->cdev,
  1043. QED_CHAIN_USE_TO_CONSUME_PRODUCE,
  1044. QED_CHAIN_MODE_NEXT_PTR,
  1045. QED_CHAIN_CNT_TYPE_U16,
  1046. rx_num_desc,
  1047. sizeof(struct core_rx_bd),
  1048. &p_ll2_info->rx_queue.rxq_chain);
  1049. if (rc) {
  1050. DP_NOTICE(p_hwfn, "Failed to allocate ll2 rxq chain\n");
  1051. goto out;
  1052. }
  1053. capacity = qed_chain_get_capacity(&p_ll2_info->rx_queue.rxq_chain);
  1054. p_descq = kcalloc(capacity, sizeof(struct qed_ll2_rx_packet),
  1055. GFP_KERNEL);
  1056. if (!p_descq) {
  1057. rc = -ENOMEM;
  1058. DP_NOTICE(p_hwfn, "Failed to allocate ll2 Rx desc\n");
  1059. goto out;
  1060. }
  1061. p_ll2_info->rx_queue.descq_array = p_descq;
  1062. rc = qed_chain_alloc(p_hwfn->cdev,
  1063. QED_CHAIN_USE_TO_CONSUME_PRODUCE,
  1064. QED_CHAIN_MODE_PBL,
  1065. QED_CHAIN_CNT_TYPE_U16,
  1066. rx_num_desc,
  1067. sizeof(struct core_rx_fast_path_cqe),
  1068. &p_ll2_info->rx_queue.rcq_chain);
  1069. if (rc) {
  1070. DP_NOTICE(p_hwfn, "Failed to allocate ll2 rcq chain\n");
  1071. goto out;
  1072. }
  1073. DP_VERBOSE(p_hwfn, QED_MSG_LL2,
  1074. "Allocated LL2 Rxq [Type %08x] with 0x%08x buffers\n",
  1075. p_ll2_info->conn.conn_type, rx_num_desc);
  1076. out:
  1077. return rc;
  1078. }
  1079. static int qed_ll2_acquire_connection_tx(struct qed_hwfn *p_hwfn,
  1080. struct qed_ll2_info *p_ll2_info,
  1081. u16 tx_num_desc)
  1082. {
  1083. struct qed_ll2_tx_packet *p_descq;
  1084. u32 capacity;
  1085. int rc = 0;
  1086. if (!tx_num_desc)
  1087. goto out;
  1088. rc = qed_chain_alloc(p_hwfn->cdev,
  1089. QED_CHAIN_USE_TO_CONSUME_PRODUCE,
  1090. QED_CHAIN_MODE_PBL,
  1091. QED_CHAIN_CNT_TYPE_U16,
  1092. tx_num_desc,
  1093. sizeof(struct core_tx_bd),
  1094. &p_ll2_info->tx_queue.txq_chain);
  1095. if (rc)
  1096. goto out;
  1097. capacity = qed_chain_get_capacity(&p_ll2_info->tx_queue.txq_chain);
  1098. p_descq = kcalloc(capacity, sizeof(struct qed_ll2_tx_packet),
  1099. GFP_KERNEL);
  1100. if (!p_descq) {
  1101. rc = -ENOMEM;
  1102. goto out;
  1103. }
  1104. p_ll2_info->tx_queue.descq_array = p_descq;
  1105. DP_VERBOSE(p_hwfn, QED_MSG_LL2,
  1106. "Allocated LL2 Txq [Type %08x] with 0x%08x buffers\n",
  1107. p_ll2_info->conn.conn_type, tx_num_desc);
  1108. out:
  1109. if (rc)
  1110. DP_NOTICE(p_hwfn,
  1111. "Can't allocate memory for Tx LL2 with 0x%08x buffers\n",
  1112. tx_num_desc);
  1113. return rc;
  1114. }
  1115. int qed_ll2_acquire_connection(struct qed_hwfn *p_hwfn,
  1116. struct qed_ll2_conn *p_params,
  1117. u16 rx_num_desc,
  1118. u16 tx_num_desc,
  1119. u8 *p_connection_handle)
  1120. {
  1121. qed_int_comp_cb_t comp_rx_cb, comp_tx_cb;
  1122. struct qed_ll2_info *p_ll2_info = NULL;
  1123. int rc;
  1124. u8 i;
  1125. if (!p_connection_handle || !p_hwfn->p_ll2_info)
  1126. return -EINVAL;
  1127. /* Find a free connection to be used */
  1128. for (i = 0; (i < QED_MAX_NUM_OF_LL2_CONNECTIONS); i++) {
  1129. mutex_lock(&p_hwfn->p_ll2_info[i].mutex);
  1130. if (p_hwfn->p_ll2_info[i].b_active) {
  1131. mutex_unlock(&p_hwfn->p_ll2_info[i].mutex);
  1132. continue;
  1133. }
  1134. p_hwfn->p_ll2_info[i].b_active = true;
  1135. p_ll2_info = &p_hwfn->p_ll2_info[i];
  1136. mutex_unlock(&p_hwfn->p_ll2_info[i].mutex);
  1137. break;
  1138. }
  1139. if (!p_ll2_info)
  1140. return -EBUSY;
  1141. p_ll2_info->conn = *p_params;
  1142. rc = qed_ll2_acquire_connection_rx(p_hwfn, p_ll2_info, rx_num_desc);
  1143. if (rc)
  1144. goto q_allocate_fail;
  1145. rc = qed_ll2_acquire_connection_tx(p_hwfn, p_ll2_info, tx_num_desc);
  1146. if (rc)
  1147. goto q_allocate_fail;
  1148. rc = qed_ll2_acquire_connection_ooo(p_hwfn, p_ll2_info,
  1149. rx_num_desc * 2, p_params->mtu);
  1150. if (rc)
  1151. goto q_allocate_fail;
  1152. /* Register callbacks for the Rx/Tx queues */
  1153. if (p_params->conn_type == QED_LL2_TYPE_ISCSI_OOO) {
  1154. comp_rx_cb = qed_ll2_lb_rxq_completion;
  1155. comp_tx_cb = qed_ll2_lb_txq_completion;
  1156. } else {
  1157. comp_rx_cb = qed_ll2_rxq_completion;
  1158. comp_tx_cb = qed_ll2_txq_completion;
  1159. }
  1160. if (rx_num_desc) {
  1161. qed_int_register_cb(p_hwfn, comp_rx_cb,
  1162. &p_hwfn->p_ll2_info[i],
  1163. &p_ll2_info->rx_queue.rx_sb_index,
  1164. &p_ll2_info->rx_queue.p_fw_cons);
  1165. p_ll2_info->rx_queue.b_cb_registred = true;
  1166. }
  1167. if (tx_num_desc) {
  1168. qed_int_register_cb(p_hwfn,
  1169. comp_tx_cb,
  1170. &p_hwfn->p_ll2_info[i],
  1171. &p_ll2_info->tx_queue.tx_sb_index,
  1172. &p_ll2_info->tx_queue.p_fw_cons);
  1173. p_ll2_info->tx_queue.b_cb_registred = true;
  1174. }
  1175. *p_connection_handle = i;
  1176. return rc;
  1177. q_allocate_fail:
  1178. qed_ll2_release_connection(p_hwfn, i);
  1179. return -ENOMEM;
  1180. }
  1181. static int qed_ll2_establish_connection_rx(struct qed_hwfn *p_hwfn,
  1182. struct qed_ll2_info *p_ll2_conn)
  1183. {
  1184. u8 action_on_error = 0;
  1185. if (!QED_LL2_RX_REGISTERED(p_ll2_conn))
  1186. return 0;
  1187. DIRECT_REG_WR(p_ll2_conn->rx_queue.set_prod_addr, 0x0);
  1188. SET_FIELD(action_on_error,
  1189. CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG,
  1190. p_ll2_conn->conn.ai_err_packet_too_big);
  1191. SET_FIELD(action_on_error,
  1192. CORE_RX_ACTION_ON_ERROR_NO_BUFF, p_ll2_conn->conn.ai_err_no_buf);
  1193. return qed_sp_ll2_rx_queue_start(p_hwfn, p_ll2_conn, action_on_error);
  1194. }
  1195. int qed_ll2_establish_connection(struct qed_hwfn *p_hwfn, u8 connection_handle)
  1196. {
  1197. struct qed_ll2_info *p_ll2_conn;
  1198. struct qed_ll2_rx_queue *p_rx;
  1199. struct qed_ll2_tx_queue *p_tx;
  1200. struct qed_ptt *p_ptt;
  1201. int rc = -EINVAL;
  1202. u32 i, capacity;
  1203. u8 qid;
  1204. p_ptt = qed_ptt_acquire(p_hwfn);
  1205. if (!p_ptt)
  1206. return -EAGAIN;
  1207. p_ll2_conn = qed_ll2_handle_sanity_lock(p_hwfn, connection_handle);
  1208. if (!p_ll2_conn) {
  1209. rc = -EINVAL;
  1210. goto out;
  1211. }
  1212. p_rx = &p_ll2_conn->rx_queue;
  1213. p_tx = &p_ll2_conn->tx_queue;
  1214. qed_chain_reset(&p_rx->rxq_chain);
  1215. qed_chain_reset(&p_rx->rcq_chain);
  1216. INIT_LIST_HEAD(&p_rx->active_descq);
  1217. INIT_LIST_HEAD(&p_rx->free_descq);
  1218. INIT_LIST_HEAD(&p_rx->posting_descq);
  1219. spin_lock_init(&p_rx->lock);
  1220. capacity = qed_chain_get_capacity(&p_rx->rxq_chain);
  1221. for (i = 0; i < capacity; i++)
  1222. list_add_tail(&p_rx->descq_array[i].list_entry,
  1223. &p_rx->free_descq);
  1224. *p_rx->p_fw_cons = 0;
  1225. qed_chain_reset(&p_tx->txq_chain);
  1226. INIT_LIST_HEAD(&p_tx->active_descq);
  1227. INIT_LIST_HEAD(&p_tx->free_descq);
  1228. INIT_LIST_HEAD(&p_tx->sending_descq);
  1229. spin_lock_init(&p_tx->lock);
  1230. capacity = qed_chain_get_capacity(&p_tx->txq_chain);
  1231. for (i = 0; i < capacity; i++)
  1232. list_add_tail(&p_tx->descq_array[i].list_entry,
  1233. &p_tx->free_descq);
  1234. p_tx->cur_completing_bd_idx = 0;
  1235. p_tx->bds_idx = 0;
  1236. p_tx->b_completing_packet = false;
  1237. p_tx->cur_send_packet = NULL;
  1238. p_tx->cur_send_frag_num = 0;
  1239. p_tx->cur_completing_frag_num = 0;
  1240. *p_tx->p_fw_cons = 0;
  1241. rc = qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_CORE, &p_ll2_conn->cid);
  1242. if (rc)
  1243. goto out;
  1244. qid = p_hwfn->hw_info.resc_start[QED_LL2_QUEUE] + connection_handle;
  1245. p_ll2_conn->queue_id = qid;
  1246. p_ll2_conn->tx_stats_id = qid;
  1247. p_rx->set_prod_addr = (u8 __iomem *)p_hwfn->regview +
  1248. GTT_BAR0_MAP_REG_TSDM_RAM +
  1249. TSTORM_LL2_RX_PRODS_OFFSET(qid);
  1250. p_tx->doorbell_addr = (u8 __iomem *)p_hwfn->doorbells +
  1251. qed_db_addr(p_ll2_conn->cid,
  1252. DQ_DEMS_LEGACY);
  1253. rc = qed_ll2_establish_connection_rx(p_hwfn, p_ll2_conn);
  1254. if (rc)
  1255. goto out;
  1256. rc = qed_sp_ll2_tx_queue_start(p_hwfn, p_ll2_conn);
  1257. if (rc)
  1258. goto out;
  1259. if (p_hwfn->hw_info.personality != QED_PCI_ETH_ROCE)
  1260. qed_wr(p_hwfn, p_ptt, PRS_REG_USE_LIGHT_L2, 1);
  1261. qed_ll2_establish_connection_ooo(p_hwfn, p_ll2_conn);
  1262. if (p_ll2_conn->conn.conn_type == QED_LL2_TYPE_FCOE) {
  1263. qed_llh_add_protocol_filter(p_hwfn, p_ptt,
  1264. 0x8906, 0,
  1265. QED_LLH_FILTER_ETHERTYPE);
  1266. qed_llh_add_protocol_filter(p_hwfn, p_ptt,
  1267. 0x8914, 0,
  1268. QED_LLH_FILTER_ETHERTYPE);
  1269. }
  1270. out:
  1271. qed_ptt_release(p_hwfn, p_ptt);
  1272. return rc;
  1273. }
  1274. static void qed_ll2_post_rx_buffer_notify_fw(struct qed_hwfn *p_hwfn,
  1275. struct qed_ll2_rx_queue *p_rx,
  1276. struct qed_ll2_rx_packet *p_curp)
  1277. {
  1278. struct qed_ll2_rx_packet *p_posting_packet = NULL;
  1279. struct core_ll2_rx_prod rx_prod = { 0, 0, 0 };
  1280. bool b_notify_fw = false;
  1281. u16 bd_prod, cq_prod;
  1282. /* This handles the flushing of already posted buffers */
  1283. while (!list_empty(&p_rx->posting_descq)) {
  1284. p_posting_packet = list_first_entry(&p_rx->posting_descq,
  1285. struct qed_ll2_rx_packet,
  1286. list_entry);
  1287. list_move_tail(&p_posting_packet->list_entry,
  1288. &p_rx->active_descq);
  1289. b_notify_fw = true;
  1290. }
  1291. /* This handles the supplied packet [if there is one] */
  1292. if (p_curp) {
  1293. list_add_tail(&p_curp->list_entry, &p_rx->active_descq);
  1294. b_notify_fw = true;
  1295. }
  1296. if (!b_notify_fw)
  1297. return;
  1298. bd_prod = qed_chain_get_prod_idx(&p_rx->rxq_chain);
  1299. cq_prod = qed_chain_get_prod_idx(&p_rx->rcq_chain);
  1300. rx_prod.bd_prod = cpu_to_le16(bd_prod);
  1301. rx_prod.cqe_prod = cpu_to_le16(cq_prod);
  1302. DIRECT_REG_WR(p_rx->set_prod_addr, *((u32 *)&rx_prod));
  1303. }
  1304. int qed_ll2_post_rx_buffer(struct qed_hwfn *p_hwfn,
  1305. u8 connection_handle,
  1306. dma_addr_t addr,
  1307. u16 buf_len, void *cookie, u8 notify_fw)
  1308. {
  1309. struct core_rx_bd_with_buff_len *p_curb = NULL;
  1310. struct qed_ll2_rx_packet *p_curp = NULL;
  1311. struct qed_ll2_info *p_ll2_conn;
  1312. struct qed_ll2_rx_queue *p_rx;
  1313. unsigned long flags;
  1314. void *p_data;
  1315. int rc = 0;
  1316. p_ll2_conn = qed_ll2_handle_sanity(p_hwfn, connection_handle);
  1317. if (!p_ll2_conn)
  1318. return -EINVAL;
  1319. p_rx = &p_ll2_conn->rx_queue;
  1320. spin_lock_irqsave(&p_rx->lock, flags);
  1321. if (!list_empty(&p_rx->free_descq))
  1322. p_curp = list_first_entry(&p_rx->free_descq,
  1323. struct qed_ll2_rx_packet, list_entry);
  1324. if (p_curp) {
  1325. if (qed_chain_get_elem_left(&p_rx->rxq_chain) &&
  1326. qed_chain_get_elem_left(&p_rx->rcq_chain)) {
  1327. p_data = qed_chain_produce(&p_rx->rxq_chain);
  1328. p_curb = (struct core_rx_bd_with_buff_len *)p_data;
  1329. qed_chain_produce(&p_rx->rcq_chain);
  1330. }
  1331. }
  1332. /* If we're lacking entires, let's try to flush buffers to FW */
  1333. if (!p_curp || !p_curb) {
  1334. rc = -EBUSY;
  1335. p_curp = NULL;
  1336. goto out_notify;
  1337. }
  1338. /* We have an Rx packet we can fill */
  1339. DMA_REGPAIR_LE(p_curb->addr, addr);
  1340. p_curb->buff_length = cpu_to_le16(buf_len);
  1341. p_curp->rx_buf_addr = addr;
  1342. p_curp->cookie = cookie;
  1343. p_curp->rxq_bd = p_curb;
  1344. p_curp->buf_length = buf_len;
  1345. list_del(&p_curp->list_entry);
  1346. /* Check if we only want to enqueue this packet without informing FW */
  1347. if (!notify_fw) {
  1348. list_add_tail(&p_curp->list_entry, &p_rx->posting_descq);
  1349. goto out;
  1350. }
  1351. out_notify:
  1352. qed_ll2_post_rx_buffer_notify_fw(p_hwfn, p_rx, p_curp);
  1353. out:
  1354. spin_unlock_irqrestore(&p_rx->lock, flags);
  1355. return rc;
  1356. }
  1357. static void qed_ll2_prepare_tx_packet_set(struct qed_hwfn *p_hwfn,
  1358. struct qed_ll2_tx_queue *p_tx,
  1359. struct qed_ll2_tx_packet *p_curp,
  1360. u8 num_of_bds,
  1361. dma_addr_t first_frag,
  1362. u16 first_frag_len, void *p_cookie,
  1363. u8 notify_fw)
  1364. {
  1365. list_del(&p_curp->list_entry);
  1366. p_curp->cookie = p_cookie;
  1367. p_curp->bd_used = num_of_bds;
  1368. p_curp->notify_fw = notify_fw;
  1369. p_tx->cur_send_packet = p_curp;
  1370. p_tx->cur_send_frag_num = 0;
  1371. p_curp->bds_set[p_tx->cur_send_frag_num].tx_frag = first_frag;
  1372. p_curp->bds_set[p_tx->cur_send_frag_num].frag_len = first_frag_len;
  1373. p_tx->cur_send_frag_num++;
  1374. }
  1375. static void
  1376. qed_ll2_prepare_tx_packet_set_bd(struct qed_hwfn *p_hwfn,
  1377. struct qed_ll2_info *p_ll2,
  1378. struct qed_ll2_tx_packet *p_curp,
  1379. u8 num_of_bds,
  1380. enum core_tx_dest tx_dest,
  1381. u16 vlan,
  1382. u8 bd_flags,
  1383. u16 l4_hdr_offset_w,
  1384. enum core_roce_flavor_type roce_flavor,
  1385. dma_addr_t first_frag,
  1386. u16 first_frag_len)
  1387. {
  1388. struct qed_chain *p_tx_chain = &p_ll2->tx_queue.txq_chain;
  1389. u16 prod_idx = qed_chain_get_prod_idx(p_tx_chain);
  1390. struct core_tx_bd *start_bd = NULL;
  1391. u16 bd_data = 0, frag_idx;
  1392. start_bd = (struct core_tx_bd *)qed_chain_produce(p_tx_chain);
  1393. start_bd->nw_vlan_or_lb_echo = cpu_to_le16(vlan);
  1394. SET_FIELD(start_bd->bitfield1, CORE_TX_BD_L4_HDR_OFFSET_W,
  1395. cpu_to_le16(l4_hdr_offset_w));
  1396. SET_FIELD(start_bd->bitfield1, CORE_TX_BD_TX_DST, tx_dest);
  1397. bd_data |= bd_flags;
  1398. SET_FIELD(bd_data, CORE_TX_BD_DATA_START_BD, 0x1);
  1399. SET_FIELD(bd_data, CORE_TX_BD_DATA_NBDS, num_of_bds);
  1400. SET_FIELD(bd_data, CORE_TX_BD_DATA_ROCE_FLAV, roce_flavor);
  1401. start_bd->bd_data.as_bitfield = cpu_to_le16(bd_data);
  1402. DMA_REGPAIR_LE(start_bd->addr, first_frag);
  1403. start_bd->nbytes = cpu_to_le16(first_frag_len);
  1404. DP_VERBOSE(p_hwfn,
  1405. (NETIF_MSG_TX_QUEUED | QED_MSG_LL2),
  1406. "LL2 [q 0x%02x cid 0x%08x type 0x%08x] Tx Producer at [0x%04x] - set with a %04x bytes %02x BDs buffer at %08x:%08x\n",
  1407. p_ll2->queue_id,
  1408. p_ll2->cid,
  1409. p_ll2->conn.conn_type,
  1410. prod_idx,
  1411. first_frag_len,
  1412. num_of_bds,
  1413. le32_to_cpu(start_bd->addr.hi),
  1414. le32_to_cpu(start_bd->addr.lo));
  1415. if (p_ll2->tx_queue.cur_send_frag_num == num_of_bds)
  1416. return;
  1417. /* Need to provide the packet with additional BDs for frags */
  1418. for (frag_idx = p_ll2->tx_queue.cur_send_frag_num;
  1419. frag_idx < num_of_bds; frag_idx++) {
  1420. struct core_tx_bd **p_bd = &p_curp->bds_set[frag_idx].txq_bd;
  1421. *p_bd = (struct core_tx_bd *)qed_chain_produce(p_tx_chain);
  1422. (*p_bd)->bd_data.as_bitfield = 0;
  1423. (*p_bd)->bitfield1 = 0;
  1424. p_curp->bds_set[frag_idx].tx_frag = 0;
  1425. p_curp->bds_set[frag_idx].frag_len = 0;
  1426. }
  1427. }
  1428. /* This should be called while the Txq spinlock is being held */
  1429. static void qed_ll2_tx_packet_notify(struct qed_hwfn *p_hwfn,
  1430. struct qed_ll2_info *p_ll2_conn)
  1431. {
  1432. bool b_notify = p_ll2_conn->tx_queue.cur_send_packet->notify_fw;
  1433. struct qed_ll2_tx_queue *p_tx = &p_ll2_conn->tx_queue;
  1434. struct qed_ll2_tx_packet *p_pkt = NULL;
  1435. struct core_db_data db_msg = { 0, 0, 0 };
  1436. u16 bd_prod;
  1437. /* If there are missing BDs, don't do anything now */
  1438. if (p_ll2_conn->tx_queue.cur_send_frag_num !=
  1439. p_ll2_conn->tx_queue.cur_send_packet->bd_used)
  1440. return;
  1441. /* Push the current packet to the list and clean after it */
  1442. list_add_tail(&p_ll2_conn->tx_queue.cur_send_packet->list_entry,
  1443. &p_ll2_conn->tx_queue.sending_descq);
  1444. p_ll2_conn->tx_queue.cur_send_packet = NULL;
  1445. p_ll2_conn->tx_queue.cur_send_frag_num = 0;
  1446. /* Notify FW of packet only if requested to */
  1447. if (!b_notify)
  1448. return;
  1449. bd_prod = qed_chain_get_prod_idx(&p_ll2_conn->tx_queue.txq_chain);
  1450. while (!list_empty(&p_tx->sending_descq)) {
  1451. p_pkt = list_first_entry(&p_tx->sending_descq,
  1452. struct qed_ll2_tx_packet, list_entry);
  1453. if (!p_pkt)
  1454. break;
  1455. list_move_tail(&p_pkt->list_entry, &p_tx->active_descq);
  1456. }
  1457. SET_FIELD(db_msg.params, CORE_DB_DATA_DEST, DB_DEST_XCM);
  1458. SET_FIELD(db_msg.params, CORE_DB_DATA_AGG_CMD, DB_AGG_CMD_SET);
  1459. SET_FIELD(db_msg.params, CORE_DB_DATA_AGG_VAL_SEL,
  1460. DQ_XCM_CORE_TX_BD_PROD_CMD);
  1461. db_msg.agg_flags = DQ_XCM_CORE_DQ_CF_CMD;
  1462. db_msg.spq_prod = cpu_to_le16(bd_prod);
  1463. /* Make sure the BDs data is updated before ringing the doorbell */
  1464. wmb();
  1465. DIRECT_REG_WR(p_tx->doorbell_addr, *((u32 *)&db_msg));
  1466. DP_VERBOSE(p_hwfn,
  1467. (NETIF_MSG_TX_QUEUED | QED_MSG_LL2),
  1468. "LL2 [q 0x%02x cid 0x%08x type 0x%08x] Doorbelled [producer 0x%04x]\n",
  1469. p_ll2_conn->queue_id,
  1470. p_ll2_conn->cid, p_ll2_conn->conn.conn_type, db_msg.spq_prod);
  1471. }
  1472. int qed_ll2_prepare_tx_packet(struct qed_hwfn *p_hwfn,
  1473. u8 connection_handle,
  1474. u8 num_of_bds,
  1475. u16 vlan,
  1476. u8 bd_flags,
  1477. u16 l4_hdr_offset_w,
  1478. enum qed_ll2_tx_dest e_tx_dest,
  1479. enum qed_ll2_roce_flavor_type qed_roce_flavor,
  1480. dma_addr_t first_frag,
  1481. u16 first_frag_len, void *cookie, u8 notify_fw)
  1482. {
  1483. struct qed_ll2_tx_packet *p_curp = NULL;
  1484. struct qed_ll2_info *p_ll2_conn = NULL;
  1485. enum core_roce_flavor_type roce_flavor;
  1486. struct qed_ll2_tx_queue *p_tx;
  1487. struct qed_chain *p_tx_chain;
  1488. enum core_tx_dest tx_dest;
  1489. unsigned long flags;
  1490. int rc = 0;
  1491. p_ll2_conn = qed_ll2_handle_sanity(p_hwfn, connection_handle);
  1492. if (!p_ll2_conn)
  1493. return -EINVAL;
  1494. p_tx = &p_ll2_conn->tx_queue;
  1495. p_tx_chain = &p_tx->txq_chain;
  1496. if (num_of_bds > CORE_LL2_TX_MAX_BDS_PER_PACKET)
  1497. return -EIO;
  1498. spin_lock_irqsave(&p_tx->lock, flags);
  1499. if (p_tx->cur_send_packet) {
  1500. rc = -EEXIST;
  1501. goto out;
  1502. }
  1503. /* Get entry, but only if we have tx elements for it */
  1504. if (!list_empty(&p_tx->free_descq))
  1505. p_curp = list_first_entry(&p_tx->free_descq,
  1506. struct qed_ll2_tx_packet, list_entry);
  1507. if (p_curp && qed_chain_get_elem_left(p_tx_chain) < num_of_bds)
  1508. p_curp = NULL;
  1509. if (!p_curp) {
  1510. rc = -EBUSY;
  1511. goto out;
  1512. }
  1513. tx_dest = e_tx_dest == QED_LL2_TX_DEST_NW ? CORE_TX_DEST_NW :
  1514. CORE_TX_DEST_LB;
  1515. if (qed_roce_flavor == QED_LL2_ROCE) {
  1516. roce_flavor = CORE_ROCE;
  1517. } else if (qed_roce_flavor == QED_LL2_RROCE) {
  1518. roce_flavor = CORE_RROCE;
  1519. } else {
  1520. rc = -EINVAL;
  1521. goto out;
  1522. }
  1523. /* Prepare packet and BD, and perhaps send a doorbell to FW */
  1524. qed_ll2_prepare_tx_packet_set(p_hwfn, p_tx, p_curp,
  1525. num_of_bds, first_frag,
  1526. first_frag_len, cookie, notify_fw);
  1527. qed_ll2_prepare_tx_packet_set_bd(p_hwfn, p_ll2_conn, p_curp,
  1528. num_of_bds, tx_dest,
  1529. vlan, bd_flags, l4_hdr_offset_w,
  1530. roce_flavor,
  1531. first_frag, first_frag_len);
  1532. qed_ll2_tx_packet_notify(p_hwfn, p_ll2_conn);
  1533. out:
  1534. spin_unlock_irqrestore(&p_tx->lock, flags);
  1535. return rc;
  1536. }
  1537. int qed_ll2_set_fragment_of_tx_packet(struct qed_hwfn *p_hwfn,
  1538. u8 connection_handle,
  1539. dma_addr_t addr, u16 nbytes)
  1540. {
  1541. struct qed_ll2_tx_packet *p_cur_send_packet = NULL;
  1542. struct qed_ll2_info *p_ll2_conn = NULL;
  1543. u16 cur_send_frag_num = 0;
  1544. struct core_tx_bd *p_bd;
  1545. unsigned long flags;
  1546. p_ll2_conn = qed_ll2_handle_sanity(p_hwfn, connection_handle);
  1547. if (!p_ll2_conn)
  1548. return -EINVAL;
  1549. if (!p_ll2_conn->tx_queue.cur_send_packet)
  1550. return -EINVAL;
  1551. p_cur_send_packet = p_ll2_conn->tx_queue.cur_send_packet;
  1552. cur_send_frag_num = p_ll2_conn->tx_queue.cur_send_frag_num;
  1553. if (cur_send_frag_num >= p_cur_send_packet->bd_used)
  1554. return -EINVAL;
  1555. /* Fill the BD information, and possibly notify FW */
  1556. p_bd = p_cur_send_packet->bds_set[cur_send_frag_num].txq_bd;
  1557. DMA_REGPAIR_LE(p_bd->addr, addr);
  1558. p_bd->nbytes = cpu_to_le16(nbytes);
  1559. p_cur_send_packet->bds_set[cur_send_frag_num].tx_frag = addr;
  1560. p_cur_send_packet->bds_set[cur_send_frag_num].frag_len = nbytes;
  1561. p_ll2_conn->tx_queue.cur_send_frag_num++;
  1562. spin_lock_irqsave(&p_ll2_conn->tx_queue.lock, flags);
  1563. qed_ll2_tx_packet_notify(p_hwfn, p_ll2_conn);
  1564. spin_unlock_irqrestore(&p_ll2_conn->tx_queue.lock, flags);
  1565. return 0;
  1566. }
  1567. int qed_ll2_terminate_connection(struct qed_hwfn *p_hwfn, u8 connection_handle)
  1568. {
  1569. struct qed_ll2_info *p_ll2_conn = NULL;
  1570. int rc = -EINVAL;
  1571. struct qed_ptt *p_ptt;
  1572. p_ptt = qed_ptt_acquire(p_hwfn);
  1573. if (!p_ptt)
  1574. return -EAGAIN;
  1575. p_ll2_conn = qed_ll2_handle_sanity_lock(p_hwfn, connection_handle);
  1576. if (!p_ll2_conn) {
  1577. rc = -EINVAL;
  1578. goto out;
  1579. }
  1580. /* Stop Tx & Rx of connection, if needed */
  1581. if (QED_LL2_TX_REGISTERED(p_ll2_conn)) {
  1582. rc = qed_sp_ll2_tx_queue_stop(p_hwfn, p_ll2_conn);
  1583. if (rc)
  1584. goto out;
  1585. qed_ll2_txq_flush(p_hwfn, connection_handle);
  1586. }
  1587. if (QED_LL2_RX_REGISTERED(p_ll2_conn)) {
  1588. rc = qed_sp_ll2_rx_queue_stop(p_hwfn, p_ll2_conn);
  1589. if (rc)
  1590. goto out;
  1591. qed_ll2_rxq_flush(p_hwfn, connection_handle);
  1592. }
  1593. if (p_ll2_conn->conn.conn_type == QED_LL2_TYPE_ISCSI_OOO)
  1594. qed_ooo_release_all_isles(p_hwfn, p_hwfn->p_ooo_info);
  1595. if (p_ll2_conn->conn.conn_type == QED_LL2_TYPE_FCOE) {
  1596. qed_llh_remove_protocol_filter(p_hwfn, p_ptt,
  1597. 0x8906, 0,
  1598. QED_LLH_FILTER_ETHERTYPE);
  1599. qed_llh_remove_protocol_filter(p_hwfn, p_ptt,
  1600. 0x8914, 0,
  1601. QED_LLH_FILTER_ETHERTYPE);
  1602. }
  1603. out:
  1604. qed_ptt_release(p_hwfn, p_ptt);
  1605. return rc;
  1606. }
  1607. void qed_ll2_release_connection(struct qed_hwfn *p_hwfn, u8 connection_handle)
  1608. {
  1609. struct qed_ll2_info *p_ll2_conn = NULL;
  1610. p_ll2_conn = qed_ll2_handle_sanity(p_hwfn, connection_handle);
  1611. if (!p_ll2_conn)
  1612. return;
  1613. if (QED_LL2_RX_REGISTERED(p_ll2_conn)) {
  1614. p_ll2_conn->rx_queue.b_cb_registred = false;
  1615. qed_int_unregister_cb(p_hwfn, p_ll2_conn->rx_queue.rx_sb_index);
  1616. }
  1617. if (QED_LL2_TX_REGISTERED(p_ll2_conn)) {
  1618. p_ll2_conn->tx_queue.b_cb_registred = false;
  1619. qed_int_unregister_cb(p_hwfn, p_ll2_conn->tx_queue.tx_sb_index);
  1620. }
  1621. kfree(p_ll2_conn->tx_queue.descq_array);
  1622. qed_chain_free(p_hwfn->cdev, &p_ll2_conn->tx_queue.txq_chain);
  1623. kfree(p_ll2_conn->rx_queue.descq_array);
  1624. qed_chain_free(p_hwfn->cdev, &p_ll2_conn->rx_queue.rxq_chain);
  1625. qed_chain_free(p_hwfn->cdev, &p_ll2_conn->rx_queue.rcq_chain);
  1626. qed_cxt_release_cid(p_hwfn, p_ll2_conn->cid);
  1627. qed_ll2_release_connection_ooo(p_hwfn, p_ll2_conn);
  1628. mutex_lock(&p_ll2_conn->mutex);
  1629. p_ll2_conn->b_active = false;
  1630. mutex_unlock(&p_ll2_conn->mutex);
  1631. }
  1632. struct qed_ll2_info *qed_ll2_alloc(struct qed_hwfn *p_hwfn)
  1633. {
  1634. struct qed_ll2_info *p_ll2_connections;
  1635. u8 i;
  1636. /* Allocate LL2's set struct */
  1637. p_ll2_connections = kcalloc(QED_MAX_NUM_OF_LL2_CONNECTIONS,
  1638. sizeof(struct qed_ll2_info), GFP_KERNEL);
  1639. if (!p_ll2_connections) {
  1640. DP_NOTICE(p_hwfn, "Failed to allocate `struct qed_ll2'\n");
  1641. return NULL;
  1642. }
  1643. for (i = 0; i < QED_MAX_NUM_OF_LL2_CONNECTIONS; i++)
  1644. p_ll2_connections[i].my_id = i;
  1645. return p_ll2_connections;
  1646. }
  1647. void qed_ll2_setup(struct qed_hwfn *p_hwfn,
  1648. struct qed_ll2_info *p_ll2_connections)
  1649. {
  1650. int i;
  1651. for (i = 0; i < QED_MAX_NUM_OF_LL2_CONNECTIONS; i++)
  1652. mutex_init(&p_ll2_connections[i].mutex);
  1653. }
  1654. void qed_ll2_free(struct qed_hwfn *p_hwfn,
  1655. struct qed_ll2_info *p_ll2_connections)
  1656. {
  1657. kfree(p_ll2_connections);
  1658. }
  1659. static void _qed_ll2_get_tstats(struct qed_hwfn *p_hwfn,
  1660. struct qed_ptt *p_ptt,
  1661. struct qed_ll2_info *p_ll2_conn,
  1662. struct qed_ll2_stats *p_stats)
  1663. {
  1664. struct core_ll2_tstorm_per_queue_stat tstats;
  1665. u8 qid = p_ll2_conn->queue_id;
  1666. u32 tstats_addr;
  1667. memset(&tstats, 0, sizeof(tstats));
  1668. tstats_addr = BAR0_MAP_REG_TSDM_RAM +
  1669. CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(qid);
  1670. qed_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, sizeof(tstats));
  1671. p_stats->packet_too_big_discard =
  1672. HILO_64_REGPAIR(tstats.packet_too_big_discard);
  1673. p_stats->no_buff_discard = HILO_64_REGPAIR(tstats.no_buff_discard);
  1674. }
  1675. static void _qed_ll2_get_ustats(struct qed_hwfn *p_hwfn,
  1676. struct qed_ptt *p_ptt,
  1677. struct qed_ll2_info *p_ll2_conn,
  1678. struct qed_ll2_stats *p_stats)
  1679. {
  1680. struct core_ll2_ustorm_per_queue_stat ustats;
  1681. u8 qid = p_ll2_conn->queue_id;
  1682. u32 ustats_addr;
  1683. memset(&ustats, 0, sizeof(ustats));
  1684. ustats_addr = BAR0_MAP_REG_USDM_RAM +
  1685. CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(qid);
  1686. qed_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, sizeof(ustats));
  1687. p_stats->rcv_ucast_bytes = HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
  1688. p_stats->rcv_mcast_bytes = HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
  1689. p_stats->rcv_bcast_bytes = HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
  1690. p_stats->rcv_ucast_pkts = HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
  1691. p_stats->rcv_mcast_pkts = HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
  1692. p_stats->rcv_bcast_pkts = HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
  1693. }
  1694. static void _qed_ll2_get_pstats(struct qed_hwfn *p_hwfn,
  1695. struct qed_ptt *p_ptt,
  1696. struct qed_ll2_info *p_ll2_conn,
  1697. struct qed_ll2_stats *p_stats)
  1698. {
  1699. struct core_ll2_pstorm_per_queue_stat pstats;
  1700. u8 stats_id = p_ll2_conn->tx_stats_id;
  1701. u32 pstats_addr;
  1702. memset(&pstats, 0, sizeof(pstats));
  1703. pstats_addr = BAR0_MAP_REG_PSDM_RAM +
  1704. CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(stats_id);
  1705. qed_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, sizeof(pstats));
  1706. p_stats->sent_ucast_bytes = HILO_64_REGPAIR(pstats.sent_ucast_bytes);
  1707. p_stats->sent_mcast_bytes = HILO_64_REGPAIR(pstats.sent_mcast_bytes);
  1708. p_stats->sent_bcast_bytes = HILO_64_REGPAIR(pstats.sent_bcast_bytes);
  1709. p_stats->sent_ucast_pkts = HILO_64_REGPAIR(pstats.sent_ucast_pkts);
  1710. p_stats->sent_mcast_pkts = HILO_64_REGPAIR(pstats.sent_mcast_pkts);
  1711. p_stats->sent_bcast_pkts = HILO_64_REGPAIR(pstats.sent_bcast_pkts);
  1712. }
  1713. int qed_ll2_get_stats(struct qed_hwfn *p_hwfn,
  1714. u8 connection_handle, struct qed_ll2_stats *p_stats)
  1715. {
  1716. struct qed_ll2_info *p_ll2_conn = NULL;
  1717. struct qed_ptt *p_ptt;
  1718. memset(p_stats, 0, sizeof(*p_stats));
  1719. if ((connection_handle >= QED_MAX_NUM_OF_LL2_CONNECTIONS) ||
  1720. !p_hwfn->p_ll2_info)
  1721. return -EINVAL;
  1722. p_ll2_conn = &p_hwfn->p_ll2_info[connection_handle];
  1723. p_ptt = qed_ptt_acquire(p_hwfn);
  1724. if (!p_ptt) {
  1725. DP_ERR(p_hwfn, "Failed to acquire ptt\n");
  1726. return -EINVAL;
  1727. }
  1728. _qed_ll2_get_tstats(p_hwfn, p_ptt, p_ll2_conn, p_stats);
  1729. _qed_ll2_get_ustats(p_hwfn, p_ptt, p_ll2_conn, p_stats);
  1730. if (p_ll2_conn->tx_stats_en)
  1731. _qed_ll2_get_pstats(p_hwfn, p_ptt, p_ll2_conn, p_stats);
  1732. qed_ptt_release(p_hwfn, p_ptt);
  1733. return 0;
  1734. }
  1735. static void qed_ll2_register_cb_ops(struct qed_dev *cdev,
  1736. const struct qed_ll2_cb_ops *ops,
  1737. void *cookie)
  1738. {
  1739. cdev->ll2->cbs = ops;
  1740. cdev->ll2->cb_cookie = cookie;
  1741. }
  1742. static int qed_ll2_start(struct qed_dev *cdev, struct qed_ll2_params *params)
  1743. {
  1744. struct qed_ll2_conn ll2_info;
  1745. struct qed_ll2_buffer *buffer, *tmp_buffer;
  1746. enum qed_ll2_conn_type conn_type;
  1747. struct qed_ptt *p_ptt;
  1748. int rc, i;
  1749. u8 gsi_enable = 1;
  1750. /* Initialize LL2 locks & lists */
  1751. INIT_LIST_HEAD(&cdev->ll2->list);
  1752. spin_lock_init(&cdev->ll2->lock);
  1753. cdev->ll2->rx_size = NET_SKB_PAD + ETH_HLEN +
  1754. L1_CACHE_BYTES + params->mtu;
  1755. cdev->ll2->frags_mapped = params->frags_mapped;
  1756. /*Allocate memory for LL2 */
  1757. DP_INFO(cdev, "Allocating LL2 buffers of size %08x bytes\n",
  1758. cdev->ll2->rx_size);
  1759. for (i = 0; i < QED_LL2_RX_SIZE; i++) {
  1760. buffer = kzalloc(sizeof(*buffer), GFP_KERNEL);
  1761. if (!buffer) {
  1762. DP_INFO(cdev, "Failed to allocate LL2 buffers\n");
  1763. goto fail;
  1764. }
  1765. rc = qed_ll2_alloc_buffer(cdev, (u8 **)&buffer->data,
  1766. &buffer->phys_addr);
  1767. if (rc) {
  1768. kfree(buffer);
  1769. goto fail;
  1770. }
  1771. list_add_tail(&buffer->list, &cdev->ll2->list);
  1772. }
  1773. switch (QED_LEADING_HWFN(cdev)->hw_info.personality) {
  1774. case QED_PCI_FCOE:
  1775. conn_type = QED_LL2_TYPE_FCOE;
  1776. gsi_enable = 0;
  1777. break;
  1778. case QED_PCI_ISCSI:
  1779. conn_type = QED_LL2_TYPE_ISCSI;
  1780. gsi_enable = 0;
  1781. break;
  1782. case QED_PCI_ETH_ROCE:
  1783. conn_type = QED_LL2_TYPE_ROCE;
  1784. break;
  1785. default:
  1786. conn_type = QED_LL2_TYPE_TEST;
  1787. }
  1788. /* Prepare the temporary ll2 information */
  1789. memset(&ll2_info, 0, sizeof(ll2_info));
  1790. ll2_info.conn_type = conn_type;
  1791. ll2_info.mtu = params->mtu;
  1792. ll2_info.rx_drop_ttl0_flg = params->drop_ttl0_packets;
  1793. ll2_info.rx_vlan_removal_en = params->rx_vlan_stripping;
  1794. ll2_info.tx_tc = 0;
  1795. ll2_info.tx_dest = CORE_TX_DEST_NW;
  1796. ll2_info.gsi_enable = gsi_enable;
  1797. rc = qed_ll2_acquire_connection(QED_LEADING_HWFN(cdev), &ll2_info,
  1798. QED_LL2_RX_SIZE, QED_LL2_TX_SIZE,
  1799. &cdev->ll2->handle);
  1800. if (rc) {
  1801. DP_INFO(cdev, "Failed to acquire LL2 connection\n");
  1802. goto fail;
  1803. }
  1804. rc = qed_ll2_establish_connection(QED_LEADING_HWFN(cdev),
  1805. cdev->ll2->handle);
  1806. if (rc) {
  1807. DP_INFO(cdev, "Failed to establish LL2 connection\n");
  1808. goto release_fail;
  1809. }
  1810. /* Post all Rx buffers to FW */
  1811. spin_lock_bh(&cdev->ll2->lock);
  1812. list_for_each_entry_safe(buffer, tmp_buffer, &cdev->ll2->list, list) {
  1813. rc = qed_ll2_post_rx_buffer(QED_LEADING_HWFN(cdev),
  1814. cdev->ll2->handle,
  1815. buffer->phys_addr, 0, buffer, 1);
  1816. if (rc) {
  1817. DP_INFO(cdev,
  1818. "Failed to post an Rx buffer; Deleting it\n");
  1819. dma_unmap_single(&cdev->pdev->dev, buffer->phys_addr,
  1820. cdev->ll2->rx_size, DMA_FROM_DEVICE);
  1821. kfree(buffer->data);
  1822. list_del(&buffer->list);
  1823. kfree(buffer);
  1824. } else {
  1825. cdev->ll2->rx_cnt++;
  1826. }
  1827. }
  1828. spin_unlock_bh(&cdev->ll2->lock);
  1829. if (!cdev->ll2->rx_cnt) {
  1830. DP_INFO(cdev, "Failed passing even a single Rx buffer\n");
  1831. goto release_terminate;
  1832. }
  1833. if (!is_valid_ether_addr(params->ll2_mac_address)) {
  1834. DP_INFO(cdev, "Invalid Ethernet address\n");
  1835. goto release_terminate;
  1836. }
  1837. if (cdev->hwfns[0].hw_info.personality == QED_PCI_ISCSI &&
  1838. cdev->hwfns[0].pf_params.iscsi_pf_params.ooo_enable) {
  1839. DP_VERBOSE(cdev, QED_MSG_STORAGE, "Starting OOO LL2 queue\n");
  1840. rc = qed_ll2_start_ooo(cdev, params);
  1841. if (rc) {
  1842. DP_INFO(cdev,
  1843. "Failed to initialize the OOO LL2 queue\n");
  1844. goto release_terminate;
  1845. }
  1846. }
  1847. p_ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev));
  1848. if (!p_ptt) {
  1849. DP_INFO(cdev, "Failed to acquire PTT\n");
  1850. goto release_terminate;
  1851. }
  1852. rc = qed_llh_add_mac_filter(QED_LEADING_HWFN(cdev), p_ptt,
  1853. params->ll2_mac_address);
  1854. qed_ptt_release(QED_LEADING_HWFN(cdev), p_ptt);
  1855. if (rc) {
  1856. DP_ERR(cdev, "Failed to allocate LLH filter\n");
  1857. goto release_terminate_all;
  1858. }
  1859. ether_addr_copy(cdev->ll2_mac_address, params->ll2_mac_address);
  1860. return 0;
  1861. release_terminate_all:
  1862. release_terminate:
  1863. qed_ll2_terminate_connection(QED_LEADING_HWFN(cdev), cdev->ll2->handle);
  1864. release_fail:
  1865. qed_ll2_release_connection(QED_LEADING_HWFN(cdev), cdev->ll2->handle);
  1866. fail:
  1867. qed_ll2_kill_buffers(cdev);
  1868. cdev->ll2->handle = QED_LL2_UNUSED_HANDLE;
  1869. return -EINVAL;
  1870. }
  1871. static int qed_ll2_stop(struct qed_dev *cdev)
  1872. {
  1873. struct qed_ptt *p_ptt;
  1874. int rc;
  1875. if (cdev->ll2->handle == QED_LL2_UNUSED_HANDLE)
  1876. return 0;
  1877. p_ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev));
  1878. if (!p_ptt) {
  1879. DP_INFO(cdev, "Failed to acquire PTT\n");
  1880. goto fail;
  1881. }
  1882. qed_llh_remove_mac_filter(QED_LEADING_HWFN(cdev), p_ptt,
  1883. cdev->ll2_mac_address);
  1884. qed_ptt_release(QED_LEADING_HWFN(cdev), p_ptt);
  1885. eth_zero_addr(cdev->ll2_mac_address);
  1886. if (cdev->hwfns[0].hw_info.personality == QED_PCI_ISCSI &&
  1887. cdev->hwfns[0].pf_params.iscsi_pf_params.ooo_enable)
  1888. qed_ll2_stop_ooo(cdev);
  1889. rc = qed_ll2_terminate_connection(QED_LEADING_HWFN(cdev),
  1890. cdev->ll2->handle);
  1891. if (rc)
  1892. DP_INFO(cdev, "Failed to terminate LL2 connection\n");
  1893. qed_ll2_kill_buffers(cdev);
  1894. qed_ll2_release_connection(QED_LEADING_HWFN(cdev), cdev->ll2->handle);
  1895. cdev->ll2->handle = QED_LL2_UNUSED_HANDLE;
  1896. return rc;
  1897. fail:
  1898. return -EINVAL;
  1899. }
  1900. static int qed_ll2_start_xmit(struct qed_dev *cdev, struct sk_buff *skb)
  1901. {
  1902. const skb_frag_t *frag;
  1903. int rc = -EINVAL, i;
  1904. dma_addr_t mapping;
  1905. u16 vlan = 0;
  1906. u8 flags = 0;
  1907. if (unlikely(skb->ip_summed != CHECKSUM_NONE)) {
  1908. DP_INFO(cdev, "Cannot transmit a checksumed packet\n");
  1909. return -EINVAL;
  1910. }
  1911. if (1 + skb_shinfo(skb)->nr_frags > CORE_LL2_TX_MAX_BDS_PER_PACKET) {
  1912. DP_ERR(cdev, "Cannot transmit a packet with %d fragments\n",
  1913. 1 + skb_shinfo(skb)->nr_frags);
  1914. return -EINVAL;
  1915. }
  1916. mapping = dma_map_single(&cdev->pdev->dev, skb->data,
  1917. skb->len, DMA_TO_DEVICE);
  1918. if (unlikely(dma_mapping_error(&cdev->pdev->dev, mapping))) {
  1919. DP_NOTICE(cdev, "SKB mapping failed\n");
  1920. return -EINVAL;
  1921. }
  1922. /* Request HW to calculate IP csum */
  1923. if (!((vlan_get_protocol(skb) == htons(ETH_P_IPV6)) &&
  1924. ipv6_hdr(skb)->nexthdr == NEXTHDR_IPV6))
  1925. flags |= BIT(CORE_TX_BD_DATA_IP_CSUM_SHIFT);
  1926. if (skb_vlan_tag_present(skb)) {
  1927. vlan = skb_vlan_tag_get(skb);
  1928. flags |= BIT(CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT);
  1929. }
  1930. rc = qed_ll2_prepare_tx_packet(QED_LEADING_HWFN(cdev),
  1931. cdev->ll2->handle,
  1932. 1 + skb_shinfo(skb)->nr_frags,
  1933. vlan, flags, 0, QED_LL2_TX_DEST_NW,
  1934. 0 /* RoCE FLAVOR */,
  1935. mapping, skb->len, skb, 1);
  1936. if (rc)
  1937. goto err;
  1938. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  1939. frag = &skb_shinfo(skb)->frags[i];
  1940. if (!cdev->ll2->frags_mapped) {
  1941. mapping = skb_frag_dma_map(&cdev->pdev->dev, frag, 0,
  1942. skb_frag_size(frag),
  1943. DMA_TO_DEVICE);
  1944. if (unlikely(dma_mapping_error(&cdev->pdev->dev,
  1945. mapping))) {
  1946. DP_NOTICE(cdev,
  1947. "Unable to map frag - dropping packet\n");
  1948. rc = -ENOMEM;
  1949. goto err;
  1950. }
  1951. } else {
  1952. mapping = page_to_phys(skb_frag_page(frag)) |
  1953. frag->page_offset;
  1954. }
  1955. rc = qed_ll2_set_fragment_of_tx_packet(QED_LEADING_HWFN(cdev),
  1956. cdev->ll2->handle,
  1957. mapping,
  1958. skb_frag_size(frag));
  1959. /* if failed not much to do here, partial packet has been posted
  1960. * we can't free memory, will need to wait for completion.
  1961. */
  1962. if (rc)
  1963. goto err2;
  1964. }
  1965. return 0;
  1966. err:
  1967. dma_unmap_single(&cdev->pdev->dev, mapping, skb->len, DMA_TO_DEVICE);
  1968. err2:
  1969. return rc;
  1970. }
  1971. static int qed_ll2_stats(struct qed_dev *cdev, struct qed_ll2_stats *stats)
  1972. {
  1973. if (!cdev->ll2)
  1974. return -EINVAL;
  1975. return qed_ll2_get_stats(QED_LEADING_HWFN(cdev),
  1976. cdev->ll2->handle, stats);
  1977. }
  1978. const struct qed_ll2_ops qed_ll2_ops_pass = {
  1979. .start = &qed_ll2_start,
  1980. .stop = &qed_ll2_stop,
  1981. .start_xmit = &qed_ll2_start_xmit,
  1982. .register_cb_ops = &qed_ll2_register_cb_ops,
  1983. .get_stats = &qed_ll2_stats,
  1984. };
  1985. int qed_ll2_alloc_if(struct qed_dev *cdev)
  1986. {
  1987. cdev->ll2 = kzalloc(sizeof(*cdev->ll2), GFP_KERNEL);
  1988. return cdev->ll2 ? 0 : -ENOMEM;
  1989. }
  1990. void qed_ll2_dealloc_if(struct qed_dev *cdev)
  1991. {
  1992. kfree(cdev->ll2);
  1993. cdev->ll2 = NULL;
  1994. }