qed_l2.c 73 KB

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  1. /* QLogic qed NIC Driver
  2. * Copyright (c) 2015-2017 QLogic Corporation
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and /or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/types.h>
  33. #include <asm/byteorder.h>
  34. #include <asm/param.h>
  35. #include <linux/delay.h>
  36. #include <linux/dma-mapping.h>
  37. #include <linux/etherdevice.h>
  38. #include <linux/interrupt.h>
  39. #include <linux/kernel.h>
  40. #include <linux/module.h>
  41. #include <linux/pci.h>
  42. #include <linux/slab.h>
  43. #include <linux/stddef.h>
  44. #include <linux/string.h>
  45. #include <linux/version.h>
  46. #include <linux/workqueue.h>
  47. #include <linux/bitops.h>
  48. #include <linux/bug.h>
  49. #include <linux/vmalloc.h>
  50. #include "qed.h"
  51. #include <linux/qed/qed_chain.h>
  52. #include "qed_cxt.h"
  53. #include "qed_dev_api.h"
  54. #include <linux/qed/qed_eth_if.h>
  55. #include "qed_hsi.h"
  56. #include "qed_hw.h"
  57. #include "qed_int.h"
  58. #include "qed_l2.h"
  59. #include "qed_mcp.h"
  60. #include "qed_reg_addr.h"
  61. #include "qed_sp.h"
  62. #include "qed_sriov.h"
  63. #define QED_MAX_SGES_NUM 16
  64. #define CRC32_POLY 0x1edc6f41
  65. void qed_eth_queue_cid_release(struct qed_hwfn *p_hwfn,
  66. struct qed_queue_cid *p_cid)
  67. {
  68. /* VFs' CIDs are 0-based in PF-view, and uninitialized on VF */
  69. if (!p_cid->is_vf && IS_PF(p_hwfn->cdev))
  70. qed_cxt_release_cid(p_hwfn, p_cid->cid);
  71. vfree(p_cid);
  72. }
  73. /* The internal is only meant to be directly called by PFs initializeing CIDs
  74. * for their VFs.
  75. */
  76. struct qed_queue_cid *
  77. _qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn,
  78. u16 opaque_fid,
  79. u32 cid,
  80. u8 vf_qid,
  81. struct qed_queue_start_common_params *p_params)
  82. {
  83. bool b_is_same = (p_hwfn->hw_info.opaque_fid == opaque_fid);
  84. struct qed_queue_cid *p_cid;
  85. int rc;
  86. p_cid = vmalloc(sizeof(*p_cid));
  87. if (!p_cid)
  88. return NULL;
  89. memset(p_cid, 0, sizeof(*p_cid));
  90. p_cid->opaque_fid = opaque_fid;
  91. p_cid->cid = cid;
  92. p_cid->vf_qid = vf_qid;
  93. p_cid->rel = *p_params;
  94. p_cid->p_owner = p_hwfn;
  95. /* Don't try calculating the absolute indices for VFs */
  96. if (IS_VF(p_hwfn->cdev)) {
  97. p_cid->abs = p_cid->rel;
  98. goto out;
  99. }
  100. /* Calculate the engine-absolute indices of the resources.
  101. * This would guarantee they're valid later on.
  102. * In some cases [SBs] we already have the right values.
  103. */
  104. rc = qed_fw_vport(p_hwfn, p_cid->rel.vport_id, &p_cid->abs.vport_id);
  105. if (rc)
  106. goto fail;
  107. rc = qed_fw_l2_queue(p_hwfn, p_cid->rel.queue_id, &p_cid->abs.queue_id);
  108. if (rc)
  109. goto fail;
  110. /* In case of a PF configuring its VF's queues, the stats-id is already
  111. * absolute [since there's a single index that's suitable per-VF].
  112. */
  113. if (b_is_same) {
  114. rc = qed_fw_vport(p_hwfn, p_cid->rel.stats_id,
  115. &p_cid->abs.stats_id);
  116. if (rc)
  117. goto fail;
  118. } else {
  119. p_cid->abs.stats_id = p_cid->rel.stats_id;
  120. }
  121. /* SBs relevant information was already provided as absolute */
  122. p_cid->abs.sb = p_cid->rel.sb;
  123. p_cid->abs.sb_idx = p_cid->rel.sb_idx;
  124. /* This is tricky - we're actually interested in whehter this is a PF
  125. * entry meant for the VF.
  126. */
  127. if (!b_is_same)
  128. p_cid->is_vf = true;
  129. out:
  130. DP_VERBOSE(p_hwfn,
  131. QED_MSG_SP,
  132. "opaque_fid: %04x CID %08x vport %02x [%02x] qzone %04x [%04x] stats %02x [%02x] SB %04x PI %02x\n",
  133. p_cid->opaque_fid,
  134. p_cid->cid,
  135. p_cid->rel.vport_id,
  136. p_cid->abs.vport_id,
  137. p_cid->rel.queue_id,
  138. p_cid->abs.queue_id,
  139. p_cid->rel.stats_id,
  140. p_cid->abs.stats_id, p_cid->abs.sb, p_cid->abs.sb_idx);
  141. return p_cid;
  142. fail:
  143. vfree(p_cid);
  144. return NULL;
  145. }
  146. static struct qed_queue_cid *qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn,
  147. u16 opaque_fid, struct
  148. qed_queue_start_common_params
  149. *p_params)
  150. {
  151. struct qed_queue_cid *p_cid;
  152. u32 cid = 0;
  153. /* Get a unique firmware CID for this queue, in case it's a PF.
  154. * VF's don't need a CID as the queue configuration will be done
  155. * by PF.
  156. */
  157. if (IS_PF(p_hwfn->cdev)) {
  158. if (qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, &cid)) {
  159. DP_NOTICE(p_hwfn, "Failed to acquire cid\n");
  160. return NULL;
  161. }
  162. }
  163. p_cid = _qed_eth_queue_to_cid(p_hwfn, opaque_fid, cid, 0, p_params);
  164. if (!p_cid && IS_PF(p_hwfn->cdev))
  165. qed_cxt_release_cid(p_hwfn, cid);
  166. return p_cid;
  167. }
  168. int qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn,
  169. struct qed_sp_vport_start_params *p_params)
  170. {
  171. struct vport_start_ramrod_data *p_ramrod = NULL;
  172. struct qed_spq_entry *p_ent = NULL;
  173. struct qed_sp_init_data init_data;
  174. u8 abs_vport_id = 0;
  175. int rc = -EINVAL;
  176. u16 rx_mode = 0;
  177. rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
  178. if (rc)
  179. return rc;
  180. memset(&init_data, 0, sizeof(init_data));
  181. init_data.cid = qed_spq_get_cid(p_hwfn);
  182. init_data.opaque_fid = p_params->opaque_fid;
  183. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  184. rc = qed_sp_init_request(p_hwfn, &p_ent,
  185. ETH_RAMROD_VPORT_START,
  186. PROTOCOLID_ETH, &init_data);
  187. if (rc)
  188. return rc;
  189. p_ramrod = &p_ent->ramrod.vport_start;
  190. p_ramrod->vport_id = abs_vport_id;
  191. p_ramrod->mtu = cpu_to_le16(p_params->mtu);
  192. p_ramrod->handle_ptp_pkts = p_params->handle_ptp_pkts;
  193. p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan;
  194. p_ramrod->drop_ttl0_en = p_params->drop_ttl0;
  195. p_ramrod->untagged = p_params->only_untagged;
  196. SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
  197. SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
  198. p_ramrod->rx_mode.state = cpu_to_le16(rx_mode);
  199. /* TPA related fields */
  200. memset(&p_ramrod->tpa_param, 0, sizeof(struct eth_vport_tpa_param));
  201. p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe;
  202. switch (p_params->tpa_mode) {
  203. case QED_TPA_MODE_GRO:
  204. p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
  205. p_ramrod->tpa_param.tpa_max_size = (u16)-1;
  206. p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2;
  207. p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2;
  208. p_ramrod->tpa_param.tpa_ipv4_en_flg = 1;
  209. p_ramrod->tpa_param.tpa_ipv6_en_flg = 1;
  210. p_ramrod->tpa_param.tpa_pkt_split_flg = 1;
  211. p_ramrod->tpa_param.tpa_gro_consistent_flg = 1;
  212. break;
  213. default:
  214. break;
  215. }
  216. p_ramrod->tx_switching_en = p_params->tx_switching;
  217. p_ramrod->ctl_frame_mac_check_en = !!p_params->check_mac;
  218. p_ramrod->ctl_frame_ethtype_check_en = !!p_params->check_ethtype;
  219. /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
  220. p_ramrod->sw_fid = qed_concrete_to_sw_fid(p_hwfn->cdev,
  221. p_params->concrete_fid);
  222. return qed_spq_post(p_hwfn, p_ent, NULL);
  223. }
  224. static int qed_sp_vport_start(struct qed_hwfn *p_hwfn,
  225. struct qed_sp_vport_start_params *p_params)
  226. {
  227. if (IS_VF(p_hwfn->cdev)) {
  228. return qed_vf_pf_vport_start(p_hwfn, p_params->vport_id,
  229. p_params->mtu,
  230. p_params->remove_inner_vlan,
  231. p_params->tpa_mode,
  232. p_params->max_buffers_per_cqe,
  233. p_params->only_untagged);
  234. }
  235. return qed_sp_eth_vport_start(p_hwfn, p_params);
  236. }
  237. static int
  238. qed_sp_vport_update_rss(struct qed_hwfn *p_hwfn,
  239. struct vport_update_ramrod_data *p_ramrod,
  240. struct qed_rss_params *p_rss)
  241. {
  242. struct eth_vport_rss_config *p_config;
  243. u16 capabilities = 0;
  244. int i, table_size;
  245. int rc = 0;
  246. if (!p_rss) {
  247. p_ramrod->common.update_rss_flg = 0;
  248. return rc;
  249. }
  250. p_config = &p_ramrod->rss_config;
  251. BUILD_BUG_ON(QED_RSS_IND_TABLE_SIZE != ETH_RSS_IND_TABLE_ENTRIES_NUM);
  252. rc = qed_fw_rss_eng(p_hwfn, p_rss->rss_eng_id, &p_config->rss_id);
  253. if (rc)
  254. return rc;
  255. p_ramrod->common.update_rss_flg = p_rss->update_rss_config;
  256. p_config->update_rss_capabilities = p_rss->update_rss_capabilities;
  257. p_config->update_rss_ind_table = p_rss->update_rss_ind_table;
  258. p_config->update_rss_key = p_rss->update_rss_key;
  259. p_config->rss_mode = p_rss->rss_enable ?
  260. ETH_VPORT_RSS_MODE_REGULAR :
  261. ETH_VPORT_RSS_MODE_DISABLED;
  262. SET_FIELD(capabilities,
  263. ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
  264. !!(p_rss->rss_caps & QED_RSS_IPV4));
  265. SET_FIELD(capabilities,
  266. ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
  267. !!(p_rss->rss_caps & QED_RSS_IPV6));
  268. SET_FIELD(capabilities,
  269. ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
  270. !!(p_rss->rss_caps & QED_RSS_IPV4_TCP));
  271. SET_FIELD(capabilities,
  272. ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
  273. !!(p_rss->rss_caps & QED_RSS_IPV6_TCP));
  274. SET_FIELD(capabilities,
  275. ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
  276. !!(p_rss->rss_caps & QED_RSS_IPV4_UDP));
  277. SET_FIELD(capabilities,
  278. ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
  279. !!(p_rss->rss_caps & QED_RSS_IPV6_UDP));
  280. p_config->tbl_size = p_rss->rss_table_size_log;
  281. p_config->capabilities = cpu_to_le16(capabilities);
  282. DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
  283. "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
  284. p_ramrod->common.update_rss_flg,
  285. p_config->rss_mode,
  286. p_config->update_rss_capabilities,
  287. p_config->capabilities,
  288. p_config->update_rss_ind_table, p_config->update_rss_key);
  289. table_size = min_t(int, QED_RSS_IND_TABLE_SIZE,
  290. 1 << p_config->tbl_size);
  291. for (i = 0; i < table_size; i++) {
  292. struct qed_queue_cid *p_queue = p_rss->rss_ind_table[i];
  293. if (!p_queue)
  294. return -EINVAL;
  295. p_config->indirection_table[i] =
  296. cpu_to_le16(p_queue->abs.queue_id);
  297. }
  298. DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
  299. "Configured RSS indirection table [%d entries]:\n",
  300. table_size);
  301. for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i += 0x10) {
  302. DP_VERBOSE(p_hwfn,
  303. NETIF_MSG_IFUP,
  304. "%04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x\n",
  305. le16_to_cpu(p_config->indirection_table[i]),
  306. le16_to_cpu(p_config->indirection_table[i + 1]),
  307. le16_to_cpu(p_config->indirection_table[i + 2]),
  308. le16_to_cpu(p_config->indirection_table[i + 3]),
  309. le16_to_cpu(p_config->indirection_table[i + 4]),
  310. le16_to_cpu(p_config->indirection_table[i + 5]),
  311. le16_to_cpu(p_config->indirection_table[i + 6]),
  312. le16_to_cpu(p_config->indirection_table[i + 7]),
  313. le16_to_cpu(p_config->indirection_table[i + 8]),
  314. le16_to_cpu(p_config->indirection_table[i + 9]),
  315. le16_to_cpu(p_config->indirection_table[i + 10]),
  316. le16_to_cpu(p_config->indirection_table[i + 11]),
  317. le16_to_cpu(p_config->indirection_table[i + 12]),
  318. le16_to_cpu(p_config->indirection_table[i + 13]),
  319. le16_to_cpu(p_config->indirection_table[i + 14]),
  320. le16_to_cpu(p_config->indirection_table[i + 15]));
  321. }
  322. for (i = 0; i < 10; i++)
  323. p_config->rss_key[i] = cpu_to_le32(p_rss->rss_key[i]);
  324. return rc;
  325. }
  326. static void
  327. qed_sp_update_accept_mode(struct qed_hwfn *p_hwfn,
  328. struct vport_update_ramrod_data *p_ramrod,
  329. struct qed_filter_accept_flags accept_flags)
  330. {
  331. p_ramrod->common.update_rx_mode_flg =
  332. accept_flags.update_rx_mode_config;
  333. p_ramrod->common.update_tx_mode_flg =
  334. accept_flags.update_tx_mode_config;
  335. /* Set Rx mode accept flags */
  336. if (p_ramrod->common.update_rx_mode_flg) {
  337. u8 accept_filter = accept_flags.rx_accept_filter;
  338. u16 state = 0;
  339. SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
  340. !(!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) ||
  341. !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)));
  342. SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
  343. !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED));
  344. SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
  345. !(!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) ||
  346. !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
  347. SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
  348. (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
  349. !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
  350. SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
  351. !!(accept_filter & QED_ACCEPT_BCAST));
  352. p_ramrod->rx_mode.state = cpu_to_le16(state);
  353. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  354. "p_ramrod->rx_mode.state = 0x%x\n", state);
  355. }
  356. /* Set Tx mode accept flags */
  357. if (p_ramrod->common.update_tx_mode_flg) {
  358. u8 accept_filter = accept_flags.tx_accept_filter;
  359. u16 state = 0;
  360. SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
  361. !!(accept_filter & QED_ACCEPT_NONE));
  362. SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
  363. !!(accept_filter & QED_ACCEPT_NONE));
  364. SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
  365. (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
  366. !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
  367. SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
  368. !!(accept_filter & QED_ACCEPT_BCAST));
  369. p_ramrod->tx_mode.state = cpu_to_le16(state);
  370. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  371. "p_ramrod->tx_mode.state = 0x%x\n", state);
  372. }
  373. }
  374. static void
  375. qed_sp_vport_update_sge_tpa(struct qed_hwfn *p_hwfn,
  376. struct vport_update_ramrod_data *p_ramrod,
  377. struct qed_sge_tpa_params *p_params)
  378. {
  379. struct eth_vport_tpa_param *p_tpa;
  380. if (!p_params) {
  381. p_ramrod->common.update_tpa_param_flg = 0;
  382. p_ramrod->common.update_tpa_en_flg = 0;
  383. p_ramrod->common.update_tpa_param_flg = 0;
  384. return;
  385. }
  386. p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg;
  387. p_tpa = &p_ramrod->tpa_param;
  388. p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg;
  389. p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg;
  390. p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg;
  391. p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg;
  392. p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg;
  393. p_tpa->max_buff_num = p_params->max_buffers_per_cqe;
  394. p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg;
  395. p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg;
  396. p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg;
  397. p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num;
  398. p_tpa->tpa_max_size = p_params->tpa_max_size;
  399. p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start;
  400. p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont;
  401. }
  402. static void
  403. qed_sp_update_mcast_bin(struct qed_hwfn *p_hwfn,
  404. struct vport_update_ramrod_data *p_ramrod,
  405. struct qed_sp_vport_update_params *p_params)
  406. {
  407. int i;
  408. memset(&p_ramrod->approx_mcast.bins, 0,
  409. sizeof(p_ramrod->approx_mcast.bins));
  410. if (!p_params->update_approx_mcast_flg)
  411. return;
  412. p_ramrod->common.update_approx_mcast_flg = 1;
  413. for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
  414. u32 *p_bins = (u32 *)p_params->bins;
  415. p_ramrod->approx_mcast.bins[i] = cpu_to_le32(p_bins[i]);
  416. }
  417. }
  418. int qed_sp_vport_update(struct qed_hwfn *p_hwfn,
  419. struct qed_sp_vport_update_params *p_params,
  420. enum spq_mode comp_mode,
  421. struct qed_spq_comp_cb *p_comp_data)
  422. {
  423. struct qed_rss_params *p_rss_params = p_params->rss_params;
  424. struct vport_update_ramrod_data_cmn *p_cmn;
  425. struct qed_sp_init_data init_data;
  426. struct vport_update_ramrod_data *p_ramrod = NULL;
  427. struct qed_spq_entry *p_ent = NULL;
  428. u8 abs_vport_id = 0, val;
  429. int rc = -EINVAL;
  430. if (IS_VF(p_hwfn->cdev)) {
  431. rc = qed_vf_pf_vport_update(p_hwfn, p_params);
  432. return rc;
  433. }
  434. rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
  435. if (rc)
  436. return rc;
  437. memset(&init_data, 0, sizeof(init_data));
  438. init_data.cid = qed_spq_get_cid(p_hwfn);
  439. init_data.opaque_fid = p_params->opaque_fid;
  440. init_data.comp_mode = comp_mode;
  441. init_data.p_comp_data = p_comp_data;
  442. rc = qed_sp_init_request(p_hwfn, &p_ent,
  443. ETH_RAMROD_VPORT_UPDATE,
  444. PROTOCOLID_ETH, &init_data);
  445. if (rc)
  446. return rc;
  447. /* Copy input params to ramrod according to FW struct */
  448. p_ramrod = &p_ent->ramrod.vport_update;
  449. p_cmn = &p_ramrod->common;
  450. p_cmn->vport_id = abs_vport_id;
  451. p_cmn->rx_active_flg = p_params->vport_active_rx_flg;
  452. p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg;
  453. p_cmn->tx_active_flg = p_params->vport_active_tx_flg;
  454. p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg;
  455. p_cmn->accept_any_vlan = p_params->accept_any_vlan;
  456. val = p_params->update_accept_any_vlan_flg;
  457. p_cmn->update_accept_any_vlan_flg = val;
  458. p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg;
  459. val = p_params->update_inner_vlan_removal_flg;
  460. p_cmn->update_inner_vlan_removal_en_flg = val;
  461. p_cmn->default_vlan_en = p_params->default_vlan_enable_flg;
  462. val = p_params->update_default_vlan_enable_flg;
  463. p_cmn->update_default_vlan_en_flg = val;
  464. p_cmn->default_vlan = cpu_to_le16(p_params->default_vlan);
  465. p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg;
  466. p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg;
  467. p_ramrod->common.tx_switching_en = p_params->tx_switching_flg;
  468. p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg;
  469. p_cmn->anti_spoofing_en = p_params->anti_spoofing_en;
  470. val = p_params->update_anti_spoofing_en_flg;
  471. p_ramrod->common.update_anti_spoofing_en_flg = val;
  472. rc = qed_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
  473. if (rc) {
  474. /* Return spq entry which is taken in qed_sp_init_request()*/
  475. qed_spq_return_entry(p_hwfn, p_ent);
  476. return rc;
  477. }
  478. /* Update mcast bins for VFs, PF doesn't use this functionality */
  479. qed_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params);
  480. qed_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
  481. qed_sp_vport_update_sge_tpa(p_hwfn, p_ramrod, p_params->sge_tpa_params);
  482. return qed_spq_post(p_hwfn, p_ent, NULL);
  483. }
  484. int qed_sp_vport_stop(struct qed_hwfn *p_hwfn, u16 opaque_fid, u8 vport_id)
  485. {
  486. struct vport_stop_ramrod_data *p_ramrod;
  487. struct qed_sp_init_data init_data;
  488. struct qed_spq_entry *p_ent;
  489. u8 abs_vport_id = 0;
  490. int rc;
  491. if (IS_VF(p_hwfn->cdev))
  492. return qed_vf_pf_vport_stop(p_hwfn);
  493. rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id);
  494. if (rc)
  495. return rc;
  496. memset(&init_data, 0, sizeof(init_data));
  497. init_data.cid = qed_spq_get_cid(p_hwfn);
  498. init_data.opaque_fid = opaque_fid;
  499. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  500. rc = qed_sp_init_request(p_hwfn, &p_ent,
  501. ETH_RAMROD_VPORT_STOP,
  502. PROTOCOLID_ETH, &init_data);
  503. if (rc)
  504. return rc;
  505. p_ramrod = &p_ent->ramrod.vport_stop;
  506. p_ramrod->vport_id = abs_vport_id;
  507. return qed_spq_post(p_hwfn, p_ent, NULL);
  508. }
  509. static int
  510. qed_vf_pf_accept_flags(struct qed_hwfn *p_hwfn,
  511. struct qed_filter_accept_flags *p_accept_flags)
  512. {
  513. struct qed_sp_vport_update_params s_params;
  514. memset(&s_params, 0, sizeof(s_params));
  515. memcpy(&s_params.accept_flags, p_accept_flags,
  516. sizeof(struct qed_filter_accept_flags));
  517. return qed_vf_pf_vport_update(p_hwfn, &s_params);
  518. }
  519. static int qed_filter_accept_cmd(struct qed_dev *cdev,
  520. u8 vport,
  521. struct qed_filter_accept_flags accept_flags,
  522. u8 update_accept_any_vlan,
  523. u8 accept_any_vlan,
  524. enum spq_mode comp_mode,
  525. struct qed_spq_comp_cb *p_comp_data)
  526. {
  527. struct qed_sp_vport_update_params vport_update_params;
  528. int i, rc;
  529. /* Prepare and send the vport rx_mode change */
  530. memset(&vport_update_params, 0, sizeof(vport_update_params));
  531. vport_update_params.vport_id = vport;
  532. vport_update_params.accept_flags = accept_flags;
  533. vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
  534. vport_update_params.accept_any_vlan = accept_any_vlan;
  535. for_each_hwfn(cdev, i) {
  536. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  537. vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
  538. if (IS_VF(cdev)) {
  539. rc = qed_vf_pf_accept_flags(p_hwfn, &accept_flags);
  540. if (rc)
  541. return rc;
  542. continue;
  543. }
  544. rc = qed_sp_vport_update(p_hwfn, &vport_update_params,
  545. comp_mode, p_comp_data);
  546. if (rc) {
  547. DP_ERR(cdev, "Update rx_mode failed %d\n", rc);
  548. return rc;
  549. }
  550. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  551. "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
  552. accept_flags.rx_accept_filter,
  553. accept_flags.tx_accept_filter);
  554. if (update_accept_any_vlan)
  555. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  556. "accept_any_vlan=%d configured\n",
  557. accept_any_vlan);
  558. }
  559. return 0;
  560. }
  561. int qed_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn,
  562. struct qed_queue_cid *p_cid,
  563. u16 bd_max_bytes,
  564. dma_addr_t bd_chain_phys_addr,
  565. dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size)
  566. {
  567. struct rx_queue_start_ramrod_data *p_ramrod = NULL;
  568. struct qed_spq_entry *p_ent = NULL;
  569. struct qed_sp_init_data init_data;
  570. int rc = -EINVAL;
  571. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  572. "opaque_fid=0x%x, cid=0x%x, rx_qzone=0x%x, vport_id=0x%x, sb_id=0x%x\n",
  573. p_cid->opaque_fid, p_cid->cid,
  574. p_cid->abs.queue_id, p_cid->abs.vport_id, p_cid->abs.sb);
  575. /* Get SPQ entry */
  576. memset(&init_data, 0, sizeof(init_data));
  577. init_data.cid = p_cid->cid;
  578. init_data.opaque_fid = p_cid->opaque_fid;
  579. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  580. rc = qed_sp_init_request(p_hwfn, &p_ent,
  581. ETH_RAMROD_RX_QUEUE_START,
  582. PROTOCOLID_ETH, &init_data);
  583. if (rc)
  584. return rc;
  585. p_ramrod = &p_ent->ramrod.rx_queue_start;
  586. p_ramrod->sb_id = cpu_to_le16(p_cid->abs.sb);
  587. p_ramrod->sb_index = p_cid->abs.sb_idx;
  588. p_ramrod->vport_id = p_cid->abs.vport_id;
  589. p_ramrod->stats_counter_id = p_cid->abs.stats_id;
  590. p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
  591. p_ramrod->complete_cqe_flg = 0;
  592. p_ramrod->complete_event_flg = 1;
  593. p_ramrod->bd_max_bytes = cpu_to_le16(bd_max_bytes);
  594. DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr);
  595. p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size);
  596. DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
  597. if (p_cid->is_vf) {
  598. p_ramrod->vf_rx_prod_index = p_cid->vf_qid;
  599. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  600. "Queue%s is meant for VF rxq[%02x]\n",
  601. !!p_cid->b_legacy_vf ? " [legacy]" : "",
  602. p_cid->vf_qid);
  603. p_ramrod->vf_rx_prod_use_zone_a = !!p_cid->b_legacy_vf;
  604. }
  605. return qed_spq_post(p_hwfn, p_ent, NULL);
  606. }
  607. static int
  608. qed_eth_pf_rx_queue_start(struct qed_hwfn *p_hwfn,
  609. struct qed_queue_cid *p_cid,
  610. u16 bd_max_bytes,
  611. dma_addr_t bd_chain_phys_addr,
  612. dma_addr_t cqe_pbl_addr,
  613. u16 cqe_pbl_size, void __iomem **pp_prod)
  614. {
  615. u32 init_prod_val = 0;
  616. *pp_prod = p_hwfn->regview +
  617. GTT_BAR0_MAP_REG_MSDM_RAM +
  618. MSTORM_ETH_PF_PRODS_OFFSET(p_cid->abs.queue_id);
  619. /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
  620. __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
  621. (u32 *)(&init_prod_val));
  622. return qed_eth_rxq_start_ramrod(p_hwfn, p_cid,
  623. bd_max_bytes,
  624. bd_chain_phys_addr,
  625. cqe_pbl_addr, cqe_pbl_size);
  626. }
  627. static int
  628. qed_eth_rx_queue_start(struct qed_hwfn *p_hwfn,
  629. u16 opaque_fid,
  630. struct qed_queue_start_common_params *p_params,
  631. u16 bd_max_bytes,
  632. dma_addr_t bd_chain_phys_addr,
  633. dma_addr_t cqe_pbl_addr,
  634. u16 cqe_pbl_size,
  635. struct qed_rxq_start_ret_params *p_ret_params)
  636. {
  637. struct qed_queue_cid *p_cid;
  638. int rc;
  639. /* Allocate a CID for the queue */
  640. p_cid = qed_eth_queue_to_cid(p_hwfn, opaque_fid, p_params);
  641. if (!p_cid)
  642. return -ENOMEM;
  643. if (IS_PF(p_hwfn->cdev)) {
  644. rc = qed_eth_pf_rx_queue_start(p_hwfn, p_cid,
  645. bd_max_bytes,
  646. bd_chain_phys_addr,
  647. cqe_pbl_addr, cqe_pbl_size,
  648. &p_ret_params->p_prod);
  649. } else {
  650. rc = qed_vf_pf_rxq_start(p_hwfn, p_cid,
  651. bd_max_bytes,
  652. bd_chain_phys_addr,
  653. cqe_pbl_addr,
  654. cqe_pbl_size, &p_ret_params->p_prod);
  655. }
  656. /* Provide the caller with a reference to as handler */
  657. if (rc)
  658. qed_eth_queue_cid_release(p_hwfn, p_cid);
  659. else
  660. p_ret_params->p_handle = (void *)p_cid;
  661. return rc;
  662. }
  663. int qed_sp_eth_rx_queues_update(struct qed_hwfn *p_hwfn,
  664. void **pp_rxq_handles,
  665. u8 num_rxqs,
  666. u8 complete_cqe_flg,
  667. u8 complete_event_flg,
  668. enum spq_mode comp_mode,
  669. struct qed_spq_comp_cb *p_comp_data)
  670. {
  671. struct rx_queue_update_ramrod_data *p_ramrod = NULL;
  672. struct qed_spq_entry *p_ent = NULL;
  673. struct qed_sp_init_data init_data;
  674. struct qed_queue_cid *p_cid;
  675. int rc = -EINVAL;
  676. u8 i;
  677. memset(&init_data, 0, sizeof(init_data));
  678. init_data.comp_mode = comp_mode;
  679. init_data.p_comp_data = p_comp_data;
  680. for (i = 0; i < num_rxqs; i++) {
  681. p_cid = ((struct qed_queue_cid **)pp_rxq_handles)[i];
  682. /* Get SPQ entry */
  683. init_data.cid = p_cid->cid;
  684. init_data.opaque_fid = p_cid->opaque_fid;
  685. rc = qed_sp_init_request(p_hwfn, &p_ent,
  686. ETH_RAMROD_RX_QUEUE_UPDATE,
  687. PROTOCOLID_ETH, &init_data);
  688. if (rc)
  689. return rc;
  690. p_ramrod = &p_ent->ramrod.rx_queue_update;
  691. p_ramrod->vport_id = p_cid->abs.vport_id;
  692. p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
  693. p_ramrod->complete_cqe_flg = complete_cqe_flg;
  694. p_ramrod->complete_event_flg = complete_event_flg;
  695. rc = qed_spq_post(p_hwfn, p_ent, NULL);
  696. if (rc)
  697. return rc;
  698. }
  699. return rc;
  700. }
  701. static int
  702. qed_eth_pf_rx_queue_stop(struct qed_hwfn *p_hwfn,
  703. struct qed_queue_cid *p_cid,
  704. bool b_eq_completion_only, bool b_cqe_completion)
  705. {
  706. struct rx_queue_stop_ramrod_data *p_ramrod = NULL;
  707. struct qed_spq_entry *p_ent = NULL;
  708. struct qed_sp_init_data init_data;
  709. int rc;
  710. memset(&init_data, 0, sizeof(init_data));
  711. init_data.cid = p_cid->cid;
  712. init_data.opaque_fid = p_cid->opaque_fid;
  713. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  714. rc = qed_sp_init_request(p_hwfn, &p_ent,
  715. ETH_RAMROD_RX_QUEUE_STOP,
  716. PROTOCOLID_ETH, &init_data);
  717. if (rc)
  718. return rc;
  719. p_ramrod = &p_ent->ramrod.rx_queue_stop;
  720. p_ramrod->vport_id = p_cid->abs.vport_id;
  721. p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
  722. /* Cleaning the queue requires the completion to arrive there.
  723. * In addition, VFs require the answer to come as eqe to PF.
  724. */
  725. p_ramrod->complete_cqe_flg = (!p_cid->is_vf &&
  726. !b_eq_completion_only) ||
  727. b_cqe_completion;
  728. p_ramrod->complete_event_flg = p_cid->is_vf || b_eq_completion_only;
  729. return qed_spq_post(p_hwfn, p_ent, NULL);
  730. }
  731. int qed_eth_rx_queue_stop(struct qed_hwfn *p_hwfn,
  732. void *p_rxq,
  733. bool eq_completion_only, bool cqe_completion)
  734. {
  735. struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_rxq;
  736. int rc = -EINVAL;
  737. if (IS_PF(p_hwfn->cdev))
  738. rc = qed_eth_pf_rx_queue_stop(p_hwfn, p_cid,
  739. eq_completion_only,
  740. cqe_completion);
  741. else
  742. rc = qed_vf_pf_rxq_stop(p_hwfn, p_cid, cqe_completion);
  743. if (!rc)
  744. qed_eth_queue_cid_release(p_hwfn, p_cid);
  745. return rc;
  746. }
  747. int
  748. qed_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn,
  749. struct qed_queue_cid *p_cid,
  750. dma_addr_t pbl_addr, u16 pbl_size, u16 pq_id)
  751. {
  752. struct tx_queue_start_ramrod_data *p_ramrod = NULL;
  753. struct qed_spq_entry *p_ent = NULL;
  754. struct qed_sp_init_data init_data;
  755. int rc = -EINVAL;
  756. /* Get SPQ entry */
  757. memset(&init_data, 0, sizeof(init_data));
  758. init_data.cid = p_cid->cid;
  759. init_data.opaque_fid = p_cid->opaque_fid;
  760. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  761. rc = qed_sp_init_request(p_hwfn, &p_ent,
  762. ETH_RAMROD_TX_QUEUE_START,
  763. PROTOCOLID_ETH, &init_data);
  764. if (rc)
  765. return rc;
  766. p_ramrod = &p_ent->ramrod.tx_queue_start;
  767. p_ramrod->vport_id = p_cid->abs.vport_id;
  768. p_ramrod->sb_id = cpu_to_le16(p_cid->abs.sb);
  769. p_ramrod->sb_index = p_cid->abs.sb_idx;
  770. p_ramrod->stats_counter_id = p_cid->abs.stats_id;
  771. p_ramrod->queue_zone_id = cpu_to_le16(p_cid->abs.queue_id);
  772. p_ramrod->same_as_last_id = cpu_to_le16(p_cid->abs.queue_id);
  773. p_ramrod->pbl_size = cpu_to_le16(pbl_size);
  774. DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr);
  775. p_ramrod->qm_pq_id = cpu_to_le16(pq_id);
  776. return qed_spq_post(p_hwfn, p_ent, NULL);
  777. }
  778. static int
  779. qed_eth_pf_tx_queue_start(struct qed_hwfn *p_hwfn,
  780. struct qed_queue_cid *p_cid,
  781. u8 tc,
  782. dma_addr_t pbl_addr,
  783. u16 pbl_size, void __iomem **pp_doorbell)
  784. {
  785. int rc;
  786. rc = qed_eth_txq_start_ramrod(p_hwfn, p_cid,
  787. pbl_addr, pbl_size,
  788. qed_get_cm_pq_idx_mcos(p_hwfn, tc));
  789. if (rc)
  790. return rc;
  791. /* Provide the caller with the necessary return values */
  792. *pp_doorbell = p_hwfn->doorbells +
  793. qed_db_addr(p_cid->cid, DQ_DEMS_LEGACY);
  794. return 0;
  795. }
  796. static int
  797. qed_eth_tx_queue_start(struct qed_hwfn *p_hwfn,
  798. u16 opaque_fid,
  799. struct qed_queue_start_common_params *p_params,
  800. u8 tc,
  801. dma_addr_t pbl_addr,
  802. u16 pbl_size,
  803. struct qed_txq_start_ret_params *p_ret_params)
  804. {
  805. struct qed_queue_cid *p_cid;
  806. int rc;
  807. p_cid = qed_eth_queue_to_cid(p_hwfn, opaque_fid, p_params);
  808. if (!p_cid)
  809. return -EINVAL;
  810. if (IS_PF(p_hwfn->cdev))
  811. rc = qed_eth_pf_tx_queue_start(p_hwfn, p_cid, tc,
  812. pbl_addr, pbl_size,
  813. &p_ret_params->p_doorbell);
  814. else
  815. rc = qed_vf_pf_txq_start(p_hwfn, p_cid,
  816. pbl_addr, pbl_size,
  817. &p_ret_params->p_doorbell);
  818. if (rc)
  819. qed_eth_queue_cid_release(p_hwfn, p_cid);
  820. else
  821. p_ret_params->p_handle = (void *)p_cid;
  822. return rc;
  823. }
  824. static int
  825. qed_eth_pf_tx_queue_stop(struct qed_hwfn *p_hwfn, struct qed_queue_cid *p_cid)
  826. {
  827. struct qed_spq_entry *p_ent = NULL;
  828. struct qed_sp_init_data init_data;
  829. int rc;
  830. memset(&init_data, 0, sizeof(init_data));
  831. init_data.cid = p_cid->cid;
  832. init_data.opaque_fid = p_cid->opaque_fid;
  833. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  834. rc = qed_sp_init_request(p_hwfn, &p_ent,
  835. ETH_RAMROD_TX_QUEUE_STOP,
  836. PROTOCOLID_ETH, &init_data);
  837. if (rc)
  838. return rc;
  839. return qed_spq_post(p_hwfn, p_ent, NULL);
  840. }
  841. int qed_eth_tx_queue_stop(struct qed_hwfn *p_hwfn, void *p_handle)
  842. {
  843. struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_handle;
  844. int rc;
  845. if (IS_PF(p_hwfn->cdev))
  846. rc = qed_eth_pf_tx_queue_stop(p_hwfn, p_cid);
  847. else
  848. rc = qed_vf_pf_txq_stop(p_hwfn, p_cid);
  849. if (!rc)
  850. qed_eth_queue_cid_release(p_hwfn, p_cid);
  851. return rc;
  852. }
  853. static enum eth_filter_action qed_filter_action(enum qed_filter_opcode opcode)
  854. {
  855. enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
  856. switch (opcode) {
  857. case QED_FILTER_ADD:
  858. action = ETH_FILTER_ACTION_ADD;
  859. break;
  860. case QED_FILTER_REMOVE:
  861. action = ETH_FILTER_ACTION_REMOVE;
  862. break;
  863. case QED_FILTER_FLUSH:
  864. action = ETH_FILTER_ACTION_REMOVE_ALL;
  865. break;
  866. default:
  867. action = MAX_ETH_FILTER_ACTION;
  868. }
  869. return action;
  870. }
  871. static void qed_set_fw_mac_addr(__le16 *fw_msb,
  872. __le16 *fw_mid,
  873. __le16 *fw_lsb,
  874. u8 *mac)
  875. {
  876. ((u8 *)fw_msb)[0] = mac[1];
  877. ((u8 *)fw_msb)[1] = mac[0];
  878. ((u8 *)fw_mid)[0] = mac[3];
  879. ((u8 *)fw_mid)[1] = mac[2];
  880. ((u8 *)fw_lsb)[0] = mac[5];
  881. ((u8 *)fw_lsb)[1] = mac[4];
  882. }
  883. static int
  884. qed_filter_ucast_common(struct qed_hwfn *p_hwfn,
  885. u16 opaque_fid,
  886. struct qed_filter_ucast *p_filter_cmd,
  887. struct vport_filter_update_ramrod_data **pp_ramrod,
  888. struct qed_spq_entry **pp_ent,
  889. enum spq_mode comp_mode,
  890. struct qed_spq_comp_cb *p_comp_data)
  891. {
  892. u8 vport_to_add_to = 0, vport_to_remove_from = 0;
  893. struct vport_filter_update_ramrod_data *p_ramrod;
  894. struct eth_filter_cmd *p_first_filter;
  895. struct eth_filter_cmd *p_second_filter;
  896. struct qed_sp_init_data init_data;
  897. enum eth_filter_action action;
  898. int rc;
  899. rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
  900. &vport_to_remove_from);
  901. if (rc)
  902. return rc;
  903. rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
  904. &vport_to_add_to);
  905. if (rc)
  906. return rc;
  907. /* Get SPQ entry */
  908. memset(&init_data, 0, sizeof(init_data));
  909. init_data.cid = qed_spq_get_cid(p_hwfn);
  910. init_data.opaque_fid = opaque_fid;
  911. init_data.comp_mode = comp_mode;
  912. init_data.p_comp_data = p_comp_data;
  913. rc = qed_sp_init_request(p_hwfn, pp_ent,
  914. ETH_RAMROD_FILTERS_UPDATE,
  915. PROTOCOLID_ETH, &init_data);
  916. if (rc)
  917. return rc;
  918. *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
  919. p_ramrod = *pp_ramrod;
  920. p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
  921. p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
  922. switch (p_filter_cmd->opcode) {
  923. case QED_FILTER_REPLACE:
  924. case QED_FILTER_MOVE:
  925. p_ramrod->filter_cmd_hdr.cmd_cnt = 2; break;
  926. default:
  927. p_ramrod->filter_cmd_hdr.cmd_cnt = 1; break;
  928. }
  929. p_first_filter = &p_ramrod->filter_cmds[0];
  930. p_second_filter = &p_ramrod->filter_cmds[1];
  931. switch (p_filter_cmd->type) {
  932. case QED_FILTER_MAC:
  933. p_first_filter->type = ETH_FILTER_TYPE_MAC; break;
  934. case QED_FILTER_VLAN:
  935. p_first_filter->type = ETH_FILTER_TYPE_VLAN; break;
  936. case QED_FILTER_MAC_VLAN:
  937. p_first_filter->type = ETH_FILTER_TYPE_PAIR; break;
  938. case QED_FILTER_INNER_MAC:
  939. p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC; break;
  940. case QED_FILTER_INNER_VLAN:
  941. p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN; break;
  942. case QED_FILTER_INNER_PAIR:
  943. p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR; break;
  944. case QED_FILTER_INNER_MAC_VNI_PAIR:
  945. p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
  946. break;
  947. case QED_FILTER_MAC_VNI_PAIR:
  948. p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR; break;
  949. case QED_FILTER_VNI:
  950. p_first_filter->type = ETH_FILTER_TYPE_VNI; break;
  951. }
  952. if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
  953. (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
  954. (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
  955. (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
  956. (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
  957. (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR)) {
  958. qed_set_fw_mac_addr(&p_first_filter->mac_msb,
  959. &p_first_filter->mac_mid,
  960. &p_first_filter->mac_lsb,
  961. (u8 *)p_filter_cmd->mac);
  962. }
  963. if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
  964. (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
  965. (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
  966. (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
  967. p_first_filter->vlan_id = cpu_to_le16(p_filter_cmd->vlan);
  968. if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
  969. (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
  970. (p_first_filter->type == ETH_FILTER_TYPE_VNI))
  971. p_first_filter->vni = cpu_to_le32(p_filter_cmd->vni);
  972. if (p_filter_cmd->opcode == QED_FILTER_MOVE) {
  973. p_second_filter->type = p_first_filter->type;
  974. p_second_filter->mac_msb = p_first_filter->mac_msb;
  975. p_second_filter->mac_mid = p_first_filter->mac_mid;
  976. p_second_filter->mac_lsb = p_first_filter->mac_lsb;
  977. p_second_filter->vlan_id = p_first_filter->vlan_id;
  978. p_second_filter->vni = p_first_filter->vni;
  979. p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
  980. p_first_filter->vport_id = vport_to_remove_from;
  981. p_second_filter->action = ETH_FILTER_ACTION_ADD;
  982. p_second_filter->vport_id = vport_to_add_to;
  983. } else if (p_filter_cmd->opcode == QED_FILTER_REPLACE) {
  984. p_first_filter->vport_id = vport_to_add_to;
  985. memcpy(p_second_filter, p_first_filter,
  986. sizeof(*p_second_filter));
  987. p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL;
  988. p_second_filter->action = ETH_FILTER_ACTION_ADD;
  989. } else {
  990. action = qed_filter_action(p_filter_cmd->opcode);
  991. if (action == MAX_ETH_FILTER_ACTION) {
  992. DP_NOTICE(p_hwfn,
  993. "%d is not supported yet\n",
  994. p_filter_cmd->opcode);
  995. return -EINVAL;
  996. }
  997. p_first_filter->action = action;
  998. p_first_filter->vport_id = (p_filter_cmd->opcode ==
  999. QED_FILTER_REMOVE) ?
  1000. vport_to_remove_from :
  1001. vport_to_add_to;
  1002. }
  1003. return 0;
  1004. }
  1005. int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn,
  1006. u16 opaque_fid,
  1007. struct qed_filter_ucast *p_filter_cmd,
  1008. enum spq_mode comp_mode,
  1009. struct qed_spq_comp_cb *p_comp_data)
  1010. {
  1011. struct vport_filter_update_ramrod_data *p_ramrod = NULL;
  1012. struct qed_spq_entry *p_ent = NULL;
  1013. struct eth_filter_cmd_header *p_header;
  1014. int rc;
  1015. rc = qed_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
  1016. &p_ramrod, &p_ent,
  1017. comp_mode, p_comp_data);
  1018. if (rc) {
  1019. DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
  1020. return rc;
  1021. }
  1022. p_header = &p_ramrod->filter_cmd_hdr;
  1023. p_header->assert_on_error = p_filter_cmd->assert_on_error;
  1024. rc = qed_spq_post(p_hwfn, p_ent, NULL);
  1025. if (rc) {
  1026. DP_ERR(p_hwfn, "Unicast filter ADD command failed %d\n", rc);
  1027. return rc;
  1028. }
  1029. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  1030. "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
  1031. (p_filter_cmd->opcode == QED_FILTER_ADD) ? "ADD" :
  1032. ((p_filter_cmd->opcode == QED_FILTER_REMOVE) ?
  1033. "REMOVE" :
  1034. ((p_filter_cmd->opcode == QED_FILTER_MOVE) ?
  1035. "MOVE" : "REPLACE")),
  1036. (p_filter_cmd->type == QED_FILTER_MAC) ? "MAC" :
  1037. ((p_filter_cmd->type == QED_FILTER_VLAN) ?
  1038. "VLAN" : "MAC & VLAN"),
  1039. p_ramrod->filter_cmd_hdr.cmd_cnt,
  1040. p_filter_cmd->is_rx_filter,
  1041. p_filter_cmd->is_tx_filter);
  1042. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  1043. "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
  1044. p_filter_cmd->vport_to_add_to,
  1045. p_filter_cmd->vport_to_remove_from,
  1046. p_filter_cmd->mac[0],
  1047. p_filter_cmd->mac[1],
  1048. p_filter_cmd->mac[2],
  1049. p_filter_cmd->mac[3],
  1050. p_filter_cmd->mac[4],
  1051. p_filter_cmd->mac[5],
  1052. p_filter_cmd->vlan);
  1053. return 0;
  1054. }
  1055. /*******************************************************************************
  1056. * Description:
  1057. * Calculates crc 32 on a buffer
  1058. * Note: crc32_length MUST be aligned to 8
  1059. * Return:
  1060. ******************************************************************************/
  1061. static u32 qed_calc_crc32c(u8 *crc32_packet,
  1062. u32 crc32_length, u32 crc32_seed, u8 complement)
  1063. {
  1064. u32 byte = 0, bit = 0, crc32_result = crc32_seed;
  1065. u8 msb = 0, current_byte = 0;
  1066. if ((!crc32_packet) ||
  1067. (crc32_length == 0) ||
  1068. ((crc32_length % 8) != 0))
  1069. return crc32_result;
  1070. for (byte = 0; byte < crc32_length; byte++) {
  1071. current_byte = crc32_packet[byte];
  1072. for (bit = 0; bit < 8; bit++) {
  1073. msb = (u8)(crc32_result >> 31);
  1074. crc32_result = crc32_result << 1;
  1075. if (msb != (0x1 & (current_byte >> bit))) {
  1076. crc32_result = crc32_result ^ CRC32_POLY;
  1077. crc32_result |= 1; /*crc32_result[0] = 1;*/
  1078. }
  1079. }
  1080. }
  1081. return crc32_result;
  1082. }
  1083. static u32 qed_crc32c_le(u32 seed, u8 *mac, u32 len)
  1084. {
  1085. u32 packet_buf[2] = { 0 };
  1086. memcpy((u8 *)(&packet_buf[0]), &mac[0], 6);
  1087. return qed_calc_crc32c((u8 *)packet_buf, 8, seed, 0);
  1088. }
  1089. u8 qed_mcast_bin_from_mac(u8 *mac)
  1090. {
  1091. u32 crc = qed_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED,
  1092. mac, ETH_ALEN);
  1093. return crc & 0xff;
  1094. }
  1095. static int
  1096. qed_sp_eth_filter_mcast(struct qed_hwfn *p_hwfn,
  1097. u16 opaque_fid,
  1098. struct qed_filter_mcast *p_filter_cmd,
  1099. enum spq_mode comp_mode,
  1100. struct qed_spq_comp_cb *p_comp_data)
  1101. {
  1102. unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
  1103. struct vport_update_ramrod_data *p_ramrod = NULL;
  1104. struct qed_spq_entry *p_ent = NULL;
  1105. struct qed_sp_init_data init_data;
  1106. u8 abs_vport_id = 0;
  1107. int rc, i;
  1108. if (p_filter_cmd->opcode == QED_FILTER_ADD)
  1109. rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
  1110. &abs_vport_id);
  1111. else
  1112. rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
  1113. &abs_vport_id);
  1114. if (rc)
  1115. return rc;
  1116. /* Get SPQ entry */
  1117. memset(&init_data, 0, sizeof(init_data));
  1118. init_data.cid = qed_spq_get_cid(p_hwfn);
  1119. init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
  1120. init_data.comp_mode = comp_mode;
  1121. init_data.p_comp_data = p_comp_data;
  1122. rc = qed_sp_init_request(p_hwfn, &p_ent,
  1123. ETH_RAMROD_VPORT_UPDATE,
  1124. PROTOCOLID_ETH, &init_data);
  1125. if (rc) {
  1126. DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
  1127. return rc;
  1128. }
  1129. p_ramrod = &p_ent->ramrod.vport_update;
  1130. p_ramrod->common.update_approx_mcast_flg = 1;
  1131. /* explicitly clear out the entire vector */
  1132. memset(&p_ramrod->approx_mcast.bins, 0,
  1133. sizeof(p_ramrod->approx_mcast.bins));
  1134. memset(bins, 0, sizeof(unsigned long) *
  1135. ETH_MULTICAST_MAC_BINS_IN_REGS);
  1136. /* filter ADD op is explicit set op and it removes
  1137. * any existing filters for the vport
  1138. */
  1139. if (p_filter_cmd->opcode == QED_FILTER_ADD) {
  1140. for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
  1141. u32 bit;
  1142. bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]);
  1143. __set_bit(bit, bins);
  1144. }
  1145. /* Convert to correct endianity */
  1146. for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
  1147. struct vport_update_ramrod_mcast *p_ramrod_bins;
  1148. u32 *p_bins = (u32 *)bins;
  1149. p_ramrod_bins = &p_ramrod->approx_mcast;
  1150. p_ramrod_bins->bins[i] = cpu_to_le32(p_bins[i]);
  1151. }
  1152. }
  1153. p_ramrod->common.vport_id = abs_vport_id;
  1154. return qed_spq_post(p_hwfn, p_ent, NULL);
  1155. }
  1156. static int qed_filter_mcast_cmd(struct qed_dev *cdev,
  1157. struct qed_filter_mcast *p_filter_cmd,
  1158. enum spq_mode comp_mode,
  1159. struct qed_spq_comp_cb *p_comp_data)
  1160. {
  1161. int rc = 0;
  1162. int i;
  1163. /* only ADD and REMOVE operations are supported for multi-cast */
  1164. if ((p_filter_cmd->opcode != QED_FILTER_ADD &&
  1165. (p_filter_cmd->opcode != QED_FILTER_REMOVE)) ||
  1166. (p_filter_cmd->num_mc_addrs > QED_MAX_MC_ADDRS))
  1167. return -EINVAL;
  1168. for_each_hwfn(cdev, i) {
  1169. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1170. u16 opaque_fid;
  1171. if (IS_VF(cdev)) {
  1172. qed_vf_pf_filter_mcast(p_hwfn, p_filter_cmd);
  1173. continue;
  1174. }
  1175. opaque_fid = p_hwfn->hw_info.opaque_fid;
  1176. rc = qed_sp_eth_filter_mcast(p_hwfn,
  1177. opaque_fid,
  1178. p_filter_cmd,
  1179. comp_mode, p_comp_data);
  1180. }
  1181. return rc;
  1182. }
  1183. static int qed_filter_ucast_cmd(struct qed_dev *cdev,
  1184. struct qed_filter_ucast *p_filter_cmd,
  1185. enum spq_mode comp_mode,
  1186. struct qed_spq_comp_cb *p_comp_data)
  1187. {
  1188. int rc = 0;
  1189. int i;
  1190. for_each_hwfn(cdev, i) {
  1191. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1192. u16 opaque_fid;
  1193. if (IS_VF(cdev)) {
  1194. rc = qed_vf_pf_filter_ucast(p_hwfn, p_filter_cmd);
  1195. continue;
  1196. }
  1197. opaque_fid = p_hwfn->hw_info.opaque_fid;
  1198. rc = qed_sp_eth_filter_ucast(p_hwfn,
  1199. opaque_fid,
  1200. p_filter_cmd,
  1201. comp_mode, p_comp_data);
  1202. if (rc)
  1203. break;
  1204. }
  1205. return rc;
  1206. }
  1207. /* Statistics related code */
  1208. static void __qed_get_vport_pstats_addrlen(struct qed_hwfn *p_hwfn,
  1209. u32 *p_addr,
  1210. u32 *p_len, u16 statistics_bin)
  1211. {
  1212. if (IS_PF(p_hwfn->cdev)) {
  1213. *p_addr = BAR0_MAP_REG_PSDM_RAM +
  1214. PSTORM_QUEUE_STAT_OFFSET(statistics_bin);
  1215. *p_len = sizeof(struct eth_pstorm_per_queue_stat);
  1216. } else {
  1217. struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
  1218. struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
  1219. *p_addr = p_resp->pfdev_info.stats_info.pstats.address;
  1220. *p_len = p_resp->pfdev_info.stats_info.pstats.len;
  1221. }
  1222. }
  1223. static void __qed_get_vport_pstats(struct qed_hwfn *p_hwfn,
  1224. struct qed_ptt *p_ptt,
  1225. struct qed_eth_stats *p_stats,
  1226. u16 statistics_bin)
  1227. {
  1228. struct eth_pstorm_per_queue_stat pstats;
  1229. u32 pstats_addr = 0, pstats_len = 0;
  1230. __qed_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len,
  1231. statistics_bin);
  1232. memset(&pstats, 0, sizeof(pstats));
  1233. qed_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len);
  1234. p_stats->common.tx_ucast_bytes +=
  1235. HILO_64_REGPAIR(pstats.sent_ucast_bytes);
  1236. p_stats->common.tx_mcast_bytes +=
  1237. HILO_64_REGPAIR(pstats.sent_mcast_bytes);
  1238. p_stats->common.tx_bcast_bytes +=
  1239. HILO_64_REGPAIR(pstats.sent_bcast_bytes);
  1240. p_stats->common.tx_ucast_pkts +=
  1241. HILO_64_REGPAIR(pstats.sent_ucast_pkts);
  1242. p_stats->common.tx_mcast_pkts +=
  1243. HILO_64_REGPAIR(pstats.sent_mcast_pkts);
  1244. p_stats->common.tx_bcast_pkts +=
  1245. HILO_64_REGPAIR(pstats.sent_bcast_pkts);
  1246. p_stats->common.tx_err_drop_pkts +=
  1247. HILO_64_REGPAIR(pstats.error_drop_pkts);
  1248. }
  1249. static void __qed_get_vport_tstats(struct qed_hwfn *p_hwfn,
  1250. struct qed_ptt *p_ptt,
  1251. struct qed_eth_stats *p_stats,
  1252. u16 statistics_bin)
  1253. {
  1254. struct tstorm_per_port_stat tstats;
  1255. u32 tstats_addr, tstats_len;
  1256. if (IS_PF(p_hwfn->cdev)) {
  1257. tstats_addr = BAR0_MAP_REG_TSDM_RAM +
  1258. TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
  1259. tstats_len = sizeof(struct tstorm_per_port_stat);
  1260. } else {
  1261. struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
  1262. struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
  1263. tstats_addr = p_resp->pfdev_info.stats_info.tstats.address;
  1264. tstats_len = p_resp->pfdev_info.stats_info.tstats.len;
  1265. }
  1266. memset(&tstats, 0, sizeof(tstats));
  1267. qed_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len);
  1268. p_stats->common.mftag_filter_discards +=
  1269. HILO_64_REGPAIR(tstats.mftag_filter_discard);
  1270. p_stats->common.mac_filter_discards +=
  1271. HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
  1272. }
  1273. static void __qed_get_vport_ustats_addrlen(struct qed_hwfn *p_hwfn,
  1274. u32 *p_addr,
  1275. u32 *p_len, u16 statistics_bin)
  1276. {
  1277. if (IS_PF(p_hwfn->cdev)) {
  1278. *p_addr = BAR0_MAP_REG_USDM_RAM +
  1279. USTORM_QUEUE_STAT_OFFSET(statistics_bin);
  1280. *p_len = sizeof(struct eth_ustorm_per_queue_stat);
  1281. } else {
  1282. struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
  1283. struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
  1284. *p_addr = p_resp->pfdev_info.stats_info.ustats.address;
  1285. *p_len = p_resp->pfdev_info.stats_info.ustats.len;
  1286. }
  1287. }
  1288. static void __qed_get_vport_ustats(struct qed_hwfn *p_hwfn,
  1289. struct qed_ptt *p_ptt,
  1290. struct qed_eth_stats *p_stats,
  1291. u16 statistics_bin)
  1292. {
  1293. struct eth_ustorm_per_queue_stat ustats;
  1294. u32 ustats_addr = 0, ustats_len = 0;
  1295. __qed_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len,
  1296. statistics_bin);
  1297. memset(&ustats, 0, sizeof(ustats));
  1298. qed_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len);
  1299. p_stats->common.rx_ucast_bytes +=
  1300. HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
  1301. p_stats->common.rx_mcast_bytes +=
  1302. HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
  1303. p_stats->common.rx_bcast_bytes +=
  1304. HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
  1305. p_stats->common.rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
  1306. p_stats->common.rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
  1307. p_stats->common.rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
  1308. }
  1309. static void __qed_get_vport_mstats_addrlen(struct qed_hwfn *p_hwfn,
  1310. u32 *p_addr,
  1311. u32 *p_len, u16 statistics_bin)
  1312. {
  1313. if (IS_PF(p_hwfn->cdev)) {
  1314. *p_addr = BAR0_MAP_REG_MSDM_RAM +
  1315. MSTORM_QUEUE_STAT_OFFSET(statistics_bin);
  1316. *p_len = sizeof(struct eth_mstorm_per_queue_stat);
  1317. } else {
  1318. struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
  1319. struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
  1320. *p_addr = p_resp->pfdev_info.stats_info.mstats.address;
  1321. *p_len = p_resp->pfdev_info.stats_info.mstats.len;
  1322. }
  1323. }
  1324. static void __qed_get_vport_mstats(struct qed_hwfn *p_hwfn,
  1325. struct qed_ptt *p_ptt,
  1326. struct qed_eth_stats *p_stats,
  1327. u16 statistics_bin)
  1328. {
  1329. struct eth_mstorm_per_queue_stat mstats;
  1330. u32 mstats_addr = 0, mstats_len = 0;
  1331. __qed_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len,
  1332. statistics_bin);
  1333. memset(&mstats, 0, sizeof(mstats));
  1334. qed_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len);
  1335. p_stats->common.no_buff_discards +=
  1336. HILO_64_REGPAIR(mstats.no_buff_discard);
  1337. p_stats->common.packet_too_big_discard +=
  1338. HILO_64_REGPAIR(mstats.packet_too_big_discard);
  1339. p_stats->common.ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard);
  1340. p_stats->common.tpa_coalesced_pkts +=
  1341. HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
  1342. p_stats->common.tpa_coalesced_events +=
  1343. HILO_64_REGPAIR(mstats.tpa_coalesced_events);
  1344. p_stats->common.tpa_aborts_num +=
  1345. HILO_64_REGPAIR(mstats.tpa_aborts_num);
  1346. p_stats->common.tpa_coalesced_bytes +=
  1347. HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
  1348. }
  1349. static void __qed_get_vport_port_stats(struct qed_hwfn *p_hwfn,
  1350. struct qed_ptt *p_ptt,
  1351. struct qed_eth_stats *p_stats)
  1352. {
  1353. struct qed_eth_stats_common *p_common = &p_stats->common;
  1354. struct port_stats port_stats;
  1355. int j;
  1356. memset(&port_stats, 0, sizeof(port_stats));
  1357. qed_memcpy_from(p_hwfn, p_ptt, &port_stats,
  1358. p_hwfn->mcp_info->port_addr +
  1359. offsetof(struct public_port, stats),
  1360. sizeof(port_stats));
  1361. p_common->rx_64_byte_packets += port_stats.eth.r64;
  1362. p_common->rx_65_to_127_byte_packets += port_stats.eth.r127;
  1363. p_common->rx_128_to_255_byte_packets += port_stats.eth.r255;
  1364. p_common->rx_256_to_511_byte_packets += port_stats.eth.r511;
  1365. p_common->rx_512_to_1023_byte_packets += port_stats.eth.r1023;
  1366. p_common->rx_1024_to_1518_byte_packets += port_stats.eth.r1518;
  1367. p_common->rx_crc_errors += port_stats.eth.rfcs;
  1368. p_common->rx_mac_crtl_frames += port_stats.eth.rxcf;
  1369. p_common->rx_pause_frames += port_stats.eth.rxpf;
  1370. p_common->rx_pfc_frames += port_stats.eth.rxpp;
  1371. p_common->rx_align_errors += port_stats.eth.raln;
  1372. p_common->rx_carrier_errors += port_stats.eth.rfcr;
  1373. p_common->rx_oversize_packets += port_stats.eth.rovr;
  1374. p_common->rx_jabbers += port_stats.eth.rjbr;
  1375. p_common->rx_undersize_packets += port_stats.eth.rund;
  1376. p_common->rx_fragments += port_stats.eth.rfrg;
  1377. p_common->tx_64_byte_packets += port_stats.eth.t64;
  1378. p_common->tx_65_to_127_byte_packets += port_stats.eth.t127;
  1379. p_common->tx_128_to_255_byte_packets += port_stats.eth.t255;
  1380. p_common->tx_256_to_511_byte_packets += port_stats.eth.t511;
  1381. p_common->tx_512_to_1023_byte_packets += port_stats.eth.t1023;
  1382. p_common->tx_1024_to_1518_byte_packets += port_stats.eth.t1518;
  1383. p_common->tx_pause_frames += port_stats.eth.txpf;
  1384. p_common->tx_pfc_frames += port_stats.eth.txpp;
  1385. p_common->rx_mac_bytes += port_stats.eth.rbyte;
  1386. p_common->rx_mac_uc_packets += port_stats.eth.rxuca;
  1387. p_common->rx_mac_mc_packets += port_stats.eth.rxmca;
  1388. p_common->rx_mac_bc_packets += port_stats.eth.rxbca;
  1389. p_common->rx_mac_frames_ok += port_stats.eth.rxpok;
  1390. p_common->tx_mac_bytes += port_stats.eth.tbyte;
  1391. p_common->tx_mac_uc_packets += port_stats.eth.txuca;
  1392. p_common->tx_mac_mc_packets += port_stats.eth.txmca;
  1393. p_common->tx_mac_bc_packets += port_stats.eth.txbca;
  1394. p_common->tx_mac_ctrl_frames += port_stats.eth.txcf;
  1395. for (j = 0; j < 8; j++) {
  1396. p_common->brb_truncates += port_stats.brb.brb_truncate[j];
  1397. p_common->brb_discards += port_stats.brb.brb_discard[j];
  1398. }
  1399. if (QED_IS_BB(p_hwfn->cdev)) {
  1400. struct qed_eth_stats_bb *p_bb = &p_stats->bb;
  1401. p_bb->rx_1519_to_1522_byte_packets +=
  1402. port_stats.eth.u0.bb0.r1522;
  1403. p_bb->rx_1519_to_2047_byte_packets +=
  1404. port_stats.eth.u0.bb0.r2047;
  1405. p_bb->rx_2048_to_4095_byte_packets +=
  1406. port_stats.eth.u0.bb0.r4095;
  1407. p_bb->rx_4096_to_9216_byte_packets +=
  1408. port_stats.eth.u0.bb0.r9216;
  1409. p_bb->rx_9217_to_16383_byte_packets +=
  1410. port_stats.eth.u0.bb0.r16383;
  1411. p_bb->tx_1519_to_2047_byte_packets +=
  1412. port_stats.eth.u1.bb1.t2047;
  1413. p_bb->tx_2048_to_4095_byte_packets +=
  1414. port_stats.eth.u1.bb1.t4095;
  1415. p_bb->tx_4096_to_9216_byte_packets +=
  1416. port_stats.eth.u1.bb1.t9216;
  1417. p_bb->tx_9217_to_16383_byte_packets +=
  1418. port_stats.eth.u1.bb1.t16383;
  1419. p_bb->tx_lpi_entry_count += port_stats.eth.u2.bb2.tlpiec;
  1420. p_bb->tx_total_collisions += port_stats.eth.u2.bb2.tncl;
  1421. } else {
  1422. struct qed_eth_stats_ah *p_ah = &p_stats->ah;
  1423. p_ah->rx_1519_to_max_byte_packets +=
  1424. port_stats.eth.u0.ah0.r1519_to_max;
  1425. p_ah->tx_1519_to_max_byte_packets =
  1426. port_stats.eth.u1.ah1.t1519_to_max;
  1427. }
  1428. }
  1429. static void __qed_get_vport_stats(struct qed_hwfn *p_hwfn,
  1430. struct qed_ptt *p_ptt,
  1431. struct qed_eth_stats *stats,
  1432. u16 statistics_bin, bool b_get_port_stats)
  1433. {
  1434. __qed_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin);
  1435. __qed_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin);
  1436. __qed_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin);
  1437. __qed_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin);
  1438. if (b_get_port_stats && p_hwfn->mcp_info)
  1439. __qed_get_vport_port_stats(p_hwfn, p_ptt, stats);
  1440. }
  1441. static void _qed_get_vport_stats(struct qed_dev *cdev,
  1442. struct qed_eth_stats *stats)
  1443. {
  1444. u8 fw_vport = 0;
  1445. int i;
  1446. memset(stats, 0, sizeof(*stats));
  1447. for_each_hwfn(cdev, i) {
  1448. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1449. struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
  1450. : NULL;
  1451. if (IS_PF(cdev)) {
  1452. /* The main vport index is relative first */
  1453. if (qed_fw_vport(p_hwfn, 0, &fw_vport)) {
  1454. DP_ERR(p_hwfn, "No vport available!\n");
  1455. goto out;
  1456. }
  1457. }
  1458. if (IS_PF(cdev) && !p_ptt) {
  1459. DP_ERR(p_hwfn, "Failed to acquire ptt\n");
  1460. continue;
  1461. }
  1462. __qed_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport,
  1463. IS_PF(cdev) ? true : false);
  1464. out:
  1465. if (IS_PF(cdev) && p_ptt)
  1466. qed_ptt_release(p_hwfn, p_ptt);
  1467. }
  1468. }
  1469. void qed_get_vport_stats(struct qed_dev *cdev, struct qed_eth_stats *stats)
  1470. {
  1471. u32 i;
  1472. if (!cdev) {
  1473. memset(stats, 0, sizeof(*stats));
  1474. return;
  1475. }
  1476. _qed_get_vport_stats(cdev, stats);
  1477. if (!cdev->reset_stats)
  1478. return;
  1479. /* Reduce the statistics baseline */
  1480. for (i = 0; i < sizeof(struct qed_eth_stats) / sizeof(u64); i++)
  1481. ((u64 *)stats)[i] -= ((u64 *)cdev->reset_stats)[i];
  1482. }
  1483. /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
  1484. void qed_reset_vport_stats(struct qed_dev *cdev)
  1485. {
  1486. int i;
  1487. for_each_hwfn(cdev, i) {
  1488. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1489. struct eth_mstorm_per_queue_stat mstats;
  1490. struct eth_ustorm_per_queue_stat ustats;
  1491. struct eth_pstorm_per_queue_stat pstats;
  1492. struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
  1493. : NULL;
  1494. u32 addr = 0, len = 0;
  1495. if (IS_PF(cdev) && !p_ptt) {
  1496. DP_ERR(p_hwfn, "Failed to acquire ptt\n");
  1497. continue;
  1498. }
  1499. memset(&mstats, 0, sizeof(mstats));
  1500. __qed_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0);
  1501. qed_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len);
  1502. memset(&ustats, 0, sizeof(ustats));
  1503. __qed_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0);
  1504. qed_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len);
  1505. memset(&pstats, 0, sizeof(pstats));
  1506. __qed_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0);
  1507. qed_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len);
  1508. if (IS_PF(cdev))
  1509. qed_ptt_release(p_hwfn, p_ptt);
  1510. }
  1511. /* PORT statistics are not necessarily reset, so we need to
  1512. * read and create a baseline for future statistics.
  1513. */
  1514. if (!cdev->reset_stats)
  1515. DP_INFO(cdev, "Reset stats not allocated\n");
  1516. else
  1517. _qed_get_vport_stats(cdev, cdev->reset_stats);
  1518. }
  1519. static void
  1520. qed_arfs_mode_configure(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
  1521. struct qed_arfs_config_params *p_cfg_params)
  1522. {
  1523. if (p_cfg_params->arfs_enable) {
  1524. qed_set_rfs_mode_enable(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
  1525. p_cfg_params->tcp, p_cfg_params->udp,
  1526. p_cfg_params->ipv4, p_cfg_params->ipv6);
  1527. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  1528. "tcp = %s, udp = %s, ipv4 = %s, ipv6 =%s\n",
  1529. p_cfg_params->tcp ? "Enable" : "Disable",
  1530. p_cfg_params->udp ? "Enable" : "Disable",
  1531. p_cfg_params->ipv4 ? "Enable" : "Disable",
  1532. p_cfg_params->ipv6 ? "Enable" : "Disable");
  1533. } else {
  1534. qed_set_rfs_mode_disable(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
  1535. }
  1536. DP_VERBOSE(p_hwfn, QED_MSG_SP, "Configured ARFS mode : %s\n",
  1537. p_cfg_params->arfs_enable ? "Enable" : "Disable");
  1538. }
  1539. static int
  1540. qed_configure_rfs_ntuple_filter(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
  1541. struct qed_spq_comp_cb *p_cb,
  1542. dma_addr_t p_addr, u16 length, u16 qid,
  1543. u8 vport_id, bool b_is_add)
  1544. {
  1545. struct rx_update_gft_filter_data *p_ramrod = NULL;
  1546. struct qed_spq_entry *p_ent = NULL;
  1547. struct qed_sp_init_data init_data;
  1548. u16 abs_rx_q_id = 0;
  1549. u8 abs_vport_id = 0;
  1550. int rc = -EINVAL;
  1551. rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id);
  1552. if (rc)
  1553. return rc;
  1554. rc = qed_fw_l2_queue(p_hwfn, qid, &abs_rx_q_id);
  1555. if (rc)
  1556. return rc;
  1557. /* Get SPQ entry */
  1558. memset(&init_data, 0, sizeof(init_data));
  1559. init_data.cid = qed_spq_get_cid(p_hwfn);
  1560. init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
  1561. if (p_cb) {
  1562. init_data.comp_mode = QED_SPQ_MODE_CB;
  1563. init_data.p_comp_data = p_cb;
  1564. } else {
  1565. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  1566. }
  1567. rc = qed_sp_init_request(p_hwfn, &p_ent,
  1568. ETH_RAMROD_GFT_UPDATE_FILTER,
  1569. PROTOCOLID_ETH, &init_data);
  1570. if (rc)
  1571. return rc;
  1572. p_ramrod = &p_ent->ramrod.rx_update_gft;
  1573. DMA_REGPAIR_LE(p_ramrod->pkt_hdr_addr, p_addr);
  1574. p_ramrod->pkt_hdr_length = cpu_to_le16(length);
  1575. p_ramrod->rx_qid_or_action_icid = cpu_to_le16(abs_rx_q_id);
  1576. p_ramrod->vport_id = abs_vport_id;
  1577. p_ramrod->filter_type = RFS_FILTER_TYPE;
  1578. p_ramrod->filter_action = b_is_add ? GFT_ADD_FILTER : GFT_DELETE_FILTER;
  1579. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  1580. "V[%0x], Q[%04x] - %s filter from 0x%llx [length %04xb]\n",
  1581. abs_vport_id, abs_rx_q_id,
  1582. b_is_add ? "Adding" : "Removing", (u64)p_addr, length);
  1583. return qed_spq_post(p_hwfn, p_ent, NULL);
  1584. }
  1585. static int qed_fill_eth_dev_info(struct qed_dev *cdev,
  1586. struct qed_dev_eth_info *info)
  1587. {
  1588. int i;
  1589. memset(info, 0, sizeof(*info));
  1590. info->num_tc = 1;
  1591. if (IS_PF(cdev)) {
  1592. int max_vf_vlan_filters = 0;
  1593. int max_vf_mac_filters = 0;
  1594. if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
  1595. u16 num_queues = 0;
  1596. /* Since the feature controls only queue-zones,
  1597. * make sure we have the contexts [rx, tx, xdp] to
  1598. * match.
  1599. */
  1600. for_each_hwfn(cdev, i) {
  1601. struct qed_hwfn *hwfn = &cdev->hwfns[i];
  1602. u16 l2_queues = (u16)FEAT_NUM(hwfn,
  1603. QED_PF_L2_QUE);
  1604. u16 cids;
  1605. cids = hwfn->pf_params.eth_pf_params.num_cons;
  1606. num_queues += min_t(u16, l2_queues, cids / 3);
  1607. }
  1608. /* queues might theoretically be >256, but interrupts'
  1609. * upper-limit guarantes that it would fit in a u8.
  1610. */
  1611. if (cdev->int_params.fp_msix_cnt) {
  1612. u8 irqs = cdev->int_params.fp_msix_cnt;
  1613. info->num_queues = (u8)min_t(u16,
  1614. num_queues, irqs);
  1615. }
  1616. } else {
  1617. info->num_queues = cdev->num_hwfns;
  1618. }
  1619. if (IS_QED_SRIOV(cdev)) {
  1620. max_vf_vlan_filters = cdev->p_iov_info->total_vfs *
  1621. QED_ETH_VF_NUM_VLAN_FILTERS;
  1622. max_vf_mac_filters = cdev->p_iov_info->total_vfs *
  1623. QED_ETH_VF_NUM_MAC_FILTERS;
  1624. }
  1625. info->num_vlan_filters = RESC_NUM(QED_LEADING_HWFN(cdev),
  1626. QED_VLAN) -
  1627. max_vf_vlan_filters;
  1628. info->num_mac_filters = RESC_NUM(QED_LEADING_HWFN(cdev),
  1629. QED_MAC) -
  1630. max_vf_mac_filters;
  1631. ether_addr_copy(info->port_mac,
  1632. cdev->hwfns[0].hw_info.hw_mac_addr);
  1633. } else {
  1634. qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev), &info->num_queues);
  1635. if (cdev->num_hwfns > 1) {
  1636. u8 queues = 0;
  1637. qed_vf_get_num_rxqs(&cdev->hwfns[1], &queues);
  1638. info->num_queues += queues;
  1639. }
  1640. qed_vf_get_num_vlan_filters(&cdev->hwfns[0],
  1641. (u8 *)&info->num_vlan_filters);
  1642. qed_vf_get_num_mac_filters(&cdev->hwfns[0],
  1643. (u8 *)&info->num_mac_filters);
  1644. qed_vf_get_port_mac(&cdev->hwfns[0], info->port_mac);
  1645. info->is_legacy = !!cdev->hwfns[0].vf_iov_info->b_pre_fp_hsi;
  1646. }
  1647. qed_fill_dev_info(cdev, &info->common);
  1648. if (IS_VF(cdev))
  1649. eth_zero_addr(info->common.hw_mac);
  1650. return 0;
  1651. }
  1652. static void qed_register_eth_ops(struct qed_dev *cdev,
  1653. struct qed_eth_cb_ops *ops, void *cookie)
  1654. {
  1655. cdev->protocol_ops.eth = ops;
  1656. cdev->ops_cookie = cookie;
  1657. /* For VF, we start bulletin reading */
  1658. if (IS_VF(cdev))
  1659. qed_vf_start_iov_wq(cdev);
  1660. }
  1661. static bool qed_check_mac(struct qed_dev *cdev, u8 *mac)
  1662. {
  1663. if (IS_PF(cdev))
  1664. return true;
  1665. return qed_vf_check_mac(&cdev->hwfns[0], mac);
  1666. }
  1667. static int qed_start_vport(struct qed_dev *cdev,
  1668. struct qed_start_vport_params *params)
  1669. {
  1670. int rc, i;
  1671. for_each_hwfn(cdev, i) {
  1672. struct qed_sp_vport_start_params start = { 0 };
  1673. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1674. start.tpa_mode = params->gro_enable ? QED_TPA_MODE_GRO :
  1675. QED_TPA_MODE_NONE;
  1676. start.remove_inner_vlan = params->remove_inner_vlan;
  1677. start.only_untagged = true; /* untagged only */
  1678. start.drop_ttl0 = params->drop_ttl0;
  1679. start.opaque_fid = p_hwfn->hw_info.opaque_fid;
  1680. start.concrete_fid = p_hwfn->hw_info.concrete_fid;
  1681. start.handle_ptp_pkts = params->handle_ptp_pkts;
  1682. start.vport_id = params->vport_id;
  1683. start.max_buffers_per_cqe = 16;
  1684. start.mtu = params->mtu;
  1685. rc = qed_sp_vport_start(p_hwfn, &start);
  1686. if (rc) {
  1687. DP_ERR(cdev, "Failed to start VPORT\n");
  1688. return rc;
  1689. }
  1690. rc = qed_hw_start_fastpath(p_hwfn);
  1691. if (rc) {
  1692. DP_ERR(cdev, "Failed to start VPORT fastpath\n");
  1693. return rc;
  1694. }
  1695. DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
  1696. "Started V-PORT %d with MTU %d\n",
  1697. start.vport_id, start.mtu);
  1698. }
  1699. if (params->clear_stats)
  1700. qed_reset_vport_stats(cdev);
  1701. return 0;
  1702. }
  1703. static int qed_stop_vport(struct qed_dev *cdev, u8 vport_id)
  1704. {
  1705. int rc, i;
  1706. for_each_hwfn(cdev, i) {
  1707. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1708. rc = qed_sp_vport_stop(p_hwfn,
  1709. p_hwfn->hw_info.opaque_fid, vport_id);
  1710. if (rc) {
  1711. DP_ERR(cdev, "Failed to stop VPORT\n");
  1712. return rc;
  1713. }
  1714. }
  1715. return 0;
  1716. }
  1717. static int qed_update_vport_rss(struct qed_dev *cdev,
  1718. struct qed_update_vport_rss_params *input,
  1719. struct qed_rss_params *rss)
  1720. {
  1721. int i, fn;
  1722. /* Update configuration with what's correct regardless of CMT */
  1723. rss->update_rss_config = 1;
  1724. rss->rss_enable = 1;
  1725. rss->update_rss_capabilities = 1;
  1726. rss->update_rss_ind_table = 1;
  1727. rss->update_rss_key = 1;
  1728. rss->rss_caps = input->rss_caps;
  1729. memcpy(rss->rss_key, input->rss_key, QED_RSS_KEY_SIZE * sizeof(u32));
  1730. /* In regular scenario, we'd simply need to take input handlers.
  1731. * But in CMT, we'd have to split the handlers according to the
  1732. * engine they were configured on. We'd then have to understand
  1733. * whether RSS is really required, since 2-queues on CMT doesn't
  1734. * require RSS.
  1735. */
  1736. if (cdev->num_hwfns == 1) {
  1737. memcpy(rss->rss_ind_table,
  1738. input->rss_ind_table,
  1739. QED_RSS_IND_TABLE_SIZE * sizeof(void *));
  1740. rss->rss_table_size_log = 7;
  1741. return 0;
  1742. }
  1743. /* Start by copying the non-spcific information to the 2nd copy */
  1744. memcpy(&rss[1], &rss[0], sizeof(struct qed_rss_params));
  1745. /* CMT should be round-robin */
  1746. for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
  1747. struct qed_queue_cid *cid = input->rss_ind_table[i];
  1748. struct qed_rss_params *t_rss;
  1749. if (cid->p_owner == QED_LEADING_HWFN(cdev))
  1750. t_rss = &rss[0];
  1751. else
  1752. t_rss = &rss[1];
  1753. t_rss->rss_ind_table[i / cdev->num_hwfns] = cid;
  1754. }
  1755. /* Make sure RSS is actually required */
  1756. for_each_hwfn(cdev, fn) {
  1757. for (i = 1; i < QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns; i++) {
  1758. if (rss[fn].rss_ind_table[i] !=
  1759. rss[fn].rss_ind_table[0])
  1760. break;
  1761. }
  1762. if (i == QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns) {
  1763. DP_VERBOSE(cdev, NETIF_MSG_IFUP,
  1764. "CMT - 1 queue per-hwfn; Disabling RSS\n");
  1765. return -EINVAL;
  1766. }
  1767. rss[fn].rss_table_size_log = 6;
  1768. }
  1769. return 0;
  1770. }
  1771. static int qed_update_vport(struct qed_dev *cdev,
  1772. struct qed_update_vport_params *params)
  1773. {
  1774. struct qed_sp_vport_update_params sp_params;
  1775. struct qed_rss_params *rss;
  1776. int rc = 0, i;
  1777. if (!cdev)
  1778. return -ENODEV;
  1779. rss = vzalloc(sizeof(*rss) * cdev->num_hwfns);
  1780. if (!rss)
  1781. return -ENOMEM;
  1782. memset(&sp_params, 0, sizeof(sp_params));
  1783. /* Translate protocol params into sp params */
  1784. sp_params.vport_id = params->vport_id;
  1785. sp_params.update_vport_active_rx_flg = params->update_vport_active_flg;
  1786. sp_params.update_vport_active_tx_flg = params->update_vport_active_flg;
  1787. sp_params.vport_active_rx_flg = params->vport_active_flg;
  1788. sp_params.vport_active_tx_flg = params->vport_active_flg;
  1789. sp_params.update_tx_switching_flg = params->update_tx_switching_flg;
  1790. sp_params.tx_switching_flg = params->tx_switching_flg;
  1791. sp_params.accept_any_vlan = params->accept_any_vlan;
  1792. sp_params.update_accept_any_vlan_flg =
  1793. params->update_accept_any_vlan_flg;
  1794. /* Prepare the RSS configuration */
  1795. if (params->update_rss_flg)
  1796. if (qed_update_vport_rss(cdev, &params->rss_params, rss))
  1797. params->update_rss_flg = 0;
  1798. for_each_hwfn(cdev, i) {
  1799. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1800. if (params->update_rss_flg)
  1801. sp_params.rss_params = &rss[i];
  1802. sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
  1803. rc = qed_sp_vport_update(p_hwfn, &sp_params,
  1804. QED_SPQ_MODE_EBLOCK,
  1805. NULL);
  1806. if (rc) {
  1807. DP_ERR(cdev, "Failed to update VPORT\n");
  1808. goto out;
  1809. }
  1810. DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
  1811. "Updated V-PORT %d: active_flag %d [update %d]\n",
  1812. params->vport_id, params->vport_active_flg,
  1813. params->update_vport_active_flg);
  1814. }
  1815. out:
  1816. vfree(rss);
  1817. return rc;
  1818. }
  1819. static int qed_start_rxq(struct qed_dev *cdev,
  1820. u8 rss_num,
  1821. struct qed_queue_start_common_params *p_params,
  1822. u16 bd_max_bytes,
  1823. dma_addr_t bd_chain_phys_addr,
  1824. dma_addr_t cqe_pbl_addr,
  1825. u16 cqe_pbl_size,
  1826. struct qed_rxq_start_ret_params *ret_params)
  1827. {
  1828. struct qed_hwfn *p_hwfn;
  1829. int rc, hwfn_index;
  1830. hwfn_index = rss_num % cdev->num_hwfns;
  1831. p_hwfn = &cdev->hwfns[hwfn_index];
  1832. p_params->queue_id = p_params->queue_id / cdev->num_hwfns;
  1833. p_params->stats_id = p_params->vport_id;
  1834. rc = qed_eth_rx_queue_start(p_hwfn,
  1835. p_hwfn->hw_info.opaque_fid,
  1836. p_params,
  1837. bd_max_bytes,
  1838. bd_chain_phys_addr,
  1839. cqe_pbl_addr, cqe_pbl_size, ret_params);
  1840. if (rc) {
  1841. DP_ERR(cdev, "Failed to start RXQ#%d\n", p_params->queue_id);
  1842. return rc;
  1843. }
  1844. DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
  1845. "Started RX-Q %d [rss_num %d] on V-PORT %d and SB %d\n",
  1846. p_params->queue_id, rss_num, p_params->vport_id,
  1847. p_params->sb);
  1848. return 0;
  1849. }
  1850. static int qed_stop_rxq(struct qed_dev *cdev, u8 rss_id, void *handle)
  1851. {
  1852. int rc, hwfn_index;
  1853. struct qed_hwfn *p_hwfn;
  1854. hwfn_index = rss_id % cdev->num_hwfns;
  1855. p_hwfn = &cdev->hwfns[hwfn_index];
  1856. rc = qed_eth_rx_queue_stop(p_hwfn, handle, false, false);
  1857. if (rc) {
  1858. DP_ERR(cdev, "Failed to stop RXQ#%02x\n", rss_id);
  1859. return rc;
  1860. }
  1861. return 0;
  1862. }
  1863. static int qed_start_txq(struct qed_dev *cdev,
  1864. u8 rss_num,
  1865. struct qed_queue_start_common_params *p_params,
  1866. dma_addr_t pbl_addr,
  1867. u16 pbl_size,
  1868. struct qed_txq_start_ret_params *ret_params)
  1869. {
  1870. struct qed_hwfn *p_hwfn;
  1871. int rc, hwfn_index;
  1872. hwfn_index = rss_num % cdev->num_hwfns;
  1873. p_hwfn = &cdev->hwfns[hwfn_index];
  1874. p_params->queue_id = p_params->queue_id / cdev->num_hwfns;
  1875. p_params->stats_id = p_params->vport_id;
  1876. rc = qed_eth_tx_queue_start(p_hwfn,
  1877. p_hwfn->hw_info.opaque_fid,
  1878. p_params, 0,
  1879. pbl_addr, pbl_size, ret_params);
  1880. if (rc) {
  1881. DP_ERR(cdev, "Failed to start TXQ#%d\n", p_params->queue_id);
  1882. return rc;
  1883. }
  1884. DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
  1885. "Started TX-Q %d [rss_num %d] on V-PORT %d and SB %d\n",
  1886. p_params->queue_id, rss_num, p_params->vport_id,
  1887. p_params->sb);
  1888. return 0;
  1889. }
  1890. #define QED_HW_STOP_RETRY_LIMIT (10)
  1891. static int qed_fastpath_stop(struct qed_dev *cdev)
  1892. {
  1893. int rc;
  1894. rc = qed_hw_stop_fastpath(cdev);
  1895. if (rc) {
  1896. DP_ERR(cdev, "Failed to stop Fastpath\n");
  1897. return rc;
  1898. }
  1899. return 0;
  1900. }
  1901. static int qed_stop_txq(struct qed_dev *cdev, u8 rss_id, void *handle)
  1902. {
  1903. struct qed_hwfn *p_hwfn;
  1904. int rc, hwfn_index;
  1905. hwfn_index = rss_id % cdev->num_hwfns;
  1906. p_hwfn = &cdev->hwfns[hwfn_index];
  1907. rc = qed_eth_tx_queue_stop(p_hwfn, handle);
  1908. if (rc) {
  1909. DP_ERR(cdev, "Failed to stop TXQ#%02x\n", rss_id);
  1910. return rc;
  1911. }
  1912. return 0;
  1913. }
  1914. static int qed_tunn_configure(struct qed_dev *cdev,
  1915. struct qed_tunn_params *tunn_params)
  1916. {
  1917. struct qed_tunnel_info tunn_info;
  1918. int i, rc;
  1919. memset(&tunn_info, 0, sizeof(tunn_info));
  1920. if (tunn_params->update_vxlan_port) {
  1921. tunn_info.vxlan_port.b_update_port = true;
  1922. tunn_info.vxlan_port.port = tunn_params->vxlan_port;
  1923. }
  1924. if (tunn_params->update_geneve_port) {
  1925. tunn_info.geneve_port.b_update_port = true;
  1926. tunn_info.geneve_port.port = tunn_params->geneve_port;
  1927. }
  1928. for_each_hwfn(cdev, i) {
  1929. struct qed_hwfn *hwfn = &cdev->hwfns[i];
  1930. struct qed_tunnel_info *tun;
  1931. tun = &hwfn->cdev->tunnel;
  1932. rc = qed_sp_pf_update_tunn_cfg(hwfn, &tunn_info,
  1933. QED_SPQ_MODE_EBLOCK, NULL);
  1934. if (rc)
  1935. return rc;
  1936. if (IS_PF_SRIOV(hwfn)) {
  1937. u16 vxlan_port, geneve_port;
  1938. int j;
  1939. vxlan_port = tun->vxlan_port.port;
  1940. geneve_port = tun->geneve_port.port;
  1941. qed_for_each_vf(hwfn, j) {
  1942. qed_iov_bulletin_set_udp_ports(hwfn, j,
  1943. vxlan_port,
  1944. geneve_port);
  1945. }
  1946. qed_schedule_iov(hwfn, QED_IOV_WQ_BULLETIN_UPDATE_FLAG);
  1947. }
  1948. }
  1949. return 0;
  1950. }
  1951. static int qed_configure_filter_rx_mode(struct qed_dev *cdev,
  1952. enum qed_filter_rx_mode_type type)
  1953. {
  1954. struct qed_filter_accept_flags accept_flags;
  1955. memset(&accept_flags, 0, sizeof(accept_flags));
  1956. accept_flags.update_rx_mode_config = 1;
  1957. accept_flags.update_tx_mode_config = 1;
  1958. accept_flags.rx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
  1959. QED_ACCEPT_MCAST_MATCHED |
  1960. QED_ACCEPT_BCAST;
  1961. accept_flags.tx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
  1962. QED_ACCEPT_MCAST_MATCHED |
  1963. QED_ACCEPT_BCAST;
  1964. if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
  1965. accept_flags.rx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED |
  1966. QED_ACCEPT_MCAST_UNMATCHED;
  1967. accept_flags.tx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
  1968. } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
  1969. accept_flags.rx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
  1970. accept_flags.tx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
  1971. }
  1972. return qed_filter_accept_cmd(cdev, 0, accept_flags, false, false,
  1973. QED_SPQ_MODE_CB, NULL);
  1974. }
  1975. static int qed_configure_filter_ucast(struct qed_dev *cdev,
  1976. struct qed_filter_ucast_params *params)
  1977. {
  1978. struct qed_filter_ucast ucast;
  1979. if (!params->vlan_valid && !params->mac_valid) {
  1980. DP_NOTICE(cdev,
  1981. "Tried configuring a unicast filter, but both MAC and VLAN are not set\n");
  1982. return -EINVAL;
  1983. }
  1984. memset(&ucast, 0, sizeof(ucast));
  1985. switch (params->type) {
  1986. case QED_FILTER_XCAST_TYPE_ADD:
  1987. ucast.opcode = QED_FILTER_ADD;
  1988. break;
  1989. case QED_FILTER_XCAST_TYPE_DEL:
  1990. ucast.opcode = QED_FILTER_REMOVE;
  1991. break;
  1992. case QED_FILTER_XCAST_TYPE_REPLACE:
  1993. ucast.opcode = QED_FILTER_REPLACE;
  1994. break;
  1995. default:
  1996. DP_NOTICE(cdev, "Unknown unicast filter type %d\n",
  1997. params->type);
  1998. }
  1999. if (params->vlan_valid && params->mac_valid) {
  2000. ucast.type = QED_FILTER_MAC_VLAN;
  2001. ether_addr_copy(ucast.mac, params->mac);
  2002. ucast.vlan = params->vlan;
  2003. } else if (params->mac_valid) {
  2004. ucast.type = QED_FILTER_MAC;
  2005. ether_addr_copy(ucast.mac, params->mac);
  2006. } else {
  2007. ucast.type = QED_FILTER_VLAN;
  2008. ucast.vlan = params->vlan;
  2009. }
  2010. ucast.is_rx_filter = true;
  2011. ucast.is_tx_filter = true;
  2012. return qed_filter_ucast_cmd(cdev, &ucast, QED_SPQ_MODE_CB, NULL);
  2013. }
  2014. static int qed_configure_filter_mcast(struct qed_dev *cdev,
  2015. struct qed_filter_mcast_params *params)
  2016. {
  2017. struct qed_filter_mcast mcast;
  2018. int i;
  2019. memset(&mcast, 0, sizeof(mcast));
  2020. switch (params->type) {
  2021. case QED_FILTER_XCAST_TYPE_ADD:
  2022. mcast.opcode = QED_FILTER_ADD;
  2023. break;
  2024. case QED_FILTER_XCAST_TYPE_DEL:
  2025. mcast.opcode = QED_FILTER_REMOVE;
  2026. break;
  2027. default:
  2028. DP_NOTICE(cdev, "Unknown multicast filter type %d\n",
  2029. params->type);
  2030. }
  2031. mcast.num_mc_addrs = params->num;
  2032. for (i = 0; i < mcast.num_mc_addrs; i++)
  2033. ether_addr_copy(mcast.mac[i], params->mac[i]);
  2034. return qed_filter_mcast_cmd(cdev, &mcast, QED_SPQ_MODE_CB, NULL);
  2035. }
  2036. static int qed_configure_filter(struct qed_dev *cdev,
  2037. struct qed_filter_params *params)
  2038. {
  2039. enum qed_filter_rx_mode_type accept_flags;
  2040. switch (params->type) {
  2041. case QED_FILTER_TYPE_UCAST:
  2042. return qed_configure_filter_ucast(cdev, &params->filter.ucast);
  2043. case QED_FILTER_TYPE_MCAST:
  2044. return qed_configure_filter_mcast(cdev, &params->filter.mcast);
  2045. case QED_FILTER_TYPE_RX_MODE:
  2046. accept_flags = params->filter.accept_flags;
  2047. return qed_configure_filter_rx_mode(cdev, accept_flags);
  2048. default:
  2049. DP_NOTICE(cdev, "Unknown filter type %d\n", (int)params->type);
  2050. return -EINVAL;
  2051. }
  2052. }
  2053. static int qed_configure_arfs_searcher(struct qed_dev *cdev, bool en_searcher)
  2054. {
  2055. struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
  2056. struct qed_arfs_config_params arfs_config_params;
  2057. memset(&arfs_config_params, 0, sizeof(arfs_config_params));
  2058. arfs_config_params.tcp = true;
  2059. arfs_config_params.udp = true;
  2060. arfs_config_params.ipv4 = true;
  2061. arfs_config_params.ipv6 = true;
  2062. arfs_config_params.arfs_enable = en_searcher;
  2063. qed_arfs_mode_configure(p_hwfn, p_hwfn->p_arfs_ptt,
  2064. &arfs_config_params);
  2065. return 0;
  2066. }
  2067. static void
  2068. qed_arfs_sp_response_handler(struct qed_hwfn *p_hwfn,
  2069. void *cookie, union event_ring_data *data,
  2070. u8 fw_return_code)
  2071. {
  2072. struct qed_common_cb_ops *op = p_hwfn->cdev->protocol_ops.common;
  2073. void *dev = p_hwfn->cdev->ops_cookie;
  2074. op->arfs_filter_op(dev, cookie, fw_return_code);
  2075. }
  2076. static int qed_ntuple_arfs_filter_config(struct qed_dev *cdev, void *cookie,
  2077. dma_addr_t mapping, u16 length,
  2078. u16 vport_id, u16 rx_queue_id,
  2079. bool add_filter)
  2080. {
  2081. struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
  2082. struct qed_spq_comp_cb cb;
  2083. int rc = -EINVAL;
  2084. cb.function = qed_arfs_sp_response_handler;
  2085. cb.cookie = cookie;
  2086. rc = qed_configure_rfs_ntuple_filter(p_hwfn, p_hwfn->p_arfs_ptt,
  2087. &cb, mapping, length, rx_queue_id,
  2088. vport_id, add_filter);
  2089. if (rc)
  2090. DP_NOTICE(p_hwfn,
  2091. "Failed to issue a-RFS filter configuration\n");
  2092. else
  2093. DP_VERBOSE(p_hwfn, NETIF_MSG_DRV,
  2094. "Successfully issued a-RFS filter configuration\n");
  2095. return rc;
  2096. }
  2097. static int qed_fp_cqe_completion(struct qed_dev *dev,
  2098. u8 rss_id, struct eth_slow_path_rx_cqe *cqe)
  2099. {
  2100. return qed_eth_cqe_completion(&dev->hwfns[rss_id % dev->num_hwfns],
  2101. cqe);
  2102. }
  2103. #ifdef CONFIG_QED_SRIOV
  2104. extern const struct qed_iov_hv_ops qed_iov_ops_pass;
  2105. #endif
  2106. #ifdef CONFIG_DCB
  2107. extern const struct qed_eth_dcbnl_ops qed_dcbnl_ops_pass;
  2108. #endif
  2109. extern const struct qed_eth_ptp_ops qed_ptp_ops_pass;
  2110. static const struct qed_eth_ops qed_eth_ops_pass = {
  2111. .common = &qed_common_ops_pass,
  2112. #ifdef CONFIG_QED_SRIOV
  2113. .iov = &qed_iov_ops_pass,
  2114. #endif
  2115. #ifdef CONFIG_DCB
  2116. .dcb = &qed_dcbnl_ops_pass,
  2117. #endif
  2118. .ptp = &qed_ptp_ops_pass,
  2119. .fill_dev_info = &qed_fill_eth_dev_info,
  2120. .register_ops = &qed_register_eth_ops,
  2121. .check_mac = &qed_check_mac,
  2122. .vport_start = &qed_start_vport,
  2123. .vport_stop = &qed_stop_vport,
  2124. .vport_update = &qed_update_vport,
  2125. .q_rx_start = &qed_start_rxq,
  2126. .q_rx_stop = &qed_stop_rxq,
  2127. .q_tx_start = &qed_start_txq,
  2128. .q_tx_stop = &qed_stop_txq,
  2129. .filter_config = &qed_configure_filter,
  2130. .fastpath_stop = &qed_fastpath_stop,
  2131. .eth_cqe_completion = &qed_fp_cqe_completion,
  2132. .get_vport_stats = &qed_get_vport_stats,
  2133. .tunn_config = &qed_tunn_configure,
  2134. .ntuple_filter_config = &qed_ntuple_arfs_filter_config,
  2135. .configure_arfs_searcher = &qed_configure_arfs_searcher,
  2136. };
  2137. const struct qed_eth_ops *qed_get_eth_ops(void)
  2138. {
  2139. return &qed_eth_ops_pass;
  2140. }
  2141. EXPORT_SYMBOL(qed_get_eth_ops);
  2142. void qed_put_eth_ops(void)
  2143. {
  2144. /* TODO - reference count for module? */
  2145. }
  2146. EXPORT_SYMBOL(qed_put_eth_ops);