w90p910_ether.c 25 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Nuvoton technology corporation.
  3. *
  4. * Wan ZongShun <mcuos.com@gmail.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation;version 2 of the License.
  9. *
  10. */
  11. #include <linux/module.h>
  12. #include <linux/init.h>
  13. #include <linux/mii.h>
  14. #include <linux/netdevice.h>
  15. #include <linux/etherdevice.h>
  16. #include <linux/skbuff.h>
  17. #include <linux/ethtool.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/clk.h>
  20. #include <linux/gfp.h>
  21. #define DRV_MODULE_NAME "w90p910-emc"
  22. #define DRV_MODULE_VERSION "0.1"
  23. /* Ethernet MAC Registers */
  24. #define REG_CAMCMR 0x00
  25. #define REG_CAMEN 0x04
  26. #define REG_CAMM_BASE 0x08
  27. #define REG_CAML_BASE 0x0c
  28. #define REG_TXDLSA 0x88
  29. #define REG_RXDLSA 0x8C
  30. #define REG_MCMDR 0x90
  31. #define REG_MIID 0x94
  32. #define REG_MIIDA 0x98
  33. #define REG_FFTCR 0x9C
  34. #define REG_TSDR 0xa0
  35. #define REG_RSDR 0xa4
  36. #define REG_DMARFC 0xa8
  37. #define REG_MIEN 0xac
  38. #define REG_MISTA 0xb0
  39. #define REG_CTXDSA 0xcc
  40. #define REG_CTXBSA 0xd0
  41. #define REG_CRXDSA 0xd4
  42. #define REG_CRXBSA 0xd8
  43. /* mac controller bit */
  44. #define MCMDR_RXON 0x01
  45. #define MCMDR_ACP (0x01 << 3)
  46. #define MCMDR_SPCRC (0x01 << 5)
  47. #define MCMDR_TXON (0x01 << 8)
  48. #define MCMDR_FDUP (0x01 << 18)
  49. #define MCMDR_ENMDC (0x01 << 19)
  50. #define MCMDR_OPMOD (0x01 << 20)
  51. #define SWR (0x01 << 24)
  52. /* cam command regiser */
  53. #define CAMCMR_AUP 0x01
  54. #define CAMCMR_AMP (0x01 << 1)
  55. #define CAMCMR_ABP (0x01 << 2)
  56. #define CAMCMR_CCAM (0x01 << 3)
  57. #define CAMCMR_ECMP (0x01 << 4)
  58. #define CAM0EN 0x01
  59. /* mac mii controller bit */
  60. #define MDCCR (0x0a << 20)
  61. #define PHYAD (0x01 << 8)
  62. #define PHYWR (0x01 << 16)
  63. #define PHYBUSY (0x01 << 17)
  64. #define PHYPRESP (0x01 << 18)
  65. #define CAM_ENTRY_SIZE 0x08
  66. /* rx and tx status */
  67. #define TXDS_TXCP (0x01 << 19)
  68. #define RXDS_CRCE (0x01 << 17)
  69. #define RXDS_PTLE (0x01 << 19)
  70. #define RXDS_RXGD (0x01 << 20)
  71. #define RXDS_ALIE (0x01 << 21)
  72. #define RXDS_RP (0x01 << 22)
  73. /* mac interrupt status*/
  74. #define MISTA_EXDEF (0x01 << 19)
  75. #define MISTA_TXBERR (0x01 << 24)
  76. #define MISTA_TDU (0x01 << 23)
  77. #define MISTA_RDU (0x01 << 10)
  78. #define MISTA_RXBERR (0x01 << 11)
  79. #define ENSTART 0x01
  80. #define ENRXINTR 0x01
  81. #define ENRXGD (0x01 << 4)
  82. #define ENRXBERR (0x01 << 11)
  83. #define ENTXINTR (0x01 << 16)
  84. #define ENTXCP (0x01 << 18)
  85. #define ENTXABT (0x01 << 21)
  86. #define ENTXBERR (0x01 << 24)
  87. #define ENMDC (0x01 << 19)
  88. #define PHYBUSY (0x01 << 17)
  89. #define MDCCR_VAL 0xa00000
  90. /* rx and tx owner bit */
  91. #define RX_OWEN_DMA (0x01 << 31)
  92. #define RX_OWEN_CPU (~(0x03 << 30))
  93. #define TX_OWEN_DMA (0x01 << 31)
  94. #define TX_OWEN_CPU (~(0x01 << 31))
  95. /* tx frame desc controller bit */
  96. #define MACTXINTEN 0x04
  97. #define CRCMODE 0x02
  98. #define PADDINGMODE 0x01
  99. /* fftcr controller bit */
  100. #define TXTHD (0x03 << 8)
  101. #define BLENGTH (0x01 << 20)
  102. /* global setting for driver */
  103. #define RX_DESC_SIZE 50
  104. #define TX_DESC_SIZE 10
  105. #define MAX_RBUFF_SZ 0x600
  106. #define MAX_TBUFF_SZ 0x600
  107. #define TX_TIMEOUT (HZ/2)
  108. #define DELAY 1000
  109. #define CAM0 0x0
  110. static int w90p910_mdio_read(struct net_device *dev, int phy_id, int reg);
  111. struct w90p910_rxbd {
  112. unsigned int sl;
  113. unsigned int buffer;
  114. unsigned int reserved;
  115. unsigned int next;
  116. };
  117. struct w90p910_txbd {
  118. unsigned int mode;
  119. unsigned int buffer;
  120. unsigned int sl;
  121. unsigned int next;
  122. };
  123. struct recv_pdesc {
  124. struct w90p910_rxbd desclist[RX_DESC_SIZE];
  125. char recv_buf[RX_DESC_SIZE][MAX_RBUFF_SZ];
  126. };
  127. struct tran_pdesc {
  128. struct w90p910_txbd desclist[TX_DESC_SIZE];
  129. char tran_buf[TX_DESC_SIZE][MAX_TBUFF_SZ];
  130. };
  131. struct w90p910_ether {
  132. struct recv_pdesc *rdesc;
  133. struct tran_pdesc *tdesc;
  134. dma_addr_t rdesc_phys;
  135. dma_addr_t tdesc_phys;
  136. struct platform_device *pdev;
  137. struct resource *res;
  138. struct sk_buff *skb;
  139. struct clk *clk;
  140. struct clk *rmiiclk;
  141. struct mii_if_info mii;
  142. struct timer_list check_timer;
  143. void __iomem *reg;
  144. int rxirq;
  145. int txirq;
  146. unsigned int cur_tx;
  147. unsigned int cur_rx;
  148. unsigned int finish_tx;
  149. unsigned int rx_packets;
  150. unsigned int rx_bytes;
  151. unsigned int start_tx_ptr;
  152. unsigned int start_rx_ptr;
  153. unsigned int linkflag;
  154. };
  155. static void update_linkspeed_register(struct net_device *dev,
  156. unsigned int speed, unsigned int duplex)
  157. {
  158. struct w90p910_ether *ether = netdev_priv(dev);
  159. unsigned int val;
  160. val = __raw_readl(ether->reg + REG_MCMDR);
  161. if (speed == SPEED_100) {
  162. /* 100 full/half duplex */
  163. if (duplex == DUPLEX_FULL) {
  164. val |= (MCMDR_OPMOD | MCMDR_FDUP);
  165. } else {
  166. val |= MCMDR_OPMOD;
  167. val &= ~MCMDR_FDUP;
  168. }
  169. } else {
  170. /* 10 full/half duplex */
  171. if (duplex == DUPLEX_FULL) {
  172. val |= MCMDR_FDUP;
  173. val &= ~MCMDR_OPMOD;
  174. } else {
  175. val &= ~(MCMDR_FDUP | MCMDR_OPMOD);
  176. }
  177. }
  178. __raw_writel(val, ether->reg + REG_MCMDR);
  179. }
  180. static void update_linkspeed(struct net_device *dev)
  181. {
  182. struct w90p910_ether *ether = netdev_priv(dev);
  183. struct platform_device *pdev;
  184. unsigned int bmsr, bmcr, lpa, speed, duplex;
  185. pdev = ether->pdev;
  186. if (!mii_link_ok(&ether->mii)) {
  187. ether->linkflag = 0x0;
  188. netif_carrier_off(dev);
  189. dev_warn(&pdev->dev, "%s: Link down.\n", dev->name);
  190. return;
  191. }
  192. if (ether->linkflag == 1)
  193. return;
  194. bmsr = w90p910_mdio_read(dev, ether->mii.phy_id, MII_BMSR);
  195. bmcr = w90p910_mdio_read(dev, ether->mii.phy_id, MII_BMCR);
  196. if (bmcr & BMCR_ANENABLE) {
  197. if (!(bmsr & BMSR_ANEGCOMPLETE))
  198. return;
  199. lpa = w90p910_mdio_read(dev, ether->mii.phy_id, MII_LPA);
  200. if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF))
  201. speed = SPEED_100;
  202. else
  203. speed = SPEED_10;
  204. if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL))
  205. duplex = DUPLEX_FULL;
  206. else
  207. duplex = DUPLEX_HALF;
  208. } else {
  209. speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
  210. duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
  211. }
  212. update_linkspeed_register(dev, speed, duplex);
  213. dev_info(&pdev->dev, "%s: Link now %i-%s\n", dev->name, speed,
  214. (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex");
  215. ether->linkflag = 0x01;
  216. netif_carrier_on(dev);
  217. }
  218. static void w90p910_check_link(unsigned long dev_id)
  219. {
  220. struct net_device *dev = (struct net_device *) dev_id;
  221. struct w90p910_ether *ether = netdev_priv(dev);
  222. update_linkspeed(dev);
  223. mod_timer(&ether->check_timer, jiffies + msecs_to_jiffies(1000));
  224. }
  225. static void w90p910_write_cam(struct net_device *dev,
  226. unsigned int x, unsigned char *pval)
  227. {
  228. struct w90p910_ether *ether = netdev_priv(dev);
  229. unsigned int msw, lsw;
  230. msw = (pval[0] << 24) | (pval[1] << 16) | (pval[2] << 8) | pval[3];
  231. lsw = (pval[4] << 24) | (pval[5] << 16);
  232. __raw_writel(lsw, ether->reg + REG_CAML_BASE + x * CAM_ENTRY_SIZE);
  233. __raw_writel(msw, ether->reg + REG_CAMM_BASE + x * CAM_ENTRY_SIZE);
  234. }
  235. static int w90p910_init_desc(struct net_device *dev)
  236. {
  237. struct w90p910_ether *ether;
  238. struct w90p910_txbd *tdesc;
  239. struct w90p910_rxbd *rdesc;
  240. struct platform_device *pdev;
  241. unsigned int i;
  242. ether = netdev_priv(dev);
  243. pdev = ether->pdev;
  244. ether->tdesc = dma_alloc_coherent(&pdev->dev, sizeof(struct tran_pdesc),
  245. &ether->tdesc_phys, GFP_KERNEL);
  246. if (!ether->tdesc)
  247. return -ENOMEM;
  248. ether->rdesc = dma_alloc_coherent(&pdev->dev, sizeof(struct recv_pdesc),
  249. &ether->rdesc_phys, GFP_KERNEL);
  250. if (!ether->rdesc) {
  251. dma_free_coherent(&pdev->dev, sizeof(struct tran_pdesc),
  252. ether->tdesc, ether->tdesc_phys);
  253. return -ENOMEM;
  254. }
  255. for (i = 0; i < TX_DESC_SIZE; i++) {
  256. unsigned int offset;
  257. tdesc = &(ether->tdesc->desclist[i]);
  258. if (i == TX_DESC_SIZE - 1)
  259. offset = offsetof(struct tran_pdesc, desclist[0]);
  260. else
  261. offset = offsetof(struct tran_pdesc, desclist[i + 1]);
  262. tdesc->next = ether->tdesc_phys + offset;
  263. tdesc->buffer = ether->tdesc_phys +
  264. offsetof(struct tran_pdesc, tran_buf[i]);
  265. tdesc->sl = 0;
  266. tdesc->mode = 0;
  267. }
  268. ether->start_tx_ptr = ether->tdesc_phys;
  269. for (i = 0; i < RX_DESC_SIZE; i++) {
  270. unsigned int offset;
  271. rdesc = &(ether->rdesc->desclist[i]);
  272. if (i == RX_DESC_SIZE - 1)
  273. offset = offsetof(struct recv_pdesc, desclist[0]);
  274. else
  275. offset = offsetof(struct recv_pdesc, desclist[i + 1]);
  276. rdesc->next = ether->rdesc_phys + offset;
  277. rdesc->sl = RX_OWEN_DMA;
  278. rdesc->buffer = ether->rdesc_phys +
  279. offsetof(struct recv_pdesc, recv_buf[i]);
  280. }
  281. ether->start_rx_ptr = ether->rdesc_phys;
  282. return 0;
  283. }
  284. static void w90p910_set_fifo_threshold(struct net_device *dev)
  285. {
  286. struct w90p910_ether *ether = netdev_priv(dev);
  287. unsigned int val;
  288. val = TXTHD | BLENGTH;
  289. __raw_writel(val, ether->reg + REG_FFTCR);
  290. }
  291. static void w90p910_return_default_idle(struct net_device *dev)
  292. {
  293. struct w90p910_ether *ether = netdev_priv(dev);
  294. unsigned int val;
  295. val = __raw_readl(ether->reg + REG_MCMDR);
  296. val |= SWR;
  297. __raw_writel(val, ether->reg + REG_MCMDR);
  298. }
  299. static void w90p910_trigger_rx(struct net_device *dev)
  300. {
  301. struct w90p910_ether *ether = netdev_priv(dev);
  302. __raw_writel(ENSTART, ether->reg + REG_RSDR);
  303. }
  304. static void w90p910_trigger_tx(struct net_device *dev)
  305. {
  306. struct w90p910_ether *ether = netdev_priv(dev);
  307. __raw_writel(ENSTART, ether->reg + REG_TSDR);
  308. }
  309. static void w90p910_enable_mac_interrupt(struct net_device *dev)
  310. {
  311. struct w90p910_ether *ether = netdev_priv(dev);
  312. unsigned int val;
  313. val = ENTXINTR | ENRXINTR | ENRXGD | ENTXCP;
  314. val |= ENTXBERR | ENRXBERR | ENTXABT;
  315. __raw_writel(val, ether->reg + REG_MIEN);
  316. }
  317. static void w90p910_get_and_clear_int(struct net_device *dev,
  318. unsigned int *val)
  319. {
  320. struct w90p910_ether *ether = netdev_priv(dev);
  321. *val = __raw_readl(ether->reg + REG_MISTA);
  322. __raw_writel(*val, ether->reg + REG_MISTA);
  323. }
  324. static void w90p910_set_global_maccmd(struct net_device *dev)
  325. {
  326. struct w90p910_ether *ether = netdev_priv(dev);
  327. unsigned int val;
  328. val = __raw_readl(ether->reg + REG_MCMDR);
  329. val |= MCMDR_SPCRC | MCMDR_ENMDC | MCMDR_ACP | ENMDC;
  330. __raw_writel(val, ether->reg + REG_MCMDR);
  331. }
  332. static void w90p910_enable_cam(struct net_device *dev)
  333. {
  334. struct w90p910_ether *ether = netdev_priv(dev);
  335. unsigned int val;
  336. w90p910_write_cam(dev, CAM0, dev->dev_addr);
  337. val = __raw_readl(ether->reg + REG_CAMEN);
  338. val |= CAM0EN;
  339. __raw_writel(val, ether->reg + REG_CAMEN);
  340. }
  341. static void w90p910_enable_cam_command(struct net_device *dev)
  342. {
  343. struct w90p910_ether *ether = netdev_priv(dev);
  344. unsigned int val;
  345. val = CAMCMR_ECMP | CAMCMR_ABP | CAMCMR_AMP;
  346. __raw_writel(val, ether->reg + REG_CAMCMR);
  347. }
  348. static void w90p910_enable_tx(struct net_device *dev, unsigned int enable)
  349. {
  350. struct w90p910_ether *ether = netdev_priv(dev);
  351. unsigned int val;
  352. val = __raw_readl(ether->reg + REG_MCMDR);
  353. if (enable)
  354. val |= MCMDR_TXON;
  355. else
  356. val &= ~MCMDR_TXON;
  357. __raw_writel(val, ether->reg + REG_MCMDR);
  358. }
  359. static void w90p910_enable_rx(struct net_device *dev, unsigned int enable)
  360. {
  361. struct w90p910_ether *ether = netdev_priv(dev);
  362. unsigned int val;
  363. val = __raw_readl(ether->reg + REG_MCMDR);
  364. if (enable)
  365. val |= MCMDR_RXON;
  366. else
  367. val &= ~MCMDR_RXON;
  368. __raw_writel(val, ether->reg + REG_MCMDR);
  369. }
  370. static void w90p910_set_curdest(struct net_device *dev)
  371. {
  372. struct w90p910_ether *ether = netdev_priv(dev);
  373. __raw_writel(ether->start_rx_ptr, ether->reg + REG_RXDLSA);
  374. __raw_writel(ether->start_tx_ptr, ether->reg + REG_TXDLSA);
  375. }
  376. static void w90p910_reset_mac(struct net_device *dev)
  377. {
  378. struct w90p910_ether *ether = netdev_priv(dev);
  379. w90p910_enable_tx(dev, 0);
  380. w90p910_enable_rx(dev, 0);
  381. w90p910_set_fifo_threshold(dev);
  382. w90p910_return_default_idle(dev);
  383. if (!netif_queue_stopped(dev))
  384. netif_stop_queue(dev);
  385. w90p910_init_desc(dev);
  386. netif_trans_update(dev); /* prevent tx timeout */
  387. ether->cur_tx = 0x0;
  388. ether->finish_tx = 0x0;
  389. ether->cur_rx = 0x0;
  390. w90p910_set_curdest(dev);
  391. w90p910_enable_cam(dev);
  392. w90p910_enable_cam_command(dev);
  393. w90p910_enable_mac_interrupt(dev);
  394. w90p910_enable_tx(dev, 1);
  395. w90p910_enable_rx(dev, 1);
  396. w90p910_trigger_tx(dev);
  397. w90p910_trigger_rx(dev);
  398. netif_trans_update(dev); /* prevent tx timeout */
  399. if (netif_queue_stopped(dev))
  400. netif_wake_queue(dev);
  401. }
  402. static void w90p910_mdio_write(struct net_device *dev,
  403. int phy_id, int reg, int data)
  404. {
  405. struct w90p910_ether *ether = netdev_priv(dev);
  406. struct platform_device *pdev;
  407. unsigned int val, i;
  408. pdev = ether->pdev;
  409. __raw_writel(data, ether->reg + REG_MIID);
  410. val = (phy_id << 0x08) | reg;
  411. val |= PHYBUSY | PHYWR | MDCCR_VAL;
  412. __raw_writel(val, ether->reg + REG_MIIDA);
  413. for (i = 0; i < DELAY; i++) {
  414. if ((__raw_readl(ether->reg + REG_MIIDA) & PHYBUSY) == 0)
  415. break;
  416. }
  417. if (i == DELAY)
  418. dev_warn(&pdev->dev, "mdio write timed out\n");
  419. }
  420. static int w90p910_mdio_read(struct net_device *dev, int phy_id, int reg)
  421. {
  422. struct w90p910_ether *ether = netdev_priv(dev);
  423. struct platform_device *pdev;
  424. unsigned int val, i, data;
  425. pdev = ether->pdev;
  426. val = (phy_id << 0x08) | reg;
  427. val |= PHYBUSY | MDCCR_VAL;
  428. __raw_writel(val, ether->reg + REG_MIIDA);
  429. for (i = 0; i < DELAY; i++) {
  430. if ((__raw_readl(ether->reg + REG_MIIDA) & PHYBUSY) == 0)
  431. break;
  432. }
  433. if (i == DELAY) {
  434. dev_warn(&pdev->dev, "mdio read timed out\n");
  435. data = 0xffff;
  436. } else {
  437. data = __raw_readl(ether->reg + REG_MIID);
  438. }
  439. return data;
  440. }
  441. static int w90p910_set_mac_address(struct net_device *dev, void *addr)
  442. {
  443. struct sockaddr *address = addr;
  444. if (!is_valid_ether_addr(address->sa_data))
  445. return -EADDRNOTAVAIL;
  446. memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
  447. w90p910_write_cam(dev, CAM0, dev->dev_addr);
  448. return 0;
  449. }
  450. static int w90p910_ether_close(struct net_device *dev)
  451. {
  452. struct w90p910_ether *ether = netdev_priv(dev);
  453. struct platform_device *pdev;
  454. pdev = ether->pdev;
  455. dma_free_coherent(&pdev->dev, sizeof(struct recv_pdesc),
  456. ether->rdesc, ether->rdesc_phys);
  457. dma_free_coherent(&pdev->dev, sizeof(struct tran_pdesc),
  458. ether->tdesc, ether->tdesc_phys);
  459. netif_stop_queue(dev);
  460. del_timer_sync(&ether->check_timer);
  461. clk_disable(ether->rmiiclk);
  462. clk_disable(ether->clk);
  463. free_irq(ether->txirq, dev);
  464. free_irq(ether->rxirq, dev);
  465. return 0;
  466. }
  467. static int w90p910_send_frame(struct net_device *dev,
  468. unsigned char *data, int length)
  469. {
  470. struct w90p910_ether *ether;
  471. struct w90p910_txbd *txbd;
  472. struct platform_device *pdev;
  473. unsigned char *buffer;
  474. ether = netdev_priv(dev);
  475. pdev = ether->pdev;
  476. txbd = &ether->tdesc->desclist[ether->cur_tx];
  477. buffer = ether->tdesc->tran_buf[ether->cur_tx];
  478. if (length > 1514) {
  479. dev_err(&pdev->dev, "send data %d bytes, check it\n", length);
  480. length = 1514;
  481. }
  482. txbd->sl = length & 0xFFFF;
  483. memcpy(buffer, data, length);
  484. txbd->mode = TX_OWEN_DMA | PADDINGMODE | CRCMODE | MACTXINTEN;
  485. w90p910_enable_tx(dev, 1);
  486. w90p910_trigger_tx(dev);
  487. if (++ether->cur_tx >= TX_DESC_SIZE)
  488. ether->cur_tx = 0;
  489. txbd = &ether->tdesc->desclist[ether->cur_tx];
  490. if (txbd->mode & TX_OWEN_DMA)
  491. netif_stop_queue(dev);
  492. return 0;
  493. }
  494. static int w90p910_ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
  495. {
  496. struct w90p910_ether *ether = netdev_priv(dev);
  497. if (!(w90p910_send_frame(dev, skb->data, skb->len))) {
  498. ether->skb = skb;
  499. dev_kfree_skb_irq(skb);
  500. return 0;
  501. }
  502. return -EAGAIN;
  503. }
  504. static irqreturn_t w90p910_tx_interrupt(int irq, void *dev_id)
  505. {
  506. struct w90p910_ether *ether;
  507. struct w90p910_txbd *txbd;
  508. struct platform_device *pdev;
  509. struct net_device *dev;
  510. unsigned int cur_entry, entry, status;
  511. dev = dev_id;
  512. ether = netdev_priv(dev);
  513. pdev = ether->pdev;
  514. w90p910_get_and_clear_int(dev, &status);
  515. cur_entry = __raw_readl(ether->reg + REG_CTXDSA);
  516. entry = ether->tdesc_phys +
  517. offsetof(struct tran_pdesc, desclist[ether->finish_tx]);
  518. while (entry != cur_entry) {
  519. txbd = &ether->tdesc->desclist[ether->finish_tx];
  520. if (++ether->finish_tx >= TX_DESC_SIZE)
  521. ether->finish_tx = 0;
  522. if (txbd->sl & TXDS_TXCP) {
  523. dev->stats.tx_packets++;
  524. dev->stats.tx_bytes += txbd->sl & 0xFFFF;
  525. } else {
  526. dev->stats.tx_errors++;
  527. }
  528. txbd->sl = 0x0;
  529. txbd->mode = 0x0;
  530. if (netif_queue_stopped(dev))
  531. netif_wake_queue(dev);
  532. entry = ether->tdesc_phys +
  533. offsetof(struct tran_pdesc, desclist[ether->finish_tx]);
  534. }
  535. if (status & MISTA_EXDEF) {
  536. dev_err(&pdev->dev, "emc defer exceed interrupt\n");
  537. } else if (status & MISTA_TXBERR) {
  538. dev_err(&pdev->dev, "emc bus error interrupt\n");
  539. w90p910_reset_mac(dev);
  540. } else if (status & MISTA_TDU) {
  541. if (netif_queue_stopped(dev))
  542. netif_wake_queue(dev);
  543. }
  544. return IRQ_HANDLED;
  545. }
  546. static void netdev_rx(struct net_device *dev)
  547. {
  548. struct w90p910_ether *ether;
  549. struct w90p910_rxbd *rxbd;
  550. struct platform_device *pdev;
  551. struct sk_buff *skb;
  552. unsigned char *data;
  553. unsigned int length, status, val, entry;
  554. ether = netdev_priv(dev);
  555. pdev = ether->pdev;
  556. rxbd = &ether->rdesc->desclist[ether->cur_rx];
  557. do {
  558. val = __raw_readl(ether->reg + REG_CRXDSA);
  559. entry = ether->rdesc_phys +
  560. offsetof(struct recv_pdesc, desclist[ether->cur_rx]);
  561. if (val == entry)
  562. break;
  563. status = rxbd->sl;
  564. length = status & 0xFFFF;
  565. if (status & RXDS_RXGD) {
  566. data = ether->rdesc->recv_buf[ether->cur_rx];
  567. skb = netdev_alloc_skb(dev, length + 2);
  568. if (!skb) {
  569. dev->stats.rx_dropped++;
  570. return;
  571. }
  572. skb_reserve(skb, 2);
  573. skb_put(skb, length);
  574. skb_copy_to_linear_data(skb, data, length);
  575. skb->protocol = eth_type_trans(skb, dev);
  576. dev->stats.rx_packets++;
  577. dev->stats.rx_bytes += length;
  578. netif_rx(skb);
  579. } else {
  580. dev->stats.rx_errors++;
  581. if (status & RXDS_RP) {
  582. dev_err(&pdev->dev, "rx runt err\n");
  583. dev->stats.rx_length_errors++;
  584. } else if (status & RXDS_CRCE) {
  585. dev_err(&pdev->dev, "rx crc err\n");
  586. dev->stats.rx_crc_errors++;
  587. } else if (status & RXDS_ALIE) {
  588. dev_err(&pdev->dev, "rx alignment err\n");
  589. dev->stats.rx_frame_errors++;
  590. } else if (status & RXDS_PTLE) {
  591. dev_err(&pdev->dev, "rx longer err\n");
  592. dev->stats.rx_over_errors++;
  593. }
  594. }
  595. rxbd->sl = RX_OWEN_DMA;
  596. rxbd->reserved = 0x0;
  597. if (++ether->cur_rx >= RX_DESC_SIZE)
  598. ether->cur_rx = 0;
  599. rxbd = &ether->rdesc->desclist[ether->cur_rx];
  600. } while (1);
  601. }
  602. static irqreturn_t w90p910_rx_interrupt(int irq, void *dev_id)
  603. {
  604. struct net_device *dev;
  605. struct w90p910_ether *ether;
  606. struct platform_device *pdev;
  607. unsigned int status;
  608. dev = dev_id;
  609. ether = netdev_priv(dev);
  610. pdev = ether->pdev;
  611. w90p910_get_and_clear_int(dev, &status);
  612. if (status & MISTA_RDU) {
  613. netdev_rx(dev);
  614. w90p910_trigger_rx(dev);
  615. return IRQ_HANDLED;
  616. } else if (status & MISTA_RXBERR) {
  617. dev_err(&pdev->dev, "emc rx bus error\n");
  618. w90p910_reset_mac(dev);
  619. }
  620. netdev_rx(dev);
  621. return IRQ_HANDLED;
  622. }
  623. static int w90p910_ether_open(struct net_device *dev)
  624. {
  625. struct w90p910_ether *ether;
  626. struct platform_device *pdev;
  627. ether = netdev_priv(dev);
  628. pdev = ether->pdev;
  629. w90p910_reset_mac(dev);
  630. w90p910_set_fifo_threshold(dev);
  631. w90p910_set_curdest(dev);
  632. w90p910_enable_cam(dev);
  633. w90p910_enable_cam_command(dev);
  634. w90p910_enable_mac_interrupt(dev);
  635. w90p910_set_global_maccmd(dev);
  636. w90p910_enable_rx(dev, 1);
  637. clk_enable(ether->rmiiclk);
  638. clk_enable(ether->clk);
  639. ether->rx_packets = 0x0;
  640. ether->rx_bytes = 0x0;
  641. if (request_irq(ether->txirq, w90p910_tx_interrupt,
  642. 0x0, pdev->name, dev)) {
  643. dev_err(&pdev->dev, "register irq tx failed\n");
  644. return -EAGAIN;
  645. }
  646. if (request_irq(ether->rxirq, w90p910_rx_interrupt,
  647. 0x0, pdev->name, dev)) {
  648. dev_err(&pdev->dev, "register irq rx failed\n");
  649. free_irq(ether->txirq, dev);
  650. return -EAGAIN;
  651. }
  652. mod_timer(&ether->check_timer, jiffies + msecs_to_jiffies(1000));
  653. netif_start_queue(dev);
  654. w90p910_trigger_rx(dev);
  655. dev_info(&pdev->dev, "%s is OPENED\n", dev->name);
  656. return 0;
  657. }
  658. static void w90p910_ether_set_multicast_list(struct net_device *dev)
  659. {
  660. struct w90p910_ether *ether;
  661. unsigned int rx_mode;
  662. ether = netdev_priv(dev);
  663. if (dev->flags & IFF_PROMISC)
  664. rx_mode = CAMCMR_AUP | CAMCMR_AMP | CAMCMR_ABP | CAMCMR_ECMP;
  665. else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev))
  666. rx_mode = CAMCMR_AMP | CAMCMR_ABP | CAMCMR_ECMP;
  667. else
  668. rx_mode = CAMCMR_ECMP | CAMCMR_ABP;
  669. __raw_writel(rx_mode, ether->reg + REG_CAMCMR);
  670. }
  671. static int w90p910_ether_ioctl(struct net_device *dev,
  672. struct ifreq *ifr, int cmd)
  673. {
  674. struct w90p910_ether *ether = netdev_priv(dev);
  675. struct mii_ioctl_data *data = if_mii(ifr);
  676. return generic_mii_ioctl(&ether->mii, data, cmd, NULL);
  677. }
  678. static void w90p910_get_drvinfo(struct net_device *dev,
  679. struct ethtool_drvinfo *info)
  680. {
  681. strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
  682. strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
  683. }
  684. static int w90p910_get_link_ksettings(struct net_device *dev,
  685. struct ethtool_link_ksettings *cmd)
  686. {
  687. struct w90p910_ether *ether = netdev_priv(dev);
  688. return mii_ethtool_get_link_ksettings(&ether->mii, cmd);
  689. }
  690. static int w90p910_set_link_ksettings(struct net_device *dev,
  691. const struct ethtool_link_ksettings *cmd)
  692. {
  693. struct w90p910_ether *ether = netdev_priv(dev);
  694. return mii_ethtool_set_link_ksettings(&ether->mii, cmd);
  695. }
  696. static int w90p910_nway_reset(struct net_device *dev)
  697. {
  698. struct w90p910_ether *ether = netdev_priv(dev);
  699. return mii_nway_restart(&ether->mii);
  700. }
  701. static u32 w90p910_get_link(struct net_device *dev)
  702. {
  703. struct w90p910_ether *ether = netdev_priv(dev);
  704. return mii_link_ok(&ether->mii);
  705. }
  706. static const struct ethtool_ops w90p910_ether_ethtool_ops = {
  707. .get_drvinfo = w90p910_get_drvinfo,
  708. .nway_reset = w90p910_nway_reset,
  709. .get_link = w90p910_get_link,
  710. .get_link_ksettings = w90p910_get_link_ksettings,
  711. .set_link_ksettings = w90p910_set_link_ksettings,
  712. };
  713. static const struct net_device_ops w90p910_ether_netdev_ops = {
  714. .ndo_open = w90p910_ether_open,
  715. .ndo_stop = w90p910_ether_close,
  716. .ndo_start_xmit = w90p910_ether_start_xmit,
  717. .ndo_set_rx_mode = w90p910_ether_set_multicast_list,
  718. .ndo_set_mac_address = w90p910_set_mac_address,
  719. .ndo_do_ioctl = w90p910_ether_ioctl,
  720. .ndo_validate_addr = eth_validate_addr,
  721. };
  722. static void __init get_mac_address(struct net_device *dev)
  723. {
  724. struct w90p910_ether *ether = netdev_priv(dev);
  725. struct platform_device *pdev;
  726. char addr[ETH_ALEN];
  727. pdev = ether->pdev;
  728. addr[0] = 0x00;
  729. addr[1] = 0x02;
  730. addr[2] = 0xac;
  731. addr[3] = 0x55;
  732. addr[4] = 0x88;
  733. addr[5] = 0xa8;
  734. if (is_valid_ether_addr(addr))
  735. memcpy(dev->dev_addr, &addr, ETH_ALEN);
  736. else
  737. dev_err(&pdev->dev, "invalid mac address\n");
  738. }
  739. static int w90p910_ether_setup(struct net_device *dev)
  740. {
  741. struct w90p910_ether *ether = netdev_priv(dev);
  742. dev->netdev_ops = &w90p910_ether_netdev_ops;
  743. dev->ethtool_ops = &w90p910_ether_ethtool_ops;
  744. dev->tx_queue_len = 16;
  745. dev->dma = 0x0;
  746. dev->watchdog_timeo = TX_TIMEOUT;
  747. get_mac_address(dev);
  748. ether->cur_tx = 0x0;
  749. ether->cur_rx = 0x0;
  750. ether->finish_tx = 0x0;
  751. ether->linkflag = 0x0;
  752. ether->mii.phy_id = 0x01;
  753. ether->mii.phy_id_mask = 0x1f;
  754. ether->mii.reg_num_mask = 0x1f;
  755. ether->mii.dev = dev;
  756. ether->mii.mdio_read = w90p910_mdio_read;
  757. ether->mii.mdio_write = w90p910_mdio_write;
  758. setup_timer(&ether->check_timer, w90p910_check_link,
  759. (unsigned long)dev);
  760. return 0;
  761. }
  762. static int w90p910_ether_probe(struct platform_device *pdev)
  763. {
  764. struct w90p910_ether *ether;
  765. struct net_device *dev;
  766. int error;
  767. dev = alloc_etherdev(sizeof(struct w90p910_ether));
  768. if (!dev)
  769. return -ENOMEM;
  770. ether = netdev_priv(dev);
  771. ether->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  772. if (ether->res == NULL) {
  773. dev_err(&pdev->dev, "failed to get I/O memory\n");
  774. error = -ENXIO;
  775. goto failed_free;
  776. }
  777. if (!request_mem_region(ether->res->start,
  778. resource_size(ether->res), pdev->name)) {
  779. dev_err(&pdev->dev, "failed to request I/O memory\n");
  780. error = -EBUSY;
  781. goto failed_free;
  782. }
  783. ether->reg = ioremap(ether->res->start, resource_size(ether->res));
  784. if (ether->reg == NULL) {
  785. dev_err(&pdev->dev, "failed to remap I/O memory\n");
  786. error = -ENXIO;
  787. goto failed_free_mem;
  788. }
  789. ether->txirq = platform_get_irq(pdev, 0);
  790. if (ether->txirq < 0) {
  791. dev_err(&pdev->dev, "failed to get ether tx irq\n");
  792. error = -ENXIO;
  793. goto failed_free_io;
  794. }
  795. ether->rxirq = platform_get_irq(pdev, 1);
  796. if (ether->rxirq < 0) {
  797. dev_err(&pdev->dev, "failed to get ether rx irq\n");
  798. error = -ENXIO;
  799. goto failed_free_io;
  800. }
  801. platform_set_drvdata(pdev, dev);
  802. ether->clk = clk_get(&pdev->dev, NULL);
  803. if (IS_ERR(ether->clk)) {
  804. dev_err(&pdev->dev, "failed to get ether clock\n");
  805. error = PTR_ERR(ether->clk);
  806. goto failed_free_io;
  807. }
  808. ether->rmiiclk = clk_get(&pdev->dev, "RMII");
  809. if (IS_ERR(ether->rmiiclk)) {
  810. dev_err(&pdev->dev, "failed to get ether clock\n");
  811. error = PTR_ERR(ether->rmiiclk);
  812. goto failed_put_clk;
  813. }
  814. ether->pdev = pdev;
  815. w90p910_ether_setup(dev);
  816. error = register_netdev(dev);
  817. if (error != 0) {
  818. dev_err(&pdev->dev, "Register EMC w90p910 FAILED\n");
  819. error = -ENODEV;
  820. goto failed_put_rmiiclk;
  821. }
  822. return 0;
  823. failed_put_rmiiclk:
  824. clk_put(ether->rmiiclk);
  825. failed_put_clk:
  826. clk_put(ether->clk);
  827. failed_free_io:
  828. iounmap(ether->reg);
  829. failed_free_mem:
  830. release_mem_region(ether->res->start, resource_size(ether->res));
  831. failed_free:
  832. free_netdev(dev);
  833. return error;
  834. }
  835. static int w90p910_ether_remove(struct platform_device *pdev)
  836. {
  837. struct net_device *dev = platform_get_drvdata(pdev);
  838. struct w90p910_ether *ether = netdev_priv(dev);
  839. unregister_netdev(dev);
  840. clk_put(ether->rmiiclk);
  841. clk_put(ether->clk);
  842. iounmap(ether->reg);
  843. release_mem_region(ether->res->start, resource_size(ether->res));
  844. del_timer_sync(&ether->check_timer);
  845. free_netdev(dev);
  846. return 0;
  847. }
  848. static struct platform_driver w90p910_ether_driver = {
  849. .probe = w90p910_ether_probe,
  850. .remove = w90p910_ether_remove,
  851. .driver = {
  852. .name = "nuc900-emc",
  853. },
  854. };
  855. module_platform_driver(w90p910_ether_driver);
  856. MODULE_AUTHOR("Wan ZongShun <mcuos.com@gmail.com>");
  857. MODULE_DESCRIPTION("w90p910 MAC driver!");
  858. MODULE_LICENSE("GPL");
  859. MODULE_ALIAS("platform:nuc900-emc");