ddbridge-core.c 42 KB

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  1. /*
  2. * ddbridge.c: Digital Devices PCIe bridge driver
  3. *
  4. * Copyright (C) 2010-2011 Digital Devices GmbH
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 only, as published by the Free Software Foundation.
  9. *
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * To obtain the license, point your browser to
  17. * http://www.gnu.org/copyleft/gpl.html
  18. */
  19. #include <linux/module.h>
  20. #include <linux/init.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/delay.h>
  23. #include <linux/slab.h>
  24. #include <linux/poll.h>
  25. #include <linux/io.h>
  26. #include <linux/pci.h>
  27. #include <linux/pci_ids.h>
  28. #include <linux/timer.h>
  29. #include <linux/i2c.h>
  30. #include <linux/swab.h>
  31. #include <linux/vmalloc.h>
  32. #include "ddbridge.h"
  33. #include "ddbridge-regs.h"
  34. #include "tda18271c2dd.h"
  35. #include "stv6110x.h"
  36. #include "stv090x.h"
  37. #include "lnbh24.h"
  38. #include "drxk.h"
  39. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  40. /* MSI had problems with lost interrupts, fixed but needs testing */
  41. #undef CONFIG_PCI_MSI
  42. /******************************************************************************/
  43. static int i2c_read(struct i2c_adapter *adapter, u8 adr, u8 *val)
  44. {
  45. struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD,
  46. .buf = val, .len = 1 } };
  47. return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1;
  48. }
  49. static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr, u8 reg, u8 *val)
  50. {
  51. struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
  52. .buf = &reg, .len = 1 },
  53. {.addr = adr, .flags = I2C_M_RD,
  54. .buf = val, .len = 1 } };
  55. return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1;
  56. }
  57. static int i2c_read_reg16(struct i2c_adapter *adapter, u8 adr,
  58. u16 reg, u8 *val)
  59. {
  60. u8 msg[2] = {reg>>8, reg&0xff};
  61. struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
  62. .buf = msg, .len = 2},
  63. {.addr = adr, .flags = I2C_M_RD,
  64. .buf = val, .len = 1} };
  65. return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1;
  66. }
  67. static int ddb_i2c_cmd(struct ddb_i2c *i2c, u32 adr, u32 cmd)
  68. {
  69. struct ddb *dev = i2c->dev;
  70. long stat;
  71. u32 val;
  72. i2c->done = 0;
  73. ddbwritel((adr << 9) | cmd, i2c->regs + I2C_COMMAND);
  74. stat = wait_event_timeout(i2c->wq, i2c->done == 1, HZ);
  75. if (stat == 0) {
  76. printk(KERN_ERR "I2C timeout\n");
  77. { /* MSI debugging*/
  78. u32 istat = ddbreadl(INTERRUPT_STATUS);
  79. printk(KERN_ERR "IRS %08x\n", istat);
  80. ddbwritel(istat, INTERRUPT_ACK);
  81. }
  82. return -EIO;
  83. }
  84. val = ddbreadl(i2c->regs+I2C_COMMAND);
  85. if (val & 0x70000)
  86. return -EIO;
  87. return 0;
  88. }
  89. static int ddb_i2c_master_xfer(struct i2c_adapter *adapter,
  90. struct i2c_msg msg[], int num)
  91. {
  92. struct ddb_i2c *i2c = (struct ddb_i2c *)i2c_get_adapdata(adapter);
  93. struct ddb *dev = i2c->dev;
  94. u8 addr = 0;
  95. if (num)
  96. addr = msg[0].addr;
  97. if (num == 2 && msg[1].flags & I2C_M_RD &&
  98. !(msg[0].flags & I2C_M_RD)) {
  99. memcpy_toio(dev->regs + I2C_TASKMEM_BASE + i2c->wbuf,
  100. msg[0].buf, msg[0].len);
  101. ddbwritel(msg[0].len|(msg[1].len << 16),
  102. i2c->regs+I2C_TASKLENGTH);
  103. if (!ddb_i2c_cmd(i2c, addr, 1)) {
  104. memcpy_fromio(msg[1].buf,
  105. dev->regs + I2C_TASKMEM_BASE + i2c->rbuf,
  106. msg[1].len);
  107. return num;
  108. }
  109. }
  110. if (num == 1 && !(msg[0].flags & I2C_M_RD)) {
  111. ddbcpyto(I2C_TASKMEM_BASE + i2c->wbuf, msg[0].buf, msg[0].len);
  112. ddbwritel(msg[0].len, i2c->regs + I2C_TASKLENGTH);
  113. if (!ddb_i2c_cmd(i2c, addr, 2))
  114. return num;
  115. }
  116. if (num == 1 && (msg[0].flags & I2C_M_RD)) {
  117. ddbwritel(msg[0].len << 16, i2c->regs + I2C_TASKLENGTH);
  118. if (!ddb_i2c_cmd(i2c, addr, 3)) {
  119. ddbcpyfrom(msg[0].buf,
  120. I2C_TASKMEM_BASE + i2c->rbuf, msg[0].len);
  121. return num;
  122. }
  123. }
  124. return -EIO;
  125. }
  126. static u32 ddb_i2c_functionality(struct i2c_adapter *adap)
  127. {
  128. return I2C_FUNC_SMBUS_EMUL;
  129. }
  130. static struct i2c_algorithm ddb_i2c_algo = {
  131. .master_xfer = ddb_i2c_master_xfer,
  132. .functionality = ddb_i2c_functionality,
  133. };
  134. static void ddb_i2c_release(struct ddb *dev)
  135. {
  136. int i;
  137. struct ddb_i2c *i2c;
  138. struct i2c_adapter *adap;
  139. for (i = 0; i < dev->info->port_num; i++) {
  140. i2c = &dev->i2c[i];
  141. adap = &i2c->adap;
  142. i2c_del_adapter(adap);
  143. }
  144. }
  145. static int ddb_i2c_init(struct ddb *dev)
  146. {
  147. int i, j, stat = 0;
  148. struct ddb_i2c *i2c;
  149. struct i2c_adapter *adap;
  150. for (i = 0; i < dev->info->port_num; i++) {
  151. i2c = &dev->i2c[i];
  152. i2c->dev = dev;
  153. i2c->nr = i;
  154. i2c->wbuf = i * (I2C_TASKMEM_SIZE / 4);
  155. i2c->rbuf = i2c->wbuf + (I2C_TASKMEM_SIZE / 8);
  156. i2c->regs = 0x80 + i * 0x20;
  157. ddbwritel(I2C_SPEED_100, i2c->regs + I2C_TIMING);
  158. ddbwritel((i2c->rbuf << 16) | i2c->wbuf,
  159. i2c->regs + I2C_TASKADDRESS);
  160. init_waitqueue_head(&i2c->wq);
  161. adap = &i2c->adap;
  162. i2c_set_adapdata(adap, i2c);
  163. #ifdef I2C_ADAP_CLASS_TV_DIGITAL
  164. adap->class = I2C_ADAP_CLASS_TV_DIGITAL|I2C_CLASS_TV_ANALOG;
  165. #else
  166. #ifdef I2C_CLASS_TV_ANALOG
  167. adap->class = I2C_CLASS_TV_ANALOG;
  168. #endif
  169. #endif
  170. strcpy(adap->name, "ddbridge");
  171. adap->algo = &ddb_i2c_algo;
  172. adap->algo_data = (void *)i2c;
  173. adap->dev.parent = &dev->pdev->dev;
  174. stat = i2c_add_adapter(adap);
  175. if (stat)
  176. break;
  177. }
  178. if (stat)
  179. for (j = 0; j < i; j++) {
  180. i2c = &dev->i2c[j];
  181. adap = &i2c->adap;
  182. i2c_del_adapter(adap);
  183. }
  184. return stat;
  185. }
  186. /******************************************************************************/
  187. /******************************************************************************/
  188. /******************************************************************************/
  189. #if 0
  190. static void set_table(struct ddb *dev, u32 off,
  191. dma_addr_t *pbuf, u32 num)
  192. {
  193. u32 i, base;
  194. u64 mem;
  195. base = DMA_BASE_ADDRESS_TABLE + off;
  196. for (i = 0; i < num; i++) {
  197. mem = pbuf[i];
  198. ddbwritel(mem & 0xffffffff, base + i * 8);
  199. ddbwritel(mem >> 32, base + i * 8 + 4);
  200. }
  201. }
  202. #endif
  203. static void ddb_address_table(struct ddb *dev)
  204. {
  205. u32 i, j, base;
  206. u64 mem;
  207. dma_addr_t *pbuf;
  208. for (i = 0; i < dev->info->port_num * 2; i++) {
  209. base = DMA_BASE_ADDRESS_TABLE + i * 0x100;
  210. pbuf = dev->input[i].pbuf;
  211. for (j = 0; j < dev->input[i].dma_buf_num; j++) {
  212. mem = pbuf[j];
  213. ddbwritel(mem & 0xffffffff, base + j * 8);
  214. ddbwritel(mem >> 32, base + j * 8 + 4);
  215. }
  216. }
  217. for (i = 0; i < dev->info->port_num; i++) {
  218. base = DMA_BASE_ADDRESS_TABLE + 0x800 + i * 0x100;
  219. pbuf = dev->output[i].pbuf;
  220. for (j = 0; j < dev->output[i].dma_buf_num; j++) {
  221. mem = pbuf[j];
  222. ddbwritel(mem & 0xffffffff, base + j * 8);
  223. ddbwritel(mem >> 32, base + j * 8 + 4);
  224. }
  225. }
  226. }
  227. static void io_free(struct pci_dev *pdev, u8 **vbuf,
  228. dma_addr_t *pbuf, u32 size, int num)
  229. {
  230. int i;
  231. for (i = 0; i < num; i++) {
  232. if (vbuf[i]) {
  233. pci_free_consistent(pdev, size, vbuf[i], pbuf[i]);
  234. vbuf[i] = NULL;
  235. }
  236. }
  237. }
  238. static int io_alloc(struct pci_dev *pdev, u8 **vbuf,
  239. dma_addr_t *pbuf, u32 size, int num)
  240. {
  241. int i;
  242. for (i = 0; i < num; i++) {
  243. vbuf[i] = pci_alloc_consistent(pdev, size, &pbuf[i]);
  244. if (!vbuf[i])
  245. return -ENOMEM;
  246. }
  247. return 0;
  248. }
  249. static int ddb_buffers_alloc(struct ddb *dev)
  250. {
  251. int i;
  252. struct ddb_port *port;
  253. for (i = 0; i < dev->info->port_num; i++) {
  254. port = &dev->port[i];
  255. switch (port->class) {
  256. case DDB_PORT_TUNER:
  257. if (io_alloc(dev->pdev, port->input[0]->vbuf,
  258. port->input[0]->pbuf,
  259. port->input[0]->dma_buf_size,
  260. port->input[0]->dma_buf_num) < 0)
  261. return -1;
  262. if (io_alloc(dev->pdev, port->input[1]->vbuf,
  263. port->input[1]->pbuf,
  264. port->input[1]->dma_buf_size,
  265. port->input[1]->dma_buf_num) < 0)
  266. return -1;
  267. break;
  268. case DDB_PORT_CI:
  269. if (io_alloc(dev->pdev, port->input[0]->vbuf,
  270. port->input[0]->pbuf,
  271. port->input[0]->dma_buf_size,
  272. port->input[0]->dma_buf_num) < 0)
  273. return -1;
  274. if (io_alloc(dev->pdev, port->output->vbuf,
  275. port->output->pbuf,
  276. port->output->dma_buf_size,
  277. port->output->dma_buf_num) < 0)
  278. return -1;
  279. break;
  280. default:
  281. break;
  282. }
  283. }
  284. ddb_address_table(dev);
  285. return 0;
  286. }
  287. static void ddb_buffers_free(struct ddb *dev)
  288. {
  289. int i;
  290. struct ddb_port *port;
  291. for (i = 0; i < dev->info->port_num; i++) {
  292. port = &dev->port[i];
  293. io_free(dev->pdev, port->input[0]->vbuf,
  294. port->input[0]->pbuf,
  295. port->input[0]->dma_buf_size,
  296. port->input[0]->dma_buf_num);
  297. io_free(dev->pdev, port->input[1]->vbuf,
  298. port->input[1]->pbuf,
  299. port->input[1]->dma_buf_size,
  300. port->input[1]->dma_buf_num);
  301. io_free(dev->pdev, port->output->vbuf,
  302. port->output->pbuf,
  303. port->output->dma_buf_size,
  304. port->output->dma_buf_num);
  305. }
  306. }
  307. static void ddb_input_start(struct ddb_input *input)
  308. {
  309. struct ddb *dev = input->port->dev;
  310. spin_lock_irq(&input->lock);
  311. input->cbuf = 0;
  312. input->coff = 0;
  313. /* reset */
  314. ddbwritel(0, TS_INPUT_CONTROL(input->nr));
  315. ddbwritel(2, TS_INPUT_CONTROL(input->nr));
  316. ddbwritel(0, TS_INPUT_CONTROL(input->nr));
  317. ddbwritel((1 << 16) |
  318. (input->dma_buf_num << 11) |
  319. (input->dma_buf_size >> 7),
  320. DMA_BUFFER_SIZE(input->nr));
  321. ddbwritel(0, DMA_BUFFER_ACK(input->nr));
  322. ddbwritel(1, DMA_BASE_WRITE);
  323. ddbwritel(3, DMA_BUFFER_CONTROL(input->nr));
  324. ddbwritel(9, TS_INPUT_CONTROL(input->nr));
  325. input->running = 1;
  326. spin_unlock_irq(&input->lock);
  327. }
  328. static void ddb_input_stop(struct ddb_input *input)
  329. {
  330. struct ddb *dev = input->port->dev;
  331. spin_lock_irq(&input->lock);
  332. ddbwritel(0, TS_INPUT_CONTROL(input->nr));
  333. ddbwritel(0, DMA_BUFFER_CONTROL(input->nr));
  334. input->running = 0;
  335. spin_unlock_irq(&input->lock);
  336. }
  337. static void ddb_output_start(struct ddb_output *output)
  338. {
  339. struct ddb *dev = output->port->dev;
  340. spin_lock_irq(&output->lock);
  341. output->cbuf = 0;
  342. output->coff = 0;
  343. ddbwritel(0, TS_OUTPUT_CONTROL(output->nr));
  344. ddbwritel(2, TS_OUTPUT_CONTROL(output->nr));
  345. ddbwritel(0, TS_OUTPUT_CONTROL(output->nr));
  346. ddbwritel(0x3c, TS_OUTPUT_CONTROL(output->nr));
  347. ddbwritel((1 << 16) |
  348. (output->dma_buf_num << 11) |
  349. (output->dma_buf_size >> 7),
  350. DMA_BUFFER_SIZE(output->nr + 8));
  351. ddbwritel(0, DMA_BUFFER_ACK(output->nr + 8));
  352. ddbwritel(1, DMA_BASE_READ);
  353. ddbwritel(3, DMA_BUFFER_CONTROL(output->nr + 8));
  354. /* ddbwritel(0xbd, TS_OUTPUT_CONTROL(output->nr)); */
  355. ddbwritel(0x1d, TS_OUTPUT_CONTROL(output->nr));
  356. output->running = 1;
  357. spin_unlock_irq(&output->lock);
  358. }
  359. static void ddb_output_stop(struct ddb_output *output)
  360. {
  361. struct ddb *dev = output->port->dev;
  362. spin_lock_irq(&output->lock);
  363. ddbwritel(0, TS_OUTPUT_CONTROL(output->nr));
  364. ddbwritel(0, DMA_BUFFER_CONTROL(output->nr + 8));
  365. output->running = 0;
  366. spin_unlock_irq(&output->lock);
  367. }
  368. static u32 ddb_output_free(struct ddb_output *output)
  369. {
  370. u32 idx, off, stat = output->stat;
  371. s32 diff;
  372. idx = (stat >> 11) & 0x1f;
  373. off = (stat & 0x7ff) << 7;
  374. if (output->cbuf != idx) {
  375. if ((((output->cbuf + 1) % output->dma_buf_num) == idx) &&
  376. (output->dma_buf_size - output->coff <= 188))
  377. return 0;
  378. return 188;
  379. }
  380. diff = off - output->coff;
  381. if (diff <= 0 || diff > 188)
  382. return 188;
  383. return 0;
  384. }
  385. static ssize_t ddb_output_write(struct ddb_output *output,
  386. const __user u8 *buf, size_t count)
  387. {
  388. struct ddb *dev = output->port->dev;
  389. u32 idx, off, stat = output->stat;
  390. u32 left = count, len;
  391. idx = (stat >> 11) & 0x1f;
  392. off = (stat & 0x7ff) << 7;
  393. while (left) {
  394. len = output->dma_buf_size - output->coff;
  395. if ((((output->cbuf + 1) % output->dma_buf_num) == idx) &&
  396. (off == 0)) {
  397. if (len <= 188)
  398. break;
  399. len -= 188;
  400. }
  401. if (output->cbuf == idx) {
  402. if (off > output->coff) {
  403. #if 1
  404. len = off - output->coff;
  405. len -= (len % 188);
  406. if (len <= 188)
  407. #endif
  408. break;
  409. len -= 188;
  410. }
  411. }
  412. if (len > left)
  413. len = left;
  414. if (copy_from_user(output->vbuf[output->cbuf] + output->coff,
  415. buf, len))
  416. return -EIO;
  417. left -= len;
  418. buf += len;
  419. output->coff += len;
  420. if (output->coff == output->dma_buf_size) {
  421. output->coff = 0;
  422. output->cbuf = ((output->cbuf + 1) % output->dma_buf_num);
  423. }
  424. ddbwritel((output->cbuf << 11) | (output->coff >> 7),
  425. DMA_BUFFER_ACK(output->nr + 8));
  426. }
  427. return count - left;
  428. }
  429. static u32 ddb_input_avail(struct ddb_input *input)
  430. {
  431. struct ddb *dev = input->port->dev;
  432. u32 idx, off, stat = input->stat;
  433. u32 ctrl = ddbreadl(DMA_BUFFER_CONTROL(input->nr));
  434. idx = (stat >> 11) & 0x1f;
  435. off = (stat & 0x7ff) << 7;
  436. if (ctrl & 4) {
  437. printk(KERN_ERR "IA %d %d %08x\n", idx, off, ctrl);
  438. ddbwritel(input->stat, DMA_BUFFER_ACK(input->nr));
  439. return 0;
  440. }
  441. if (input->cbuf != idx)
  442. return 188;
  443. return 0;
  444. }
  445. static ssize_t ddb_input_read(struct ddb_input *input, __user u8 *buf, size_t count)
  446. {
  447. struct ddb *dev = input->port->dev;
  448. u32 left = count;
  449. u32 idx, free, stat = input->stat;
  450. int ret;
  451. idx = (stat >> 11) & 0x1f;
  452. while (left) {
  453. if (input->cbuf == idx)
  454. return count - left;
  455. free = input->dma_buf_size - input->coff;
  456. if (free > left)
  457. free = left;
  458. ret = copy_to_user(buf, input->vbuf[input->cbuf] +
  459. input->coff, free);
  460. if (ret)
  461. return -EFAULT;
  462. input->coff += free;
  463. if (input->coff == input->dma_buf_size) {
  464. input->coff = 0;
  465. input->cbuf = (input->cbuf+1) % input->dma_buf_num;
  466. }
  467. left -= free;
  468. ddbwritel((input->cbuf << 11) | (input->coff >> 7),
  469. DMA_BUFFER_ACK(input->nr));
  470. }
  471. return count;
  472. }
  473. /******************************************************************************/
  474. /******************************************************************************/
  475. /******************************************************************************/
  476. #if 0
  477. static struct ddb_input *fe2input(struct ddb *dev, struct dvb_frontend *fe)
  478. {
  479. int i;
  480. for (i = 0; i < dev->info->port_num * 2; i++) {
  481. if (dev->input[i].fe == fe)
  482. return &dev->input[i];
  483. }
  484. return NULL;
  485. }
  486. #endif
  487. static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
  488. {
  489. struct ddb_input *input = fe->sec_priv;
  490. struct ddb_port *port = input->port;
  491. int status;
  492. if (enable) {
  493. mutex_lock(&port->i2c_gate_lock);
  494. status = input->gate_ctrl(fe, 1);
  495. } else {
  496. status = input->gate_ctrl(fe, 0);
  497. mutex_unlock(&port->i2c_gate_lock);
  498. }
  499. return status;
  500. }
  501. static int demod_attach_drxk(struct ddb_input *input)
  502. {
  503. struct i2c_adapter *i2c = &input->port->i2c->adap;
  504. struct dvb_frontend *fe;
  505. struct drxk_config config;
  506. memset(&config, 0, sizeof(config));
  507. config.microcode_name = "drxk_a3.mc";
  508. config.qam_demod_parameter_count = 4;
  509. config.adr = 0x29 + (input->nr & 1);
  510. fe = input->fe = dvb_attach(drxk_attach, &config, i2c);
  511. if (!input->fe) {
  512. printk(KERN_ERR "No DRXK found!\n");
  513. return -ENODEV;
  514. }
  515. fe->sec_priv = input;
  516. input->gate_ctrl = fe->ops.i2c_gate_ctrl;
  517. fe->ops.i2c_gate_ctrl = drxk_gate_ctrl;
  518. return 0;
  519. }
  520. static int tuner_attach_tda18271(struct ddb_input *input)
  521. {
  522. struct i2c_adapter *i2c = &input->port->i2c->adap;
  523. struct dvb_frontend *fe;
  524. if (input->fe->ops.i2c_gate_ctrl)
  525. input->fe->ops.i2c_gate_ctrl(input->fe, 1);
  526. fe = dvb_attach(tda18271c2dd_attach, input->fe, i2c, 0x60);
  527. if (!fe) {
  528. printk(KERN_ERR "No TDA18271 found!\n");
  529. return -ENODEV;
  530. }
  531. if (input->fe->ops.i2c_gate_ctrl)
  532. input->fe->ops.i2c_gate_ctrl(input->fe, 0);
  533. return 0;
  534. }
  535. /******************************************************************************/
  536. /******************************************************************************/
  537. /******************************************************************************/
  538. static struct stv090x_config stv0900 = {
  539. .device = STV0900,
  540. .demod_mode = STV090x_DUAL,
  541. .clk_mode = STV090x_CLK_EXT,
  542. .xtal = 27000000,
  543. .address = 0x69,
  544. .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
  545. .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
  546. .repeater_level = STV090x_RPTLEVEL_16,
  547. .adc1_range = STV090x_ADC_1Vpp,
  548. .adc2_range = STV090x_ADC_1Vpp,
  549. .diseqc_envelope_mode = true,
  550. };
  551. static struct stv090x_config stv0900_aa = {
  552. .device = STV0900,
  553. .demod_mode = STV090x_DUAL,
  554. .clk_mode = STV090x_CLK_EXT,
  555. .xtal = 27000000,
  556. .address = 0x68,
  557. .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
  558. .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
  559. .repeater_level = STV090x_RPTLEVEL_16,
  560. .adc1_range = STV090x_ADC_1Vpp,
  561. .adc2_range = STV090x_ADC_1Vpp,
  562. .diseqc_envelope_mode = true,
  563. };
  564. static struct stv6110x_config stv6110a = {
  565. .addr = 0x60,
  566. .refclk = 27000000,
  567. .clk_div = 1,
  568. };
  569. static struct stv6110x_config stv6110b = {
  570. .addr = 0x63,
  571. .refclk = 27000000,
  572. .clk_div = 1,
  573. };
  574. static int demod_attach_stv0900(struct ddb_input *input, int type)
  575. {
  576. struct i2c_adapter *i2c = &input->port->i2c->adap;
  577. struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900;
  578. input->fe = dvb_attach(stv090x_attach, feconf, i2c,
  579. (input->nr & 1) ? STV090x_DEMODULATOR_1
  580. : STV090x_DEMODULATOR_0);
  581. if (!input->fe) {
  582. printk(KERN_ERR "No STV0900 found!\n");
  583. return -ENODEV;
  584. }
  585. if (!dvb_attach(lnbh24_attach, input->fe, i2c, 0,
  586. 0, (input->nr & 1) ?
  587. (0x09 - type) : (0x0b - type))) {
  588. printk(KERN_ERR "No LNBH24 found!\n");
  589. return -ENODEV;
  590. }
  591. return 0;
  592. }
  593. static int tuner_attach_stv6110(struct ddb_input *input, int type)
  594. {
  595. struct i2c_adapter *i2c = &input->port->i2c->adap;
  596. struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900;
  597. struct stv6110x_config *tunerconf = (input->nr & 1) ?
  598. &stv6110b : &stv6110a;
  599. const struct stv6110x_devctl *ctl;
  600. ctl = dvb_attach(stv6110x_attach, input->fe, tunerconf, i2c);
  601. if (!ctl) {
  602. printk(KERN_ERR "No STV6110X found!\n");
  603. return -ENODEV;
  604. }
  605. printk(KERN_INFO "attach tuner input %d adr %02x\n",
  606. input->nr, tunerconf->addr);
  607. feconf->tuner_init = ctl->tuner_init;
  608. feconf->tuner_sleep = ctl->tuner_sleep;
  609. feconf->tuner_set_mode = ctl->tuner_set_mode;
  610. feconf->tuner_set_frequency = ctl->tuner_set_frequency;
  611. feconf->tuner_get_frequency = ctl->tuner_get_frequency;
  612. feconf->tuner_set_bandwidth = ctl->tuner_set_bandwidth;
  613. feconf->tuner_get_bandwidth = ctl->tuner_get_bandwidth;
  614. feconf->tuner_set_bbgain = ctl->tuner_set_bbgain;
  615. feconf->tuner_get_bbgain = ctl->tuner_get_bbgain;
  616. feconf->tuner_set_refclk = ctl->tuner_set_refclk;
  617. feconf->tuner_get_status = ctl->tuner_get_status;
  618. return 0;
  619. }
  620. static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
  621. int (*start_feed)(struct dvb_demux_feed *),
  622. int (*stop_feed)(struct dvb_demux_feed *),
  623. void *priv)
  624. {
  625. dvbdemux->priv = priv;
  626. dvbdemux->filternum = 256;
  627. dvbdemux->feednum = 256;
  628. dvbdemux->start_feed = start_feed;
  629. dvbdemux->stop_feed = stop_feed;
  630. dvbdemux->write_to_decoder = NULL;
  631. dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
  632. DMX_SECTION_FILTERING |
  633. DMX_MEMORY_BASED_FILTERING);
  634. return dvb_dmx_init(dvbdemux);
  635. }
  636. static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
  637. struct dvb_demux *dvbdemux,
  638. struct dmx_frontend *hw_frontend,
  639. struct dmx_frontend *mem_frontend,
  640. struct dvb_adapter *dvb_adapter)
  641. {
  642. int ret;
  643. dmxdev->filternum = 256;
  644. dmxdev->demux = &dvbdemux->dmx;
  645. dmxdev->capabilities = 0;
  646. ret = dvb_dmxdev_init(dmxdev, dvb_adapter);
  647. if (ret < 0)
  648. return ret;
  649. hw_frontend->source = DMX_FRONTEND_0;
  650. dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend);
  651. mem_frontend->source = DMX_MEMORY_FE;
  652. dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend);
  653. return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend);
  654. }
  655. static int start_feed(struct dvb_demux_feed *dvbdmxfeed)
  656. {
  657. struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
  658. struct ddb_input *input = dvbdmx->priv;
  659. if (!input->users)
  660. ddb_input_start(input);
  661. return ++input->users;
  662. }
  663. static int stop_feed(struct dvb_demux_feed *dvbdmxfeed)
  664. {
  665. struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
  666. struct ddb_input *input = dvbdmx->priv;
  667. if (--input->users)
  668. return input->users;
  669. ddb_input_stop(input);
  670. return 0;
  671. }
  672. static void dvb_input_detach(struct ddb_input *input)
  673. {
  674. struct dvb_adapter *adap = &input->adap;
  675. struct dvb_demux *dvbdemux = &input->demux;
  676. switch (input->attached) {
  677. case 5:
  678. if (input->fe2)
  679. dvb_unregister_frontend(input->fe2);
  680. if (input->fe) {
  681. dvb_unregister_frontend(input->fe);
  682. dvb_frontend_detach(input->fe);
  683. input->fe = NULL;
  684. }
  685. case 4:
  686. dvb_net_release(&input->dvbnet);
  687. case 3:
  688. dvbdemux->dmx.close(&dvbdemux->dmx);
  689. dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
  690. &input->hw_frontend);
  691. dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
  692. &input->mem_frontend);
  693. dvb_dmxdev_release(&input->dmxdev);
  694. case 2:
  695. dvb_dmx_release(&input->demux);
  696. case 1:
  697. dvb_unregister_adapter(adap);
  698. }
  699. input->attached = 0;
  700. }
  701. static int dvb_input_attach(struct ddb_input *input)
  702. {
  703. int ret;
  704. struct ddb_port *port = input->port;
  705. struct dvb_adapter *adap = &input->adap;
  706. struct dvb_demux *dvbdemux = &input->demux;
  707. ret = dvb_register_adapter(adap, "DDBridge", THIS_MODULE,
  708. &input->port->dev->pdev->dev,
  709. adapter_nr);
  710. if (ret < 0) {
  711. printk(KERN_ERR "ddbridge: Could not register adapter.Check if you enabled enough adapters in dvb-core!\n");
  712. return ret;
  713. }
  714. input->attached = 1;
  715. ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
  716. start_feed,
  717. stop_feed, input);
  718. if (ret < 0)
  719. return ret;
  720. input->attached = 2;
  721. ret = my_dvb_dmxdev_ts_card_init(&input->dmxdev, &input->demux,
  722. &input->hw_frontend,
  723. &input->mem_frontend, adap);
  724. if (ret < 0)
  725. return ret;
  726. input->attached = 3;
  727. ret = dvb_net_init(adap, &input->dvbnet, input->dmxdev.demux);
  728. if (ret < 0)
  729. return ret;
  730. input->attached = 4;
  731. input->fe = NULL;
  732. switch (port->type) {
  733. case DDB_TUNER_DVBS_ST:
  734. if (demod_attach_stv0900(input, 0) < 0)
  735. return -ENODEV;
  736. if (tuner_attach_stv6110(input, 0) < 0)
  737. return -ENODEV;
  738. if (input->fe) {
  739. if (dvb_register_frontend(adap, input->fe) < 0)
  740. return -ENODEV;
  741. }
  742. break;
  743. case DDB_TUNER_DVBS_ST_AA:
  744. if (demod_attach_stv0900(input, 1) < 0)
  745. return -ENODEV;
  746. if (tuner_attach_stv6110(input, 1) < 0)
  747. return -ENODEV;
  748. if (input->fe) {
  749. if (dvb_register_frontend(adap, input->fe) < 0)
  750. return -ENODEV;
  751. }
  752. break;
  753. case DDB_TUNER_DVBCT_TR:
  754. if (demod_attach_drxk(input) < 0)
  755. return -ENODEV;
  756. if (tuner_attach_tda18271(input) < 0)
  757. return -ENODEV;
  758. if (dvb_register_frontend(adap, input->fe) < 0)
  759. return -ENODEV;
  760. if (input->fe2) {
  761. if (dvb_register_frontend(adap, input->fe2) < 0)
  762. return -ENODEV;
  763. input->fe2->tuner_priv = input->fe->tuner_priv;
  764. memcpy(&input->fe2->ops.tuner_ops,
  765. &input->fe->ops.tuner_ops,
  766. sizeof(struct dvb_tuner_ops));
  767. }
  768. break;
  769. }
  770. input->attached = 5;
  771. return 0;
  772. }
  773. /****************************************************************************/
  774. /****************************************************************************/
  775. static ssize_t ts_write(struct file *file, const __user char *buf,
  776. size_t count, loff_t *ppos)
  777. {
  778. struct dvb_device *dvbdev = file->private_data;
  779. struct ddb_output *output = dvbdev->priv;
  780. size_t left = count;
  781. int stat;
  782. while (left) {
  783. if (ddb_output_free(output) < 188) {
  784. if (file->f_flags & O_NONBLOCK)
  785. break;
  786. if (wait_event_interruptible(
  787. output->wq, ddb_output_free(output) >= 188) < 0)
  788. break;
  789. }
  790. stat = ddb_output_write(output, buf, left);
  791. if (stat < 0)
  792. break;
  793. buf += stat;
  794. left -= stat;
  795. }
  796. return (left == count) ? -EAGAIN : (count - left);
  797. }
  798. static ssize_t ts_read(struct file *file, __user char *buf,
  799. size_t count, loff_t *ppos)
  800. {
  801. struct dvb_device *dvbdev = file->private_data;
  802. struct ddb_output *output = dvbdev->priv;
  803. struct ddb_input *input = output->port->input[0];
  804. int left, read;
  805. count -= count % 188;
  806. left = count;
  807. while (left) {
  808. if (ddb_input_avail(input) < 188) {
  809. if (file->f_flags & O_NONBLOCK)
  810. break;
  811. if (wait_event_interruptible(
  812. input->wq, ddb_input_avail(input) >= 188) < 0)
  813. break;
  814. }
  815. read = ddb_input_read(input, buf, left);
  816. if (read < 0)
  817. return read;
  818. left -= read;
  819. buf += read;
  820. }
  821. return (left == count) ? -EAGAIN : (count - left);
  822. }
  823. static unsigned int ts_poll(struct file *file, poll_table *wait)
  824. {
  825. /*
  826. struct dvb_device *dvbdev = file->private_data;
  827. struct ddb_output *output = dvbdev->priv;
  828. struct ddb_input *input = output->port->input[0];
  829. */
  830. unsigned int mask = 0;
  831. #if 0
  832. if (data_avail_to_read)
  833. mask |= POLLIN | POLLRDNORM;
  834. if (data_avail_to_write)
  835. mask |= POLLOUT | POLLWRNORM;
  836. poll_wait(file, &read_queue, wait);
  837. poll_wait(file, &write_queue, wait);
  838. #endif
  839. return mask;
  840. }
  841. static const struct file_operations ci_fops = {
  842. .owner = THIS_MODULE,
  843. .read = ts_read,
  844. .write = ts_write,
  845. .open = dvb_generic_open,
  846. .release = dvb_generic_release,
  847. .poll = ts_poll,
  848. };
  849. static struct dvb_device dvbdev_ci = {
  850. .readers = -1,
  851. .writers = -1,
  852. .users = -1,
  853. .fops = &ci_fops,
  854. };
  855. /****************************************************************************/
  856. /****************************************************************************/
  857. /****************************************************************************/
  858. static void input_tasklet(unsigned long data)
  859. {
  860. struct ddb_input *input = (struct ddb_input *) data;
  861. struct ddb *dev = input->port->dev;
  862. spin_lock(&input->lock);
  863. if (!input->running) {
  864. spin_unlock(&input->lock);
  865. return;
  866. }
  867. input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr));
  868. if (input->port->class == DDB_PORT_TUNER) {
  869. if (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr)))
  870. printk(KERN_ERR "Overflow input %d\n", input->nr);
  871. while (input->cbuf != ((input->stat >> 11) & 0x1f)
  872. || (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr)))) {
  873. dvb_dmx_swfilter_packets(&input->demux,
  874. input->vbuf[input->cbuf],
  875. input->dma_buf_size / 188);
  876. input->cbuf = (input->cbuf + 1) % input->dma_buf_num;
  877. ddbwritel((input->cbuf << 11),
  878. DMA_BUFFER_ACK(input->nr));
  879. input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr));
  880. }
  881. }
  882. if (input->port->class == DDB_PORT_CI)
  883. wake_up(&input->wq);
  884. spin_unlock(&input->lock);
  885. }
  886. static void output_tasklet(unsigned long data)
  887. {
  888. struct ddb_output *output = (struct ddb_output *) data;
  889. struct ddb *dev = output->port->dev;
  890. spin_lock(&output->lock);
  891. if (!output->running) {
  892. spin_unlock(&output->lock);
  893. return;
  894. }
  895. output->stat = ddbreadl(DMA_BUFFER_CURRENT(output->nr + 8));
  896. wake_up(&output->wq);
  897. spin_unlock(&output->lock);
  898. }
  899. static struct cxd2099_cfg cxd_cfg = {
  900. .bitrate = 62000,
  901. .adr = 0x40,
  902. .polarity = 1,
  903. .clock_mode = 1,
  904. };
  905. static int ddb_ci_attach(struct ddb_port *port)
  906. {
  907. int ret;
  908. ret = dvb_register_adapter(&port->output->adap,
  909. "DDBridge",
  910. THIS_MODULE,
  911. &port->dev->pdev->dev,
  912. adapter_nr);
  913. if (ret < 0)
  914. return ret;
  915. port->en = cxd2099_attach(&cxd_cfg, port, &port->i2c->adap);
  916. if (!port->en) {
  917. dvb_unregister_adapter(&port->output->adap);
  918. return -ENODEV;
  919. }
  920. ddb_input_start(port->input[0]);
  921. ddb_output_start(port->output);
  922. dvb_ca_en50221_init(&port->output->adap,
  923. port->en, 0, 1);
  924. ret = dvb_register_device(&port->output->adap, &port->output->dev,
  925. &dvbdev_ci, (void *) port->output,
  926. DVB_DEVICE_SEC, 0);
  927. return ret;
  928. }
  929. static int ddb_port_attach(struct ddb_port *port)
  930. {
  931. int ret = 0;
  932. switch (port->class) {
  933. case DDB_PORT_TUNER:
  934. ret = dvb_input_attach(port->input[0]);
  935. if (ret < 0)
  936. break;
  937. ret = dvb_input_attach(port->input[1]);
  938. break;
  939. case DDB_PORT_CI:
  940. ret = ddb_ci_attach(port);
  941. break;
  942. default:
  943. break;
  944. }
  945. if (ret < 0)
  946. printk(KERN_ERR "port_attach on port %d failed\n", port->nr);
  947. return ret;
  948. }
  949. static int ddb_ports_attach(struct ddb *dev)
  950. {
  951. int i, ret = 0;
  952. struct ddb_port *port;
  953. for (i = 0; i < dev->info->port_num; i++) {
  954. port = &dev->port[i];
  955. ret = ddb_port_attach(port);
  956. if (ret < 0)
  957. break;
  958. }
  959. return ret;
  960. }
  961. static void ddb_ports_detach(struct ddb *dev)
  962. {
  963. int i;
  964. struct ddb_port *port;
  965. for (i = 0; i < dev->info->port_num; i++) {
  966. port = &dev->port[i];
  967. switch (port->class) {
  968. case DDB_PORT_TUNER:
  969. dvb_input_detach(port->input[0]);
  970. dvb_input_detach(port->input[1]);
  971. break;
  972. case DDB_PORT_CI:
  973. dvb_unregister_device(port->output->dev);
  974. if (port->en) {
  975. ddb_input_stop(port->input[0]);
  976. ddb_output_stop(port->output);
  977. dvb_ca_en50221_release(port->en);
  978. kfree(port->en);
  979. port->en = NULL;
  980. dvb_unregister_adapter(&port->output->adap);
  981. }
  982. break;
  983. }
  984. }
  985. }
  986. /****************************************************************************/
  987. /****************************************************************************/
  988. static int port_has_ci(struct ddb_port *port)
  989. {
  990. u8 val;
  991. return i2c_read_reg(&port->i2c->adap, 0x40, 0, &val) ? 0 : 1;
  992. }
  993. static int port_has_stv0900(struct ddb_port *port)
  994. {
  995. u8 val;
  996. if (i2c_read_reg16(&port->i2c->adap, 0x69, 0xf100, &val) < 0)
  997. return 0;
  998. return 1;
  999. }
  1000. static int port_has_stv0900_aa(struct ddb_port *port)
  1001. {
  1002. u8 val;
  1003. if (i2c_read_reg16(&port->i2c->adap, 0x68, 0xf100, &val) < 0)
  1004. return 0;
  1005. return 1;
  1006. }
  1007. static int port_has_drxks(struct ddb_port *port)
  1008. {
  1009. u8 val;
  1010. if (i2c_read(&port->i2c->adap, 0x29, &val) < 0)
  1011. return 0;
  1012. if (i2c_read(&port->i2c->adap, 0x2a, &val) < 0)
  1013. return 0;
  1014. return 1;
  1015. }
  1016. static void ddb_port_probe(struct ddb_port *port)
  1017. {
  1018. struct ddb *dev = port->dev;
  1019. char *modname = "NO MODULE";
  1020. port->class = DDB_PORT_NONE;
  1021. if (port_has_ci(port)) {
  1022. modname = "CI";
  1023. port->class = DDB_PORT_CI;
  1024. ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING);
  1025. } else if (port_has_stv0900(port)) {
  1026. modname = "DUAL DVB-S2";
  1027. port->class = DDB_PORT_TUNER;
  1028. port->type = DDB_TUNER_DVBS_ST;
  1029. ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING);
  1030. } else if (port_has_stv0900_aa(port)) {
  1031. modname = "DUAL DVB-S2";
  1032. port->class = DDB_PORT_TUNER;
  1033. port->type = DDB_TUNER_DVBS_ST_AA;
  1034. ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING);
  1035. } else if (port_has_drxks(port)) {
  1036. modname = "DUAL DVB-C/T";
  1037. port->class = DDB_PORT_TUNER;
  1038. port->type = DDB_TUNER_DVBCT_TR;
  1039. ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING);
  1040. }
  1041. printk(KERN_INFO "Port %d (TAB %d): %s\n",
  1042. port->nr, port->nr+1, modname);
  1043. }
  1044. static void ddb_input_init(struct ddb_port *port, int nr)
  1045. {
  1046. struct ddb *dev = port->dev;
  1047. struct ddb_input *input = &dev->input[nr];
  1048. input->nr = nr;
  1049. input->port = port;
  1050. input->dma_buf_num = INPUT_DMA_BUFS;
  1051. input->dma_buf_size = INPUT_DMA_SIZE;
  1052. ddbwritel(0, TS_INPUT_CONTROL(nr));
  1053. ddbwritel(2, TS_INPUT_CONTROL(nr));
  1054. ddbwritel(0, TS_INPUT_CONTROL(nr));
  1055. ddbwritel(0, DMA_BUFFER_ACK(nr));
  1056. tasklet_init(&input->tasklet, input_tasklet, (unsigned long) input);
  1057. spin_lock_init(&input->lock);
  1058. init_waitqueue_head(&input->wq);
  1059. }
  1060. static void ddb_output_init(struct ddb_port *port, int nr)
  1061. {
  1062. struct ddb *dev = port->dev;
  1063. struct ddb_output *output = &dev->output[nr];
  1064. output->nr = nr;
  1065. output->port = port;
  1066. output->dma_buf_num = OUTPUT_DMA_BUFS;
  1067. output->dma_buf_size = OUTPUT_DMA_SIZE;
  1068. ddbwritel(0, TS_OUTPUT_CONTROL(nr));
  1069. ddbwritel(2, TS_OUTPUT_CONTROL(nr));
  1070. ddbwritel(0, TS_OUTPUT_CONTROL(nr));
  1071. tasklet_init(&output->tasklet, output_tasklet, (unsigned long) output);
  1072. init_waitqueue_head(&output->wq);
  1073. }
  1074. static void ddb_ports_init(struct ddb *dev)
  1075. {
  1076. int i;
  1077. struct ddb_port *port;
  1078. for (i = 0; i < dev->info->port_num; i++) {
  1079. port = &dev->port[i];
  1080. port->dev = dev;
  1081. port->nr = i;
  1082. port->i2c = &dev->i2c[i];
  1083. port->input[0] = &dev->input[2 * i];
  1084. port->input[1] = &dev->input[2 * i + 1];
  1085. port->output = &dev->output[i];
  1086. mutex_init(&port->i2c_gate_lock);
  1087. ddb_port_probe(port);
  1088. ddb_input_init(port, 2 * i);
  1089. ddb_input_init(port, 2 * i + 1);
  1090. ddb_output_init(port, i);
  1091. }
  1092. }
  1093. static void ddb_ports_release(struct ddb *dev)
  1094. {
  1095. int i;
  1096. struct ddb_port *port;
  1097. for (i = 0; i < dev->info->port_num; i++) {
  1098. port = &dev->port[i];
  1099. port->dev = dev;
  1100. tasklet_kill(&port->input[0]->tasklet);
  1101. tasklet_kill(&port->input[1]->tasklet);
  1102. tasklet_kill(&port->output->tasklet);
  1103. }
  1104. }
  1105. /****************************************************************************/
  1106. /****************************************************************************/
  1107. /****************************************************************************/
  1108. static void irq_handle_i2c(struct ddb *dev, int n)
  1109. {
  1110. struct ddb_i2c *i2c = &dev->i2c[n];
  1111. i2c->done = 1;
  1112. wake_up(&i2c->wq);
  1113. }
  1114. static irqreturn_t irq_handler(int irq, void *dev_id)
  1115. {
  1116. struct ddb *dev = (struct ddb *) dev_id;
  1117. u32 s = ddbreadl(INTERRUPT_STATUS);
  1118. if (!s)
  1119. return IRQ_NONE;
  1120. do {
  1121. ddbwritel(s, INTERRUPT_ACK);
  1122. if (s & 0x00000001)
  1123. irq_handle_i2c(dev, 0);
  1124. if (s & 0x00000002)
  1125. irq_handle_i2c(dev, 1);
  1126. if (s & 0x00000004)
  1127. irq_handle_i2c(dev, 2);
  1128. if (s & 0x00000008)
  1129. irq_handle_i2c(dev, 3);
  1130. if (s & 0x00000100)
  1131. tasklet_schedule(&dev->input[0].tasklet);
  1132. if (s & 0x00000200)
  1133. tasklet_schedule(&dev->input[1].tasklet);
  1134. if (s & 0x00000400)
  1135. tasklet_schedule(&dev->input[2].tasklet);
  1136. if (s & 0x00000800)
  1137. tasklet_schedule(&dev->input[3].tasklet);
  1138. if (s & 0x00001000)
  1139. tasklet_schedule(&dev->input[4].tasklet);
  1140. if (s & 0x00002000)
  1141. tasklet_schedule(&dev->input[5].tasklet);
  1142. if (s & 0x00004000)
  1143. tasklet_schedule(&dev->input[6].tasklet);
  1144. if (s & 0x00008000)
  1145. tasklet_schedule(&dev->input[7].tasklet);
  1146. if (s & 0x00010000)
  1147. tasklet_schedule(&dev->output[0].tasklet);
  1148. if (s & 0x00020000)
  1149. tasklet_schedule(&dev->output[1].tasklet);
  1150. if (s & 0x00040000)
  1151. tasklet_schedule(&dev->output[2].tasklet);
  1152. if (s & 0x00080000)
  1153. tasklet_schedule(&dev->output[3].tasklet);
  1154. /* if (s & 0x000f0000) printk(KERN_DEBUG "%08x\n", istat); */
  1155. } while ((s = ddbreadl(INTERRUPT_STATUS)));
  1156. return IRQ_HANDLED;
  1157. }
  1158. /******************************************************************************/
  1159. /******************************************************************************/
  1160. /******************************************************************************/
  1161. static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen)
  1162. {
  1163. u32 data, shift;
  1164. if (wlen > 4)
  1165. ddbwritel(1, SPI_CONTROL);
  1166. while (wlen > 4) {
  1167. /* FIXME: check for big-endian */
  1168. data = swab32(*(u32 *)wbuf);
  1169. wbuf += 4;
  1170. wlen -= 4;
  1171. ddbwritel(data, SPI_DATA);
  1172. while (ddbreadl(SPI_CONTROL) & 0x0004)
  1173. ;
  1174. }
  1175. if (rlen)
  1176. ddbwritel(0x0001 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL);
  1177. else
  1178. ddbwritel(0x0003 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL);
  1179. data = 0;
  1180. shift = ((4 - wlen) * 8);
  1181. while (wlen) {
  1182. data <<= 8;
  1183. data |= *wbuf;
  1184. wlen--;
  1185. wbuf++;
  1186. }
  1187. if (shift)
  1188. data <<= shift;
  1189. ddbwritel(data, SPI_DATA);
  1190. while (ddbreadl(SPI_CONTROL) & 0x0004)
  1191. ;
  1192. if (!rlen) {
  1193. ddbwritel(0, SPI_CONTROL);
  1194. return 0;
  1195. }
  1196. if (rlen > 4)
  1197. ddbwritel(1, SPI_CONTROL);
  1198. while (rlen > 4) {
  1199. ddbwritel(0xffffffff, SPI_DATA);
  1200. while (ddbreadl(SPI_CONTROL) & 0x0004)
  1201. ;
  1202. data = ddbreadl(SPI_DATA);
  1203. *(u32 *) rbuf = swab32(data);
  1204. rbuf += 4;
  1205. rlen -= 4;
  1206. }
  1207. ddbwritel(0x0003 | ((rlen << (8 + 3)) & 0x1F00), SPI_CONTROL);
  1208. ddbwritel(0xffffffff, SPI_DATA);
  1209. while (ddbreadl(SPI_CONTROL) & 0x0004)
  1210. ;
  1211. data = ddbreadl(SPI_DATA);
  1212. ddbwritel(0, SPI_CONTROL);
  1213. if (rlen < 4)
  1214. data <<= ((4 - rlen) * 8);
  1215. while (rlen > 0) {
  1216. *rbuf = ((data >> 24) & 0xff);
  1217. data <<= 8;
  1218. rbuf++;
  1219. rlen--;
  1220. }
  1221. return 0;
  1222. }
  1223. #define DDB_MAGIC 'd'
  1224. struct ddb_flashio {
  1225. __user __u8 *write_buf;
  1226. __u32 write_len;
  1227. __user __u8 *read_buf;
  1228. __u32 read_len;
  1229. };
  1230. #define IOCTL_DDB_FLASHIO _IOWR(DDB_MAGIC, 0x00, struct ddb_flashio)
  1231. #define DDB_NAME "ddbridge"
  1232. static u32 ddb_num;
  1233. static struct ddb *ddbs[32];
  1234. static struct class *ddb_class;
  1235. static int ddb_major;
  1236. static int ddb_open(struct inode *inode, struct file *file)
  1237. {
  1238. struct ddb *dev = ddbs[iminor(inode)];
  1239. file->private_data = dev;
  1240. return 0;
  1241. }
  1242. static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
  1243. {
  1244. struct ddb *dev = file->private_data;
  1245. __user void *parg = (__user void *)arg;
  1246. int res;
  1247. switch (cmd) {
  1248. case IOCTL_DDB_FLASHIO:
  1249. {
  1250. struct ddb_flashio fio;
  1251. u8 *rbuf, *wbuf;
  1252. if (copy_from_user(&fio, parg, sizeof(fio)))
  1253. return -EFAULT;
  1254. if (fio.write_len > 1028 || fio.read_len > 1028)
  1255. return -EINVAL;
  1256. if (fio.write_len + fio.read_len > 1028)
  1257. return -EINVAL;
  1258. wbuf = &dev->iobuf[0];
  1259. rbuf = wbuf + fio.write_len;
  1260. if (copy_from_user(wbuf, fio.write_buf, fio.write_len))
  1261. return -EFAULT;
  1262. res = flashio(dev, wbuf, fio.write_len, rbuf, fio.read_len);
  1263. if (res)
  1264. return res;
  1265. if (copy_to_user(fio.read_buf, rbuf, fio.read_len))
  1266. return -EFAULT;
  1267. break;
  1268. }
  1269. default:
  1270. return -ENOTTY;
  1271. }
  1272. return 0;
  1273. }
  1274. static const struct file_operations ddb_fops = {
  1275. .unlocked_ioctl = ddb_ioctl,
  1276. .open = ddb_open,
  1277. };
  1278. static char *ddb_devnode(struct device *device, umode_t *mode)
  1279. {
  1280. struct ddb *dev = dev_get_drvdata(device);
  1281. return kasprintf(GFP_KERNEL, "ddbridge/card%d", dev->nr);
  1282. }
  1283. static int ddb_class_create(void)
  1284. {
  1285. ddb_major = register_chrdev(0, DDB_NAME, &ddb_fops);
  1286. if (ddb_major < 0)
  1287. return ddb_major;
  1288. ddb_class = class_create(THIS_MODULE, DDB_NAME);
  1289. if (IS_ERR(ddb_class)) {
  1290. unregister_chrdev(ddb_major, DDB_NAME);
  1291. return PTR_ERR(ddb_class);
  1292. }
  1293. ddb_class->devnode = ddb_devnode;
  1294. return 0;
  1295. }
  1296. static void ddb_class_destroy(void)
  1297. {
  1298. class_destroy(ddb_class);
  1299. unregister_chrdev(ddb_major, DDB_NAME);
  1300. }
  1301. static int ddb_device_create(struct ddb *dev)
  1302. {
  1303. dev->nr = ddb_num++;
  1304. dev->ddb_dev = device_create(ddb_class, NULL,
  1305. MKDEV(ddb_major, dev->nr),
  1306. dev, "ddbridge%d", dev->nr);
  1307. ddbs[dev->nr] = dev;
  1308. if (IS_ERR(dev->ddb_dev))
  1309. return -1;
  1310. return 0;
  1311. }
  1312. static void ddb_device_destroy(struct ddb *dev)
  1313. {
  1314. ddb_num--;
  1315. if (IS_ERR(dev->ddb_dev))
  1316. return;
  1317. device_destroy(ddb_class, MKDEV(ddb_major, 0));
  1318. }
  1319. /****************************************************************************/
  1320. /****************************************************************************/
  1321. /****************************************************************************/
  1322. static void ddb_unmap(struct ddb *dev)
  1323. {
  1324. if (dev->regs)
  1325. iounmap(dev->regs);
  1326. vfree(dev);
  1327. }
  1328. static void ddb_remove(struct pci_dev *pdev)
  1329. {
  1330. struct ddb *dev = pci_get_drvdata(pdev);
  1331. ddb_ports_detach(dev);
  1332. ddb_i2c_release(dev);
  1333. ddbwritel(0, INTERRUPT_ENABLE);
  1334. free_irq(dev->pdev->irq, dev);
  1335. #ifdef CONFIG_PCI_MSI
  1336. if (dev->msi)
  1337. pci_disable_msi(dev->pdev);
  1338. #endif
  1339. ddb_ports_release(dev);
  1340. ddb_buffers_free(dev);
  1341. ddb_device_destroy(dev);
  1342. ddb_unmap(dev);
  1343. pci_set_drvdata(pdev, NULL);
  1344. pci_disable_device(pdev);
  1345. }
  1346. static int ddb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  1347. {
  1348. struct ddb *dev;
  1349. int stat = 0;
  1350. int irq_flag = IRQF_SHARED;
  1351. if (pci_enable_device(pdev) < 0)
  1352. return -ENODEV;
  1353. dev = vzalloc(sizeof(struct ddb));
  1354. if (dev == NULL)
  1355. return -ENOMEM;
  1356. dev->pdev = pdev;
  1357. pci_set_drvdata(pdev, dev);
  1358. dev->info = (struct ddb_info *) id->driver_data;
  1359. printk(KERN_INFO "DDBridge driver detected: %s\n", dev->info->name);
  1360. dev->regs = ioremap(pci_resource_start(dev->pdev, 0),
  1361. pci_resource_len(dev->pdev, 0));
  1362. if (!dev->regs) {
  1363. stat = -ENOMEM;
  1364. goto fail;
  1365. }
  1366. printk(KERN_INFO "HW %08x FW %08x\n", ddbreadl(0), ddbreadl(4));
  1367. #ifdef CONFIG_PCI_MSI
  1368. if (pci_msi_enabled())
  1369. stat = pci_enable_msi(dev->pdev);
  1370. if (stat) {
  1371. printk(KERN_INFO ": MSI not available.\n");
  1372. } else {
  1373. irq_flag = 0;
  1374. dev->msi = 1;
  1375. }
  1376. #endif
  1377. stat = request_irq(dev->pdev->irq, irq_handler,
  1378. irq_flag, "DDBridge", (void *) dev);
  1379. if (stat < 0)
  1380. goto fail1;
  1381. ddbwritel(0, DMA_BASE_WRITE);
  1382. ddbwritel(0, DMA_BASE_READ);
  1383. ddbwritel(0xffffffff, INTERRUPT_ACK);
  1384. ddbwritel(0xfff0f, INTERRUPT_ENABLE);
  1385. ddbwritel(0, MSI1_ENABLE);
  1386. if (ddb_i2c_init(dev) < 0)
  1387. goto fail1;
  1388. ddb_ports_init(dev);
  1389. if (ddb_buffers_alloc(dev) < 0) {
  1390. printk(KERN_INFO ": Could not allocate buffer memory\n");
  1391. goto fail2;
  1392. }
  1393. if (ddb_ports_attach(dev) < 0)
  1394. goto fail3;
  1395. ddb_device_create(dev);
  1396. return 0;
  1397. fail3:
  1398. ddb_ports_detach(dev);
  1399. printk(KERN_ERR "fail3\n");
  1400. ddb_ports_release(dev);
  1401. fail2:
  1402. printk(KERN_ERR "fail2\n");
  1403. ddb_buffers_free(dev);
  1404. fail1:
  1405. printk(KERN_ERR "fail1\n");
  1406. if (dev->msi)
  1407. pci_disable_msi(dev->pdev);
  1408. if (stat == 0)
  1409. free_irq(dev->pdev->irq, dev);
  1410. fail:
  1411. printk(KERN_ERR "fail\n");
  1412. ddb_unmap(dev);
  1413. pci_set_drvdata(pdev, NULL);
  1414. pci_disable_device(pdev);
  1415. return -1;
  1416. }
  1417. /******************************************************************************/
  1418. /******************************************************************************/
  1419. /******************************************************************************/
  1420. static const struct ddb_info ddb_none = {
  1421. .type = DDB_NONE,
  1422. .name = "Digital Devices PCIe bridge",
  1423. };
  1424. static const struct ddb_info ddb_octopus = {
  1425. .type = DDB_OCTOPUS,
  1426. .name = "Digital Devices Octopus DVB adapter",
  1427. .port_num = 4,
  1428. };
  1429. static const struct ddb_info ddb_octopus_le = {
  1430. .type = DDB_OCTOPUS,
  1431. .name = "Digital Devices Octopus LE DVB adapter",
  1432. .port_num = 2,
  1433. };
  1434. static const struct ddb_info ddb_octopus_mini = {
  1435. .type = DDB_OCTOPUS,
  1436. .name = "Digital Devices Octopus Mini",
  1437. .port_num = 4,
  1438. };
  1439. static const struct ddb_info ddb_v6 = {
  1440. .type = DDB_OCTOPUS,
  1441. .name = "Digital Devices Cine S2 V6 DVB adapter",
  1442. .port_num = 3,
  1443. };
  1444. static const struct ddb_info ddb_v6_5 = {
  1445. .type = DDB_OCTOPUS,
  1446. .name = "Digital Devices Cine S2 V6.5 DVB adapter",
  1447. .port_num = 4,
  1448. };
  1449. static const struct ddb_info ddb_dvbct = {
  1450. .type = DDB_OCTOPUS,
  1451. .name = "Digital Devices DVBCT V6.1 DVB adapter",
  1452. .port_num = 3,
  1453. };
  1454. static const struct ddb_info ddb_satixS2v3 = {
  1455. .type = DDB_OCTOPUS,
  1456. .name = "Mystique SaTiX-S2 V3 DVB adapter",
  1457. .port_num = 3,
  1458. };
  1459. static const struct ddb_info ddb_octopusv3 = {
  1460. .type = DDB_OCTOPUS,
  1461. .name = "Digital Devices Octopus V3 DVB adapter",
  1462. .port_num = 4,
  1463. };
  1464. #define DDVID 0xdd01 /* Digital Devices Vendor ID */
  1465. #define DDB_ID(_vend, _dev, _subvend, _subdev, _driverdata) { \
  1466. .vendor = _vend, .device = _dev, \
  1467. .subvendor = _subvend, .subdevice = _subdev, \
  1468. .driver_data = (unsigned long)&_driverdata }
  1469. static const struct pci_device_id ddb_id_tbl[] = {
  1470. DDB_ID(DDVID, 0x0002, DDVID, 0x0001, ddb_octopus),
  1471. DDB_ID(DDVID, 0x0003, DDVID, 0x0001, ddb_octopus),
  1472. DDB_ID(DDVID, 0x0003, DDVID, 0x0002, ddb_octopus_le),
  1473. DDB_ID(DDVID, 0x0003, DDVID, 0x0010, ddb_octopus_mini),
  1474. DDB_ID(DDVID, 0x0003, DDVID, 0x0020, ddb_v6),
  1475. DDB_ID(DDVID, 0x0003, DDVID, 0x0021, ddb_v6_5),
  1476. DDB_ID(DDVID, 0x0003, DDVID, 0x0030, ddb_dvbct),
  1477. DDB_ID(DDVID, 0x0003, DDVID, 0xdb03, ddb_satixS2v3),
  1478. DDB_ID(DDVID, 0x0005, DDVID, 0x0004, ddb_octopusv3),
  1479. /* in case sub-ids got deleted in flash */
  1480. DDB_ID(DDVID, 0x0003, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
  1481. {0}
  1482. };
  1483. MODULE_DEVICE_TABLE(pci, ddb_id_tbl);
  1484. static struct pci_driver ddb_pci_driver = {
  1485. .name = "DDBridge",
  1486. .id_table = ddb_id_tbl,
  1487. .probe = ddb_probe,
  1488. .remove = ddb_remove,
  1489. };
  1490. static __init int module_init_ddbridge(void)
  1491. {
  1492. int ret;
  1493. printk(KERN_INFO "Digital Devices PCIE bridge driver, Copyright (C) 2010-11 Digital Devices GmbH\n");
  1494. ret = ddb_class_create();
  1495. if (ret < 0)
  1496. return ret;
  1497. ret = pci_register_driver(&ddb_pci_driver);
  1498. if (ret < 0)
  1499. ddb_class_destroy();
  1500. return ret;
  1501. }
  1502. static __exit void module_exit_ddbridge(void)
  1503. {
  1504. pci_unregister_driver(&ddb_pci_driver);
  1505. ddb_class_destroy();
  1506. }
  1507. module_init(module_init_ddbridge);
  1508. module_exit(module_exit_ddbridge);
  1509. MODULE_DESCRIPTION("Digital Devices PCIe Bridge");
  1510. MODULE_AUTHOR("Ralph Metzler");
  1511. MODULE_LICENSE("GPL");
  1512. MODULE_VERSION("0.5");