cobalt-driver.c 23 KB

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  1. /*
  2. * cobalt driver initialization and card probing
  3. *
  4. * Derived from cx18-driver.c
  5. *
  6. * Copyright 2012-2015 Cisco Systems, Inc. and/or its affiliates.
  7. * All rights reserved.
  8. *
  9. * This program is free software; you may redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; version 2 of the License.
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  14. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  15. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  16. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  17. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  18. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20. * SOFTWARE.
  21. */
  22. #include <linux/delay.h>
  23. #include <media/i2c/adv7604.h>
  24. #include <media/i2c/adv7842.h>
  25. #include <media/i2c/adv7511.h>
  26. #include <media/v4l2-event.h>
  27. #include <media/v4l2-ctrls.h>
  28. #include "cobalt-driver.h"
  29. #include "cobalt-irq.h"
  30. #include "cobalt-i2c.h"
  31. #include "cobalt-v4l2.h"
  32. #include "cobalt-flash.h"
  33. #include "cobalt-alsa.h"
  34. #include "cobalt-omnitek.h"
  35. /* add your revision and whatnot here */
  36. static struct pci_device_id cobalt_pci_tbl[] = {
  37. {PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_COBALT,
  38. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  39. {0,}
  40. };
  41. MODULE_DEVICE_TABLE(pci, cobalt_pci_tbl);
  42. static atomic_t cobalt_instance = ATOMIC_INIT(0);
  43. int cobalt_debug;
  44. module_param_named(debug, cobalt_debug, int, 0644);
  45. MODULE_PARM_DESC(debug, "Debug level. Default: 0\n");
  46. int cobalt_ignore_err;
  47. module_param_named(ignore_err, cobalt_ignore_err, int, 0644);
  48. MODULE_PARM_DESC(ignore_err,
  49. "If set then ignore missing i2c adapters/receivers. Default: 0\n");
  50. MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com> & Morten Hestnes");
  51. MODULE_DESCRIPTION("cobalt driver");
  52. MODULE_LICENSE("GPL");
  53. static u8 edid[256] = {
  54. 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
  55. 0x50, 0x21, 0x32, 0x27, 0x00, 0x00, 0x00, 0x00,
  56. 0x22, 0x1a, 0x01, 0x03, 0x80, 0x30, 0x1b, 0x78,
  57. 0x0f, 0xee, 0x91, 0xa3, 0x54, 0x4c, 0x99, 0x26,
  58. 0x0f, 0x50, 0x54, 0x2f, 0xcf, 0x00, 0x31, 0x59,
  59. 0x45, 0x59, 0x61, 0x59, 0x81, 0x99, 0x01, 0x01,
  60. 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3a,
  61. 0x80, 0x18, 0x71, 0x38, 0x2d, 0x40, 0x58, 0x2c,
  62. 0x46, 0x00, 0xe0, 0x0e, 0x11, 0x00, 0x00, 0x1e,
  63. 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x55, 0x18,
  64. 0x5e, 0x11, 0x00, 0x0a, 0x20, 0x20, 0x20, 0x20,
  65. 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x63,
  66. 0x6f, 0x62, 0x61, 0x6c, 0x74, 0x0a, 0x20, 0x20,
  67. 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0x10,
  68. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  69. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x9c,
  70. 0x02, 0x03, 0x1f, 0xf0, 0x4a, 0x90, 0x1f, 0x04,
  71. 0x13, 0x22, 0x21, 0x20, 0x02, 0x11, 0x01, 0x23,
  72. 0x09, 0x07, 0x07, 0x68, 0x03, 0x0c, 0x00, 0x10,
  73. 0x00, 0x00, 0x22, 0x0f, 0xe2, 0x00, 0xea, 0x00,
  74. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  75. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  76. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  77. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  78. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  79. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  80. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  81. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  82. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  83. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  84. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  85. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
  86. };
  87. static void cobalt_set_interrupt(struct cobalt *cobalt, bool enable)
  88. {
  89. if (enable) {
  90. unsigned irqs = COBALT_SYSSTAT_VI0_INT1_MSK |
  91. COBALT_SYSSTAT_VI1_INT1_MSK |
  92. COBALT_SYSSTAT_VI2_INT1_MSK |
  93. COBALT_SYSSTAT_VI3_INT1_MSK |
  94. COBALT_SYSSTAT_VI0_INT2_MSK |
  95. COBALT_SYSSTAT_VI1_INT2_MSK |
  96. COBALT_SYSSTAT_VI2_INT2_MSK |
  97. COBALT_SYSSTAT_VI3_INT2_MSK |
  98. COBALT_SYSSTAT_VI0_LOST_DATA_MSK |
  99. COBALT_SYSSTAT_VI1_LOST_DATA_MSK |
  100. COBALT_SYSSTAT_VI2_LOST_DATA_MSK |
  101. COBALT_SYSSTAT_VI3_LOST_DATA_MSK |
  102. COBALT_SYSSTAT_AUD_IN_LOST_DATA_MSK;
  103. if (cobalt->have_hsma_rx)
  104. irqs |= COBALT_SYSSTAT_VIHSMA_INT1_MSK |
  105. COBALT_SYSSTAT_VIHSMA_INT2_MSK |
  106. COBALT_SYSSTAT_VIHSMA_LOST_DATA_MSK;
  107. if (cobalt->have_hsma_tx)
  108. irqs |= COBALT_SYSSTAT_VOHSMA_INT1_MSK |
  109. COBALT_SYSSTAT_VOHSMA_LOST_DATA_MSK |
  110. COBALT_SYSSTAT_AUD_OUT_LOST_DATA_MSK;
  111. /* Clear any existing interrupts */
  112. cobalt_write_bar1(cobalt, COBALT_SYS_STAT_EDGE, 0xffffffff);
  113. /* PIO Core interrupt mask register.
  114. Enable ADV7604 INT1 interrupts */
  115. cobalt_write_bar1(cobalt, COBALT_SYS_STAT_MASK, irqs);
  116. } else {
  117. /* Disable all ADV7604 interrupts */
  118. cobalt_write_bar1(cobalt, COBALT_SYS_STAT_MASK, 0);
  119. }
  120. }
  121. static unsigned cobalt_get_sd_nr(struct v4l2_subdev *sd)
  122. {
  123. struct cobalt *cobalt = to_cobalt(sd->v4l2_dev);
  124. unsigned i;
  125. for (i = 0; i < COBALT_NUM_NODES; i++)
  126. if (sd == cobalt->streams[i].sd)
  127. return i;
  128. cobalt_err("Invalid adv7604 subdev pointer!\n");
  129. return 0;
  130. }
  131. static void cobalt_notify(struct v4l2_subdev *sd,
  132. unsigned int notification, void *arg)
  133. {
  134. struct cobalt *cobalt = to_cobalt(sd->v4l2_dev);
  135. unsigned sd_nr = cobalt_get_sd_nr(sd);
  136. struct cobalt_stream *s = &cobalt->streams[sd_nr];
  137. bool hotplug = arg ? *((int *)arg) : false;
  138. if (s->is_output)
  139. return;
  140. switch (notification) {
  141. case ADV76XX_HOTPLUG:
  142. cobalt_s_bit_sysctrl(cobalt,
  143. COBALT_SYS_CTRL_HPD_TO_CONNECTOR_BIT(sd_nr), hotplug);
  144. cobalt_dbg(1, "Set hotplug for adv %d to %d\n", sd_nr, hotplug);
  145. break;
  146. case V4L2_DEVICE_NOTIFY_EVENT:
  147. cobalt_dbg(1, "Format changed for adv %d\n", sd_nr);
  148. v4l2_event_queue(&s->vdev, arg);
  149. break;
  150. default:
  151. break;
  152. }
  153. }
  154. static int get_payload_size(u16 code)
  155. {
  156. switch (code) {
  157. case 0: return 128;
  158. case 1: return 256;
  159. case 2: return 512;
  160. case 3: return 1024;
  161. case 4: return 2048;
  162. case 5: return 4096;
  163. default: return 0;
  164. }
  165. return 0;
  166. }
  167. static const char *get_link_speed(u16 stat)
  168. {
  169. switch (stat & PCI_EXP_LNKSTA_CLS) {
  170. case 1: return "2.5 Gbit/s";
  171. case 2: return "5 Gbit/s";
  172. case 3: return "10 Gbit/s";
  173. }
  174. return "Unknown speed";
  175. }
  176. void cobalt_pcie_status_show(struct cobalt *cobalt)
  177. {
  178. struct pci_dev *pci_dev = cobalt->pci_dev;
  179. struct pci_dev *pci_bus_dev = cobalt->pci_dev->bus->self;
  180. int offset;
  181. int bus_offset;
  182. u32 capa;
  183. u16 stat, ctrl;
  184. offset = pci_find_capability(pci_dev, PCI_CAP_ID_EXP);
  185. bus_offset = pci_find_capability(pci_bus_dev, PCI_CAP_ID_EXP);
  186. /* Device */
  187. pci_read_config_dword(pci_dev, offset + PCI_EXP_DEVCAP, &capa);
  188. pci_read_config_word(pci_dev, offset + PCI_EXP_DEVCTL, &ctrl);
  189. pci_read_config_word(pci_dev, offset + PCI_EXP_DEVSTA, &stat);
  190. cobalt_info("PCIe device capability 0x%08x: Max payload %d\n",
  191. capa, get_payload_size(capa & PCI_EXP_DEVCAP_PAYLOAD));
  192. cobalt_info("PCIe device control 0x%04x: Max payload %d. Max read request %d\n",
  193. ctrl,
  194. get_payload_size((ctrl & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
  195. get_payload_size((ctrl & PCI_EXP_DEVCTL_READRQ) >> 12));
  196. cobalt_info("PCIe device status 0x%04x\n", stat);
  197. /* Link */
  198. pci_read_config_dword(pci_dev, offset + PCI_EXP_LNKCAP, &capa);
  199. pci_read_config_word(pci_dev, offset + PCI_EXP_LNKCTL, &ctrl);
  200. pci_read_config_word(pci_dev, offset + PCI_EXP_LNKSTA, &stat);
  201. cobalt_info("PCIe link capability 0x%08x: %s per lane and %u lanes\n",
  202. capa, get_link_speed(capa),
  203. (capa & PCI_EXP_LNKCAP_MLW) >> 4);
  204. cobalt_info("PCIe link control 0x%04x\n", ctrl);
  205. cobalt_info("PCIe link status 0x%04x: %s per lane and %u lanes\n",
  206. stat, get_link_speed(stat),
  207. (stat & PCI_EXP_LNKSTA_NLW) >> 4);
  208. /* Bus */
  209. pci_read_config_dword(pci_bus_dev, bus_offset + PCI_EXP_LNKCAP, &capa);
  210. cobalt_info("PCIe bus link capability 0x%08x: %s per lane and %u lanes\n",
  211. capa, get_link_speed(capa),
  212. (capa & PCI_EXP_LNKCAP_MLW) >> 4);
  213. /* Slot */
  214. pci_read_config_dword(pci_dev, offset + PCI_EXP_SLTCAP, &capa);
  215. pci_read_config_word(pci_dev, offset + PCI_EXP_SLTCTL, &ctrl);
  216. pci_read_config_word(pci_dev, offset + PCI_EXP_SLTSTA, &stat);
  217. cobalt_info("PCIe slot capability 0x%08x\n", capa);
  218. cobalt_info("PCIe slot control 0x%04x\n", ctrl);
  219. cobalt_info("PCIe slot status 0x%04x\n", stat);
  220. }
  221. static unsigned pcie_link_get_lanes(struct cobalt *cobalt)
  222. {
  223. struct pci_dev *pci_dev = cobalt->pci_dev;
  224. unsigned offset;
  225. u16 link;
  226. offset = pci_find_capability(pci_dev, PCI_CAP_ID_EXP);
  227. if (!offset)
  228. return 0;
  229. pci_read_config_word(pci_dev, offset + PCI_EXP_LNKSTA, &link);
  230. return (link & PCI_EXP_LNKSTA_NLW) >> 4;
  231. }
  232. static unsigned pcie_bus_link_get_lanes(struct cobalt *cobalt)
  233. {
  234. struct pci_dev *pci_dev = cobalt->pci_dev->bus->self;
  235. unsigned offset;
  236. u32 link;
  237. offset = pci_find_capability(pci_dev, PCI_CAP_ID_EXP);
  238. if (!offset)
  239. return 0;
  240. pci_read_config_dword(pci_dev, offset + PCI_EXP_LNKCAP, &link);
  241. return (link & PCI_EXP_LNKCAP_MLW) >> 4;
  242. }
  243. static void msi_config_show(struct cobalt *cobalt, struct pci_dev *pci_dev)
  244. {
  245. u16 ctrl, data;
  246. u32 adrs_l, adrs_h;
  247. pci_read_config_word(pci_dev, 0x52, &ctrl);
  248. cobalt_info("MSI %s\n", ctrl & 1 ? "enable" : "disable");
  249. cobalt_info("MSI multiple message: Capable %u. Enable %u\n",
  250. (1 << ((ctrl >> 1) & 7)), (1 << ((ctrl >> 4) & 7)));
  251. if (ctrl & 0x80)
  252. cobalt_info("MSI: 64-bit address capable\n");
  253. pci_read_config_dword(pci_dev, 0x54, &adrs_l);
  254. pci_read_config_dword(pci_dev, 0x58, &adrs_h);
  255. pci_read_config_word(pci_dev, 0x5c, &data);
  256. if (ctrl & 0x80)
  257. cobalt_info("MSI: Address 0x%08x%08x. Data 0x%04x\n",
  258. adrs_h, adrs_l, data);
  259. else
  260. cobalt_info("MSI: Address 0x%08x. Data 0x%04x\n",
  261. adrs_l, data);
  262. }
  263. static void cobalt_pci_iounmap(struct cobalt *cobalt, struct pci_dev *pci_dev)
  264. {
  265. if (cobalt->bar0) {
  266. pci_iounmap(pci_dev, cobalt->bar0);
  267. cobalt->bar0 = NULL;
  268. }
  269. if (cobalt->bar1) {
  270. pci_iounmap(pci_dev, cobalt->bar1);
  271. cobalt->bar1 = NULL;
  272. }
  273. }
  274. static void cobalt_free_msi(struct cobalt *cobalt, struct pci_dev *pci_dev)
  275. {
  276. free_irq(pci_dev->irq, (void *)cobalt);
  277. pci_free_irq_vectors(pci_dev);
  278. }
  279. static int cobalt_setup_pci(struct cobalt *cobalt, struct pci_dev *pci_dev,
  280. const struct pci_device_id *pci_id)
  281. {
  282. u32 ctrl;
  283. int ret;
  284. cobalt_dbg(1, "enabling pci device\n");
  285. ret = pci_enable_device(pci_dev);
  286. if (ret) {
  287. cobalt_err("can't enable device\n");
  288. return ret;
  289. }
  290. pci_set_master(pci_dev);
  291. pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &cobalt->card_rev);
  292. pci_read_config_word(pci_dev, PCI_DEVICE_ID, &cobalt->device_id);
  293. switch (cobalt->device_id) {
  294. case PCI_DEVICE_ID_COBALT:
  295. cobalt_info("PCI Express interface from Omnitek\n");
  296. break;
  297. default:
  298. cobalt_info("PCI Express interface provider is unknown!\n");
  299. break;
  300. }
  301. if (pcie_link_get_lanes(cobalt) != 8) {
  302. cobalt_warn("PCI Express link width is %d lanes.\n",
  303. pcie_link_get_lanes(cobalt));
  304. if (pcie_bus_link_get_lanes(cobalt) < 8)
  305. cobalt_warn("The current slot only supports %d lanes, for best performance 8 are needed\n",
  306. pcie_bus_link_get_lanes(cobalt));
  307. if (pcie_link_get_lanes(cobalt) != pcie_bus_link_get_lanes(cobalt)) {
  308. cobalt_err("The card is most likely not seated correctly in the PCIe slot\n");
  309. ret = -EIO;
  310. goto err_disable;
  311. }
  312. }
  313. if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(64))) {
  314. ret = pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32));
  315. if (ret) {
  316. cobalt_err("no suitable DMA available\n");
  317. goto err_disable;
  318. }
  319. }
  320. ret = pci_request_regions(pci_dev, "cobalt");
  321. if (ret) {
  322. cobalt_err("error requesting regions\n");
  323. goto err_disable;
  324. }
  325. cobalt_pcie_status_show(cobalt);
  326. cobalt->bar0 = pci_iomap(pci_dev, 0, 0);
  327. cobalt->bar1 = pci_iomap(pci_dev, 1, 0);
  328. if (cobalt->bar1 == NULL) {
  329. cobalt->bar1 = pci_iomap(pci_dev, 2, 0);
  330. cobalt_info("64-bit BAR\n");
  331. }
  332. if (!cobalt->bar0 || !cobalt->bar1) {
  333. ret = -EIO;
  334. goto err_release;
  335. }
  336. /* Reset the video inputs before enabling any interrupts */
  337. ctrl = cobalt_read_bar1(cobalt, COBALT_SYS_CTRL_BASE);
  338. cobalt_write_bar1(cobalt, COBALT_SYS_CTRL_BASE, ctrl & ~0xf00);
  339. /* Disable interrupts to prevent any spurious interrupts
  340. from being generated. */
  341. cobalt_set_interrupt(cobalt, false);
  342. if (pci_alloc_irq_vectors(pci_dev, 1, 1, PCI_IRQ_MSI) < 1) {
  343. cobalt_err("Could not enable MSI\n");
  344. ret = -EIO;
  345. goto err_release;
  346. }
  347. msi_config_show(cobalt, pci_dev);
  348. /* Register IRQ */
  349. if (request_irq(pci_dev->irq, cobalt_irq_handler, IRQF_SHARED,
  350. cobalt->v4l2_dev.name, (void *)cobalt)) {
  351. cobalt_err("Failed to register irq %d\n", pci_dev->irq);
  352. ret = -EIO;
  353. goto err_msi;
  354. }
  355. omni_sg_dma_init(cobalt);
  356. return 0;
  357. err_msi:
  358. pci_disable_msi(pci_dev);
  359. err_release:
  360. cobalt_pci_iounmap(cobalt, pci_dev);
  361. pci_release_regions(pci_dev);
  362. err_disable:
  363. pci_disable_device(cobalt->pci_dev);
  364. return ret;
  365. }
  366. static int cobalt_hdl_info_get(struct cobalt *cobalt)
  367. {
  368. int i;
  369. for (i = 0; i < COBALT_HDL_INFO_SIZE; i++)
  370. cobalt->hdl_info[i] =
  371. ioread8(cobalt->bar1 + COBALT_HDL_INFO_BASE + i);
  372. cobalt->hdl_info[COBALT_HDL_INFO_SIZE - 1] = '\0';
  373. if (strstr(cobalt->hdl_info, COBALT_HDL_SEARCH_STR))
  374. return 0;
  375. return 1;
  376. }
  377. static void cobalt_stream_struct_init(struct cobalt *cobalt)
  378. {
  379. int i;
  380. for (i = 0; i < COBALT_NUM_STREAMS; i++) {
  381. struct cobalt_stream *s = &cobalt->streams[i];
  382. s->cobalt = cobalt;
  383. s->flags = 0;
  384. s->is_audio = false;
  385. s->is_output = false;
  386. s->is_dummy = true;
  387. /* The Memory DMA channels will always get a lower channel
  388. * number than the FIFO DMA. Video input should map to the
  389. * stream 0-3. The other can use stream struct from 4 and
  390. * higher */
  391. if (i <= COBALT_HSMA_IN_NODE) {
  392. s->dma_channel = i + cobalt->first_fifo_channel;
  393. s->video_channel = i;
  394. s->dma_fifo_mask =
  395. COBALT_SYSSTAT_VI0_LOST_DATA_MSK << (4 * i);
  396. s->adv_irq_mask =
  397. COBALT_SYSSTAT_VI0_INT1_MSK << (4 * i);
  398. } else if (i >= COBALT_AUDIO_IN_STREAM &&
  399. i <= COBALT_AUDIO_IN_STREAM + 4) {
  400. unsigned idx = i - COBALT_AUDIO_IN_STREAM;
  401. s->dma_channel = 6 + idx;
  402. s->is_audio = true;
  403. s->video_channel = idx;
  404. s->dma_fifo_mask = COBALT_SYSSTAT_AUD_IN_LOST_DATA_MSK;
  405. } else if (i == COBALT_HSMA_OUT_NODE) {
  406. s->dma_channel = 11;
  407. s->is_output = true;
  408. s->video_channel = 5;
  409. s->dma_fifo_mask = COBALT_SYSSTAT_VOHSMA_LOST_DATA_MSK;
  410. s->adv_irq_mask = COBALT_SYSSTAT_VOHSMA_INT1_MSK;
  411. } else if (i == COBALT_AUDIO_OUT_STREAM) {
  412. s->dma_channel = 12;
  413. s->is_audio = true;
  414. s->is_output = true;
  415. s->video_channel = 5;
  416. s->dma_fifo_mask = COBALT_SYSSTAT_AUD_OUT_LOST_DATA_MSK;
  417. } else {
  418. /* FIXME: Memory DMA for debug purpose */
  419. s->dma_channel = i - COBALT_NUM_NODES;
  420. }
  421. cobalt_info("stream #%d -> dma channel #%d <- video channel %d\n",
  422. i, s->dma_channel, s->video_channel);
  423. }
  424. }
  425. static int cobalt_subdevs_init(struct cobalt *cobalt)
  426. {
  427. static struct adv76xx_platform_data adv7604_pdata = {
  428. .disable_pwrdnb = 1,
  429. .ain_sel = ADV7604_AIN7_8_9_NC_SYNC_3_1,
  430. .bus_order = ADV7604_BUS_ORDER_BRG,
  431. .blank_data = 1,
  432. .op_format_mode_sel = ADV7604_OP_FORMAT_MODE0,
  433. .int1_config = ADV76XX_INT1_CONFIG_ACTIVE_HIGH,
  434. .dr_str_data = ADV76XX_DR_STR_HIGH,
  435. .dr_str_clk = ADV76XX_DR_STR_HIGH,
  436. .dr_str_sync = ADV76XX_DR_STR_HIGH,
  437. .hdmi_free_run_mode = 1,
  438. .inv_vs_pol = 1,
  439. .inv_hs_pol = 1,
  440. };
  441. static struct i2c_board_info adv7604_info = {
  442. .type = "adv7604",
  443. .addr = 0x20,
  444. .platform_data = &adv7604_pdata,
  445. };
  446. struct cobalt_stream *s = cobalt->streams;
  447. int i;
  448. for (i = 0; i < COBALT_NUM_INPUTS; i++) {
  449. struct v4l2_subdev_format sd_fmt = {
  450. .pad = ADV7604_PAD_SOURCE,
  451. .which = V4L2_SUBDEV_FORMAT_ACTIVE,
  452. .format.code = MEDIA_BUS_FMT_YUYV8_1X16,
  453. };
  454. struct v4l2_subdev_edid cobalt_edid = {
  455. .pad = ADV76XX_PAD_HDMI_PORT_A,
  456. .start_block = 0,
  457. .blocks = 2,
  458. .edid = edid,
  459. };
  460. int err;
  461. s[i].pad_source = ADV7604_PAD_SOURCE;
  462. s[i].i2c_adap = &cobalt->i2c_adap[i];
  463. if (s[i].i2c_adap->dev.parent == NULL)
  464. continue;
  465. cobalt_s_bit_sysctrl(cobalt,
  466. COBALT_SYS_CTRL_NRESET_TO_HDMI_BIT(i), 1);
  467. s[i].sd = v4l2_i2c_new_subdev_board(&cobalt->v4l2_dev,
  468. s[i].i2c_adap, &adv7604_info, NULL);
  469. if (!s[i].sd) {
  470. if (cobalt_ignore_err)
  471. continue;
  472. return -ENODEV;
  473. }
  474. err = v4l2_subdev_call(s[i].sd, video, s_routing,
  475. ADV76XX_PAD_HDMI_PORT_A, 0, 0);
  476. if (err)
  477. return err;
  478. err = v4l2_subdev_call(s[i].sd, pad, set_edid,
  479. &cobalt_edid);
  480. if (err)
  481. return err;
  482. err = v4l2_subdev_call(s[i].sd, pad, set_fmt, NULL,
  483. &sd_fmt);
  484. if (err)
  485. return err;
  486. /* Reset channel video module */
  487. cobalt_s_bit_sysctrl(cobalt,
  488. COBALT_SYS_CTRL_VIDEO_RX_RESETN_BIT(i), 0);
  489. mdelay(2);
  490. cobalt_s_bit_sysctrl(cobalt,
  491. COBALT_SYS_CTRL_VIDEO_RX_RESETN_BIT(i), 1);
  492. mdelay(1);
  493. s[i].is_dummy = false;
  494. cobalt->streams[i + COBALT_AUDIO_IN_STREAM].is_dummy = false;
  495. }
  496. return 0;
  497. }
  498. static int cobalt_subdevs_hsma_init(struct cobalt *cobalt)
  499. {
  500. static struct adv7842_platform_data adv7842_pdata = {
  501. .disable_pwrdnb = 1,
  502. .ain_sel = ADV7842_AIN1_2_3_NC_SYNC_1_2,
  503. .bus_order = ADV7842_BUS_ORDER_RBG,
  504. .op_format_mode_sel = ADV7842_OP_FORMAT_MODE0,
  505. .blank_data = 1,
  506. .dr_str_data = 3,
  507. .dr_str_clk = 3,
  508. .dr_str_sync = 3,
  509. .mode = ADV7842_MODE_HDMI,
  510. .hdmi_free_run_enable = 1,
  511. .vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P,
  512. .i2c_sdp_io = 0x4a,
  513. .i2c_sdp = 0x48,
  514. .i2c_cp = 0x22,
  515. .i2c_vdp = 0x24,
  516. .i2c_afe = 0x26,
  517. .i2c_hdmi = 0x34,
  518. .i2c_repeater = 0x32,
  519. .i2c_edid = 0x36,
  520. .i2c_infoframe = 0x3e,
  521. .i2c_cec = 0x40,
  522. .i2c_avlink = 0x42,
  523. };
  524. static struct i2c_board_info adv7842_info = {
  525. .type = "adv7842",
  526. .addr = 0x20,
  527. .platform_data = &adv7842_pdata,
  528. };
  529. static struct v4l2_subdev_format sd_fmt = {
  530. .pad = ADV7842_PAD_SOURCE,
  531. .which = V4L2_SUBDEV_FORMAT_ACTIVE,
  532. .format.code = MEDIA_BUS_FMT_YUYV8_1X16,
  533. };
  534. static struct adv7511_platform_data adv7511_pdata = {
  535. .i2c_edid = 0x7e >> 1,
  536. .i2c_cec = 0x7c >> 1,
  537. .i2c_pktmem = 0x70 >> 1,
  538. .cec_clk = 12000000,
  539. };
  540. static struct i2c_board_info adv7511_info = {
  541. .type = "adv7511",
  542. .addr = 0x39, /* 0x39 or 0x3d */
  543. .platform_data = &adv7511_pdata,
  544. };
  545. struct v4l2_subdev_edid cobalt_edid = {
  546. .pad = ADV7842_EDID_PORT_A,
  547. .start_block = 0,
  548. .blocks = 2,
  549. .edid = edid,
  550. };
  551. struct cobalt_stream *s = &cobalt->streams[COBALT_HSMA_IN_NODE];
  552. s->i2c_adap = &cobalt->i2c_adap[COBALT_NUM_ADAPTERS - 1];
  553. if (s->i2c_adap->dev.parent == NULL)
  554. return 0;
  555. cobalt_s_bit_sysctrl(cobalt, COBALT_SYS_CTRL_NRESET_TO_HDMI_BIT(4), 1);
  556. s->sd = v4l2_i2c_new_subdev_board(&cobalt->v4l2_dev,
  557. s->i2c_adap, &adv7842_info, NULL);
  558. if (s->sd) {
  559. int err = v4l2_subdev_call(s->sd, pad, set_edid, &cobalt_edid);
  560. if (err)
  561. return err;
  562. err = v4l2_subdev_call(s->sd, pad, set_fmt, NULL,
  563. &sd_fmt);
  564. if (err)
  565. return err;
  566. cobalt->have_hsma_rx = true;
  567. s->pad_source = ADV7842_PAD_SOURCE;
  568. s->is_dummy = false;
  569. cobalt->streams[4 + COBALT_AUDIO_IN_STREAM].is_dummy = false;
  570. /* Reset channel video module */
  571. cobalt_s_bit_sysctrl(cobalt,
  572. COBALT_SYS_CTRL_VIDEO_RX_RESETN_BIT(4), 0);
  573. mdelay(2);
  574. cobalt_s_bit_sysctrl(cobalt,
  575. COBALT_SYS_CTRL_VIDEO_RX_RESETN_BIT(4), 1);
  576. mdelay(1);
  577. return err;
  578. }
  579. cobalt_s_bit_sysctrl(cobalt, COBALT_SYS_CTRL_NRESET_TO_HDMI_BIT(4), 0);
  580. cobalt_s_bit_sysctrl(cobalt, COBALT_SYS_CTRL_PWRDN0_TO_HSMA_TX_BIT, 0);
  581. s++;
  582. s->i2c_adap = &cobalt->i2c_adap[COBALT_NUM_ADAPTERS - 1];
  583. s->sd = v4l2_i2c_new_subdev_board(&cobalt->v4l2_dev,
  584. s->i2c_adap, &adv7511_info, NULL);
  585. if (s->sd) {
  586. /* A transmitter is hooked up, so we can set this bit */
  587. cobalt_s_bit_sysctrl(cobalt,
  588. COBALT_SYS_CTRL_HSMA_TX_ENABLE_BIT, 1);
  589. cobalt_s_bit_sysctrl(cobalt,
  590. COBALT_SYS_CTRL_VIDEO_RX_RESETN_BIT(4), 0);
  591. cobalt_s_bit_sysctrl(cobalt,
  592. COBALT_SYS_CTRL_VIDEO_TX_RESETN_BIT, 1);
  593. cobalt->have_hsma_tx = true;
  594. v4l2_subdev_call(s->sd, core, s_power, 1);
  595. v4l2_subdev_call(s->sd, video, s_stream, 1);
  596. v4l2_subdev_call(s->sd, audio, s_stream, 1);
  597. v4l2_ctrl_s_ctrl(v4l2_ctrl_find(s->sd->ctrl_handler,
  598. V4L2_CID_DV_TX_MODE), V4L2_DV_TX_MODE_HDMI);
  599. s->is_dummy = false;
  600. cobalt->streams[COBALT_AUDIO_OUT_STREAM].is_dummy = false;
  601. return 0;
  602. }
  603. return -ENODEV;
  604. }
  605. static int cobalt_probe(struct pci_dev *pci_dev,
  606. const struct pci_device_id *pci_id)
  607. {
  608. struct cobalt *cobalt;
  609. int retval = 0;
  610. int i;
  611. /* FIXME - module parameter arrays constrain max instances */
  612. i = atomic_inc_return(&cobalt_instance) - 1;
  613. cobalt = kzalloc(sizeof(struct cobalt), GFP_ATOMIC);
  614. if (cobalt == NULL)
  615. return -ENOMEM;
  616. cobalt->pci_dev = pci_dev;
  617. cobalt->instance = i;
  618. retval = v4l2_device_register(&pci_dev->dev, &cobalt->v4l2_dev);
  619. if (retval) {
  620. pr_err("cobalt: v4l2_device_register of card %d failed\n",
  621. cobalt->instance);
  622. kfree(cobalt);
  623. return retval;
  624. }
  625. snprintf(cobalt->v4l2_dev.name, sizeof(cobalt->v4l2_dev.name),
  626. "cobalt-%d", cobalt->instance);
  627. cobalt->v4l2_dev.notify = cobalt_notify;
  628. cobalt_info("Initializing card %d\n", cobalt->instance);
  629. cobalt->irq_work_queues =
  630. create_singlethread_workqueue(cobalt->v4l2_dev.name);
  631. if (cobalt->irq_work_queues == NULL) {
  632. cobalt_err("Could not create workqueue\n");
  633. retval = -ENOMEM;
  634. goto err;
  635. }
  636. INIT_WORK(&cobalt->irq_work_queue, cobalt_irq_work_handler);
  637. /* PCI Device Setup */
  638. retval = cobalt_setup_pci(cobalt, pci_dev, pci_id);
  639. if (retval != 0)
  640. goto err_wq;
  641. /* Show HDL version info */
  642. if (cobalt_hdl_info_get(cobalt))
  643. cobalt_info("Not able to read the HDL info\n");
  644. else
  645. cobalt_info("%s", cobalt->hdl_info);
  646. retval = cobalt_i2c_init(cobalt);
  647. if (retval)
  648. goto err_pci;
  649. cobalt_stream_struct_init(cobalt);
  650. retval = cobalt_subdevs_init(cobalt);
  651. if (retval)
  652. goto err_i2c;
  653. if (!(cobalt_read_bar1(cobalt, COBALT_SYS_STAT_BASE) &
  654. COBALT_SYSSTAT_HSMA_PRSNTN_MSK)) {
  655. retval = cobalt_subdevs_hsma_init(cobalt);
  656. if (retval)
  657. goto err_i2c;
  658. }
  659. retval = v4l2_device_register_subdev_nodes(&cobalt->v4l2_dev);
  660. if (retval)
  661. goto err_i2c;
  662. retval = cobalt_nodes_register(cobalt);
  663. if (retval) {
  664. cobalt_err("Error %d registering device nodes\n", retval);
  665. goto err_i2c;
  666. }
  667. cobalt_set_interrupt(cobalt, true);
  668. v4l2_device_call_all(&cobalt->v4l2_dev, 0, core,
  669. interrupt_service_routine, 0, NULL);
  670. cobalt_info("Initialized cobalt card\n");
  671. cobalt_flash_probe(cobalt);
  672. return 0;
  673. err_i2c:
  674. cobalt_i2c_exit(cobalt);
  675. cobalt_s_bit_sysctrl(cobalt, COBALT_SYS_CTRL_HSMA_TX_ENABLE_BIT, 0);
  676. err_pci:
  677. cobalt_free_msi(cobalt, pci_dev);
  678. cobalt_pci_iounmap(cobalt, pci_dev);
  679. pci_release_regions(cobalt->pci_dev);
  680. pci_disable_device(cobalt->pci_dev);
  681. err_wq:
  682. destroy_workqueue(cobalt->irq_work_queues);
  683. err:
  684. if (retval == 0)
  685. retval = -ENODEV;
  686. cobalt_err("error %d on initialization\n", retval);
  687. v4l2_device_unregister(&cobalt->v4l2_dev);
  688. kfree(cobalt);
  689. return retval;
  690. }
  691. static void cobalt_remove(struct pci_dev *pci_dev)
  692. {
  693. struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
  694. struct cobalt *cobalt = to_cobalt(v4l2_dev);
  695. int i;
  696. cobalt_flash_remove(cobalt);
  697. cobalt_set_interrupt(cobalt, false);
  698. flush_workqueue(cobalt->irq_work_queues);
  699. cobalt_nodes_unregister(cobalt);
  700. for (i = 0; i < COBALT_NUM_ADAPTERS; i++) {
  701. struct v4l2_subdev *sd = cobalt->streams[i].sd;
  702. struct i2c_client *client;
  703. if (sd == NULL)
  704. continue;
  705. client = v4l2_get_subdevdata(sd);
  706. v4l2_device_unregister_subdev(sd);
  707. i2c_unregister_device(client);
  708. }
  709. cobalt_i2c_exit(cobalt);
  710. cobalt_free_msi(cobalt, pci_dev);
  711. cobalt_s_bit_sysctrl(cobalt, COBALT_SYS_CTRL_HSMA_TX_ENABLE_BIT, 0);
  712. cobalt_pci_iounmap(cobalt, pci_dev);
  713. pci_release_regions(cobalt->pci_dev);
  714. pci_disable_device(cobalt->pci_dev);
  715. destroy_workqueue(cobalt->irq_work_queues);
  716. cobalt_info("removed cobalt card\n");
  717. v4l2_device_unregister(v4l2_dev);
  718. kfree(cobalt);
  719. }
  720. /* define a pci_driver for card detection */
  721. static struct pci_driver cobalt_pci_driver = {
  722. .name = "cobalt",
  723. .id_table = cobalt_pci_tbl,
  724. .probe = cobalt_probe,
  725. .remove = cobalt_remove,
  726. };
  727. module_pci_driver(cobalt_pci_driver);