adv7180.c 40 KB

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  1. /*
  2. * adv7180.c Analog Devices ADV7180 video decoder driver
  3. * Copyright (c) 2009 Intel Corporation
  4. * Copyright (C) 2013 Cogent Embedded, Inc.
  5. * Copyright (C) 2013 Renesas Solutions Corp.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #include <linux/module.h>
  17. #include <linux/init.h>
  18. #include <linux/errno.h>
  19. #include <linux/kernel.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/i2c.h>
  22. #include <linux/slab.h>
  23. #include <linux/of.h>
  24. #include <linux/gpio/consumer.h>
  25. #include <linux/videodev2.h>
  26. #include <media/v4l2-ioctl.h>
  27. #include <media/v4l2-event.h>
  28. #include <media/v4l2-device.h>
  29. #include <media/v4l2-ctrls.h>
  30. #include <linux/mutex.h>
  31. #include <linux/delay.h>
  32. #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM 0x0
  33. #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM_PED 0x1
  34. #define ADV7180_STD_AD_PAL_N_NTSC_J_SECAM 0x2
  35. #define ADV7180_STD_AD_PAL_N_NTSC_M_SECAM 0x3
  36. #define ADV7180_STD_NTSC_J 0x4
  37. #define ADV7180_STD_NTSC_M 0x5
  38. #define ADV7180_STD_PAL60 0x6
  39. #define ADV7180_STD_NTSC_443 0x7
  40. #define ADV7180_STD_PAL_BG 0x8
  41. #define ADV7180_STD_PAL_N 0x9
  42. #define ADV7180_STD_PAL_M 0xa
  43. #define ADV7180_STD_PAL_M_PED 0xb
  44. #define ADV7180_STD_PAL_COMB_N 0xc
  45. #define ADV7180_STD_PAL_COMB_N_PED 0xd
  46. #define ADV7180_STD_PAL_SECAM 0xe
  47. #define ADV7180_STD_PAL_SECAM_PED 0xf
  48. #define ADV7180_REG_INPUT_CONTROL 0x0000
  49. #define ADV7180_INPUT_CONTROL_INSEL_MASK 0x0f
  50. #define ADV7182_REG_INPUT_VIDSEL 0x0002
  51. #define ADV7180_REG_OUTPUT_CONTROL 0x0003
  52. #define ADV7180_REG_EXTENDED_OUTPUT_CONTROL 0x0004
  53. #define ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS 0xC5
  54. #define ADV7180_REG_AUTODETECT_ENABLE 0x0007
  55. #define ADV7180_AUTODETECT_DEFAULT 0x7f
  56. /* Contrast */
  57. #define ADV7180_REG_CON 0x0008 /*Unsigned */
  58. #define ADV7180_CON_MIN 0
  59. #define ADV7180_CON_DEF 128
  60. #define ADV7180_CON_MAX 255
  61. /* Brightness*/
  62. #define ADV7180_REG_BRI 0x000a /*Signed */
  63. #define ADV7180_BRI_MIN -128
  64. #define ADV7180_BRI_DEF 0
  65. #define ADV7180_BRI_MAX 127
  66. /* Hue */
  67. #define ADV7180_REG_HUE 0x000b /*Signed, inverted */
  68. #define ADV7180_HUE_MIN -127
  69. #define ADV7180_HUE_DEF 0
  70. #define ADV7180_HUE_MAX 128
  71. #define ADV7180_REG_CTRL 0x000e
  72. #define ADV7180_CTRL_IRQ_SPACE 0x20
  73. #define ADV7180_REG_PWR_MAN 0x0f
  74. #define ADV7180_PWR_MAN_ON 0x04
  75. #define ADV7180_PWR_MAN_OFF 0x24
  76. #define ADV7180_PWR_MAN_RES 0x80
  77. #define ADV7180_REG_STATUS1 0x0010
  78. #define ADV7180_STATUS1_IN_LOCK 0x01
  79. #define ADV7180_STATUS1_AUTOD_MASK 0x70
  80. #define ADV7180_STATUS1_AUTOD_NTSM_M_J 0x00
  81. #define ADV7180_STATUS1_AUTOD_NTSC_4_43 0x10
  82. #define ADV7180_STATUS1_AUTOD_PAL_M 0x20
  83. #define ADV7180_STATUS1_AUTOD_PAL_60 0x30
  84. #define ADV7180_STATUS1_AUTOD_PAL_B_G 0x40
  85. #define ADV7180_STATUS1_AUTOD_SECAM 0x50
  86. #define ADV7180_STATUS1_AUTOD_PAL_COMB 0x60
  87. #define ADV7180_STATUS1_AUTOD_SECAM_525 0x70
  88. #define ADV7180_REG_IDENT 0x0011
  89. #define ADV7180_ID_7180 0x18
  90. #define ADV7180_REG_STATUS3 0x0013
  91. #define ADV7180_REG_ANALOG_CLAMP_CTL 0x0014
  92. #define ADV7180_REG_SHAP_FILTER_CTL_1 0x0017
  93. #define ADV7180_REG_CTRL_2 0x001d
  94. #define ADV7180_REG_VSYNC_FIELD_CTL_1 0x0031
  95. #define ADV7180_REG_MANUAL_WIN_CTL_1 0x003d
  96. #define ADV7180_REG_MANUAL_WIN_CTL_2 0x003e
  97. #define ADV7180_REG_MANUAL_WIN_CTL_3 0x003f
  98. #define ADV7180_REG_LOCK_CNT 0x0051
  99. #define ADV7180_REG_CVBS_TRIM 0x0052
  100. #define ADV7180_REG_CLAMP_ADJ 0x005a
  101. #define ADV7180_REG_RES_CIR 0x005f
  102. #define ADV7180_REG_DIFF_MODE 0x0060
  103. #define ADV7180_REG_ICONF1 0x2040
  104. #define ADV7180_ICONF1_ACTIVE_LOW 0x01
  105. #define ADV7180_ICONF1_PSYNC_ONLY 0x10
  106. #define ADV7180_ICONF1_ACTIVE_TO_CLR 0xC0
  107. /* Saturation */
  108. #define ADV7180_REG_SD_SAT_CB 0x00e3 /*Unsigned */
  109. #define ADV7180_REG_SD_SAT_CR 0x00e4 /*Unsigned */
  110. #define ADV7180_SAT_MIN 0
  111. #define ADV7180_SAT_DEF 128
  112. #define ADV7180_SAT_MAX 255
  113. #define ADV7180_IRQ1_LOCK 0x01
  114. #define ADV7180_IRQ1_UNLOCK 0x02
  115. #define ADV7180_REG_ISR1 0x2042
  116. #define ADV7180_REG_ICR1 0x2043
  117. #define ADV7180_REG_IMR1 0x2044
  118. #define ADV7180_REG_IMR2 0x2048
  119. #define ADV7180_IRQ3_AD_CHANGE 0x08
  120. #define ADV7180_REG_ISR3 0x204A
  121. #define ADV7180_REG_ICR3 0x204B
  122. #define ADV7180_REG_IMR3 0x204C
  123. #define ADV7180_REG_IMR4 0x2050
  124. #define ADV7180_REG_NTSC_V_BIT_END 0x00E6
  125. #define ADV7180_NTSC_V_BIT_END_MANUAL_NVEND 0x4F
  126. #define ADV7180_REG_VPP_SLAVE_ADDR 0xFD
  127. #define ADV7180_REG_CSI_SLAVE_ADDR 0xFE
  128. #define ADV7180_REG_ACE_CTRL1 0x4080
  129. #define ADV7180_REG_ACE_CTRL5 0x4084
  130. #define ADV7180_REG_FLCONTROL 0x40e0
  131. #define ADV7180_FLCONTROL_FL_ENABLE 0x1
  132. #define ADV7180_REG_RST_CLAMP 0x809c
  133. #define ADV7180_REG_AGC_ADJ1 0x80b6
  134. #define ADV7180_REG_AGC_ADJ2 0x80c0
  135. #define ADV7180_CSI_REG_PWRDN 0x00
  136. #define ADV7180_CSI_PWRDN 0x80
  137. #define ADV7180_INPUT_CVBS_AIN1 0x00
  138. #define ADV7180_INPUT_CVBS_AIN2 0x01
  139. #define ADV7180_INPUT_CVBS_AIN3 0x02
  140. #define ADV7180_INPUT_CVBS_AIN4 0x03
  141. #define ADV7180_INPUT_CVBS_AIN5 0x04
  142. #define ADV7180_INPUT_CVBS_AIN6 0x05
  143. #define ADV7180_INPUT_SVIDEO_AIN1_AIN2 0x06
  144. #define ADV7180_INPUT_SVIDEO_AIN3_AIN4 0x07
  145. #define ADV7180_INPUT_SVIDEO_AIN5_AIN6 0x08
  146. #define ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3 0x09
  147. #define ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0a
  148. #define ADV7182_INPUT_CVBS_AIN1 0x00
  149. #define ADV7182_INPUT_CVBS_AIN2 0x01
  150. #define ADV7182_INPUT_CVBS_AIN3 0x02
  151. #define ADV7182_INPUT_CVBS_AIN4 0x03
  152. #define ADV7182_INPUT_CVBS_AIN5 0x04
  153. #define ADV7182_INPUT_CVBS_AIN6 0x05
  154. #define ADV7182_INPUT_CVBS_AIN7 0x06
  155. #define ADV7182_INPUT_CVBS_AIN8 0x07
  156. #define ADV7182_INPUT_SVIDEO_AIN1_AIN2 0x08
  157. #define ADV7182_INPUT_SVIDEO_AIN3_AIN4 0x09
  158. #define ADV7182_INPUT_SVIDEO_AIN5_AIN6 0x0a
  159. #define ADV7182_INPUT_SVIDEO_AIN7_AIN8 0x0b
  160. #define ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3 0x0c
  161. #define ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0d
  162. #define ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2 0x0e
  163. #define ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4 0x0f
  164. #define ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6 0x10
  165. #define ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8 0x11
  166. #define ADV7180_DEFAULT_CSI_I2C_ADDR 0x44
  167. #define ADV7180_DEFAULT_VPP_I2C_ADDR 0x42
  168. #define V4L2_CID_ADV_FAST_SWITCH (V4L2_CID_USER_ADV7180_BASE + 0x00)
  169. struct adv7180_state;
  170. #define ADV7180_FLAG_RESET_POWERED BIT(0)
  171. #define ADV7180_FLAG_V2 BIT(1)
  172. #define ADV7180_FLAG_MIPI_CSI2 BIT(2)
  173. #define ADV7180_FLAG_I2P BIT(3)
  174. struct adv7180_chip_info {
  175. unsigned int flags;
  176. unsigned int valid_input_mask;
  177. int (*set_std)(struct adv7180_state *st, unsigned int std);
  178. int (*select_input)(struct adv7180_state *st, unsigned int input);
  179. int (*init)(struct adv7180_state *state);
  180. };
  181. struct adv7180_state {
  182. struct v4l2_ctrl_handler ctrl_hdl;
  183. struct v4l2_subdev sd;
  184. struct media_pad pad;
  185. struct mutex mutex; /* mutual excl. when accessing chip */
  186. int irq;
  187. struct gpio_desc *pwdn_gpio;
  188. v4l2_std_id curr_norm;
  189. bool powered;
  190. bool streaming;
  191. u8 input;
  192. struct i2c_client *client;
  193. unsigned int register_page;
  194. struct i2c_client *csi_client;
  195. struct i2c_client *vpp_client;
  196. const struct adv7180_chip_info *chip_info;
  197. enum v4l2_field field;
  198. };
  199. #define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler, \
  200. struct adv7180_state, \
  201. ctrl_hdl)->sd)
  202. static int adv7180_select_page(struct adv7180_state *state, unsigned int page)
  203. {
  204. if (state->register_page != page) {
  205. i2c_smbus_write_byte_data(state->client, ADV7180_REG_CTRL,
  206. page);
  207. state->register_page = page;
  208. }
  209. return 0;
  210. }
  211. static int adv7180_write(struct adv7180_state *state, unsigned int reg,
  212. unsigned int value)
  213. {
  214. lockdep_assert_held(&state->mutex);
  215. adv7180_select_page(state, reg >> 8);
  216. return i2c_smbus_write_byte_data(state->client, reg & 0xff, value);
  217. }
  218. static int adv7180_read(struct adv7180_state *state, unsigned int reg)
  219. {
  220. lockdep_assert_held(&state->mutex);
  221. adv7180_select_page(state, reg >> 8);
  222. return i2c_smbus_read_byte_data(state->client, reg & 0xff);
  223. }
  224. static int adv7180_csi_write(struct adv7180_state *state, unsigned int reg,
  225. unsigned int value)
  226. {
  227. return i2c_smbus_write_byte_data(state->csi_client, reg, value);
  228. }
  229. static int adv7180_set_video_standard(struct adv7180_state *state,
  230. unsigned int std)
  231. {
  232. return state->chip_info->set_std(state, std);
  233. }
  234. static int adv7180_vpp_write(struct adv7180_state *state, unsigned int reg,
  235. unsigned int value)
  236. {
  237. return i2c_smbus_write_byte_data(state->vpp_client, reg, value);
  238. }
  239. static v4l2_std_id adv7180_std_to_v4l2(u8 status1)
  240. {
  241. /* in case V4L2_IN_ST_NO_SIGNAL */
  242. if (!(status1 & ADV7180_STATUS1_IN_LOCK))
  243. return V4L2_STD_UNKNOWN;
  244. switch (status1 & ADV7180_STATUS1_AUTOD_MASK) {
  245. case ADV7180_STATUS1_AUTOD_NTSM_M_J:
  246. return V4L2_STD_NTSC;
  247. case ADV7180_STATUS1_AUTOD_NTSC_4_43:
  248. return V4L2_STD_NTSC_443;
  249. case ADV7180_STATUS1_AUTOD_PAL_M:
  250. return V4L2_STD_PAL_M;
  251. case ADV7180_STATUS1_AUTOD_PAL_60:
  252. return V4L2_STD_PAL_60;
  253. case ADV7180_STATUS1_AUTOD_PAL_B_G:
  254. return V4L2_STD_PAL;
  255. case ADV7180_STATUS1_AUTOD_SECAM:
  256. return V4L2_STD_SECAM;
  257. case ADV7180_STATUS1_AUTOD_PAL_COMB:
  258. return V4L2_STD_PAL_Nc | V4L2_STD_PAL_N;
  259. case ADV7180_STATUS1_AUTOD_SECAM_525:
  260. return V4L2_STD_SECAM;
  261. default:
  262. return V4L2_STD_UNKNOWN;
  263. }
  264. }
  265. static int v4l2_std_to_adv7180(v4l2_std_id std)
  266. {
  267. if (std == V4L2_STD_PAL_60)
  268. return ADV7180_STD_PAL60;
  269. if (std == V4L2_STD_NTSC_443)
  270. return ADV7180_STD_NTSC_443;
  271. if (std == V4L2_STD_PAL_N)
  272. return ADV7180_STD_PAL_N;
  273. if (std == V4L2_STD_PAL_M)
  274. return ADV7180_STD_PAL_M;
  275. if (std == V4L2_STD_PAL_Nc)
  276. return ADV7180_STD_PAL_COMB_N;
  277. if (std & V4L2_STD_PAL)
  278. return ADV7180_STD_PAL_BG;
  279. if (std & V4L2_STD_NTSC)
  280. return ADV7180_STD_NTSC_M;
  281. if (std & V4L2_STD_SECAM)
  282. return ADV7180_STD_PAL_SECAM;
  283. return -EINVAL;
  284. }
  285. static u32 adv7180_status_to_v4l2(u8 status1)
  286. {
  287. if (!(status1 & ADV7180_STATUS1_IN_LOCK))
  288. return V4L2_IN_ST_NO_SIGNAL;
  289. return 0;
  290. }
  291. static int __adv7180_status(struct adv7180_state *state, u32 *status,
  292. v4l2_std_id *std)
  293. {
  294. int status1 = adv7180_read(state, ADV7180_REG_STATUS1);
  295. if (status1 < 0)
  296. return status1;
  297. if (status)
  298. *status = adv7180_status_to_v4l2(status1);
  299. if (std)
  300. *std = adv7180_std_to_v4l2(status1);
  301. return 0;
  302. }
  303. static inline struct adv7180_state *to_state(struct v4l2_subdev *sd)
  304. {
  305. return container_of(sd, struct adv7180_state, sd);
  306. }
  307. static int adv7180_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
  308. {
  309. struct adv7180_state *state = to_state(sd);
  310. int err = mutex_lock_interruptible(&state->mutex);
  311. if (err)
  312. return err;
  313. if (state->streaming) {
  314. err = -EBUSY;
  315. goto unlock;
  316. }
  317. err = adv7180_set_video_standard(state,
  318. ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM);
  319. if (err)
  320. goto unlock;
  321. msleep(100);
  322. __adv7180_status(state, NULL, std);
  323. err = v4l2_std_to_adv7180(state->curr_norm);
  324. if (err < 0)
  325. goto unlock;
  326. err = adv7180_set_video_standard(state, err);
  327. unlock:
  328. mutex_unlock(&state->mutex);
  329. return err;
  330. }
  331. static int adv7180_s_routing(struct v4l2_subdev *sd, u32 input,
  332. u32 output, u32 config)
  333. {
  334. struct adv7180_state *state = to_state(sd);
  335. int ret = mutex_lock_interruptible(&state->mutex);
  336. if (ret)
  337. return ret;
  338. if (input > 31 || !(BIT(input) & state->chip_info->valid_input_mask)) {
  339. ret = -EINVAL;
  340. goto out;
  341. }
  342. ret = state->chip_info->select_input(state, input);
  343. if (ret == 0)
  344. state->input = input;
  345. out:
  346. mutex_unlock(&state->mutex);
  347. return ret;
  348. }
  349. static int adv7180_g_input_status(struct v4l2_subdev *sd, u32 *status)
  350. {
  351. struct adv7180_state *state = to_state(sd);
  352. int ret = mutex_lock_interruptible(&state->mutex);
  353. if (ret)
  354. return ret;
  355. ret = __adv7180_status(state, status, NULL);
  356. mutex_unlock(&state->mutex);
  357. return ret;
  358. }
  359. static int adv7180_program_std(struct adv7180_state *state)
  360. {
  361. int ret;
  362. ret = v4l2_std_to_adv7180(state->curr_norm);
  363. if (ret < 0)
  364. return ret;
  365. ret = adv7180_set_video_standard(state, ret);
  366. if (ret < 0)
  367. return ret;
  368. return 0;
  369. }
  370. static int adv7180_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
  371. {
  372. struct adv7180_state *state = to_state(sd);
  373. int ret = mutex_lock_interruptible(&state->mutex);
  374. if (ret)
  375. return ret;
  376. /* Make sure we can support this std */
  377. ret = v4l2_std_to_adv7180(std);
  378. if (ret < 0)
  379. goto out;
  380. state->curr_norm = std;
  381. ret = adv7180_program_std(state);
  382. out:
  383. mutex_unlock(&state->mutex);
  384. return ret;
  385. }
  386. static int adv7180_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
  387. {
  388. struct adv7180_state *state = to_state(sd);
  389. *norm = state->curr_norm;
  390. return 0;
  391. }
  392. static void adv7180_set_power_pin(struct adv7180_state *state, bool on)
  393. {
  394. if (!state->pwdn_gpio)
  395. return;
  396. if (on) {
  397. gpiod_set_value_cansleep(state->pwdn_gpio, 0);
  398. usleep_range(5000, 10000);
  399. } else {
  400. gpiod_set_value_cansleep(state->pwdn_gpio, 1);
  401. }
  402. }
  403. static int adv7180_set_power(struct adv7180_state *state, bool on)
  404. {
  405. u8 val;
  406. int ret;
  407. if (on)
  408. val = ADV7180_PWR_MAN_ON;
  409. else
  410. val = ADV7180_PWR_MAN_OFF;
  411. ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val);
  412. if (ret)
  413. return ret;
  414. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  415. if (on) {
  416. adv7180_csi_write(state, 0xDE, 0x02);
  417. adv7180_csi_write(state, 0xD2, 0xF7);
  418. adv7180_csi_write(state, 0xD8, 0x65);
  419. adv7180_csi_write(state, 0xE0, 0x09);
  420. adv7180_csi_write(state, 0x2C, 0x00);
  421. if (state->field == V4L2_FIELD_NONE)
  422. adv7180_csi_write(state, 0x1D, 0x80);
  423. adv7180_csi_write(state, 0x00, 0x00);
  424. } else {
  425. adv7180_csi_write(state, 0x00, 0x80);
  426. }
  427. }
  428. return 0;
  429. }
  430. static int adv7180_s_power(struct v4l2_subdev *sd, int on)
  431. {
  432. struct adv7180_state *state = to_state(sd);
  433. int ret;
  434. ret = mutex_lock_interruptible(&state->mutex);
  435. if (ret)
  436. return ret;
  437. ret = adv7180_set_power(state, on);
  438. if (ret == 0)
  439. state->powered = on;
  440. mutex_unlock(&state->mutex);
  441. return ret;
  442. }
  443. static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl)
  444. {
  445. struct v4l2_subdev *sd = to_adv7180_sd(ctrl);
  446. struct adv7180_state *state = to_state(sd);
  447. int ret = mutex_lock_interruptible(&state->mutex);
  448. int val;
  449. if (ret)
  450. return ret;
  451. val = ctrl->val;
  452. switch (ctrl->id) {
  453. case V4L2_CID_BRIGHTNESS:
  454. ret = adv7180_write(state, ADV7180_REG_BRI, val);
  455. break;
  456. case V4L2_CID_HUE:
  457. /*Hue is inverted according to HSL chart */
  458. ret = adv7180_write(state, ADV7180_REG_HUE, -val);
  459. break;
  460. case V4L2_CID_CONTRAST:
  461. ret = adv7180_write(state, ADV7180_REG_CON, val);
  462. break;
  463. case V4L2_CID_SATURATION:
  464. /*
  465. *This could be V4L2_CID_BLUE_BALANCE/V4L2_CID_RED_BALANCE
  466. *Let's not confuse the user, everybody understands saturation
  467. */
  468. ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val);
  469. if (ret < 0)
  470. break;
  471. ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val);
  472. break;
  473. case V4L2_CID_ADV_FAST_SWITCH:
  474. if (ctrl->val) {
  475. /* ADI required write */
  476. adv7180_write(state, 0x80d9, 0x44);
  477. adv7180_write(state, ADV7180_REG_FLCONTROL,
  478. ADV7180_FLCONTROL_FL_ENABLE);
  479. } else {
  480. /* ADI required write */
  481. adv7180_write(state, 0x80d9, 0xc4);
  482. adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00);
  483. }
  484. break;
  485. default:
  486. ret = -EINVAL;
  487. }
  488. mutex_unlock(&state->mutex);
  489. return ret;
  490. }
  491. static const struct v4l2_ctrl_ops adv7180_ctrl_ops = {
  492. .s_ctrl = adv7180_s_ctrl,
  493. };
  494. static const struct v4l2_ctrl_config adv7180_ctrl_fast_switch = {
  495. .ops = &adv7180_ctrl_ops,
  496. .id = V4L2_CID_ADV_FAST_SWITCH,
  497. .name = "Fast Switching",
  498. .type = V4L2_CTRL_TYPE_BOOLEAN,
  499. .min = 0,
  500. .max = 1,
  501. .step = 1,
  502. };
  503. static int adv7180_init_controls(struct adv7180_state *state)
  504. {
  505. v4l2_ctrl_handler_init(&state->ctrl_hdl, 4);
  506. v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
  507. V4L2_CID_BRIGHTNESS, ADV7180_BRI_MIN,
  508. ADV7180_BRI_MAX, 1, ADV7180_BRI_DEF);
  509. v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
  510. V4L2_CID_CONTRAST, ADV7180_CON_MIN,
  511. ADV7180_CON_MAX, 1, ADV7180_CON_DEF);
  512. v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
  513. V4L2_CID_SATURATION, ADV7180_SAT_MIN,
  514. ADV7180_SAT_MAX, 1, ADV7180_SAT_DEF);
  515. v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
  516. V4L2_CID_HUE, ADV7180_HUE_MIN,
  517. ADV7180_HUE_MAX, 1, ADV7180_HUE_DEF);
  518. v4l2_ctrl_new_custom(&state->ctrl_hdl, &adv7180_ctrl_fast_switch, NULL);
  519. state->sd.ctrl_handler = &state->ctrl_hdl;
  520. if (state->ctrl_hdl.error) {
  521. int err = state->ctrl_hdl.error;
  522. v4l2_ctrl_handler_free(&state->ctrl_hdl);
  523. return err;
  524. }
  525. v4l2_ctrl_handler_setup(&state->ctrl_hdl);
  526. return 0;
  527. }
  528. static void adv7180_exit_controls(struct adv7180_state *state)
  529. {
  530. v4l2_ctrl_handler_free(&state->ctrl_hdl);
  531. }
  532. static int adv7180_enum_mbus_code(struct v4l2_subdev *sd,
  533. struct v4l2_subdev_pad_config *cfg,
  534. struct v4l2_subdev_mbus_code_enum *code)
  535. {
  536. if (code->index != 0)
  537. return -EINVAL;
  538. code->code = MEDIA_BUS_FMT_UYVY8_2X8;
  539. return 0;
  540. }
  541. static int adv7180_mbus_fmt(struct v4l2_subdev *sd,
  542. struct v4l2_mbus_framefmt *fmt)
  543. {
  544. struct adv7180_state *state = to_state(sd);
  545. fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
  546. fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
  547. fmt->width = 720;
  548. fmt->height = state->curr_norm & V4L2_STD_525_60 ? 480 : 576;
  549. return 0;
  550. }
  551. static int adv7180_set_field_mode(struct adv7180_state *state)
  552. {
  553. if (!(state->chip_info->flags & ADV7180_FLAG_I2P))
  554. return 0;
  555. if (state->field == V4L2_FIELD_NONE) {
  556. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  557. adv7180_csi_write(state, 0x01, 0x20);
  558. adv7180_csi_write(state, 0x02, 0x28);
  559. adv7180_csi_write(state, 0x03, 0x38);
  560. adv7180_csi_write(state, 0x04, 0x30);
  561. adv7180_csi_write(state, 0x05, 0x30);
  562. adv7180_csi_write(state, 0x06, 0x80);
  563. adv7180_csi_write(state, 0x07, 0x70);
  564. adv7180_csi_write(state, 0x08, 0x50);
  565. }
  566. adv7180_vpp_write(state, 0xa3, 0x00);
  567. adv7180_vpp_write(state, 0x5b, 0x00);
  568. adv7180_vpp_write(state, 0x55, 0x80);
  569. } else {
  570. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  571. adv7180_csi_write(state, 0x01, 0x18);
  572. adv7180_csi_write(state, 0x02, 0x18);
  573. adv7180_csi_write(state, 0x03, 0x30);
  574. adv7180_csi_write(state, 0x04, 0x20);
  575. adv7180_csi_write(state, 0x05, 0x28);
  576. adv7180_csi_write(state, 0x06, 0x40);
  577. adv7180_csi_write(state, 0x07, 0x58);
  578. adv7180_csi_write(state, 0x08, 0x30);
  579. }
  580. adv7180_vpp_write(state, 0xa3, 0x70);
  581. adv7180_vpp_write(state, 0x5b, 0x80);
  582. adv7180_vpp_write(state, 0x55, 0x00);
  583. }
  584. return 0;
  585. }
  586. static int adv7180_get_pad_format(struct v4l2_subdev *sd,
  587. struct v4l2_subdev_pad_config *cfg,
  588. struct v4l2_subdev_format *format)
  589. {
  590. struct adv7180_state *state = to_state(sd);
  591. if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
  592. format->format = *v4l2_subdev_get_try_format(sd, cfg, 0);
  593. } else {
  594. adv7180_mbus_fmt(sd, &format->format);
  595. format->format.field = state->field;
  596. }
  597. return 0;
  598. }
  599. static int adv7180_set_pad_format(struct v4l2_subdev *sd,
  600. struct v4l2_subdev_pad_config *cfg,
  601. struct v4l2_subdev_format *format)
  602. {
  603. struct adv7180_state *state = to_state(sd);
  604. struct v4l2_mbus_framefmt *framefmt;
  605. int ret;
  606. switch (format->format.field) {
  607. case V4L2_FIELD_NONE:
  608. if (!(state->chip_info->flags & ADV7180_FLAG_I2P))
  609. format->format.field = V4L2_FIELD_INTERLACED;
  610. break;
  611. default:
  612. format->format.field = V4L2_FIELD_INTERLACED;
  613. break;
  614. }
  615. ret = adv7180_mbus_fmt(sd, &format->format);
  616. if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
  617. if (state->field != format->format.field) {
  618. state->field = format->format.field;
  619. adv7180_set_power(state, false);
  620. adv7180_set_field_mode(state);
  621. adv7180_set_power(state, true);
  622. }
  623. } else {
  624. framefmt = v4l2_subdev_get_try_format(sd, cfg, 0);
  625. *framefmt = format->format;
  626. }
  627. return ret;
  628. }
  629. static int adv7180_g_mbus_config(struct v4l2_subdev *sd,
  630. struct v4l2_mbus_config *cfg)
  631. {
  632. struct adv7180_state *state = to_state(sd);
  633. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  634. cfg->type = V4L2_MBUS_CSI2;
  635. cfg->flags = V4L2_MBUS_CSI2_1_LANE |
  636. V4L2_MBUS_CSI2_CHANNEL_0 |
  637. V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
  638. } else {
  639. /*
  640. * The ADV7180 sensor supports BT.601/656 output modes.
  641. * The BT.656 is default and not yet configurable by s/w.
  642. */
  643. cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING |
  644. V4L2_MBUS_DATA_ACTIVE_HIGH;
  645. cfg->type = V4L2_MBUS_BT656;
  646. }
  647. return 0;
  648. }
  649. static int adv7180_g_pixelaspect(struct v4l2_subdev *sd, struct v4l2_fract *aspect)
  650. {
  651. struct adv7180_state *state = to_state(sd);
  652. if (state->curr_norm & V4L2_STD_525_60) {
  653. aspect->numerator = 11;
  654. aspect->denominator = 10;
  655. } else {
  656. aspect->numerator = 54;
  657. aspect->denominator = 59;
  658. }
  659. return 0;
  660. }
  661. static int adv7180_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *norm)
  662. {
  663. *norm = V4L2_STD_ALL;
  664. return 0;
  665. }
  666. static int adv7180_s_stream(struct v4l2_subdev *sd, int enable)
  667. {
  668. struct adv7180_state *state = to_state(sd);
  669. int ret;
  670. /* It's always safe to stop streaming, no need to take the lock */
  671. if (!enable) {
  672. state->streaming = enable;
  673. return 0;
  674. }
  675. /* Must wait until querystd released the lock */
  676. ret = mutex_lock_interruptible(&state->mutex);
  677. if (ret)
  678. return ret;
  679. state->streaming = enable;
  680. mutex_unlock(&state->mutex);
  681. return 0;
  682. }
  683. static int adv7180_subscribe_event(struct v4l2_subdev *sd,
  684. struct v4l2_fh *fh,
  685. struct v4l2_event_subscription *sub)
  686. {
  687. switch (sub->type) {
  688. case V4L2_EVENT_SOURCE_CHANGE:
  689. return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
  690. case V4L2_EVENT_CTRL:
  691. return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
  692. default:
  693. return -EINVAL;
  694. }
  695. }
  696. static const struct v4l2_subdev_video_ops adv7180_video_ops = {
  697. .s_std = adv7180_s_std,
  698. .g_std = adv7180_g_std,
  699. .querystd = adv7180_querystd,
  700. .g_input_status = adv7180_g_input_status,
  701. .s_routing = adv7180_s_routing,
  702. .g_mbus_config = adv7180_g_mbus_config,
  703. .g_pixelaspect = adv7180_g_pixelaspect,
  704. .g_tvnorms = adv7180_g_tvnorms,
  705. .s_stream = adv7180_s_stream,
  706. };
  707. static const struct v4l2_subdev_core_ops adv7180_core_ops = {
  708. .s_power = adv7180_s_power,
  709. .subscribe_event = adv7180_subscribe_event,
  710. .unsubscribe_event = v4l2_event_subdev_unsubscribe,
  711. };
  712. static const struct v4l2_subdev_pad_ops adv7180_pad_ops = {
  713. .enum_mbus_code = adv7180_enum_mbus_code,
  714. .set_fmt = adv7180_set_pad_format,
  715. .get_fmt = adv7180_get_pad_format,
  716. };
  717. static const struct v4l2_subdev_ops adv7180_ops = {
  718. .core = &adv7180_core_ops,
  719. .video = &adv7180_video_ops,
  720. .pad = &adv7180_pad_ops,
  721. };
  722. static irqreturn_t adv7180_irq(int irq, void *devid)
  723. {
  724. struct adv7180_state *state = devid;
  725. u8 isr3;
  726. mutex_lock(&state->mutex);
  727. isr3 = adv7180_read(state, ADV7180_REG_ISR3);
  728. /* clear */
  729. adv7180_write(state, ADV7180_REG_ICR3, isr3);
  730. if (isr3 & ADV7180_IRQ3_AD_CHANGE) {
  731. static const struct v4l2_event src_ch = {
  732. .type = V4L2_EVENT_SOURCE_CHANGE,
  733. .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
  734. };
  735. v4l2_subdev_notify_event(&state->sd, &src_ch);
  736. }
  737. mutex_unlock(&state->mutex);
  738. return IRQ_HANDLED;
  739. }
  740. static int adv7180_init(struct adv7180_state *state)
  741. {
  742. int ret;
  743. /* ITU-R BT.656-4 compatible */
  744. ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
  745. ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS);
  746. if (ret < 0)
  747. return ret;
  748. /* Manually set V bit end position in NTSC mode */
  749. return adv7180_write(state, ADV7180_REG_NTSC_V_BIT_END,
  750. ADV7180_NTSC_V_BIT_END_MANUAL_NVEND);
  751. }
  752. static int adv7180_set_std(struct adv7180_state *state, unsigned int std)
  753. {
  754. return adv7180_write(state, ADV7180_REG_INPUT_CONTROL,
  755. (std << 4) | state->input);
  756. }
  757. static int adv7180_select_input(struct adv7180_state *state, unsigned int input)
  758. {
  759. int ret;
  760. ret = adv7180_read(state, ADV7180_REG_INPUT_CONTROL);
  761. if (ret < 0)
  762. return ret;
  763. ret &= ~ADV7180_INPUT_CONTROL_INSEL_MASK;
  764. ret |= input;
  765. return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, ret);
  766. }
  767. static int adv7182_init(struct adv7180_state *state)
  768. {
  769. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
  770. adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR,
  771. ADV7180_DEFAULT_CSI_I2C_ADDR << 1);
  772. if (state->chip_info->flags & ADV7180_FLAG_I2P)
  773. adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR,
  774. ADV7180_DEFAULT_VPP_I2C_ADDR << 1);
  775. if (state->chip_info->flags & ADV7180_FLAG_V2) {
  776. /* ADI recommended writes for improved video quality */
  777. adv7180_write(state, 0x0080, 0x51);
  778. adv7180_write(state, 0x0081, 0x51);
  779. adv7180_write(state, 0x0082, 0x68);
  780. }
  781. /* ADI required writes */
  782. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  783. adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x4e);
  784. adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 0x57);
  785. adv7180_write(state, ADV7180_REG_CTRL_2, 0xc0);
  786. } else {
  787. if (state->chip_info->flags & ADV7180_FLAG_V2)
  788. adv7180_write(state,
  789. ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
  790. 0x17);
  791. else
  792. adv7180_write(state,
  793. ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
  794. 0x07);
  795. adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x0c);
  796. adv7180_write(state, ADV7180_REG_CTRL_2, 0x40);
  797. }
  798. adv7180_write(state, 0x0013, 0x00);
  799. return 0;
  800. }
  801. static int adv7182_set_std(struct adv7180_state *state, unsigned int std)
  802. {
  803. return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL, std << 4);
  804. }
  805. enum adv7182_input_type {
  806. ADV7182_INPUT_TYPE_CVBS,
  807. ADV7182_INPUT_TYPE_DIFF_CVBS,
  808. ADV7182_INPUT_TYPE_SVIDEO,
  809. ADV7182_INPUT_TYPE_YPBPR,
  810. };
  811. static enum adv7182_input_type adv7182_get_input_type(unsigned int input)
  812. {
  813. switch (input) {
  814. case ADV7182_INPUT_CVBS_AIN1:
  815. case ADV7182_INPUT_CVBS_AIN2:
  816. case ADV7182_INPUT_CVBS_AIN3:
  817. case ADV7182_INPUT_CVBS_AIN4:
  818. case ADV7182_INPUT_CVBS_AIN5:
  819. case ADV7182_INPUT_CVBS_AIN6:
  820. case ADV7182_INPUT_CVBS_AIN7:
  821. case ADV7182_INPUT_CVBS_AIN8:
  822. return ADV7182_INPUT_TYPE_CVBS;
  823. case ADV7182_INPUT_SVIDEO_AIN1_AIN2:
  824. case ADV7182_INPUT_SVIDEO_AIN3_AIN4:
  825. case ADV7182_INPUT_SVIDEO_AIN5_AIN6:
  826. case ADV7182_INPUT_SVIDEO_AIN7_AIN8:
  827. return ADV7182_INPUT_TYPE_SVIDEO;
  828. case ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3:
  829. case ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6:
  830. return ADV7182_INPUT_TYPE_YPBPR;
  831. case ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2:
  832. case ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4:
  833. case ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6:
  834. case ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8:
  835. return ADV7182_INPUT_TYPE_DIFF_CVBS;
  836. default: /* Will never happen */
  837. return 0;
  838. }
  839. }
  840. /* ADI recommended writes to registers 0x52, 0x53, 0x54 */
  841. static unsigned int adv7182_lbias_settings[][3] = {
  842. [ADV7182_INPUT_TYPE_CVBS] = { 0xCB, 0x4E, 0x80 },
  843. [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
  844. [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
  845. [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
  846. };
  847. static unsigned int adv7280_lbias_settings[][3] = {
  848. [ADV7182_INPUT_TYPE_CVBS] = { 0xCD, 0x4E, 0x80 },
  849. [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
  850. [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
  851. [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
  852. };
  853. static int adv7182_select_input(struct adv7180_state *state, unsigned int input)
  854. {
  855. enum adv7182_input_type input_type;
  856. unsigned int *lbias;
  857. unsigned int i;
  858. int ret;
  859. ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input);
  860. if (ret)
  861. return ret;
  862. /* Reset clamp circuitry - ADI recommended writes */
  863. adv7180_write(state, ADV7180_REG_RST_CLAMP, 0x00);
  864. adv7180_write(state, ADV7180_REG_RST_CLAMP, 0xff);
  865. input_type = adv7182_get_input_type(input);
  866. switch (input_type) {
  867. case ADV7182_INPUT_TYPE_CVBS:
  868. case ADV7182_INPUT_TYPE_DIFF_CVBS:
  869. /* ADI recommends to use the SH1 filter */
  870. adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x41);
  871. break;
  872. default:
  873. adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x01);
  874. break;
  875. }
  876. if (state->chip_info->flags & ADV7180_FLAG_V2)
  877. lbias = adv7280_lbias_settings[input_type];
  878. else
  879. lbias = adv7182_lbias_settings[input_type];
  880. for (i = 0; i < ARRAY_SIZE(adv7182_lbias_settings[0]); i++)
  881. adv7180_write(state, ADV7180_REG_CVBS_TRIM + i, lbias[i]);
  882. if (input_type == ADV7182_INPUT_TYPE_DIFF_CVBS) {
  883. /* ADI required writes to make differential CVBS work */
  884. adv7180_write(state, ADV7180_REG_RES_CIR, 0xa8);
  885. adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0x90);
  886. adv7180_write(state, ADV7180_REG_DIFF_MODE, 0xb0);
  887. adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x08);
  888. adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0xa0);
  889. } else {
  890. adv7180_write(state, ADV7180_REG_RES_CIR, 0xf0);
  891. adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0xd0);
  892. adv7180_write(state, ADV7180_REG_DIFF_MODE, 0x10);
  893. adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x9c);
  894. adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0x00);
  895. }
  896. return 0;
  897. }
  898. static const struct adv7180_chip_info adv7180_info = {
  899. .flags = ADV7180_FLAG_RESET_POWERED,
  900. /* We cannot discriminate between LQFP and 40-pin LFCSP, so accept
  901. * all inputs and let the card driver take care of validation
  902. */
  903. .valid_input_mask = BIT(ADV7180_INPUT_CVBS_AIN1) |
  904. BIT(ADV7180_INPUT_CVBS_AIN2) |
  905. BIT(ADV7180_INPUT_CVBS_AIN3) |
  906. BIT(ADV7180_INPUT_CVBS_AIN4) |
  907. BIT(ADV7180_INPUT_CVBS_AIN5) |
  908. BIT(ADV7180_INPUT_CVBS_AIN6) |
  909. BIT(ADV7180_INPUT_SVIDEO_AIN1_AIN2) |
  910. BIT(ADV7180_INPUT_SVIDEO_AIN3_AIN4) |
  911. BIT(ADV7180_INPUT_SVIDEO_AIN5_AIN6) |
  912. BIT(ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3) |
  913. BIT(ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6),
  914. .init = adv7180_init,
  915. .set_std = adv7180_set_std,
  916. .select_input = adv7180_select_input,
  917. };
  918. static const struct adv7180_chip_info adv7182_info = {
  919. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  920. BIT(ADV7182_INPUT_CVBS_AIN2) |
  921. BIT(ADV7182_INPUT_CVBS_AIN3) |
  922. BIT(ADV7182_INPUT_CVBS_AIN4) |
  923. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  924. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  925. BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
  926. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  927. BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4),
  928. .init = adv7182_init,
  929. .set_std = adv7182_set_std,
  930. .select_input = adv7182_select_input,
  931. };
  932. static const struct adv7180_chip_info adv7280_info = {
  933. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P,
  934. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  935. BIT(ADV7182_INPUT_CVBS_AIN2) |
  936. BIT(ADV7182_INPUT_CVBS_AIN3) |
  937. BIT(ADV7182_INPUT_CVBS_AIN4) |
  938. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  939. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  940. BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3),
  941. .init = adv7182_init,
  942. .set_std = adv7182_set_std,
  943. .select_input = adv7182_select_input,
  944. };
  945. static const struct adv7180_chip_info adv7280_m_info = {
  946. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P,
  947. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  948. BIT(ADV7182_INPUT_CVBS_AIN2) |
  949. BIT(ADV7182_INPUT_CVBS_AIN3) |
  950. BIT(ADV7182_INPUT_CVBS_AIN4) |
  951. BIT(ADV7182_INPUT_CVBS_AIN5) |
  952. BIT(ADV7182_INPUT_CVBS_AIN6) |
  953. BIT(ADV7182_INPUT_CVBS_AIN7) |
  954. BIT(ADV7182_INPUT_CVBS_AIN8) |
  955. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  956. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  957. BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
  958. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  959. BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
  960. BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6),
  961. .init = adv7182_init,
  962. .set_std = adv7182_set_std,
  963. .select_input = adv7182_select_input,
  964. };
  965. static const struct adv7180_chip_info adv7281_info = {
  966. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
  967. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  968. BIT(ADV7182_INPUT_CVBS_AIN2) |
  969. BIT(ADV7182_INPUT_CVBS_AIN7) |
  970. BIT(ADV7182_INPUT_CVBS_AIN8) |
  971. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  972. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  973. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  974. BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
  975. .init = adv7182_init,
  976. .set_std = adv7182_set_std,
  977. .select_input = adv7182_select_input,
  978. };
  979. static const struct adv7180_chip_info adv7281_m_info = {
  980. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
  981. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  982. BIT(ADV7182_INPUT_CVBS_AIN2) |
  983. BIT(ADV7182_INPUT_CVBS_AIN3) |
  984. BIT(ADV7182_INPUT_CVBS_AIN4) |
  985. BIT(ADV7182_INPUT_CVBS_AIN7) |
  986. BIT(ADV7182_INPUT_CVBS_AIN8) |
  987. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  988. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  989. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  990. BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
  991. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  992. BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
  993. BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
  994. .init = adv7182_init,
  995. .set_std = adv7182_set_std,
  996. .select_input = adv7182_select_input,
  997. };
  998. static const struct adv7180_chip_info adv7281_ma_info = {
  999. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
  1000. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  1001. BIT(ADV7182_INPUT_CVBS_AIN2) |
  1002. BIT(ADV7182_INPUT_CVBS_AIN3) |
  1003. BIT(ADV7182_INPUT_CVBS_AIN4) |
  1004. BIT(ADV7182_INPUT_CVBS_AIN5) |
  1005. BIT(ADV7182_INPUT_CVBS_AIN6) |
  1006. BIT(ADV7182_INPUT_CVBS_AIN7) |
  1007. BIT(ADV7182_INPUT_CVBS_AIN8) |
  1008. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  1009. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  1010. BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
  1011. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  1012. BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
  1013. BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6) |
  1014. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  1015. BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
  1016. BIT(ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6) |
  1017. BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
  1018. .init = adv7182_init,
  1019. .set_std = adv7182_set_std,
  1020. .select_input = adv7182_select_input,
  1021. };
  1022. static const struct adv7180_chip_info adv7282_info = {
  1023. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P,
  1024. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  1025. BIT(ADV7182_INPUT_CVBS_AIN2) |
  1026. BIT(ADV7182_INPUT_CVBS_AIN7) |
  1027. BIT(ADV7182_INPUT_CVBS_AIN8) |
  1028. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  1029. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  1030. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  1031. BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
  1032. .init = adv7182_init,
  1033. .set_std = adv7182_set_std,
  1034. .select_input = adv7182_select_input,
  1035. };
  1036. static const struct adv7180_chip_info adv7282_m_info = {
  1037. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P,
  1038. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  1039. BIT(ADV7182_INPUT_CVBS_AIN2) |
  1040. BIT(ADV7182_INPUT_CVBS_AIN3) |
  1041. BIT(ADV7182_INPUT_CVBS_AIN4) |
  1042. BIT(ADV7182_INPUT_CVBS_AIN7) |
  1043. BIT(ADV7182_INPUT_CVBS_AIN8) |
  1044. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  1045. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  1046. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  1047. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  1048. BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
  1049. BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
  1050. .init = adv7182_init,
  1051. .set_std = adv7182_set_std,
  1052. .select_input = adv7182_select_input,
  1053. };
  1054. static int init_device(struct adv7180_state *state)
  1055. {
  1056. int ret;
  1057. mutex_lock(&state->mutex);
  1058. adv7180_set_power_pin(state, true);
  1059. adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES);
  1060. usleep_range(5000, 10000);
  1061. ret = state->chip_info->init(state);
  1062. if (ret)
  1063. goto out_unlock;
  1064. ret = adv7180_program_std(state);
  1065. if (ret)
  1066. goto out_unlock;
  1067. adv7180_set_field_mode(state);
  1068. /* register for interrupts */
  1069. if (state->irq > 0) {
  1070. /* config the Interrupt pin to be active low */
  1071. ret = adv7180_write(state, ADV7180_REG_ICONF1,
  1072. ADV7180_ICONF1_ACTIVE_LOW |
  1073. ADV7180_ICONF1_PSYNC_ONLY);
  1074. if (ret < 0)
  1075. goto out_unlock;
  1076. ret = adv7180_write(state, ADV7180_REG_IMR1, 0);
  1077. if (ret < 0)
  1078. goto out_unlock;
  1079. ret = adv7180_write(state, ADV7180_REG_IMR2, 0);
  1080. if (ret < 0)
  1081. goto out_unlock;
  1082. /* enable AD change interrupts interrupts */
  1083. ret = adv7180_write(state, ADV7180_REG_IMR3,
  1084. ADV7180_IRQ3_AD_CHANGE);
  1085. if (ret < 0)
  1086. goto out_unlock;
  1087. ret = adv7180_write(state, ADV7180_REG_IMR4, 0);
  1088. if (ret < 0)
  1089. goto out_unlock;
  1090. }
  1091. out_unlock:
  1092. mutex_unlock(&state->mutex);
  1093. return ret;
  1094. }
  1095. static int adv7180_probe(struct i2c_client *client,
  1096. const struct i2c_device_id *id)
  1097. {
  1098. struct adv7180_state *state;
  1099. struct v4l2_subdev *sd;
  1100. int ret;
  1101. /* Check if the adapter supports the needed features */
  1102. if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
  1103. return -EIO;
  1104. v4l_info(client, "chip found @ 0x%02x (%s)\n",
  1105. client->addr, client->adapter->name);
  1106. state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
  1107. if (state == NULL)
  1108. return -ENOMEM;
  1109. state->client = client;
  1110. state->field = V4L2_FIELD_INTERLACED;
  1111. state->chip_info = (struct adv7180_chip_info *)id->driver_data;
  1112. state->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown",
  1113. GPIOD_OUT_HIGH);
  1114. if (IS_ERR(state->pwdn_gpio)) {
  1115. ret = PTR_ERR(state->pwdn_gpio);
  1116. v4l_err(client, "request for power pin failed: %d\n", ret);
  1117. return ret;
  1118. }
  1119. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  1120. state->csi_client = i2c_new_dummy(client->adapter,
  1121. ADV7180_DEFAULT_CSI_I2C_ADDR);
  1122. if (!state->csi_client)
  1123. return -ENOMEM;
  1124. }
  1125. if (state->chip_info->flags & ADV7180_FLAG_I2P) {
  1126. state->vpp_client = i2c_new_dummy(client->adapter,
  1127. ADV7180_DEFAULT_VPP_I2C_ADDR);
  1128. if (!state->vpp_client) {
  1129. ret = -ENOMEM;
  1130. goto err_unregister_csi_client;
  1131. }
  1132. }
  1133. state->irq = client->irq;
  1134. mutex_init(&state->mutex);
  1135. state->curr_norm = V4L2_STD_NTSC;
  1136. if (state->chip_info->flags & ADV7180_FLAG_RESET_POWERED)
  1137. state->powered = true;
  1138. else
  1139. state->powered = false;
  1140. state->input = 0;
  1141. sd = &state->sd;
  1142. v4l2_i2c_subdev_init(sd, client, &adv7180_ops);
  1143. sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
  1144. ret = adv7180_init_controls(state);
  1145. if (ret)
  1146. goto err_unregister_vpp_client;
  1147. state->pad.flags = MEDIA_PAD_FL_SOURCE;
  1148. sd->entity.flags |= MEDIA_ENT_F_ATV_DECODER;
  1149. ret = media_entity_pads_init(&sd->entity, 1, &state->pad);
  1150. if (ret)
  1151. goto err_free_ctrl;
  1152. ret = init_device(state);
  1153. if (ret)
  1154. goto err_media_entity_cleanup;
  1155. if (state->irq) {
  1156. ret = request_threaded_irq(client->irq, NULL, adv7180_irq,
  1157. IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
  1158. KBUILD_MODNAME, state);
  1159. if (ret)
  1160. goto err_media_entity_cleanup;
  1161. }
  1162. ret = v4l2_async_register_subdev(sd);
  1163. if (ret)
  1164. goto err_free_irq;
  1165. return 0;
  1166. err_free_irq:
  1167. if (state->irq > 0)
  1168. free_irq(client->irq, state);
  1169. err_media_entity_cleanup:
  1170. media_entity_cleanup(&sd->entity);
  1171. err_free_ctrl:
  1172. adv7180_exit_controls(state);
  1173. err_unregister_vpp_client:
  1174. if (state->chip_info->flags & ADV7180_FLAG_I2P)
  1175. i2c_unregister_device(state->vpp_client);
  1176. err_unregister_csi_client:
  1177. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
  1178. i2c_unregister_device(state->csi_client);
  1179. mutex_destroy(&state->mutex);
  1180. return ret;
  1181. }
  1182. static int adv7180_remove(struct i2c_client *client)
  1183. {
  1184. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1185. struct adv7180_state *state = to_state(sd);
  1186. v4l2_async_unregister_subdev(sd);
  1187. if (state->irq > 0)
  1188. free_irq(client->irq, state);
  1189. media_entity_cleanup(&sd->entity);
  1190. adv7180_exit_controls(state);
  1191. if (state->chip_info->flags & ADV7180_FLAG_I2P)
  1192. i2c_unregister_device(state->vpp_client);
  1193. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
  1194. i2c_unregister_device(state->csi_client);
  1195. adv7180_set_power_pin(state, false);
  1196. mutex_destroy(&state->mutex);
  1197. return 0;
  1198. }
  1199. static const struct i2c_device_id adv7180_id[] = {
  1200. { "adv7180", (kernel_ulong_t)&adv7180_info },
  1201. { "adv7182", (kernel_ulong_t)&adv7182_info },
  1202. { "adv7280", (kernel_ulong_t)&adv7280_info },
  1203. { "adv7280-m", (kernel_ulong_t)&adv7280_m_info },
  1204. { "adv7281", (kernel_ulong_t)&adv7281_info },
  1205. { "adv7281-m", (kernel_ulong_t)&adv7281_m_info },
  1206. { "adv7281-ma", (kernel_ulong_t)&adv7281_ma_info },
  1207. { "adv7282", (kernel_ulong_t)&adv7282_info },
  1208. { "adv7282-m", (kernel_ulong_t)&adv7282_m_info },
  1209. {},
  1210. };
  1211. MODULE_DEVICE_TABLE(i2c, adv7180_id);
  1212. #ifdef CONFIG_PM_SLEEP
  1213. static int adv7180_suspend(struct device *dev)
  1214. {
  1215. struct i2c_client *client = to_i2c_client(dev);
  1216. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1217. struct adv7180_state *state = to_state(sd);
  1218. return adv7180_set_power(state, false);
  1219. }
  1220. static int adv7180_resume(struct device *dev)
  1221. {
  1222. struct i2c_client *client = to_i2c_client(dev);
  1223. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1224. struct adv7180_state *state = to_state(sd);
  1225. int ret;
  1226. ret = init_device(state);
  1227. if (ret < 0)
  1228. return ret;
  1229. ret = adv7180_set_power(state, state->powered);
  1230. if (ret)
  1231. return ret;
  1232. return 0;
  1233. }
  1234. static SIMPLE_DEV_PM_OPS(adv7180_pm_ops, adv7180_suspend, adv7180_resume);
  1235. #define ADV7180_PM_OPS (&adv7180_pm_ops)
  1236. #else
  1237. #define ADV7180_PM_OPS NULL
  1238. #endif
  1239. #ifdef CONFIG_OF
  1240. static const struct of_device_id adv7180_of_id[] = {
  1241. { .compatible = "adi,adv7180", },
  1242. { .compatible = "adi,adv7182", },
  1243. { .compatible = "adi,adv7280", },
  1244. { .compatible = "adi,adv7280-m", },
  1245. { .compatible = "adi,adv7281", },
  1246. { .compatible = "adi,adv7281-m", },
  1247. { .compatible = "adi,adv7281-ma", },
  1248. { .compatible = "adi,adv7282", },
  1249. { .compatible = "adi,adv7282-m", },
  1250. { },
  1251. };
  1252. MODULE_DEVICE_TABLE(of, adv7180_of_id);
  1253. #endif
  1254. static struct i2c_driver adv7180_driver = {
  1255. .driver = {
  1256. .name = KBUILD_MODNAME,
  1257. .pm = ADV7180_PM_OPS,
  1258. .of_match_table = of_match_ptr(adv7180_of_id),
  1259. },
  1260. .probe = adv7180_probe,
  1261. .remove = adv7180_remove,
  1262. .id_table = adv7180_id,
  1263. };
  1264. module_i2c_driver(adv7180_driver);
  1265. MODULE_DESCRIPTION("Analog Devices ADV7180 video decoder driver");
  1266. MODULE_AUTHOR("Mocean Laboratories");
  1267. MODULE_LICENSE("GPL v2");