rxe_req.c 19 KB

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  1. /*
  2. * Copyright (c) 2016 Mellanox Technologies Ltd. All rights reserved.
  3. * Copyright (c) 2015 System Fabric Works, Inc. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/skbuff.h>
  34. #include <crypto/hash.h>
  35. #include "rxe.h"
  36. #include "rxe_loc.h"
  37. #include "rxe_queue.h"
  38. static int next_opcode(struct rxe_qp *qp, struct rxe_send_wqe *wqe,
  39. u32 opcode);
  40. static inline void retry_first_write_send(struct rxe_qp *qp,
  41. struct rxe_send_wqe *wqe,
  42. unsigned mask, int npsn)
  43. {
  44. int i;
  45. for (i = 0; i < npsn; i++) {
  46. int to_send = (wqe->dma.resid > qp->mtu) ?
  47. qp->mtu : wqe->dma.resid;
  48. qp->req.opcode = next_opcode(qp, wqe,
  49. wqe->wr.opcode);
  50. if (wqe->wr.send_flags & IB_SEND_INLINE) {
  51. wqe->dma.resid -= to_send;
  52. wqe->dma.sge_offset += to_send;
  53. } else {
  54. advance_dma_data(&wqe->dma, to_send);
  55. }
  56. if (mask & WR_WRITE_MASK)
  57. wqe->iova += qp->mtu;
  58. }
  59. }
  60. static void req_retry(struct rxe_qp *qp)
  61. {
  62. struct rxe_send_wqe *wqe;
  63. unsigned int wqe_index;
  64. unsigned int mask;
  65. int npsn;
  66. int first = 1;
  67. wqe = queue_head(qp->sq.queue);
  68. npsn = (qp->comp.psn - wqe->first_psn) & BTH_PSN_MASK;
  69. qp->req.wqe_index = consumer_index(qp->sq.queue);
  70. qp->req.psn = qp->comp.psn;
  71. qp->req.opcode = -1;
  72. for (wqe_index = consumer_index(qp->sq.queue);
  73. wqe_index != producer_index(qp->sq.queue);
  74. wqe_index = next_index(qp->sq.queue, wqe_index)) {
  75. wqe = addr_from_index(qp->sq.queue, wqe_index);
  76. mask = wr_opcode_mask(wqe->wr.opcode, qp);
  77. if (wqe->state == wqe_state_posted)
  78. break;
  79. if (wqe->state == wqe_state_done)
  80. continue;
  81. wqe->iova = (mask & WR_ATOMIC_MASK) ?
  82. wqe->wr.wr.atomic.remote_addr :
  83. (mask & WR_READ_OR_WRITE_MASK) ?
  84. wqe->wr.wr.rdma.remote_addr :
  85. 0;
  86. if (!first || (mask & WR_READ_MASK) == 0) {
  87. wqe->dma.resid = wqe->dma.length;
  88. wqe->dma.cur_sge = 0;
  89. wqe->dma.sge_offset = 0;
  90. }
  91. if (first) {
  92. first = 0;
  93. if (mask & WR_WRITE_OR_SEND_MASK)
  94. retry_first_write_send(qp, wqe, mask, npsn);
  95. if (mask & WR_READ_MASK)
  96. wqe->iova += npsn * qp->mtu;
  97. }
  98. wqe->state = wqe_state_posted;
  99. }
  100. }
  101. void rnr_nak_timer(unsigned long data)
  102. {
  103. struct rxe_qp *qp = (struct rxe_qp *)data;
  104. pr_debug("qp#%d rnr nak timer fired\n", qp_num(qp));
  105. rxe_run_task(&qp->req.task, 1);
  106. }
  107. static struct rxe_send_wqe *req_next_wqe(struct rxe_qp *qp)
  108. {
  109. struct rxe_send_wqe *wqe = queue_head(qp->sq.queue);
  110. unsigned long flags;
  111. if (unlikely(qp->req.state == QP_STATE_DRAIN)) {
  112. /* check to see if we are drained;
  113. * state_lock used by requester and completer
  114. */
  115. spin_lock_irqsave(&qp->state_lock, flags);
  116. do {
  117. if (qp->req.state != QP_STATE_DRAIN) {
  118. /* comp just finished */
  119. spin_unlock_irqrestore(&qp->state_lock,
  120. flags);
  121. break;
  122. }
  123. if (wqe && ((qp->req.wqe_index !=
  124. consumer_index(qp->sq.queue)) ||
  125. (wqe->state != wqe_state_posted))) {
  126. /* comp not done yet */
  127. spin_unlock_irqrestore(&qp->state_lock,
  128. flags);
  129. break;
  130. }
  131. qp->req.state = QP_STATE_DRAINED;
  132. spin_unlock_irqrestore(&qp->state_lock, flags);
  133. if (qp->ibqp.event_handler) {
  134. struct ib_event ev;
  135. ev.device = qp->ibqp.device;
  136. ev.element.qp = &qp->ibqp;
  137. ev.event = IB_EVENT_SQ_DRAINED;
  138. qp->ibqp.event_handler(&ev,
  139. qp->ibqp.qp_context);
  140. }
  141. } while (0);
  142. }
  143. if (qp->req.wqe_index == producer_index(qp->sq.queue))
  144. return NULL;
  145. wqe = addr_from_index(qp->sq.queue, qp->req.wqe_index);
  146. if (unlikely((qp->req.state == QP_STATE_DRAIN ||
  147. qp->req.state == QP_STATE_DRAINED) &&
  148. (wqe->state != wqe_state_processing)))
  149. return NULL;
  150. if (unlikely((wqe->wr.send_flags & IB_SEND_FENCE) &&
  151. (qp->req.wqe_index != consumer_index(qp->sq.queue)))) {
  152. qp->req.wait_fence = 1;
  153. return NULL;
  154. }
  155. wqe->mask = wr_opcode_mask(wqe->wr.opcode, qp);
  156. return wqe;
  157. }
  158. static int next_opcode_rc(struct rxe_qp *qp, u32 opcode, int fits)
  159. {
  160. switch (opcode) {
  161. case IB_WR_RDMA_WRITE:
  162. if (qp->req.opcode == IB_OPCODE_RC_RDMA_WRITE_FIRST ||
  163. qp->req.opcode == IB_OPCODE_RC_RDMA_WRITE_MIDDLE)
  164. return fits ?
  165. IB_OPCODE_RC_RDMA_WRITE_LAST :
  166. IB_OPCODE_RC_RDMA_WRITE_MIDDLE;
  167. else
  168. return fits ?
  169. IB_OPCODE_RC_RDMA_WRITE_ONLY :
  170. IB_OPCODE_RC_RDMA_WRITE_FIRST;
  171. case IB_WR_RDMA_WRITE_WITH_IMM:
  172. if (qp->req.opcode == IB_OPCODE_RC_RDMA_WRITE_FIRST ||
  173. qp->req.opcode == IB_OPCODE_RC_RDMA_WRITE_MIDDLE)
  174. return fits ?
  175. IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE :
  176. IB_OPCODE_RC_RDMA_WRITE_MIDDLE;
  177. else
  178. return fits ?
  179. IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE :
  180. IB_OPCODE_RC_RDMA_WRITE_FIRST;
  181. case IB_WR_SEND:
  182. if (qp->req.opcode == IB_OPCODE_RC_SEND_FIRST ||
  183. qp->req.opcode == IB_OPCODE_RC_SEND_MIDDLE)
  184. return fits ?
  185. IB_OPCODE_RC_SEND_LAST :
  186. IB_OPCODE_RC_SEND_MIDDLE;
  187. else
  188. return fits ?
  189. IB_OPCODE_RC_SEND_ONLY :
  190. IB_OPCODE_RC_SEND_FIRST;
  191. case IB_WR_SEND_WITH_IMM:
  192. if (qp->req.opcode == IB_OPCODE_RC_SEND_FIRST ||
  193. qp->req.opcode == IB_OPCODE_RC_SEND_MIDDLE)
  194. return fits ?
  195. IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE :
  196. IB_OPCODE_RC_SEND_MIDDLE;
  197. else
  198. return fits ?
  199. IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE :
  200. IB_OPCODE_RC_SEND_FIRST;
  201. case IB_WR_RDMA_READ:
  202. return IB_OPCODE_RC_RDMA_READ_REQUEST;
  203. case IB_WR_ATOMIC_CMP_AND_SWP:
  204. return IB_OPCODE_RC_COMPARE_SWAP;
  205. case IB_WR_ATOMIC_FETCH_AND_ADD:
  206. return IB_OPCODE_RC_FETCH_ADD;
  207. case IB_WR_SEND_WITH_INV:
  208. if (qp->req.opcode == IB_OPCODE_RC_SEND_FIRST ||
  209. qp->req.opcode == IB_OPCODE_RC_SEND_MIDDLE)
  210. return fits ? IB_OPCODE_RC_SEND_LAST_WITH_INVALIDATE :
  211. IB_OPCODE_RC_SEND_MIDDLE;
  212. else
  213. return fits ? IB_OPCODE_RC_SEND_ONLY_WITH_INVALIDATE :
  214. IB_OPCODE_RC_SEND_FIRST;
  215. case IB_WR_REG_MR:
  216. case IB_WR_LOCAL_INV:
  217. return opcode;
  218. }
  219. return -EINVAL;
  220. }
  221. static int next_opcode_uc(struct rxe_qp *qp, u32 opcode, int fits)
  222. {
  223. switch (opcode) {
  224. case IB_WR_RDMA_WRITE:
  225. if (qp->req.opcode == IB_OPCODE_UC_RDMA_WRITE_FIRST ||
  226. qp->req.opcode == IB_OPCODE_UC_RDMA_WRITE_MIDDLE)
  227. return fits ?
  228. IB_OPCODE_UC_RDMA_WRITE_LAST :
  229. IB_OPCODE_UC_RDMA_WRITE_MIDDLE;
  230. else
  231. return fits ?
  232. IB_OPCODE_UC_RDMA_WRITE_ONLY :
  233. IB_OPCODE_UC_RDMA_WRITE_FIRST;
  234. case IB_WR_RDMA_WRITE_WITH_IMM:
  235. if (qp->req.opcode == IB_OPCODE_UC_RDMA_WRITE_FIRST ||
  236. qp->req.opcode == IB_OPCODE_UC_RDMA_WRITE_MIDDLE)
  237. return fits ?
  238. IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE :
  239. IB_OPCODE_UC_RDMA_WRITE_MIDDLE;
  240. else
  241. return fits ?
  242. IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE :
  243. IB_OPCODE_UC_RDMA_WRITE_FIRST;
  244. case IB_WR_SEND:
  245. if (qp->req.opcode == IB_OPCODE_UC_SEND_FIRST ||
  246. qp->req.opcode == IB_OPCODE_UC_SEND_MIDDLE)
  247. return fits ?
  248. IB_OPCODE_UC_SEND_LAST :
  249. IB_OPCODE_UC_SEND_MIDDLE;
  250. else
  251. return fits ?
  252. IB_OPCODE_UC_SEND_ONLY :
  253. IB_OPCODE_UC_SEND_FIRST;
  254. case IB_WR_SEND_WITH_IMM:
  255. if (qp->req.opcode == IB_OPCODE_UC_SEND_FIRST ||
  256. qp->req.opcode == IB_OPCODE_UC_SEND_MIDDLE)
  257. return fits ?
  258. IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE :
  259. IB_OPCODE_UC_SEND_MIDDLE;
  260. else
  261. return fits ?
  262. IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE :
  263. IB_OPCODE_UC_SEND_FIRST;
  264. }
  265. return -EINVAL;
  266. }
  267. static int next_opcode(struct rxe_qp *qp, struct rxe_send_wqe *wqe,
  268. u32 opcode)
  269. {
  270. int fits = (wqe->dma.resid <= qp->mtu);
  271. switch (qp_type(qp)) {
  272. case IB_QPT_RC:
  273. return next_opcode_rc(qp, opcode, fits);
  274. case IB_QPT_UC:
  275. return next_opcode_uc(qp, opcode, fits);
  276. case IB_QPT_SMI:
  277. case IB_QPT_UD:
  278. case IB_QPT_GSI:
  279. switch (opcode) {
  280. case IB_WR_SEND:
  281. return IB_OPCODE_UD_SEND_ONLY;
  282. case IB_WR_SEND_WITH_IMM:
  283. return IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
  284. }
  285. break;
  286. default:
  287. break;
  288. }
  289. return -EINVAL;
  290. }
  291. static inline int check_init_depth(struct rxe_qp *qp, struct rxe_send_wqe *wqe)
  292. {
  293. int depth;
  294. if (wqe->has_rd_atomic)
  295. return 0;
  296. qp->req.need_rd_atomic = 1;
  297. depth = atomic_dec_return(&qp->req.rd_atomic);
  298. if (depth >= 0) {
  299. qp->req.need_rd_atomic = 0;
  300. wqe->has_rd_atomic = 1;
  301. return 0;
  302. }
  303. atomic_inc(&qp->req.rd_atomic);
  304. return -EAGAIN;
  305. }
  306. static inline int get_mtu(struct rxe_qp *qp)
  307. {
  308. struct rxe_dev *rxe = to_rdev(qp->ibqp.device);
  309. if ((qp_type(qp) == IB_QPT_RC) || (qp_type(qp) == IB_QPT_UC))
  310. return qp->mtu;
  311. return rxe->port.mtu_cap;
  312. }
  313. static struct sk_buff *init_req_packet(struct rxe_qp *qp,
  314. struct rxe_send_wqe *wqe,
  315. int opcode, int payload,
  316. struct rxe_pkt_info *pkt)
  317. {
  318. struct rxe_dev *rxe = to_rdev(qp->ibqp.device);
  319. struct rxe_port *port = &rxe->port;
  320. struct sk_buff *skb;
  321. struct rxe_send_wr *ibwr = &wqe->wr;
  322. struct rxe_av *av;
  323. int pad = (-payload) & 0x3;
  324. int paylen;
  325. int solicited;
  326. u16 pkey;
  327. u32 qp_num;
  328. int ack_req;
  329. /* length from start of bth to end of icrc */
  330. paylen = rxe_opcode[opcode].length + payload + pad + RXE_ICRC_SIZE;
  331. /* pkt->hdr, rxe, port_num and mask are initialized in ifc
  332. * layer
  333. */
  334. pkt->opcode = opcode;
  335. pkt->qp = qp;
  336. pkt->psn = qp->req.psn;
  337. pkt->mask = rxe_opcode[opcode].mask;
  338. pkt->paylen = paylen;
  339. pkt->offset = 0;
  340. pkt->wqe = wqe;
  341. /* init skb */
  342. av = rxe_get_av(pkt);
  343. skb = rxe_init_packet(rxe, av, paylen, pkt);
  344. if (unlikely(!skb))
  345. return NULL;
  346. /* init bth */
  347. solicited = (ibwr->send_flags & IB_SEND_SOLICITED) &&
  348. (pkt->mask & RXE_END_MASK) &&
  349. ((pkt->mask & (RXE_SEND_MASK)) ||
  350. (pkt->mask & (RXE_WRITE_MASK | RXE_IMMDT_MASK)) ==
  351. (RXE_WRITE_MASK | RXE_IMMDT_MASK));
  352. pkey = (qp_type(qp) == IB_QPT_GSI) ?
  353. port->pkey_tbl[ibwr->wr.ud.pkey_index] :
  354. port->pkey_tbl[qp->attr.pkey_index];
  355. qp_num = (pkt->mask & RXE_DETH_MASK) ? ibwr->wr.ud.remote_qpn :
  356. qp->attr.dest_qp_num;
  357. ack_req = ((pkt->mask & RXE_END_MASK) ||
  358. (qp->req.noack_pkts++ > RXE_MAX_PKT_PER_ACK));
  359. if (ack_req)
  360. qp->req.noack_pkts = 0;
  361. bth_init(pkt, pkt->opcode, solicited, 0, pad, pkey, qp_num,
  362. ack_req, pkt->psn);
  363. /* init optional headers */
  364. if (pkt->mask & RXE_RETH_MASK) {
  365. reth_set_rkey(pkt, ibwr->wr.rdma.rkey);
  366. reth_set_va(pkt, wqe->iova);
  367. reth_set_len(pkt, wqe->dma.length);
  368. }
  369. if (pkt->mask & RXE_IMMDT_MASK)
  370. immdt_set_imm(pkt, ibwr->ex.imm_data);
  371. if (pkt->mask & RXE_IETH_MASK)
  372. ieth_set_rkey(pkt, ibwr->ex.invalidate_rkey);
  373. if (pkt->mask & RXE_ATMETH_MASK) {
  374. atmeth_set_va(pkt, wqe->iova);
  375. if (opcode == IB_OPCODE_RC_COMPARE_SWAP ||
  376. opcode == IB_OPCODE_RD_COMPARE_SWAP) {
  377. atmeth_set_swap_add(pkt, ibwr->wr.atomic.swap);
  378. atmeth_set_comp(pkt, ibwr->wr.atomic.compare_add);
  379. } else {
  380. atmeth_set_swap_add(pkt, ibwr->wr.atomic.compare_add);
  381. }
  382. atmeth_set_rkey(pkt, ibwr->wr.atomic.rkey);
  383. }
  384. if (pkt->mask & RXE_DETH_MASK) {
  385. if (qp->ibqp.qp_num == 1)
  386. deth_set_qkey(pkt, GSI_QKEY);
  387. else
  388. deth_set_qkey(pkt, ibwr->wr.ud.remote_qkey);
  389. deth_set_sqp(pkt, qp->ibqp.qp_num);
  390. }
  391. return skb;
  392. }
  393. static int fill_packet(struct rxe_qp *qp, struct rxe_send_wqe *wqe,
  394. struct rxe_pkt_info *pkt, struct sk_buff *skb,
  395. int paylen)
  396. {
  397. struct rxe_dev *rxe = to_rdev(qp->ibqp.device);
  398. u32 crc = 0;
  399. u32 *p;
  400. int err;
  401. err = rxe_prepare(rxe, pkt, skb, &crc);
  402. if (err)
  403. return err;
  404. if (pkt->mask & RXE_WRITE_OR_SEND) {
  405. if (wqe->wr.send_flags & IB_SEND_INLINE) {
  406. u8 *tmp = &wqe->dma.inline_data[wqe->dma.sge_offset];
  407. crc = rxe_crc32(rxe, crc, tmp, paylen);
  408. memcpy(payload_addr(pkt), tmp, paylen);
  409. wqe->dma.resid -= paylen;
  410. wqe->dma.sge_offset += paylen;
  411. } else {
  412. err = copy_data(rxe, qp->pd, 0, &wqe->dma,
  413. payload_addr(pkt), paylen,
  414. from_mem_obj,
  415. &crc);
  416. if (err)
  417. return err;
  418. }
  419. }
  420. p = payload_addr(pkt) + paylen + bth_pad(pkt);
  421. *p = ~crc;
  422. return 0;
  423. }
  424. static void update_wqe_state(struct rxe_qp *qp,
  425. struct rxe_send_wqe *wqe,
  426. struct rxe_pkt_info *pkt)
  427. {
  428. if (pkt->mask & RXE_END_MASK) {
  429. if (qp_type(qp) == IB_QPT_RC)
  430. wqe->state = wqe_state_pending;
  431. } else {
  432. wqe->state = wqe_state_processing;
  433. }
  434. }
  435. static void update_wqe_psn(struct rxe_qp *qp,
  436. struct rxe_send_wqe *wqe,
  437. struct rxe_pkt_info *pkt,
  438. int payload)
  439. {
  440. /* number of packets left to send including current one */
  441. int num_pkt = (wqe->dma.resid + payload + qp->mtu - 1) / qp->mtu;
  442. /* handle zero length packet case */
  443. if (num_pkt == 0)
  444. num_pkt = 1;
  445. if (pkt->mask & RXE_START_MASK) {
  446. wqe->first_psn = qp->req.psn;
  447. wqe->last_psn = (qp->req.psn + num_pkt - 1) & BTH_PSN_MASK;
  448. }
  449. if (pkt->mask & RXE_READ_MASK)
  450. qp->req.psn = (wqe->first_psn + num_pkt) & BTH_PSN_MASK;
  451. else
  452. qp->req.psn = (qp->req.psn + 1) & BTH_PSN_MASK;
  453. }
  454. static void save_state(struct rxe_send_wqe *wqe,
  455. struct rxe_qp *qp,
  456. struct rxe_send_wqe *rollback_wqe,
  457. u32 *rollback_psn)
  458. {
  459. rollback_wqe->state = wqe->state;
  460. rollback_wqe->first_psn = wqe->first_psn;
  461. rollback_wqe->last_psn = wqe->last_psn;
  462. *rollback_psn = qp->req.psn;
  463. }
  464. static void rollback_state(struct rxe_send_wqe *wqe,
  465. struct rxe_qp *qp,
  466. struct rxe_send_wqe *rollback_wqe,
  467. u32 rollback_psn)
  468. {
  469. wqe->state = rollback_wqe->state;
  470. wqe->first_psn = rollback_wqe->first_psn;
  471. wqe->last_psn = rollback_wqe->last_psn;
  472. qp->req.psn = rollback_psn;
  473. }
  474. static void update_state(struct rxe_qp *qp, struct rxe_send_wqe *wqe,
  475. struct rxe_pkt_info *pkt, int payload)
  476. {
  477. qp->req.opcode = pkt->opcode;
  478. if (pkt->mask & RXE_END_MASK)
  479. qp->req.wqe_index = next_index(qp->sq.queue, qp->req.wqe_index);
  480. qp->need_req_skb = 0;
  481. if (qp->qp_timeout_jiffies && !timer_pending(&qp->retrans_timer))
  482. mod_timer(&qp->retrans_timer,
  483. jiffies + qp->qp_timeout_jiffies);
  484. }
  485. int rxe_requester(void *arg)
  486. {
  487. struct rxe_qp *qp = (struct rxe_qp *)arg;
  488. struct rxe_pkt_info pkt;
  489. struct sk_buff *skb;
  490. struct rxe_send_wqe *wqe;
  491. enum rxe_hdr_mask mask;
  492. int payload;
  493. int mtu;
  494. int opcode;
  495. int ret;
  496. struct rxe_send_wqe rollback_wqe;
  497. u32 rollback_psn;
  498. rxe_add_ref(qp);
  499. next_wqe:
  500. if (unlikely(!qp->valid))
  501. goto exit;
  502. if (unlikely(qp->req.state == QP_STATE_ERROR)) {
  503. rxe_drain_req_pkts(qp, true);
  504. goto exit;
  505. }
  506. if (unlikely(qp->req.state == QP_STATE_RESET)) {
  507. qp->req.wqe_index = consumer_index(qp->sq.queue);
  508. qp->req.opcode = -1;
  509. qp->req.need_rd_atomic = 0;
  510. qp->req.wait_psn = 0;
  511. qp->req.need_retry = 0;
  512. goto exit;
  513. }
  514. if (unlikely(qp->req.need_retry)) {
  515. req_retry(qp);
  516. qp->req.need_retry = 0;
  517. }
  518. wqe = req_next_wqe(qp);
  519. if (unlikely(!wqe))
  520. goto exit;
  521. if (wqe->mask & WR_REG_MASK) {
  522. if (wqe->wr.opcode == IB_WR_LOCAL_INV) {
  523. struct rxe_dev *rxe = to_rdev(qp->ibqp.device);
  524. struct rxe_mem *rmr;
  525. rmr = rxe_pool_get_index(&rxe->mr_pool,
  526. wqe->wr.ex.invalidate_rkey >> 8);
  527. if (!rmr) {
  528. pr_err("No mr for key %#x\n",
  529. wqe->wr.ex.invalidate_rkey);
  530. wqe->state = wqe_state_error;
  531. wqe->status = IB_WC_MW_BIND_ERR;
  532. goto exit;
  533. }
  534. rmr->state = RXE_MEM_STATE_FREE;
  535. rxe_drop_ref(rmr);
  536. wqe->state = wqe_state_done;
  537. wqe->status = IB_WC_SUCCESS;
  538. } else if (wqe->wr.opcode == IB_WR_REG_MR) {
  539. struct rxe_mem *rmr = to_rmr(wqe->wr.wr.reg.mr);
  540. rmr->state = RXE_MEM_STATE_VALID;
  541. rmr->access = wqe->wr.wr.reg.access;
  542. rmr->lkey = wqe->wr.wr.reg.key;
  543. rmr->rkey = wqe->wr.wr.reg.key;
  544. wqe->state = wqe_state_done;
  545. wqe->status = IB_WC_SUCCESS;
  546. } else {
  547. goto exit;
  548. }
  549. qp->req.wqe_index = next_index(qp->sq.queue,
  550. qp->req.wqe_index);
  551. goto next_wqe;
  552. }
  553. if (unlikely(qp_type(qp) == IB_QPT_RC &&
  554. qp->req.psn > (qp->comp.psn + RXE_MAX_UNACKED_PSNS))) {
  555. qp->req.wait_psn = 1;
  556. goto exit;
  557. }
  558. /* Limit the number of inflight SKBs per QP */
  559. if (unlikely(atomic_read(&qp->skb_out) >
  560. RXE_INFLIGHT_SKBS_PER_QP_HIGH)) {
  561. qp->need_req_skb = 1;
  562. goto exit;
  563. }
  564. opcode = next_opcode(qp, wqe, wqe->wr.opcode);
  565. if (unlikely(opcode < 0)) {
  566. wqe->status = IB_WC_LOC_QP_OP_ERR;
  567. goto exit;
  568. }
  569. mask = rxe_opcode[opcode].mask;
  570. if (unlikely(mask & RXE_READ_OR_ATOMIC)) {
  571. if (check_init_depth(qp, wqe))
  572. goto exit;
  573. }
  574. mtu = get_mtu(qp);
  575. payload = (mask & RXE_WRITE_OR_SEND) ? wqe->dma.resid : 0;
  576. if (payload > mtu) {
  577. if (qp_type(qp) == IB_QPT_UD) {
  578. /* C10-93.1.1: If the total sum of all the buffer lengths specified for a
  579. * UD message exceeds the MTU of the port as returned by QueryHCA, the CI
  580. * shall not emit any packets for this message. Further, the CI shall not
  581. * generate an error due to this condition.
  582. */
  583. /* fake a successful UD send */
  584. wqe->first_psn = qp->req.psn;
  585. wqe->last_psn = qp->req.psn;
  586. qp->req.psn = (qp->req.psn + 1) & BTH_PSN_MASK;
  587. qp->req.opcode = IB_OPCODE_UD_SEND_ONLY;
  588. qp->req.wqe_index = next_index(qp->sq.queue,
  589. qp->req.wqe_index);
  590. wqe->state = wqe_state_done;
  591. wqe->status = IB_WC_SUCCESS;
  592. __rxe_do_task(&qp->comp.task);
  593. rxe_drop_ref(qp);
  594. return 0;
  595. }
  596. payload = mtu;
  597. }
  598. skb = init_req_packet(qp, wqe, opcode, payload, &pkt);
  599. if (unlikely(!skb)) {
  600. pr_err("qp#%d Failed allocating skb\n", qp_num(qp));
  601. goto err;
  602. }
  603. if (fill_packet(qp, wqe, &pkt, skb, payload)) {
  604. pr_debug("qp#%d Error during fill packet\n", qp_num(qp));
  605. goto err;
  606. }
  607. /*
  608. * To prevent a race on wqe access between requester and completer,
  609. * wqe members state and psn need to be set before calling
  610. * rxe_xmit_packet().
  611. * Otherwise, completer might initiate an unjustified retry flow.
  612. */
  613. save_state(wqe, qp, &rollback_wqe, &rollback_psn);
  614. update_wqe_state(qp, wqe, &pkt);
  615. update_wqe_psn(qp, wqe, &pkt, payload);
  616. ret = rxe_xmit_packet(to_rdev(qp->ibqp.device), qp, &pkt, skb);
  617. if (ret) {
  618. qp->need_req_skb = 1;
  619. rollback_state(wqe, qp, &rollback_wqe, rollback_psn);
  620. if (ret == -EAGAIN) {
  621. kfree_skb(skb);
  622. rxe_run_task(&qp->req.task, 1);
  623. goto exit;
  624. }
  625. goto err;
  626. }
  627. update_state(qp, wqe, &pkt, payload);
  628. goto next_wqe;
  629. err:
  630. kfree_skb(skb);
  631. wqe->status = IB_WC_LOC_PROT_ERR;
  632. wqe->state = wqe_state_error;
  633. __rxe_do_task(&qp->comp.task);
  634. exit:
  635. rxe_drop_ref(qp);
  636. return -EAGAIN;
  637. }