hns_roce_main.c 25 KB

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  1. /*
  2. * Copyright (c) 2016 Hisilicon Limited.
  3. * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/acpi.h>
  34. #include <linux/of_platform.h>
  35. #include <linux/module.h>
  36. #include <rdma/ib_addr.h>
  37. #include <rdma/ib_smi.h>
  38. #include <rdma/ib_user_verbs.h>
  39. #include <rdma/ib_cache.h>
  40. #include "hns_roce_common.h"
  41. #include "hns_roce_device.h"
  42. #include <rdma/hns-abi.h>
  43. #include "hns_roce_hem.h"
  44. /**
  45. * hns_get_gid_index - Get gid index.
  46. * @hr_dev: pointer to structure hns_roce_dev.
  47. * @port: port, value range: 0 ~ MAX
  48. * @gid_index: gid_index, value range: 0 ~ MAX
  49. * Description:
  50. * N ports shared gids, allocation method as follow:
  51. * GID[0][0], GID[1][0],.....GID[N - 1][0],
  52. * GID[0][0], GID[1][0],.....GID[N - 1][0],
  53. * And so on
  54. */
  55. int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index)
  56. {
  57. return gid_index * hr_dev->caps.num_ports + port;
  58. }
  59. static void hns_roce_set_mac(struct hns_roce_dev *hr_dev, u8 port, u8 *addr)
  60. {
  61. u8 phy_port;
  62. u32 i = 0;
  63. if (!memcmp(hr_dev->dev_addr[port], addr, MAC_ADDR_OCTET_NUM))
  64. return;
  65. for (i = 0; i < MAC_ADDR_OCTET_NUM; i++)
  66. hr_dev->dev_addr[port][i] = addr[i];
  67. phy_port = hr_dev->iboe.phy_port[port];
  68. hr_dev->hw->set_mac(hr_dev, phy_port, addr);
  69. }
  70. static int hns_roce_add_gid(struct ib_device *device, u8 port_num,
  71. unsigned int index, const union ib_gid *gid,
  72. const struct ib_gid_attr *attr, void **context)
  73. {
  74. struct hns_roce_dev *hr_dev = to_hr_dev(device);
  75. u8 port = port_num - 1;
  76. unsigned long flags;
  77. if (port >= hr_dev->caps.num_ports)
  78. return -EINVAL;
  79. spin_lock_irqsave(&hr_dev->iboe.lock, flags);
  80. hr_dev->hw->set_gid(hr_dev, port, index, (union ib_gid *)gid);
  81. spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
  82. return 0;
  83. }
  84. static int hns_roce_del_gid(struct ib_device *device, u8 port_num,
  85. unsigned int index, void **context)
  86. {
  87. struct hns_roce_dev *hr_dev = to_hr_dev(device);
  88. union ib_gid zgid = { {0} };
  89. u8 port = port_num - 1;
  90. unsigned long flags;
  91. if (port >= hr_dev->caps.num_ports)
  92. return -EINVAL;
  93. spin_lock_irqsave(&hr_dev->iboe.lock, flags);
  94. hr_dev->hw->set_gid(hr_dev, port, index, &zgid);
  95. spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
  96. return 0;
  97. }
  98. static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port,
  99. unsigned long event)
  100. {
  101. struct device *dev = &hr_dev->pdev->dev;
  102. struct net_device *netdev;
  103. netdev = hr_dev->iboe.netdevs[port];
  104. if (!netdev) {
  105. dev_err(dev, "port(%d) can't find netdev\n", port);
  106. return -ENODEV;
  107. }
  108. spin_lock_bh(&hr_dev->iboe.lock);
  109. switch (event) {
  110. case NETDEV_UP:
  111. case NETDEV_CHANGE:
  112. case NETDEV_REGISTER:
  113. case NETDEV_CHANGEADDR:
  114. hns_roce_set_mac(hr_dev, port, netdev->dev_addr);
  115. break;
  116. case NETDEV_DOWN:
  117. /*
  118. * In v1 engine, only support all ports closed together.
  119. */
  120. break;
  121. default:
  122. dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event));
  123. break;
  124. }
  125. spin_unlock_bh(&hr_dev->iboe.lock);
  126. return 0;
  127. }
  128. static int hns_roce_netdev_event(struct notifier_block *self,
  129. unsigned long event, void *ptr)
  130. {
  131. struct net_device *dev = netdev_notifier_info_to_dev(ptr);
  132. struct hns_roce_ib_iboe *iboe = NULL;
  133. struct hns_roce_dev *hr_dev = NULL;
  134. u8 port = 0;
  135. int ret = 0;
  136. hr_dev = container_of(self, struct hns_roce_dev, iboe.nb);
  137. iboe = &hr_dev->iboe;
  138. for (port = 0; port < hr_dev->caps.num_ports; port++) {
  139. if (dev == iboe->netdevs[port]) {
  140. ret = handle_en_event(hr_dev, port, event);
  141. if (ret)
  142. return NOTIFY_DONE;
  143. break;
  144. }
  145. }
  146. return NOTIFY_DONE;
  147. }
  148. static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev)
  149. {
  150. u8 i;
  151. for (i = 0; i < hr_dev->caps.num_ports; i++) {
  152. hr_dev->hw->set_mtu(hr_dev, hr_dev->iboe.phy_port[i],
  153. hr_dev->caps.max_mtu);
  154. hns_roce_set_mac(hr_dev, i, hr_dev->iboe.netdevs[i]->dev_addr);
  155. }
  156. return 0;
  157. }
  158. static int hns_roce_query_device(struct ib_device *ib_dev,
  159. struct ib_device_attr *props,
  160. struct ib_udata *uhw)
  161. {
  162. struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
  163. memset(props, 0, sizeof(*props));
  164. props->sys_image_guid = hr_dev->sys_image_guid;
  165. props->max_mr_size = (u64)(~(0ULL));
  166. props->page_size_cap = hr_dev->caps.page_size_cap;
  167. props->vendor_id = hr_dev->vendor_id;
  168. props->vendor_part_id = hr_dev->vendor_part_id;
  169. props->hw_ver = hr_dev->hw_rev;
  170. props->max_qp = hr_dev->caps.num_qps;
  171. props->max_qp_wr = hr_dev->caps.max_wqes;
  172. props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT |
  173. IB_DEVICE_RC_RNR_NAK_GEN;
  174. props->max_sge = hr_dev->caps.max_sq_sg;
  175. props->max_sge_rd = 1;
  176. props->max_cq = hr_dev->caps.num_cqs;
  177. props->max_cqe = hr_dev->caps.max_cqes;
  178. props->max_mr = hr_dev->caps.num_mtpts;
  179. props->max_pd = hr_dev->caps.num_pds;
  180. props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma;
  181. props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma;
  182. props->atomic_cap = IB_ATOMIC_NONE;
  183. props->max_pkeys = 1;
  184. props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;
  185. return 0;
  186. }
  187. static struct net_device *hns_roce_get_netdev(struct ib_device *ib_dev,
  188. u8 port_num)
  189. {
  190. struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
  191. struct net_device *ndev;
  192. if (port_num < 1 || port_num > hr_dev->caps.num_ports)
  193. return NULL;
  194. rcu_read_lock();
  195. ndev = hr_dev->iboe.netdevs[port_num - 1];
  196. if (ndev)
  197. dev_hold(ndev);
  198. rcu_read_unlock();
  199. return ndev;
  200. }
  201. static int hns_roce_query_port(struct ib_device *ib_dev, u8 port_num,
  202. struct ib_port_attr *props)
  203. {
  204. struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
  205. struct device *dev = &hr_dev->pdev->dev;
  206. struct net_device *net_dev;
  207. unsigned long flags;
  208. enum ib_mtu mtu;
  209. u8 port;
  210. assert(port_num > 0);
  211. port = port_num - 1;
  212. /* props being zeroed by the caller, avoid zeroing it here */
  213. props->max_mtu = hr_dev->caps.max_mtu;
  214. props->gid_tbl_len = hr_dev->caps.gid_table_len[port];
  215. props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
  216. IB_PORT_VENDOR_CLASS_SUP |
  217. IB_PORT_BOOT_MGMT_SUP;
  218. props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN;
  219. props->pkey_tbl_len = 1;
  220. props->active_width = IB_WIDTH_4X;
  221. props->active_speed = 1;
  222. spin_lock_irqsave(&hr_dev->iboe.lock, flags);
  223. net_dev = hr_dev->iboe.netdevs[port];
  224. if (!net_dev) {
  225. spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
  226. dev_err(dev, "find netdev %d failed!\r\n", port);
  227. return -EINVAL;
  228. }
  229. mtu = iboe_get_mtu(net_dev->mtu);
  230. props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256;
  231. props->state = (netif_running(net_dev) && netif_carrier_ok(net_dev)) ?
  232. IB_PORT_ACTIVE : IB_PORT_DOWN;
  233. props->phys_state = (props->state == IB_PORT_ACTIVE) ? 5 : 3;
  234. spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
  235. return 0;
  236. }
  237. static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device,
  238. u8 port_num)
  239. {
  240. return IB_LINK_LAYER_ETHERNET;
  241. }
  242. static int hns_roce_query_gid(struct ib_device *ib_dev, u8 port_num, int index,
  243. union ib_gid *gid)
  244. {
  245. return 0;
  246. }
  247. static int hns_roce_query_pkey(struct ib_device *ib_dev, u8 port, u16 index,
  248. u16 *pkey)
  249. {
  250. *pkey = PKEY_ID;
  251. return 0;
  252. }
  253. static int hns_roce_modify_device(struct ib_device *ib_dev, int mask,
  254. struct ib_device_modify *props)
  255. {
  256. unsigned long flags;
  257. if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
  258. return -EOPNOTSUPP;
  259. if (mask & IB_DEVICE_MODIFY_NODE_DESC) {
  260. spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags);
  261. memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE);
  262. spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags);
  263. }
  264. return 0;
  265. }
  266. static int hns_roce_modify_port(struct ib_device *ib_dev, u8 port_num, int mask,
  267. struct ib_port_modify *props)
  268. {
  269. return 0;
  270. }
  271. static struct ib_ucontext *hns_roce_alloc_ucontext(struct ib_device *ib_dev,
  272. struct ib_udata *udata)
  273. {
  274. int ret = 0;
  275. struct hns_roce_ucontext *context;
  276. struct hns_roce_ib_alloc_ucontext_resp resp;
  277. struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
  278. resp.qp_tab_size = hr_dev->caps.num_qps;
  279. context = kmalloc(sizeof(*context), GFP_KERNEL);
  280. if (!context)
  281. return ERR_PTR(-ENOMEM);
  282. ret = hns_roce_uar_alloc(hr_dev, &context->uar);
  283. if (ret)
  284. goto error_fail_uar_alloc;
  285. ret = ib_copy_to_udata(udata, &resp, sizeof(resp));
  286. if (ret)
  287. goto error_fail_copy_to_udata;
  288. return &context->ibucontext;
  289. error_fail_copy_to_udata:
  290. hns_roce_uar_free(hr_dev, &context->uar);
  291. error_fail_uar_alloc:
  292. kfree(context);
  293. return ERR_PTR(ret);
  294. }
  295. static int hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext)
  296. {
  297. struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext);
  298. hns_roce_uar_free(to_hr_dev(ibcontext->device), &context->uar);
  299. kfree(context);
  300. return 0;
  301. }
  302. static int hns_roce_mmap(struct ib_ucontext *context,
  303. struct vm_area_struct *vma)
  304. {
  305. struct hns_roce_dev *hr_dev = to_hr_dev(context->device);
  306. if (((vma->vm_end - vma->vm_start) % PAGE_SIZE) != 0)
  307. return -EINVAL;
  308. if (vma->vm_pgoff == 0) {
  309. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  310. if (io_remap_pfn_range(vma, vma->vm_start,
  311. to_hr_ucontext(context)->uar.pfn,
  312. PAGE_SIZE, vma->vm_page_prot))
  313. return -EAGAIN;
  314. } else if (vma->vm_pgoff == 1 && hr_dev->hw_rev == HNS_ROCE_HW_VER1) {
  315. /* vm_pgoff: 1 -- TPTR */
  316. if (io_remap_pfn_range(vma, vma->vm_start,
  317. hr_dev->tptr_dma_addr >> PAGE_SHIFT,
  318. hr_dev->tptr_size,
  319. vma->vm_page_prot))
  320. return -EAGAIN;
  321. } else
  322. return -EINVAL;
  323. return 0;
  324. }
  325. static int hns_roce_port_immutable(struct ib_device *ib_dev, u8 port_num,
  326. struct ib_port_immutable *immutable)
  327. {
  328. struct ib_port_attr attr;
  329. int ret;
  330. immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
  331. ret = ib_query_port(ib_dev, port_num, &attr);
  332. if (ret)
  333. return ret;
  334. immutable->pkey_tbl_len = attr.pkey_tbl_len;
  335. immutable->gid_tbl_len = attr.gid_tbl_len;
  336. immutable->max_mad_size = IB_MGMT_MAD_SIZE;
  337. return 0;
  338. }
  339. static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev)
  340. {
  341. struct hns_roce_ib_iboe *iboe = &hr_dev->iboe;
  342. unregister_inetaddr_notifier(&iboe->nb_inet);
  343. unregister_netdevice_notifier(&iboe->nb);
  344. ib_unregister_device(&hr_dev->ib_dev);
  345. }
  346. static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
  347. {
  348. int ret;
  349. struct hns_roce_ib_iboe *iboe = NULL;
  350. struct ib_device *ib_dev = NULL;
  351. struct device *dev = &hr_dev->pdev->dev;
  352. iboe = &hr_dev->iboe;
  353. spin_lock_init(&iboe->lock);
  354. ib_dev = &hr_dev->ib_dev;
  355. strlcpy(ib_dev->name, "hns_%d", IB_DEVICE_NAME_MAX);
  356. ib_dev->owner = THIS_MODULE;
  357. ib_dev->node_type = RDMA_NODE_IB_CA;
  358. ib_dev->dev.parent = dev;
  359. ib_dev->phys_port_cnt = hr_dev->caps.num_ports;
  360. ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey;
  361. ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors;
  362. ib_dev->uverbs_abi_ver = 1;
  363. ib_dev->uverbs_cmd_mask =
  364. (1ULL << IB_USER_VERBS_CMD_GET_CONTEXT) |
  365. (1ULL << IB_USER_VERBS_CMD_QUERY_DEVICE) |
  366. (1ULL << IB_USER_VERBS_CMD_QUERY_PORT) |
  367. (1ULL << IB_USER_VERBS_CMD_ALLOC_PD) |
  368. (1ULL << IB_USER_VERBS_CMD_DEALLOC_PD) |
  369. (1ULL << IB_USER_VERBS_CMD_REG_MR) |
  370. (1ULL << IB_USER_VERBS_CMD_DEREG_MR) |
  371. (1ULL << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
  372. (1ULL << IB_USER_VERBS_CMD_CREATE_CQ) |
  373. (1ULL << IB_USER_VERBS_CMD_DESTROY_CQ) |
  374. (1ULL << IB_USER_VERBS_CMD_CREATE_QP) |
  375. (1ULL << IB_USER_VERBS_CMD_MODIFY_QP) |
  376. (1ULL << IB_USER_VERBS_CMD_QUERY_QP) |
  377. (1ULL << IB_USER_VERBS_CMD_DESTROY_QP);
  378. /* HCA||device||port */
  379. ib_dev->modify_device = hns_roce_modify_device;
  380. ib_dev->query_device = hns_roce_query_device;
  381. ib_dev->query_port = hns_roce_query_port;
  382. ib_dev->modify_port = hns_roce_modify_port;
  383. ib_dev->get_link_layer = hns_roce_get_link_layer;
  384. ib_dev->get_netdev = hns_roce_get_netdev;
  385. ib_dev->query_gid = hns_roce_query_gid;
  386. ib_dev->add_gid = hns_roce_add_gid;
  387. ib_dev->del_gid = hns_roce_del_gid;
  388. ib_dev->query_pkey = hns_roce_query_pkey;
  389. ib_dev->alloc_ucontext = hns_roce_alloc_ucontext;
  390. ib_dev->dealloc_ucontext = hns_roce_dealloc_ucontext;
  391. ib_dev->mmap = hns_roce_mmap;
  392. /* PD */
  393. ib_dev->alloc_pd = hns_roce_alloc_pd;
  394. ib_dev->dealloc_pd = hns_roce_dealloc_pd;
  395. /* AH */
  396. ib_dev->create_ah = hns_roce_create_ah;
  397. ib_dev->query_ah = hns_roce_query_ah;
  398. ib_dev->destroy_ah = hns_roce_destroy_ah;
  399. /* QP */
  400. ib_dev->create_qp = hns_roce_create_qp;
  401. ib_dev->modify_qp = hns_roce_modify_qp;
  402. ib_dev->query_qp = hr_dev->hw->query_qp;
  403. ib_dev->destroy_qp = hr_dev->hw->destroy_qp;
  404. ib_dev->post_send = hr_dev->hw->post_send;
  405. ib_dev->post_recv = hr_dev->hw->post_recv;
  406. /* CQ */
  407. ib_dev->create_cq = hns_roce_ib_create_cq;
  408. ib_dev->destroy_cq = hns_roce_ib_destroy_cq;
  409. ib_dev->req_notify_cq = hr_dev->hw->req_notify_cq;
  410. ib_dev->poll_cq = hr_dev->hw->poll_cq;
  411. /* MR */
  412. ib_dev->get_dma_mr = hns_roce_get_dma_mr;
  413. ib_dev->reg_user_mr = hns_roce_reg_user_mr;
  414. ib_dev->dereg_mr = hns_roce_dereg_mr;
  415. /* OTHERS */
  416. ib_dev->get_port_immutable = hns_roce_port_immutable;
  417. ret = ib_register_device(ib_dev, NULL);
  418. if (ret) {
  419. dev_err(dev, "ib_register_device failed!\n");
  420. return ret;
  421. }
  422. ret = hns_roce_setup_mtu_mac(hr_dev);
  423. if (ret) {
  424. dev_err(dev, "setup_mtu_mac failed!\n");
  425. goto error_failed_setup_mtu_mac;
  426. }
  427. iboe->nb.notifier_call = hns_roce_netdev_event;
  428. ret = register_netdevice_notifier(&iboe->nb);
  429. if (ret) {
  430. dev_err(dev, "register_netdevice_notifier failed!\n");
  431. goto error_failed_setup_mtu_mac;
  432. }
  433. return 0;
  434. error_failed_setup_mtu_mac:
  435. ib_unregister_device(ib_dev);
  436. return ret;
  437. }
  438. static const struct of_device_id hns_roce_of_match[] = {
  439. { .compatible = "hisilicon,hns-roce-v1", .data = &hns_roce_hw_v1, },
  440. {},
  441. };
  442. MODULE_DEVICE_TABLE(of, hns_roce_of_match);
  443. static const struct acpi_device_id hns_roce_acpi_match[] = {
  444. { "HISI00D1", (kernel_ulong_t)&hns_roce_hw_v1 },
  445. {},
  446. };
  447. MODULE_DEVICE_TABLE(acpi, hns_roce_acpi_match);
  448. static int hns_roce_node_match(struct device *dev, void *fwnode)
  449. {
  450. return dev->fwnode == fwnode;
  451. }
  452. static struct
  453. platform_device *hns_roce_find_pdev(struct fwnode_handle *fwnode)
  454. {
  455. struct device *dev;
  456. /* get the 'device'corresponding to matching 'fwnode' */
  457. dev = bus_find_device(&platform_bus_type, NULL,
  458. fwnode, hns_roce_node_match);
  459. /* get the platform device */
  460. return dev ? to_platform_device(dev) : NULL;
  461. }
  462. static int hns_roce_get_cfg(struct hns_roce_dev *hr_dev)
  463. {
  464. int i;
  465. int ret;
  466. u8 phy_port;
  467. int port_cnt = 0;
  468. struct device *dev = &hr_dev->pdev->dev;
  469. struct device_node *net_node;
  470. struct net_device *netdev = NULL;
  471. struct platform_device *pdev = NULL;
  472. struct resource *res;
  473. /* check if we are compatible with the underlying SoC */
  474. if (dev_of_node(dev)) {
  475. const struct of_device_id *of_id;
  476. of_id = of_match_node(hns_roce_of_match, dev->of_node);
  477. if (!of_id) {
  478. dev_err(dev, "device is not compatible!\n");
  479. return -ENXIO;
  480. }
  481. hr_dev->hw = (struct hns_roce_hw *)of_id->data;
  482. if (!hr_dev->hw) {
  483. dev_err(dev, "couldn't get H/W specific DT data!\n");
  484. return -ENXIO;
  485. }
  486. } else if (is_acpi_device_node(dev->fwnode)) {
  487. const struct acpi_device_id *acpi_id;
  488. acpi_id = acpi_match_device(hns_roce_acpi_match, dev);
  489. if (!acpi_id) {
  490. dev_err(dev, "device is not compatible!\n");
  491. return -ENXIO;
  492. }
  493. hr_dev->hw = (struct hns_roce_hw *) acpi_id->driver_data;
  494. if (!hr_dev->hw) {
  495. dev_err(dev, "couldn't get H/W specific ACPI data!\n");
  496. return -ENXIO;
  497. }
  498. } else {
  499. dev_err(dev, "can't read compatibility data from DT or ACPI\n");
  500. return -ENXIO;
  501. }
  502. /* get the mapped register base address */
  503. res = platform_get_resource(hr_dev->pdev, IORESOURCE_MEM, 0);
  504. if (!res) {
  505. dev_err(dev, "memory resource not found!\n");
  506. return -EINVAL;
  507. }
  508. hr_dev->reg_base = devm_ioremap_resource(dev, res);
  509. if (IS_ERR(hr_dev->reg_base))
  510. return PTR_ERR(hr_dev->reg_base);
  511. /* read the node_guid of IB device from the DT or ACPI */
  512. ret = device_property_read_u8_array(dev, "node-guid",
  513. (u8 *)&hr_dev->ib_dev.node_guid,
  514. GUID_LEN);
  515. if (ret) {
  516. dev_err(dev, "couldn't get node_guid from DT or ACPI!\n");
  517. return ret;
  518. }
  519. /* get the RoCE associated ethernet ports or netdevices */
  520. for (i = 0; i < HNS_ROCE_MAX_PORTS; i++) {
  521. if (dev_of_node(dev)) {
  522. net_node = of_parse_phandle(dev->of_node, "eth-handle",
  523. i);
  524. if (!net_node)
  525. continue;
  526. pdev = of_find_device_by_node(net_node);
  527. } else if (is_acpi_device_node(dev->fwnode)) {
  528. struct acpi_reference_args args;
  529. struct fwnode_handle *fwnode;
  530. ret = acpi_node_get_property_reference(dev->fwnode,
  531. "eth-handle",
  532. i, &args);
  533. if (ret)
  534. continue;
  535. fwnode = acpi_fwnode_handle(args.adev);
  536. pdev = hns_roce_find_pdev(fwnode);
  537. } else {
  538. dev_err(dev, "cannot read data from DT or ACPI\n");
  539. return -ENXIO;
  540. }
  541. if (pdev) {
  542. netdev = platform_get_drvdata(pdev);
  543. phy_port = (u8)i;
  544. if (netdev) {
  545. hr_dev->iboe.netdevs[port_cnt] = netdev;
  546. hr_dev->iboe.phy_port[port_cnt] = phy_port;
  547. } else {
  548. dev_err(dev, "no netdev found with pdev %s\n",
  549. pdev->name);
  550. return -ENODEV;
  551. }
  552. port_cnt++;
  553. }
  554. }
  555. if (port_cnt == 0) {
  556. dev_err(dev, "unable to get eth-handle for available ports!\n");
  557. return -EINVAL;
  558. }
  559. hr_dev->caps.num_ports = port_cnt;
  560. /* cmd issue mode: 0 is poll, 1 is event */
  561. hr_dev->cmd_mod = 1;
  562. hr_dev->loop_idc = 0;
  563. /* read the interrupt names from the DT or ACPI */
  564. ret = device_property_read_string_array(dev, "interrupt-names",
  565. hr_dev->irq_names,
  566. HNS_ROCE_MAX_IRQ_NUM);
  567. if (ret < 0) {
  568. dev_err(dev, "couldn't get interrupt names from DT or ACPI!\n");
  569. return ret;
  570. }
  571. /* fetch the interrupt numbers */
  572. for (i = 0; i < HNS_ROCE_MAX_IRQ_NUM; i++) {
  573. hr_dev->irq[i] = platform_get_irq(hr_dev->pdev, i);
  574. if (hr_dev->irq[i] <= 0) {
  575. dev_err(dev, "platform get of irq[=%d] failed!\n", i);
  576. return -EINVAL;
  577. }
  578. }
  579. return 0;
  580. }
  581. static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
  582. {
  583. int ret;
  584. struct device *dev = &hr_dev->pdev->dev;
  585. ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtt_table,
  586. HEM_TYPE_MTT, hr_dev->caps.mtt_entry_sz,
  587. hr_dev->caps.num_mtt_segs, 1);
  588. if (ret) {
  589. dev_err(dev, "Failed to init MTT context memory, aborting.\n");
  590. return ret;
  591. }
  592. ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table,
  593. HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz,
  594. hr_dev->caps.num_mtpts, 1);
  595. if (ret) {
  596. dev_err(dev, "Failed to init MTPT context memory, aborting.\n");
  597. goto err_unmap_mtt;
  598. }
  599. ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table,
  600. HEM_TYPE_QPC, hr_dev->caps.qpc_entry_sz,
  601. hr_dev->caps.num_qps, 1);
  602. if (ret) {
  603. dev_err(dev, "Failed to init QP context memory, aborting.\n");
  604. goto err_unmap_dmpt;
  605. }
  606. ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table,
  607. HEM_TYPE_IRRL,
  608. hr_dev->caps.irrl_entry_sz *
  609. hr_dev->caps.max_qp_init_rdma,
  610. hr_dev->caps.num_qps, 1);
  611. if (ret) {
  612. dev_err(dev, "Failed to init irrl_table memory, aborting.\n");
  613. goto err_unmap_qp;
  614. }
  615. ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table,
  616. HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz,
  617. hr_dev->caps.num_cqs, 1);
  618. if (ret) {
  619. dev_err(dev, "Failed to init CQ context memory, aborting.\n");
  620. goto err_unmap_irrl;
  621. }
  622. return 0;
  623. err_unmap_irrl:
  624. hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
  625. err_unmap_qp:
  626. hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
  627. err_unmap_dmpt:
  628. hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
  629. err_unmap_mtt:
  630. hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtt_table);
  631. return ret;
  632. }
  633. /**
  634. * hns_roce_setup_hca - setup host channel adapter
  635. * @hr_dev: pointer to hns roce device
  636. * Return : int
  637. */
  638. static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
  639. {
  640. int ret;
  641. struct device *dev = &hr_dev->pdev->dev;
  642. spin_lock_init(&hr_dev->sm_lock);
  643. spin_lock_init(&hr_dev->bt_cmd_lock);
  644. ret = hns_roce_init_uar_table(hr_dev);
  645. if (ret) {
  646. dev_err(dev, "Failed to initialize uar table. aborting\n");
  647. return ret;
  648. }
  649. ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar);
  650. if (ret) {
  651. dev_err(dev, "Failed to allocate priv_uar.\n");
  652. goto err_uar_table_free;
  653. }
  654. ret = hns_roce_init_pd_table(hr_dev);
  655. if (ret) {
  656. dev_err(dev, "Failed to init protected domain table.\n");
  657. goto err_uar_alloc_free;
  658. }
  659. ret = hns_roce_init_mr_table(hr_dev);
  660. if (ret) {
  661. dev_err(dev, "Failed to init memory region table.\n");
  662. goto err_pd_table_free;
  663. }
  664. ret = hns_roce_init_cq_table(hr_dev);
  665. if (ret) {
  666. dev_err(dev, "Failed to init completion queue table.\n");
  667. goto err_mr_table_free;
  668. }
  669. ret = hns_roce_init_qp_table(hr_dev);
  670. if (ret) {
  671. dev_err(dev, "Failed to init queue pair table.\n");
  672. goto err_cq_table_free;
  673. }
  674. return 0;
  675. err_cq_table_free:
  676. hns_roce_cleanup_cq_table(hr_dev);
  677. err_mr_table_free:
  678. hns_roce_cleanup_mr_table(hr_dev);
  679. err_pd_table_free:
  680. hns_roce_cleanup_pd_table(hr_dev);
  681. err_uar_alloc_free:
  682. hns_roce_uar_free(hr_dev, &hr_dev->priv_uar);
  683. err_uar_table_free:
  684. hns_roce_cleanup_uar_table(hr_dev);
  685. return ret;
  686. }
  687. /**
  688. * hns_roce_probe - RoCE driver entrance
  689. * @pdev: pointer to platform device
  690. * Return : int
  691. *
  692. */
  693. static int hns_roce_probe(struct platform_device *pdev)
  694. {
  695. int ret;
  696. struct hns_roce_dev *hr_dev;
  697. struct device *dev = &pdev->dev;
  698. hr_dev = (struct hns_roce_dev *)ib_alloc_device(sizeof(*hr_dev));
  699. if (!hr_dev)
  700. return -ENOMEM;
  701. hr_dev->pdev = pdev;
  702. platform_set_drvdata(pdev, hr_dev);
  703. if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64ULL)) &&
  704. dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32ULL))) {
  705. dev_err(dev, "Not usable DMA addressing mode\n");
  706. ret = -EIO;
  707. goto error_failed_get_cfg;
  708. }
  709. ret = hns_roce_get_cfg(hr_dev);
  710. if (ret) {
  711. dev_err(dev, "Get Configuration failed!\n");
  712. goto error_failed_get_cfg;
  713. }
  714. ret = hr_dev->hw->reset(hr_dev, true);
  715. if (ret) {
  716. dev_err(dev, "Reset RoCE engine failed!\n");
  717. goto error_failed_get_cfg;
  718. }
  719. hr_dev->hw->hw_profile(hr_dev);
  720. ret = hns_roce_cmd_init(hr_dev);
  721. if (ret) {
  722. dev_err(dev, "cmd init failed!\n");
  723. goto error_failed_cmd_init;
  724. }
  725. ret = hns_roce_init_eq_table(hr_dev);
  726. if (ret) {
  727. dev_err(dev, "eq init failed!\n");
  728. goto error_failed_eq_table;
  729. }
  730. if (hr_dev->cmd_mod) {
  731. ret = hns_roce_cmd_use_events(hr_dev);
  732. if (ret) {
  733. dev_err(dev, "Switch to event-driven cmd failed!\n");
  734. goto error_failed_use_event;
  735. }
  736. }
  737. ret = hns_roce_init_hem(hr_dev);
  738. if (ret) {
  739. dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n");
  740. goto error_failed_init_hem;
  741. }
  742. ret = hns_roce_setup_hca(hr_dev);
  743. if (ret) {
  744. dev_err(dev, "setup hca failed!\n");
  745. goto error_failed_setup_hca;
  746. }
  747. ret = hr_dev->hw->hw_init(hr_dev);
  748. if (ret) {
  749. dev_err(dev, "hw_init failed!\n");
  750. goto error_failed_engine_init;
  751. }
  752. ret = hns_roce_register_device(hr_dev);
  753. if (ret)
  754. goto error_failed_register_device;
  755. return 0;
  756. error_failed_register_device:
  757. hr_dev->hw->hw_exit(hr_dev);
  758. error_failed_engine_init:
  759. hns_roce_cleanup_bitmap(hr_dev);
  760. error_failed_setup_hca:
  761. hns_roce_cleanup_hem(hr_dev);
  762. error_failed_init_hem:
  763. if (hr_dev->cmd_mod)
  764. hns_roce_cmd_use_polling(hr_dev);
  765. error_failed_use_event:
  766. hns_roce_cleanup_eq_table(hr_dev);
  767. error_failed_eq_table:
  768. hns_roce_cmd_cleanup(hr_dev);
  769. error_failed_cmd_init:
  770. ret = hr_dev->hw->reset(hr_dev, false);
  771. if (ret)
  772. dev_err(&hr_dev->pdev->dev, "roce_engine reset fail\n");
  773. error_failed_get_cfg:
  774. ib_dealloc_device(&hr_dev->ib_dev);
  775. return ret;
  776. }
  777. /**
  778. * hns_roce_remove - remove RoCE device
  779. * @pdev: pointer to platform device
  780. */
  781. static int hns_roce_remove(struct platform_device *pdev)
  782. {
  783. struct hns_roce_dev *hr_dev = platform_get_drvdata(pdev);
  784. hns_roce_unregister_device(hr_dev);
  785. hr_dev->hw->hw_exit(hr_dev);
  786. hns_roce_cleanup_bitmap(hr_dev);
  787. hns_roce_cleanup_hem(hr_dev);
  788. if (hr_dev->cmd_mod)
  789. hns_roce_cmd_use_polling(hr_dev);
  790. hns_roce_cleanup_eq_table(hr_dev);
  791. hns_roce_cmd_cleanup(hr_dev);
  792. hr_dev->hw->reset(hr_dev, false);
  793. ib_dealloc_device(&hr_dev->ib_dev);
  794. return 0;
  795. }
  796. static struct platform_driver hns_roce_driver = {
  797. .probe = hns_roce_probe,
  798. .remove = hns_roce_remove,
  799. .driver = {
  800. .name = DRV_NAME,
  801. .of_match_table = hns_roce_of_match,
  802. .acpi_match_table = ACPI_PTR(hns_roce_acpi_match),
  803. },
  804. };
  805. module_platform_driver(hns_roce_driver);
  806. MODULE_LICENSE("Dual BSD/GPL");
  807. MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
  808. MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
  809. MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
  810. MODULE_DESCRIPTION("HNS RoCE Driver");