device.c 42 KB

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  1. /*
  2. * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/module.h>
  33. #include <linux/moduleparam.h>
  34. #include <linux/debugfs.h>
  35. #include <linux/vmalloc.h>
  36. #include <linux/math64.h>
  37. #include <rdma/ib_verbs.h>
  38. #include "iw_cxgb4.h"
  39. #define DRV_VERSION "0.1"
  40. MODULE_AUTHOR("Steve Wise");
  41. MODULE_DESCRIPTION("Chelsio T4/T5 RDMA Driver");
  42. MODULE_LICENSE("Dual BSD/GPL");
  43. MODULE_VERSION(DRV_VERSION);
  44. static int allow_db_fc_on_t5;
  45. module_param(allow_db_fc_on_t5, int, 0644);
  46. MODULE_PARM_DESC(allow_db_fc_on_t5,
  47. "Allow DB Flow Control on T5 (default = 0)");
  48. static int allow_db_coalescing_on_t5;
  49. module_param(allow_db_coalescing_on_t5, int, 0644);
  50. MODULE_PARM_DESC(allow_db_coalescing_on_t5,
  51. "Allow DB Coalescing on T5 (default = 0)");
  52. int c4iw_wr_log = 0;
  53. module_param(c4iw_wr_log, int, 0444);
  54. MODULE_PARM_DESC(c4iw_wr_log, "Enables logging of work request timing data.");
  55. static int c4iw_wr_log_size_order = 12;
  56. module_param(c4iw_wr_log_size_order, int, 0444);
  57. MODULE_PARM_DESC(c4iw_wr_log_size_order,
  58. "Number of entries (log2) in the work request timing log.");
  59. struct uld_ctx {
  60. struct list_head entry;
  61. struct cxgb4_lld_info lldi;
  62. struct c4iw_dev *dev;
  63. };
  64. static LIST_HEAD(uld_ctx_list);
  65. static DEFINE_MUTEX(dev_mutex);
  66. #define DB_FC_RESUME_SIZE 64
  67. #define DB_FC_RESUME_DELAY 1
  68. #define DB_FC_DRAIN_THRESH 0
  69. static struct dentry *c4iw_debugfs_root;
  70. struct c4iw_debugfs_data {
  71. struct c4iw_dev *devp;
  72. char *buf;
  73. int bufsize;
  74. int pos;
  75. };
  76. static int count_idrs(int id, void *p, void *data)
  77. {
  78. int *countp = data;
  79. *countp = *countp + 1;
  80. return 0;
  81. }
  82. static ssize_t debugfs_read(struct file *file, char __user *buf, size_t count,
  83. loff_t *ppos)
  84. {
  85. struct c4iw_debugfs_data *d = file->private_data;
  86. return simple_read_from_buffer(buf, count, ppos, d->buf, d->pos);
  87. }
  88. void c4iw_log_wr_stats(struct t4_wq *wq, struct t4_cqe *cqe)
  89. {
  90. struct wr_log_entry le;
  91. int idx;
  92. if (!wq->rdev->wr_log)
  93. return;
  94. idx = (atomic_inc_return(&wq->rdev->wr_log_idx) - 1) &
  95. (wq->rdev->wr_log_size - 1);
  96. le.poll_sge_ts = cxgb4_read_sge_timestamp(wq->rdev->lldi.ports[0]);
  97. getnstimeofday(&le.poll_host_ts);
  98. le.valid = 1;
  99. le.cqe_sge_ts = CQE_TS(cqe);
  100. if (SQ_TYPE(cqe)) {
  101. le.qid = wq->sq.qid;
  102. le.opcode = CQE_OPCODE(cqe);
  103. le.post_host_ts = wq->sq.sw_sq[wq->sq.cidx].host_ts;
  104. le.post_sge_ts = wq->sq.sw_sq[wq->sq.cidx].sge_ts;
  105. le.wr_id = CQE_WRID_SQ_IDX(cqe);
  106. } else {
  107. le.qid = wq->rq.qid;
  108. le.opcode = FW_RI_RECEIVE;
  109. le.post_host_ts = wq->rq.sw_rq[wq->rq.cidx].host_ts;
  110. le.post_sge_ts = wq->rq.sw_rq[wq->rq.cidx].sge_ts;
  111. le.wr_id = CQE_WRID_MSN(cqe);
  112. }
  113. wq->rdev->wr_log[idx] = le;
  114. }
  115. static int wr_log_show(struct seq_file *seq, void *v)
  116. {
  117. struct c4iw_dev *dev = seq->private;
  118. struct timespec prev_ts = {0, 0};
  119. struct wr_log_entry *lep;
  120. int prev_ts_set = 0;
  121. int idx, end;
  122. #define ts2ns(ts) div64_u64((ts) * dev->rdev.lldi.cclk_ps, 1000)
  123. idx = atomic_read(&dev->rdev.wr_log_idx) &
  124. (dev->rdev.wr_log_size - 1);
  125. end = idx - 1;
  126. if (end < 0)
  127. end = dev->rdev.wr_log_size - 1;
  128. lep = &dev->rdev.wr_log[idx];
  129. while (idx != end) {
  130. if (lep->valid) {
  131. if (!prev_ts_set) {
  132. prev_ts_set = 1;
  133. prev_ts = lep->poll_host_ts;
  134. }
  135. seq_printf(seq, "%04u: sec %lu nsec %lu qid %u opcode "
  136. "%u %s 0x%x host_wr_delta sec %lu nsec %lu "
  137. "post_sge_ts 0x%llx cqe_sge_ts 0x%llx "
  138. "poll_sge_ts 0x%llx post_poll_delta_ns %llu "
  139. "cqe_poll_delta_ns %llu\n",
  140. idx,
  141. timespec_sub(lep->poll_host_ts,
  142. prev_ts).tv_sec,
  143. timespec_sub(lep->poll_host_ts,
  144. prev_ts).tv_nsec,
  145. lep->qid, lep->opcode,
  146. lep->opcode == FW_RI_RECEIVE ?
  147. "msn" : "wrid",
  148. lep->wr_id,
  149. timespec_sub(lep->poll_host_ts,
  150. lep->post_host_ts).tv_sec,
  151. timespec_sub(lep->poll_host_ts,
  152. lep->post_host_ts).tv_nsec,
  153. lep->post_sge_ts, lep->cqe_sge_ts,
  154. lep->poll_sge_ts,
  155. ts2ns(lep->poll_sge_ts - lep->post_sge_ts),
  156. ts2ns(lep->poll_sge_ts - lep->cqe_sge_ts));
  157. prev_ts = lep->poll_host_ts;
  158. }
  159. idx++;
  160. if (idx > (dev->rdev.wr_log_size - 1))
  161. idx = 0;
  162. lep = &dev->rdev.wr_log[idx];
  163. }
  164. #undef ts2ns
  165. return 0;
  166. }
  167. static int wr_log_open(struct inode *inode, struct file *file)
  168. {
  169. return single_open(file, wr_log_show, inode->i_private);
  170. }
  171. static ssize_t wr_log_clear(struct file *file, const char __user *buf,
  172. size_t count, loff_t *pos)
  173. {
  174. struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private;
  175. int i;
  176. if (dev->rdev.wr_log)
  177. for (i = 0; i < dev->rdev.wr_log_size; i++)
  178. dev->rdev.wr_log[i].valid = 0;
  179. return count;
  180. }
  181. static const struct file_operations wr_log_debugfs_fops = {
  182. .owner = THIS_MODULE,
  183. .open = wr_log_open,
  184. .release = single_release,
  185. .read = seq_read,
  186. .llseek = seq_lseek,
  187. .write = wr_log_clear,
  188. };
  189. static struct sockaddr_in zero_sin = {
  190. .sin_family = AF_INET,
  191. };
  192. static struct sockaddr_in6 zero_sin6 = {
  193. .sin6_family = AF_INET6,
  194. };
  195. static void set_ep_sin_addrs(struct c4iw_ep *ep,
  196. struct sockaddr_in **lsin,
  197. struct sockaddr_in **rsin,
  198. struct sockaddr_in **m_lsin,
  199. struct sockaddr_in **m_rsin)
  200. {
  201. struct iw_cm_id *id = ep->com.cm_id;
  202. *lsin = (struct sockaddr_in *)&ep->com.local_addr;
  203. *rsin = (struct sockaddr_in *)&ep->com.remote_addr;
  204. if (id) {
  205. *m_lsin = (struct sockaddr_in *)&id->m_local_addr;
  206. *m_rsin = (struct sockaddr_in *)&id->m_remote_addr;
  207. } else {
  208. *m_lsin = &zero_sin;
  209. *m_rsin = &zero_sin;
  210. }
  211. }
  212. static void set_ep_sin6_addrs(struct c4iw_ep *ep,
  213. struct sockaddr_in6 **lsin6,
  214. struct sockaddr_in6 **rsin6,
  215. struct sockaddr_in6 **m_lsin6,
  216. struct sockaddr_in6 **m_rsin6)
  217. {
  218. struct iw_cm_id *id = ep->com.cm_id;
  219. *lsin6 = (struct sockaddr_in6 *)&ep->com.local_addr;
  220. *rsin6 = (struct sockaddr_in6 *)&ep->com.remote_addr;
  221. if (id) {
  222. *m_lsin6 = (struct sockaddr_in6 *)&id->m_local_addr;
  223. *m_rsin6 = (struct sockaddr_in6 *)&id->m_remote_addr;
  224. } else {
  225. *m_lsin6 = &zero_sin6;
  226. *m_rsin6 = &zero_sin6;
  227. }
  228. }
  229. static int dump_qp(int id, void *p, void *data)
  230. {
  231. struct c4iw_qp *qp = p;
  232. struct c4iw_debugfs_data *qpd = data;
  233. int space;
  234. int cc;
  235. if (id != qp->wq.sq.qid)
  236. return 0;
  237. space = qpd->bufsize - qpd->pos - 1;
  238. if (space == 0)
  239. return 1;
  240. if (qp->ep) {
  241. struct c4iw_ep *ep = qp->ep;
  242. if (ep->com.local_addr.ss_family == AF_INET) {
  243. struct sockaddr_in *lsin;
  244. struct sockaddr_in *rsin;
  245. struct sockaddr_in *m_lsin;
  246. struct sockaddr_in *m_rsin;
  247. set_ep_sin_addrs(ep, &lsin, &rsin, &m_lsin, &m_rsin);
  248. cc = snprintf(qpd->buf + qpd->pos, space,
  249. "rc qp sq id %u rq id %u state %u "
  250. "onchip %u ep tid %u state %u "
  251. "%pI4:%u/%u->%pI4:%u/%u\n",
  252. qp->wq.sq.qid, qp->wq.rq.qid,
  253. (int)qp->attr.state,
  254. qp->wq.sq.flags & T4_SQ_ONCHIP,
  255. ep->hwtid, (int)ep->com.state,
  256. &lsin->sin_addr, ntohs(lsin->sin_port),
  257. ntohs(m_lsin->sin_port),
  258. &rsin->sin_addr, ntohs(rsin->sin_port),
  259. ntohs(m_rsin->sin_port));
  260. } else {
  261. struct sockaddr_in6 *lsin6;
  262. struct sockaddr_in6 *rsin6;
  263. struct sockaddr_in6 *m_lsin6;
  264. struct sockaddr_in6 *m_rsin6;
  265. set_ep_sin6_addrs(ep, &lsin6, &rsin6, &m_lsin6,
  266. &m_rsin6);
  267. cc = snprintf(qpd->buf + qpd->pos, space,
  268. "rc qp sq id %u rq id %u state %u "
  269. "onchip %u ep tid %u state %u "
  270. "%pI6:%u/%u->%pI6:%u/%u\n",
  271. qp->wq.sq.qid, qp->wq.rq.qid,
  272. (int)qp->attr.state,
  273. qp->wq.sq.flags & T4_SQ_ONCHIP,
  274. ep->hwtid, (int)ep->com.state,
  275. &lsin6->sin6_addr,
  276. ntohs(lsin6->sin6_port),
  277. ntohs(m_lsin6->sin6_port),
  278. &rsin6->sin6_addr,
  279. ntohs(rsin6->sin6_port),
  280. ntohs(m_rsin6->sin6_port));
  281. }
  282. } else
  283. cc = snprintf(qpd->buf + qpd->pos, space,
  284. "qp sq id %u rq id %u state %u onchip %u\n",
  285. qp->wq.sq.qid, qp->wq.rq.qid,
  286. (int)qp->attr.state,
  287. qp->wq.sq.flags & T4_SQ_ONCHIP);
  288. if (cc < space)
  289. qpd->pos += cc;
  290. return 0;
  291. }
  292. static int qp_release(struct inode *inode, struct file *file)
  293. {
  294. struct c4iw_debugfs_data *qpd = file->private_data;
  295. if (!qpd) {
  296. pr_info("%s null qpd?\n", __func__);
  297. return 0;
  298. }
  299. vfree(qpd->buf);
  300. kfree(qpd);
  301. return 0;
  302. }
  303. static int qp_open(struct inode *inode, struct file *file)
  304. {
  305. struct c4iw_debugfs_data *qpd;
  306. int count = 1;
  307. qpd = kmalloc(sizeof *qpd, GFP_KERNEL);
  308. if (!qpd)
  309. return -ENOMEM;
  310. qpd->devp = inode->i_private;
  311. qpd->pos = 0;
  312. spin_lock_irq(&qpd->devp->lock);
  313. idr_for_each(&qpd->devp->qpidr, count_idrs, &count);
  314. spin_unlock_irq(&qpd->devp->lock);
  315. qpd->bufsize = count * 180;
  316. qpd->buf = vmalloc(qpd->bufsize);
  317. if (!qpd->buf) {
  318. kfree(qpd);
  319. return -ENOMEM;
  320. }
  321. spin_lock_irq(&qpd->devp->lock);
  322. idr_for_each(&qpd->devp->qpidr, dump_qp, qpd);
  323. spin_unlock_irq(&qpd->devp->lock);
  324. qpd->buf[qpd->pos++] = 0;
  325. file->private_data = qpd;
  326. return 0;
  327. }
  328. static const struct file_operations qp_debugfs_fops = {
  329. .owner = THIS_MODULE,
  330. .open = qp_open,
  331. .release = qp_release,
  332. .read = debugfs_read,
  333. .llseek = default_llseek,
  334. };
  335. static int dump_stag(int id, void *p, void *data)
  336. {
  337. struct c4iw_debugfs_data *stagd = data;
  338. int space;
  339. int cc;
  340. struct fw_ri_tpte tpte;
  341. int ret;
  342. space = stagd->bufsize - stagd->pos - 1;
  343. if (space == 0)
  344. return 1;
  345. ret = cxgb4_read_tpte(stagd->devp->rdev.lldi.ports[0], (u32)id<<8,
  346. (__be32 *)&tpte);
  347. if (ret) {
  348. dev_err(&stagd->devp->rdev.lldi.pdev->dev,
  349. "%s cxgb4_read_tpte err %d\n", __func__, ret);
  350. return ret;
  351. }
  352. cc = snprintf(stagd->buf + stagd->pos, space,
  353. "stag: idx 0x%x valid %d key 0x%x state %d pdid %d "
  354. "perm 0x%x ps %d len 0x%llx va 0x%llx\n",
  355. (u32)id<<8,
  356. FW_RI_TPTE_VALID_G(ntohl(tpte.valid_to_pdid)),
  357. FW_RI_TPTE_STAGKEY_G(ntohl(tpte.valid_to_pdid)),
  358. FW_RI_TPTE_STAGSTATE_G(ntohl(tpte.valid_to_pdid)),
  359. FW_RI_TPTE_PDID_G(ntohl(tpte.valid_to_pdid)),
  360. FW_RI_TPTE_PERM_G(ntohl(tpte.locread_to_qpid)),
  361. FW_RI_TPTE_PS_G(ntohl(tpte.locread_to_qpid)),
  362. ((u64)ntohl(tpte.len_hi) << 32) | ntohl(tpte.len_lo),
  363. ((u64)ntohl(tpte.va_hi) << 32) | ntohl(tpte.va_lo_fbo));
  364. if (cc < space)
  365. stagd->pos += cc;
  366. return 0;
  367. }
  368. static int stag_release(struct inode *inode, struct file *file)
  369. {
  370. struct c4iw_debugfs_data *stagd = file->private_data;
  371. if (!stagd) {
  372. pr_info("%s null stagd?\n", __func__);
  373. return 0;
  374. }
  375. vfree(stagd->buf);
  376. kfree(stagd);
  377. return 0;
  378. }
  379. static int stag_open(struct inode *inode, struct file *file)
  380. {
  381. struct c4iw_debugfs_data *stagd;
  382. int ret = 0;
  383. int count = 1;
  384. stagd = kmalloc(sizeof *stagd, GFP_KERNEL);
  385. if (!stagd) {
  386. ret = -ENOMEM;
  387. goto out;
  388. }
  389. stagd->devp = inode->i_private;
  390. stagd->pos = 0;
  391. spin_lock_irq(&stagd->devp->lock);
  392. idr_for_each(&stagd->devp->mmidr, count_idrs, &count);
  393. spin_unlock_irq(&stagd->devp->lock);
  394. stagd->bufsize = count * 256;
  395. stagd->buf = vmalloc(stagd->bufsize);
  396. if (!stagd->buf) {
  397. ret = -ENOMEM;
  398. goto err1;
  399. }
  400. spin_lock_irq(&stagd->devp->lock);
  401. idr_for_each(&stagd->devp->mmidr, dump_stag, stagd);
  402. spin_unlock_irq(&stagd->devp->lock);
  403. stagd->buf[stagd->pos++] = 0;
  404. file->private_data = stagd;
  405. goto out;
  406. err1:
  407. kfree(stagd);
  408. out:
  409. return ret;
  410. }
  411. static const struct file_operations stag_debugfs_fops = {
  412. .owner = THIS_MODULE,
  413. .open = stag_open,
  414. .release = stag_release,
  415. .read = debugfs_read,
  416. .llseek = default_llseek,
  417. };
  418. static char *db_state_str[] = {"NORMAL", "FLOW_CONTROL", "RECOVERY", "STOPPED"};
  419. static int stats_show(struct seq_file *seq, void *v)
  420. {
  421. struct c4iw_dev *dev = seq->private;
  422. seq_printf(seq, " Object: %10s %10s %10s %10s\n", "Total", "Current",
  423. "Max", "Fail");
  424. seq_printf(seq, " PDID: %10llu %10llu %10llu %10llu\n",
  425. dev->rdev.stats.pd.total, dev->rdev.stats.pd.cur,
  426. dev->rdev.stats.pd.max, dev->rdev.stats.pd.fail);
  427. seq_printf(seq, " QID: %10llu %10llu %10llu %10llu\n",
  428. dev->rdev.stats.qid.total, dev->rdev.stats.qid.cur,
  429. dev->rdev.stats.qid.max, dev->rdev.stats.qid.fail);
  430. seq_printf(seq, " TPTMEM: %10llu %10llu %10llu %10llu\n",
  431. dev->rdev.stats.stag.total, dev->rdev.stats.stag.cur,
  432. dev->rdev.stats.stag.max, dev->rdev.stats.stag.fail);
  433. seq_printf(seq, " PBLMEM: %10llu %10llu %10llu %10llu\n",
  434. dev->rdev.stats.pbl.total, dev->rdev.stats.pbl.cur,
  435. dev->rdev.stats.pbl.max, dev->rdev.stats.pbl.fail);
  436. seq_printf(seq, " RQTMEM: %10llu %10llu %10llu %10llu\n",
  437. dev->rdev.stats.rqt.total, dev->rdev.stats.rqt.cur,
  438. dev->rdev.stats.rqt.max, dev->rdev.stats.rqt.fail);
  439. seq_printf(seq, " OCQPMEM: %10llu %10llu %10llu %10llu\n",
  440. dev->rdev.stats.ocqp.total, dev->rdev.stats.ocqp.cur,
  441. dev->rdev.stats.ocqp.max, dev->rdev.stats.ocqp.fail);
  442. seq_printf(seq, " DB FULL: %10llu\n", dev->rdev.stats.db_full);
  443. seq_printf(seq, " DB EMPTY: %10llu\n", dev->rdev.stats.db_empty);
  444. seq_printf(seq, " DB DROP: %10llu\n", dev->rdev.stats.db_drop);
  445. seq_printf(seq, " DB State: %s Transitions %llu FC Interruptions %llu\n",
  446. db_state_str[dev->db_state],
  447. dev->rdev.stats.db_state_transitions,
  448. dev->rdev.stats.db_fc_interruptions);
  449. seq_printf(seq, "TCAM_FULL: %10llu\n", dev->rdev.stats.tcam_full);
  450. seq_printf(seq, "ACT_OFLD_CONN_FAILS: %10llu\n",
  451. dev->rdev.stats.act_ofld_conn_fails);
  452. seq_printf(seq, "PAS_OFLD_CONN_FAILS: %10llu\n",
  453. dev->rdev.stats.pas_ofld_conn_fails);
  454. seq_printf(seq, "NEG_ADV_RCVD: %10llu\n", dev->rdev.stats.neg_adv);
  455. seq_printf(seq, "AVAILABLE IRD: %10u\n", dev->avail_ird);
  456. return 0;
  457. }
  458. static int stats_open(struct inode *inode, struct file *file)
  459. {
  460. return single_open(file, stats_show, inode->i_private);
  461. }
  462. static ssize_t stats_clear(struct file *file, const char __user *buf,
  463. size_t count, loff_t *pos)
  464. {
  465. struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private;
  466. mutex_lock(&dev->rdev.stats.lock);
  467. dev->rdev.stats.pd.max = 0;
  468. dev->rdev.stats.pd.fail = 0;
  469. dev->rdev.stats.qid.max = 0;
  470. dev->rdev.stats.qid.fail = 0;
  471. dev->rdev.stats.stag.max = 0;
  472. dev->rdev.stats.stag.fail = 0;
  473. dev->rdev.stats.pbl.max = 0;
  474. dev->rdev.stats.pbl.fail = 0;
  475. dev->rdev.stats.rqt.max = 0;
  476. dev->rdev.stats.rqt.fail = 0;
  477. dev->rdev.stats.ocqp.max = 0;
  478. dev->rdev.stats.ocqp.fail = 0;
  479. dev->rdev.stats.db_full = 0;
  480. dev->rdev.stats.db_empty = 0;
  481. dev->rdev.stats.db_drop = 0;
  482. dev->rdev.stats.db_state_transitions = 0;
  483. dev->rdev.stats.tcam_full = 0;
  484. dev->rdev.stats.act_ofld_conn_fails = 0;
  485. dev->rdev.stats.pas_ofld_conn_fails = 0;
  486. mutex_unlock(&dev->rdev.stats.lock);
  487. return count;
  488. }
  489. static const struct file_operations stats_debugfs_fops = {
  490. .owner = THIS_MODULE,
  491. .open = stats_open,
  492. .release = single_release,
  493. .read = seq_read,
  494. .llseek = seq_lseek,
  495. .write = stats_clear,
  496. };
  497. static int dump_ep(int id, void *p, void *data)
  498. {
  499. struct c4iw_ep *ep = p;
  500. struct c4iw_debugfs_data *epd = data;
  501. int space;
  502. int cc;
  503. space = epd->bufsize - epd->pos - 1;
  504. if (space == 0)
  505. return 1;
  506. if (ep->com.local_addr.ss_family == AF_INET) {
  507. struct sockaddr_in *lsin;
  508. struct sockaddr_in *rsin;
  509. struct sockaddr_in *m_lsin;
  510. struct sockaddr_in *m_rsin;
  511. set_ep_sin_addrs(ep, &lsin, &rsin, &m_lsin, &m_rsin);
  512. cc = snprintf(epd->buf + epd->pos, space,
  513. "ep %p cm_id %p qp %p state %d flags 0x%lx "
  514. "history 0x%lx hwtid %d atid %d "
  515. "conn_na %u abort_na %u "
  516. "%pI4:%d/%d <-> %pI4:%d/%d\n",
  517. ep, ep->com.cm_id, ep->com.qp,
  518. (int)ep->com.state, ep->com.flags,
  519. ep->com.history, ep->hwtid, ep->atid,
  520. ep->stats.connect_neg_adv,
  521. ep->stats.abort_neg_adv,
  522. &lsin->sin_addr, ntohs(lsin->sin_port),
  523. ntohs(m_lsin->sin_port),
  524. &rsin->sin_addr, ntohs(rsin->sin_port),
  525. ntohs(m_rsin->sin_port));
  526. } else {
  527. struct sockaddr_in6 *lsin6;
  528. struct sockaddr_in6 *rsin6;
  529. struct sockaddr_in6 *m_lsin6;
  530. struct sockaddr_in6 *m_rsin6;
  531. set_ep_sin6_addrs(ep, &lsin6, &rsin6, &m_lsin6, &m_rsin6);
  532. cc = snprintf(epd->buf + epd->pos, space,
  533. "ep %p cm_id %p qp %p state %d flags 0x%lx "
  534. "history 0x%lx hwtid %d atid %d "
  535. "conn_na %u abort_na %u "
  536. "%pI6:%d/%d <-> %pI6:%d/%d\n",
  537. ep, ep->com.cm_id, ep->com.qp,
  538. (int)ep->com.state, ep->com.flags,
  539. ep->com.history, ep->hwtid, ep->atid,
  540. ep->stats.connect_neg_adv,
  541. ep->stats.abort_neg_adv,
  542. &lsin6->sin6_addr, ntohs(lsin6->sin6_port),
  543. ntohs(m_lsin6->sin6_port),
  544. &rsin6->sin6_addr, ntohs(rsin6->sin6_port),
  545. ntohs(m_rsin6->sin6_port));
  546. }
  547. if (cc < space)
  548. epd->pos += cc;
  549. return 0;
  550. }
  551. static int dump_listen_ep(int id, void *p, void *data)
  552. {
  553. struct c4iw_listen_ep *ep = p;
  554. struct c4iw_debugfs_data *epd = data;
  555. int space;
  556. int cc;
  557. space = epd->bufsize - epd->pos - 1;
  558. if (space == 0)
  559. return 1;
  560. if (ep->com.local_addr.ss_family == AF_INET) {
  561. struct sockaddr_in *lsin = (struct sockaddr_in *)
  562. &ep->com.cm_id->local_addr;
  563. struct sockaddr_in *m_lsin = (struct sockaddr_in *)
  564. &ep->com.cm_id->m_local_addr;
  565. cc = snprintf(epd->buf + epd->pos, space,
  566. "ep %p cm_id %p state %d flags 0x%lx stid %d "
  567. "backlog %d %pI4:%d/%d\n",
  568. ep, ep->com.cm_id, (int)ep->com.state,
  569. ep->com.flags, ep->stid, ep->backlog,
  570. &lsin->sin_addr, ntohs(lsin->sin_port),
  571. ntohs(m_lsin->sin_port));
  572. } else {
  573. struct sockaddr_in6 *lsin6 = (struct sockaddr_in6 *)
  574. &ep->com.cm_id->local_addr;
  575. struct sockaddr_in6 *m_lsin6 = (struct sockaddr_in6 *)
  576. &ep->com.cm_id->m_local_addr;
  577. cc = snprintf(epd->buf + epd->pos, space,
  578. "ep %p cm_id %p state %d flags 0x%lx stid %d "
  579. "backlog %d %pI6:%d/%d\n",
  580. ep, ep->com.cm_id, (int)ep->com.state,
  581. ep->com.flags, ep->stid, ep->backlog,
  582. &lsin6->sin6_addr, ntohs(lsin6->sin6_port),
  583. ntohs(m_lsin6->sin6_port));
  584. }
  585. if (cc < space)
  586. epd->pos += cc;
  587. return 0;
  588. }
  589. static int ep_release(struct inode *inode, struct file *file)
  590. {
  591. struct c4iw_debugfs_data *epd = file->private_data;
  592. if (!epd) {
  593. pr_info("%s null qpd?\n", __func__);
  594. return 0;
  595. }
  596. vfree(epd->buf);
  597. kfree(epd);
  598. return 0;
  599. }
  600. static int ep_open(struct inode *inode, struct file *file)
  601. {
  602. struct c4iw_debugfs_data *epd;
  603. int ret = 0;
  604. int count = 1;
  605. epd = kmalloc(sizeof(*epd), GFP_KERNEL);
  606. if (!epd) {
  607. ret = -ENOMEM;
  608. goto out;
  609. }
  610. epd->devp = inode->i_private;
  611. epd->pos = 0;
  612. spin_lock_irq(&epd->devp->lock);
  613. idr_for_each(&epd->devp->hwtid_idr, count_idrs, &count);
  614. idr_for_each(&epd->devp->atid_idr, count_idrs, &count);
  615. idr_for_each(&epd->devp->stid_idr, count_idrs, &count);
  616. spin_unlock_irq(&epd->devp->lock);
  617. epd->bufsize = count * 240;
  618. epd->buf = vmalloc(epd->bufsize);
  619. if (!epd->buf) {
  620. ret = -ENOMEM;
  621. goto err1;
  622. }
  623. spin_lock_irq(&epd->devp->lock);
  624. idr_for_each(&epd->devp->hwtid_idr, dump_ep, epd);
  625. idr_for_each(&epd->devp->atid_idr, dump_ep, epd);
  626. idr_for_each(&epd->devp->stid_idr, dump_listen_ep, epd);
  627. spin_unlock_irq(&epd->devp->lock);
  628. file->private_data = epd;
  629. goto out;
  630. err1:
  631. kfree(epd);
  632. out:
  633. return ret;
  634. }
  635. static const struct file_operations ep_debugfs_fops = {
  636. .owner = THIS_MODULE,
  637. .open = ep_open,
  638. .release = ep_release,
  639. .read = debugfs_read,
  640. };
  641. static int setup_debugfs(struct c4iw_dev *devp)
  642. {
  643. if (!devp->debugfs_root)
  644. return -1;
  645. debugfs_create_file_size("qps", S_IWUSR, devp->debugfs_root,
  646. (void *)devp, &qp_debugfs_fops, 4096);
  647. debugfs_create_file_size("stags", S_IWUSR, devp->debugfs_root,
  648. (void *)devp, &stag_debugfs_fops, 4096);
  649. debugfs_create_file_size("stats", S_IWUSR, devp->debugfs_root,
  650. (void *)devp, &stats_debugfs_fops, 4096);
  651. debugfs_create_file_size("eps", S_IWUSR, devp->debugfs_root,
  652. (void *)devp, &ep_debugfs_fops, 4096);
  653. if (c4iw_wr_log)
  654. debugfs_create_file_size("wr_log", S_IWUSR, devp->debugfs_root,
  655. (void *)devp, &wr_log_debugfs_fops, 4096);
  656. return 0;
  657. }
  658. void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
  659. struct c4iw_dev_ucontext *uctx)
  660. {
  661. struct list_head *pos, *nxt;
  662. struct c4iw_qid_list *entry;
  663. mutex_lock(&uctx->lock);
  664. list_for_each_safe(pos, nxt, &uctx->qpids) {
  665. entry = list_entry(pos, struct c4iw_qid_list, entry);
  666. list_del_init(&entry->entry);
  667. if (!(entry->qid & rdev->qpmask)) {
  668. c4iw_put_resource(&rdev->resource.qid_table,
  669. entry->qid);
  670. mutex_lock(&rdev->stats.lock);
  671. rdev->stats.qid.cur -= rdev->qpmask + 1;
  672. mutex_unlock(&rdev->stats.lock);
  673. }
  674. kfree(entry);
  675. }
  676. list_for_each_safe(pos, nxt, &uctx->qpids) {
  677. entry = list_entry(pos, struct c4iw_qid_list, entry);
  678. list_del_init(&entry->entry);
  679. kfree(entry);
  680. }
  681. mutex_unlock(&uctx->lock);
  682. }
  683. void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
  684. struct c4iw_dev_ucontext *uctx)
  685. {
  686. INIT_LIST_HEAD(&uctx->qpids);
  687. INIT_LIST_HEAD(&uctx->cqids);
  688. mutex_init(&uctx->lock);
  689. }
  690. /* Caller takes care of locking if needed */
  691. static int c4iw_rdev_open(struct c4iw_rdev *rdev)
  692. {
  693. int err;
  694. c4iw_init_dev_ucontext(rdev, &rdev->uctx);
  695. /*
  696. * This implementation assumes udb_density == ucq_density! Eventually
  697. * we might need to support this but for now fail the open. Also the
  698. * cqid and qpid range must match for now.
  699. */
  700. if (rdev->lldi.udb_density != rdev->lldi.ucq_density) {
  701. pr_err("%s: unsupported udb/ucq densities %u/%u\n",
  702. pci_name(rdev->lldi.pdev), rdev->lldi.udb_density,
  703. rdev->lldi.ucq_density);
  704. return -EINVAL;
  705. }
  706. if (rdev->lldi.vr->qp.start != rdev->lldi.vr->cq.start ||
  707. rdev->lldi.vr->qp.size != rdev->lldi.vr->cq.size) {
  708. pr_err("%s: unsupported qp and cq id ranges qp start %u size %u cq start %u size %u\n",
  709. pci_name(rdev->lldi.pdev), rdev->lldi.vr->qp.start,
  710. rdev->lldi.vr->qp.size, rdev->lldi.vr->cq.size,
  711. rdev->lldi.vr->cq.size);
  712. return -EINVAL;
  713. }
  714. rdev->qpmask = rdev->lldi.udb_density - 1;
  715. rdev->cqmask = rdev->lldi.ucq_density - 1;
  716. pr_debug("%s dev %s stag start 0x%0x size 0x%0x num stags %d pbl start 0x%0x size 0x%0x rq start 0x%0x size 0x%0x qp qid start %u size %u cq qid start %u size %u\n",
  717. __func__, pci_name(rdev->lldi.pdev), rdev->lldi.vr->stag.start,
  718. rdev->lldi.vr->stag.size, c4iw_num_stags(rdev),
  719. rdev->lldi.vr->pbl.start,
  720. rdev->lldi.vr->pbl.size, rdev->lldi.vr->rq.start,
  721. rdev->lldi.vr->rq.size,
  722. rdev->lldi.vr->qp.start,
  723. rdev->lldi.vr->qp.size,
  724. rdev->lldi.vr->cq.start,
  725. rdev->lldi.vr->cq.size);
  726. pr_debug("udb %pR db_reg %p gts_reg %p qpmask 0x%x cqmask 0x%x\n",
  727. &rdev->lldi.pdev->resource[2],
  728. rdev->lldi.db_reg, rdev->lldi.gts_reg,
  729. rdev->qpmask, rdev->cqmask);
  730. if (c4iw_num_stags(rdev) == 0)
  731. return -EINVAL;
  732. rdev->stats.pd.total = T4_MAX_NUM_PD;
  733. rdev->stats.stag.total = rdev->lldi.vr->stag.size;
  734. rdev->stats.pbl.total = rdev->lldi.vr->pbl.size;
  735. rdev->stats.rqt.total = rdev->lldi.vr->rq.size;
  736. rdev->stats.ocqp.total = rdev->lldi.vr->ocq.size;
  737. rdev->stats.qid.total = rdev->lldi.vr->qp.size;
  738. err = c4iw_init_resource(rdev, c4iw_num_stags(rdev), T4_MAX_NUM_PD);
  739. if (err) {
  740. pr_err("error %d initializing resources\n", err);
  741. return err;
  742. }
  743. err = c4iw_pblpool_create(rdev);
  744. if (err) {
  745. pr_err("error %d initializing pbl pool\n", err);
  746. goto destroy_resource;
  747. }
  748. err = c4iw_rqtpool_create(rdev);
  749. if (err) {
  750. pr_err("error %d initializing rqt pool\n", err);
  751. goto destroy_pblpool;
  752. }
  753. err = c4iw_ocqp_pool_create(rdev);
  754. if (err) {
  755. pr_err("error %d initializing ocqp pool\n", err);
  756. goto destroy_rqtpool;
  757. }
  758. rdev->status_page = (struct t4_dev_status_page *)
  759. __get_free_page(GFP_KERNEL);
  760. if (!rdev->status_page) {
  761. err = -ENOMEM;
  762. goto destroy_ocqp_pool;
  763. }
  764. rdev->status_page->qp_start = rdev->lldi.vr->qp.start;
  765. rdev->status_page->qp_size = rdev->lldi.vr->qp.size;
  766. rdev->status_page->cq_start = rdev->lldi.vr->cq.start;
  767. rdev->status_page->cq_size = rdev->lldi.vr->cq.size;
  768. if (c4iw_wr_log) {
  769. rdev->wr_log = kzalloc((1 << c4iw_wr_log_size_order) *
  770. sizeof(*rdev->wr_log), GFP_KERNEL);
  771. if (rdev->wr_log) {
  772. rdev->wr_log_size = 1 << c4iw_wr_log_size_order;
  773. atomic_set(&rdev->wr_log_idx, 0);
  774. }
  775. }
  776. rdev->free_workq = create_singlethread_workqueue("iw_cxgb4_free");
  777. if (!rdev->free_workq) {
  778. err = -ENOMEM;
  779. goto err_free_status_page;
  780. }
  781. rdev->status_page->db_off = 0;
  782. return 0;
  783. err_free_status_page:
  784. free_page((unsigned long)rdev->status_page);
  785. destroy_ocqp_pool:
  786. c4iw_ocqp_pool_destroy(rdev);
  787. destroy_rqtpool:
  788. c4iw_rqtpool_destroy(rdev);
  789. destroy_pblpool:
  790. c4iw_pblpool_destroy(rdev);
  791. destroy_resource:
  792. c4iw_destroy_resource(&rdev->resource);
  793. return err;
  794. }
  795. static void c4iw_rdev_close(struct c4iw_rdev *rdev)
  796. {
  797. destroy_workqueue(rdev->free_workq);
  798. kfree(rdev->wr_log);
  799. free_page((unsigned long)rdev->status_page);
  800. c4iw_pblpool_destroy(rdev);
  801. c4iw_rqtpool_destroy(rdev);
  802. c4iw_destroy_resource(&rdev->resource);
  803. }
  804. static void c4iw_dealloc(struct uld_ctx *ctx)
  805. {
  806. c4iw_rdev_close(&ctx->dev->rdev);
  807. WARN_ON_ONCE(!idr_is_empty(&ctx->dev->cqidr));
  808. idr_destroy(&ctx->dev->cqidr);
  809. WARN_ON_ONCE(!idr_is_empty(&ctx->dev->qpidr));
  810. idr_destroy(&ctx->dev->qpidr);
  811. WARN_ON_ONCE(!idr_is_empty(&ctx->dev->mmidr));
  812. idr_destroy(&ctx->dev->mmidr);
  813. wait_event(ctx->dev->wait, idr_is_empty(&ctx->dev->hwtid_idr));
  814. idr_destroy(&ctx->dev->hwtid_idr);
  815. idr_destroy(&ctx->dev->stid_idr);
  816. idr_destroy(&ctx->dev->atid_idr);
  817. if (ctx->dev->rdev.bar2_kva)
  818. iounmap(ctx->dev->rdev.bar2_kva);
  819. if (ctx->dev->rdev.oc_mw_kva)
  820. iounmap(ctx->dev->rdev.oc_mw_kva);
  821. ib_dealloc_device(&ctx->dev->ibdev);
  822. ctx->dev = NULL;
  823. }
  824. static void c4iw_remove(struct uld_ctx *ctx)
  825. {
  826. pr_debug("%s c4iw_dev %p\n", __func__, ctx->dev);
  827. c4iw_unregister_device(ctx->dev);
  828. c4iw_dealloc(ctx);
  829. }
  830. static int rdma_supported(const struct cxgb4_lld_info *infop)
  831. {
  832. return infop->vr->stag.size > 0 && infop->vr->pbl.size > 0 &&
  833. infop->vr->rq.size > 0 && infop->vr->qp.size > 0 &&
  834. infop->vr->cq.size > 0;
  835. }
  836. static struct c4iw_dev *c4iw_alloc(const struct cxgb4_lld_info *infop)
  837. {
  838. struct c4iw_dev *devp;
  839. int ret;
  840. if (!rdma_supported(infop)) {
  841. pr_info("%s: RDMA not supported on this device\n",
  842. pci_name(infop->pdev));
  843. return ERR_PTR(-ENOSYS);
  844. }
  845. if (!ocqp_supported(infop))
  846. pr_info("%s: On-Chip Queues not supported on this device\n",
  847. pci_name(infop->pdev));
  848. devp = (struct c4iw_dev *)ib_alloc_device(sizeof(*devp));
  849. if (!devp) {
  850. pr_err("Cannot allocate ib device\n");
  851. return ERR_PTR(-ENOMEM);
  852. }
  853. devp->rdev.lldi = *infop;
  854. /* init various hw-queue params based on lld info */
  855. pr_debug("%s: Ing. padding boundary is %d, egrsstatuspagesize = %d\n",
  856. __func__, devp->rdev.lldi.sge_ingpadboundary,
  857. devp->rdev.lldi.sge_egrstatuspagesize);
  858. devp->rdev.hw_queue.t4_eq_status_entries =
  859. devp->rdev.lldi.sge_egrstatuspagesize / 64;
  860. devp->rdev.hw_queue.t4_max_eq_size = 65520;
  861. devp->rdev.hw_queue.t4_max_iq_size = 65520;
  862. devp->rdev.hw_queue.t4_max_rq_size = 8192 -
  863. devp->rdev.hw_queue.t4_eq_status_entries - 1;
  864. devp->rdev.hw_queue.t4_max_sq_size =
  865. devp->rdev.hw_queue.t4_max_eq_size -
  866. devp->rdev.hw_queue.t4_eq_status_entries - 1;
  867. devp->rdev.hw_queue.t4_max_qp_depth =
  868. devp->rdev.hw_queue.t4_max_rq_size;
  869. devp->rdev.hw_queue.t4_max_cq_depth =
  870. devp->rdev.hw_queue.t4_max_iq_size - 2;
  871. devp->rdev.hw_queue.t4_stat_len =
  872. devp->rdev.lldi.sge_egrstatuspagesize;
  873. /*
  874. * For T5/T6 devices, we map all of BAR2 with WC.
  875. * For T4 devices with onchip qp mem, we map only that part
  876. * of BAR2 with WC.
  877. */
  878. devp->rdev.bar2_pa = pci_resource_start(devp->rdev.lldi.pdev, 2);
  879. if (!is_t4(devp->rdev.lldi.adapter_type)) {
  880. devp->rdev.bar2_kva = ioremap_wc(devp->rdev.bar2_pa,
  881. pci_resource_len(devp->rdev.lldi.pdev, 2));
  882. if (!devp->rdev.bar2_kva) {
  883. pr_err("Unable to ioremap BAR2\n");
  884. ib_dealloc_device(&devp->ibdev);
  885. return ERR_PTR(-EINVAL);
  886. }
  887. } else if (ocqp_supported(infop)) {
  888. devp->rdev.oc_mw_pa =
  889. pci_resource_start(devp->rdev.lldi.pdev, 2) +
  890. pci_resource_len(devp->rdev.lldi.pdev, 2) -
  891. roundup_pow_of_two(devp->rdev.lldi.vr->ocq.size);
  892. devp->rdev.oc_mw_kva = ioremap_wc(devp->rdev.oc_mw_pa,
  893. devp->rdev.lldi.vr->ocq.size);
  894. if (!devp->rdev.oc_mw_kva) {
  895. pr_err("Unable to ioremap onchip mem\n");
  896. ib_dealloc_device(&devp->ibdev);
  897. return ERR_PTR(-EINVAL);
  898. }
  899. }
  900. pr_debug("ocq memory: hw_start 0x%x size %u mw_pa 0x%lx mw_kva %p\n",
  901. devp->rdev.lldi.vr->ocq.start, devp->rdev.lldi.vr->ocq.size,
  902. devp->rdev.oc_mw_pa, devp->rdev.oc_mw_kva);
  903. ret = c4iw_rdev_open(&devp->rdev);
  904. if (ret) {
  905. pr_err("Unable to open CXIO rdev err %d\n", ret);
  906. ib_dealloc_device(&devp->ibdev);
  907. return ERR_PTR(ret);
  908. }
  909. idr_init(&devp->cqidr);
  910. idr_init(&devp->qpidr);
  911. idr_init(&devp->mmidr);
  912. idr_init(&devp->hwtid_idr);
  913. idr_init(&devp->stid_idr);
  914. idr_init(&devp->atid_idr);
  915. spin_lock_init(&devp->lock);
  916. mutex_init(&devp->rdev.stats.lock);
  917. mutex_init(&devp->db_mutex);
  918. INIT_LIST_HEAD(&devp->db_fc_list);
  919. init_waitqueue_head(&devp->wait);
  920. devp->avail_ird = devp->rdev.lldi.max_ird_adapter;
  921. if (c4iw_debugfs_root) {
  922. devp->debugfs_root = debugfs_create_dir(
  923. pci_name(devp->rdev.lldi.pdev),
  924. c4iw_debugfs_root);
  925. setup_debugfs(devp);
  926. }
  927. return devp;
  928. }
  929. static void *c4iw_uld_add(const struct cxgb4_lld_info *infop)
  930. {
  931. struct uld_ctx *ctx;
  932. static int vers_printed;
  933. int i;
  934. if (!vers_printed++)
  935. pr_info("Chelsio T4/T5 RDMA Driver - version %s\n",
  936. DRV_VERSION);
  937. ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
  938. if (!ctx) {
  939. ctx = ERR_PTR(-ENOMEM);
  940. goto out;
  941. }
  942. ctx->lldi = *infop;
  943. pr_debug("%s found device %s nchan %u nrxq %u ntxq %u nports %u\n",
  944. __func__, pci_name(ctx->lldi.pdev),
  945. ctx->lldi.nchan, ctx->lldi.nrxq,
  946. ctx->lldi.ntxq, ctx->lldi.nports);
  947. mutex_lock(&dev_mutex);
  948. list_add_tail(&ctx->entry, &uld_ctx_list);
  949. mutex_unlock(&dev_mutex);
  950. for (i = 0; i < ctx->lldi.nrxq; i++)
  951. pr_debug("rxqid[%u] %u\n", i, ctx->lldi.rxq_ids[i]);
  952. out:
  953. return ctx;
  954. }
  955. static inline struct sk_buff *copy_gl_to_skb_pkt(const struct pkt_gl *gl,
  956. const __be64 *rsp,
  957. u32 pktshift)
  958. {
  959. struct sk_buff *skb;
  960. /*
  961. * Allocate space for cpl_pass_accept_req which will be synthesized by
  962. * driver. Once the driver synthesizes the request the skb will go
  963. * through the regular cpl_pass_accept_req processing.
  964. * The math here assumes sizeof cpl_pass_accept_req >= sizeof
  965. * cpl_rx_pkt.
  966. */
  967. skb = alloc_skb(gl->tot_len + sizeof(struct cpl_pass_accept_req) +
  968. sizeof(struct rss_header) - pktshift, GFP_ATOMIC);
  969. if (unlikely(!skb))
  970. return NULL;
  971. __skb_put(skb, gl->tot_len + sizeof(struct cpl_pass_accept_req) +
  972. sizeof(struct rss_header) - pktshift);
  973. /*
  974. * This skb will contain:
  975. * rss_header from the rspq descriptor (1 flit)
  976. * cpl_rx_pkt struct from the rspq descriptor (2 flits)
  977. * space for the difference between the size of an
  978. * rx_pkt and pass_accept_req cpl (1 flit)
  979. * the packet data from the gl
  980. */
  981. skb_copy_to_linear_data(skb, rsp, sizeof(struct cpl_pass_accept_req) +
  982. sizeof(struct rss_header));
  983. skb_copy_to_linear_data_offset(skb, sizeof(struct rss_header) +
  984. sizeof(struct cpl_pass_accept_req),
  985. gl->va + pktshift,
  986. gl->tot_len - pktshift);
  987. return skb;
  988. }
  989. static inline int recv_rx_pkt(struct c4iw_dev *dev, const struct pkt_gl *gl,
  990. const __be64 *rsp)
  991. {
  992. unsigned int opcode = *(u8 *)rsp;
  993. struct sk_buff *skb;
  994. if (opcode != CPL_RX_PKT)
  995. goto out;
  996. skb = copy_gl_to_skb_pkt(gl , rsp, dev->rdev.lldi.sge_pktshift);
  997. if (skb == NULL)
  998. goto out;
  999. if (c4iw_handlers[opcode] == NULL) {
  1000. pr_info("%s no handler opcode 0x%x...\n", __func__, opcode);
  1001. kfree_skb(skb);
  1002. goto out;
  1003. }
  1004. c4iw_handlers[opcode](dev, skb);
  1005. return 1;
  1006. out:
  1007. return 0;
  1008. }
  1009. static int c4iw_uld_rx_handler(void *handle, const __be64 *rsp,
  1010. const struct pkt_gl *gl)
  1011. {
  1012. struct uld_ctx *ctx = handle;
  1013. struct c4iw_dev *dev = ctx->dev;
  1014. struct sk_buff *skb;
  1015. u8 opcode;
  1016. if (gl == NULL) {
  1017. /* omit RSS and rsp_ctrl at end of descriptor */
  1018. unsigned int len = 64 - sizeof(struct rsp_ctrl) - 8;
  1019. skb = alloc_skb(256, GFP_ATOMIC);
  1020. if (!skb)
  1021. goto nomem;
  1022. __skb_put(skb, len);
  1023. skb_copy_to_linear_data(skb, &rsp[1], len);
  1024. } else if (gl == CXGB4_MSG_AN) {
  1025. const struct rsp_ctrl *rc = (void *)rsp;
  1026. u32 qid = be32_to_cpu(rc->pldbuflen_qid);
  1027. c4iw_ev_handler(dev, qid);
  1028. return 0;
  1029. } else if (unlikely(*(u8 *)rsp != *(u8 *)gl->va)) {
  1030. if (recv_rx_pkt(dev, gl, rsp))
  1031. return 0;
  1032. pr_info("%s: unexpected FL contents at %p, RSS %#llx, FL %#llx, len %u\n",
  1033. pci_name(ctx->lldi.pdev), gl->va,
  1034. be64_to_cpu(*rsp),
  1035. be64_to_cpu(*(__force __be64 *)gl->va),
  1036. gl->tot_len);
  1037. return 0;
  1038. } else {
  1039. skb = cxgb4_pktgl_to_skb(gl, 128, 128);
  1040. if (unlikely(!skb))
  1041. goto nomem;
  1042. }
  1043. opcode = *(u8 *)rsp;
  1044. if (c4iw_handlers[opcode]) {
  1045. c4iw_handlers[opcode](dev, skb);
  1046. } else {
  1047. pr_info("%s no handler opcode 0x%x...\n", __func__, opcode);
  1048. kfree_skb(skb);
  1049. }
  1050. return 0;
  1051. nomem:
  1052. return -1;
  1053. }
  1054. static int c4iw_uld_state_change(void *handle, enum cxgb4_state new_state)
  1055. {
  1056. struct uld_ctx *ctx = handle;
  1057. pr_debug("%s new_state %u\n", __func__, new_state);
  1058. switch (new_state) {
  1059. case CXGB4_STATE_UP:
  1060. pr_info("%s: Up\n", pci_name(ctx->lldi.pdev));
  1061. if (!ctx->dev) {
  1062. int ret;
  1063. ctx->dev = c4iw_alloc(&ctx->lldi);
  1064. if (IS_ERR(ctx->dev)) {
  1065. pr_err("%s: initialization failed: %ld\n",
  1066. pci_name(ctx->lldi.pdev),
  1067. PTR_ERR(ctx->dev));
  1068. ctx->dev = NULL;
  1069. break;
  1070. }
  1071. ret = c4iw_register_device(ctx->dev);
  1072. if (ret) {
  1073. pr_err("%s: RDMA registration failed: %d\n",
  1074. pci_name(ctx->lldi.pdev), ret);
  1075. c4iw_dealloc(ctx);
  1076. }
  1077. }
  1078. break;
  1079. case CXGB4_STATE_DOWN:
  1080. pr_info("%s: Down\n", pci_name(ctx->lldi.pdev));
  1081. if (ctx->dev)
  1082. c4iw_remove(ctx);
  1083. break;
  1084. case CXGB4_STATE_START_RECOVERY:
  1085. pr_info("%s: Fatal Error\n", pci_name(ctx->lldi.pdev));
  1086. if (ctx->dev) {
  1087. struct ib_event event;
  1088. ctx->dev->rdev.flags |= T4_FATAL_ERROR;
  1089. memset(&event, 0, sizeof event);
  1090. event.event = IB_EVENT_DEVICE_FATAL;
  1091. event.device = &ctx->dev->ibdev;
  1092. ib_dispatch_event(&event);
  1093. c4iw_remove(ctx);
  1094. }
  1095. break;
  1096. case CXGB4_STATE_DETACH:
  1097. pr_info("%s: Detach\n", pci_name(ctx->lldi.pdev));
  1098. if (ctx->dev)
  1099. c4iw_remove(ctx);
  1100. break;
  1101. }
  1102. return 0;
  1103. }
  1104. static int disable_qp_db(int id, void *p, void *data)
  1105. {
  1106. struct c4iw_qp *qp = p;
  1107. t4_disable_wq_db(&qp->wq);
  1108. return 0;
  1109. }
  1110. static void stop_queues(struct uld_ctx *ctx)
  1111. {
  1112. unsigned long flags;
  1113. spin_lock_irqsave(&ctx->dev->lock, flags);
  1114. ctx->dev->rdev.stats.db_state_transitions++;
  1115. ctx->dev->db_state = STOPPED;
  1116. if (ctx->dev->rdev.flags & T4_STATUS_PAGE_DISABLED)
  1117. idr_for_each(&ctx->dev->qpidr, disable_qp_db, NULL);
  1118. else
  1119. ctx->dev->rdev.status_page->db_off = 1;
  1120. spin_unlock_irqrestore(&ctx->dev->lock, flags);
  1121. }
  1122. static int enable_qp_db(int id, void *p, void *data)
  1123. {
  1124. struct c4iw_qp *qp = p;
  1125. t4_enable_wq_db(&qp->wq);
  1126. return 0;
  1127. }
  1128. static void resume_rc_qp(struct c4iw_qp *qp)
  1129. {
  1130. spin_lock(&qp->lock);
  1131. t4_ring_sq_db(&qp->wq, qp->wq.sq.wq_pidx_inc, NULL);
  1132. qp->wq.sq.wq_pidx_inc = 0;
  1133. t4_ring_rq_db(&qp->wq, qp->wq.rq.wq_pidx_inc, NULL);
  1134. qp->wq.rq.wq_pidx_inc = 0;
  1135. spin_unlock(&qp->lock);
  1136. }
  1137. static void resume_a_chunk(struct uld_ctx *ctx)
  1138. {
  1139. int i;
  1140. struct c4iw_qp *qp;
  1141. for (i = 0; i < DB_FC_RESUME_SIZE; i++) {
  1142. qp = list_first_entry(&ctx->dev->db_fc_list, struct c4iw_qp,
  1143. db_fc_entry);
  1144. list_del_init(&qp->db_fc_entry);
  1145. resume_rc_qp(qp);
  1146. if (list_empty(&ctx->dev->db_fc_list))
  1147. break;
  1148. }
  1149. }
  1150. static void resume_queues(struct uld_ctx *ctx)
  1151. {
  1152. spin_lock_irq(&ctx->dev->lock);
  1153. if (ctx->dev->db_state != STOPPED)
  1154. goto out;
  1155. ctx->dev->db_state = FLOW_CONTROL;
  1156. while (1) {
  1157. if (list_empty(&ctx->dev->db_fc_list)) {
  1158. WARN_ON(ctx->dev->db_state != FLOW_CONTROL);
  1159. ctx->dev->db_state = NORMAL;
  1160. ctx->dev->rdev.stats.db_state_transitions++;
  1161. if (ctx->dev->rdev.flags & T4_STATUS_PAGE_DISABLED) {
  1162. idr_for_each(&ctx->dev->qpidr, enable_qp_db,
  1163. NULL);
  1164. } else {
  1165. ctx->dev->rdev.status_page->db_off = 0;
  1166. }
  1167. break;
  1168. } else {
  1169. if (cxgb4_dbfifo_count(ctx->dev->rdev.lldi.ports[0], 1)
  1170. < (ctx->dev->rdev.lldi.dbfifo_int_thresh <<
  1171. DB_FC_DRAIN_THRESH)) {
  1172. resume_a_chunk(ctx);
  1173. }
  1174. if (!list_empty(&ctx->dev->db_fc_list)) {
  1175. spin_unlock_irq(&ctx->dev->lock);
  1176. if (DB_FC_RESUME_DELAY) {
  1177. set_current_state(TASK_UNINTERRUPTIBLE);
  1178. schedule_timeout(DB_FC_RESUME_DELAY);
  1179. }
  1180. spin_lock_irq(&ctx->dev->lock);
  1181. if (ctx->dev->db_state != FLOW_CONTROL)
  1182. break;
  1183. }
  1184. }
  1185. }
  1186. out:
  1187. if (ctx->dev->db_state != NORMAL)
  1188. ctx->dev->rdev.stats.db_fc_interruptions++;
  1189. spin_unlock_irq(&ctx->dev->lock);
  1190. }
  1191. struct qp_list {
  1192. unsigned idx;
  1193. struct c4iw_qp **qps;
  1194. };
  1195. static int add_and_ref_qp(int id, void *p, void *data)
  1196. {
  1197. struct qp_list *qp_listp = data;
  1198. struct c4iw_qp *qp = p;
  1199. c4iw_qp_add_ref(&qp->ibqp);
  1200. qp_listp->qps[qp_listp->idx++] = qp;
  1201. return 0;
  1202. }
  1203. static int count_qps(int id, void *p, void *data)
  1204. {
  1205. unsigned *countp = data;
  1206. (*countp)++;
  1207. return 0;
  1208. }
  1209. static void deref_qps(struct qp_list *qp_list)
  1210. {
  1211. int idx;
  1212. for (idx = 0; idx < qp_list->idx; idx++)
  1213. c4iw_qp_rem_ref(&qp_list->qps[idx]->ibqp);
  1214. }
  1215. static void recover_lost_dbs(struct uld_ctx *ctx, struct qp_list *qp_list)
  1216. {
  1217. int idx;
  1218. int ret;
  1219. for (idx = 0; idx < qp_list->idx; idx++) {
  1220. struct c4iw_qp *qp = qp_list->qps[idx];
  1221. spin_lock_irq(&qp->rhp->lock);
  1222. spin_lock(&qp->lock);
  1223. ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0],
  1224. qp->wq.sq.qid,
  1225. t4_sq_host_wq_pidx(&qp->wq),
  1226. t4_sq_wq_size(&qp->wq));
  1227. if (ret) {
  1228. pr_err("%s: Fatal error - DB overflow recovery failed - error syncing SQ qid %u\n",
  1229. pci_name(ctx->lldi.pdev), qp->wq.sq.qid);
  1230. spin_unlock(&qp->lock);
  1231. spin_unlock_irq(&qp->rhp->lock);
  1232. return;
  1233. }
  1234. qp->wq.sq.wq_pidx_inc = 0;
  1235. ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0],
  1236. qp->wq.rq.qid,
  1237. t4_rq_host_wq_pidx(&qp->wq),
  1238. t4_rq_wq_size(&qp->wq));
  1239. if (ret) {
  1240. pr_err("%s: Fatal error - DB overflow recovery failed - error syncing RQ qid %u\n",
  1241. pci_name(ctx->lldi.pdev), qp->wq.rq.qid);
  1242. spin_unlock(&qp->lock);
  1243. spin_unlock_irq(&qp->rhp->lock);
  1244. return;
  1245. }
  1246. qp->wq.rq.wq_pidx_inc = 0;
  1247. spin_unlock(&qp->lock);
  1248. spin_unlock_irq(&qp->rhp->lock);
  1249. /* Wait for the dbfifo to drain */
  1250. while (cxgb4_dbfifo_count(qp->rhp->rdev.lldi.ports[0], 1) > 0) {
  1251. set_current_state(TASK_UNINTERRUPTIBLE);
  1252. schedule_timeout(usecs_to_jiffies(10));
  1253. }
  1254. }
  1255. }
  1256. static void recover_queues(struct uld_ctx *ctx)
  1257. {
  1258. int count = 0;
  1259. struct qp_list qp_list;
  1260. int ret;
  1261. /* slow everybody down */
  1262. set_current_state(TASK_UNINTERRUPTIBLE);
  1263. schedule_timeout(usecs_to_jiffies(1000));
  1264. /* flush the SGE contexts */
  1265. ret = cxgb4_flush_eq_cache(ctx->dev->rdev.lldi.ports[0]);
  1266. if (ret) {
  1267. pr_err("%s: Fatal error - DB overflow recovery failed\n",
  1268. pci_name(ctx->lldi.pdev));
  1269. return;
  1270. }
  1271. /* Count active queues so we can build a list of queues to recover */
  1272. spin_lock_irq(&ctx->dev->lock);
  1273. WARN_ON(ctx->dev->db_state != STOPPED);
  1274. ctx->dev->db_state = RECOVERY;
  1275. idr_for_each(&ctx->dev->qpidr, count_qps, &count);
  1276. qp_list.qps = kzalloc(count * sizeof *qp_list.qps, GFP_ATOMIC);
  1277. if (!qp_list.qps) {
  1278. spin_unlock_irq(&ctx->dev->lock);
  1279. return;
  1280. }
  1281. qp_list.idx = 0;
  1282. /* add and ref each qp so it doesn't get freed */
  1283. idr_for_each(&ctx->dev->qpidr, add_and_ref_qp, &qp_list);
  1284. spin_unlock_irq(&ctx->dev->lock);
  1285. /* now traverse the list in a safe context to recover the db state*/
  1286. recover_lost_dbs(ctx, &qp_list);
  1287. /* we're almost done! deref the qps and clean up */
  1288. deref_qps(&qp_list);
  1289. kfree(qp_list.qps);
  1290. spin_lock_irq(&ctx->dev->lock);
  1291. WARN_ON(ctx->dev->db_state != RECOVERY);
  1292. ctx->dev->db_state = STOPPED;
  1293. spin_unlock_irq(&ctx->dev->lock);
  1294. }
  1295. static int c4iw_uld_control(void *handle, enum cxgb4_control control, ...)
  1296. {
  1297. struct uld_ctx *ctx = handle;
  1298. switch (control) {
  1299. case CXGB4_CONTROL_DB_FULL:
  1300. stop_queues(ctx);
  1301. ctx->dev->rdev.stats.db_full++;
  1302. break;
  1303. case CXGB4_CONTROL_DB_EMPTY:
  1304. resume_queues(ctx);
  1305. mutex_lock(&ctx->dev->rdev.stats.lock);
  1306. ctx->dev->rdev.stats.db_empty++;
  1307. mutex_unlock(&ctx->dev->rdev.stats.lock);
  1308. break;
  1309. case CXGB4_CONTROL_DB_DROP:
  1310. recover_queues(ctx);
  1311. mutex_lock(&ctx->dev->rdev.stats.lock);
  1312. ctx->dev->rdev.stats.db_drop++;
  1313. mutex_unlock(&ctx->dev->rdev.stats.lock);
  1314. break;
  1315. default:
  1316. pr_warn("%s: unknown control cmd %u\n",
  1317. pci_name(ctx->lldi.pdev), control);
  1318. break;
  1319. }
  1320. return 0;
  1321. }
  1322. static struct cxgb4_uld_info c4iw_uld_info = {
  1323. .name = DRV_NAME,
  1324. .nrxq = MAX_ULD_QSETS,
  1325. .ntxq = MAX_ULD_QSETS,
  1326. .rxq_size = 511,
  1327. .ciq = true,
  1328. .lro = false,
  1329. .add = c4iw_uld_add,
  1330. .rx_handler = c4iw_uld_rx_handler,
  1331. .state_change = c4iw_uld_state_change,
  1332. .control = c4iw_uld_control,
  1333. };
  1334. static int __init c4iw_init_module(void)
  1335. {
  1336. int err;
  1337. err = c4iw_cm_init();
  1338. if (err)
  1339. return err;
  1340. c4iw_debugfs_root = debugfs_create_dir(DRV_NAME, NULL);
  1341. if (!c4iw_debugfs_root)
  1342. pr_warn("could not create debugfs entry, continuing\n");
  1343. cxgb4_register_uld(CXGB4_ULD_RDMA, &c4iw_uld_info);
  1344. return 0;
  1345. }
  1346. static void __exit c4iw_exit_module(void)
  1347. {
  1348. struct uld_ctx *ctx, *tmp;
  1349. mutex_lock(&dev_mutex);
  1350. list_for_each_entry_safe(ctx, tmp, &uld_ctx_list, entry) {
  1351. if (ctx->dev)
  1352. c4iw_remove(ctx);
  1353. kfree(ctx);
  1354. }
  1355. mutex_unlock(&dev_mutex);
  1356. cxgb4_unregister_uld(CXGB4_ULD_RDMA);
  1357. c4iw_cm_term();
  1358. debugfs_remove_recursive(c4iw_debugfs_root);
  1359. }
  1360. module_init(c4iw_init_module);
  1361. module_exit(c4iw_exit_module);