ib_verbs.c 86 KB

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  1. /*
  2. * Broadcom NetXtreme-E RoCE driver.
  3. *
  4. * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
  5. * Broadcom refers to Broadcom Limited and/or its subsidiaries.
  6. *
  7. * This software is available to you under a choice of one of two
  8. * licenses. You may choose to be licensed under the terms of the GNU
  9. * General Public License (GPL) Version 2, available from the file
  10. * COPYING in the main directory of this source tree, or the
  11. * BSD license below:
  12. *
  13. * Redistribution and use in source and binary forms, with or without
  14. * modification, are permitted provided that the following conditions
  15. * are met:
  16. *
  17. * 1. Redistributions of source code must retain the above copyright
  18. * notice, this list of conditions and the following disclaimer.
  19. * 2. Redistributions in binary form must reproduce the above copyright
  20. * notice, this list of conditions and the following disclaimer in
  21. * the documentation and/or other materials provided with the
  22. * distribution.
  23. *
  24. * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
  25. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26. * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27. * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
  28. * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  31. * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  32. * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  33. * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  34. * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35. *
  36. * Description: IB Verbs interpreter
  37. */
  38. #include <linux/interrupt.h>
  39. #include <linux/types.h>
  40. #include <linux/pci.h>
  41. #include <linux/netdevice.h>
  42. #include <linux/if_ether.h>
  43. #include <rdma/ib_verbs.h>
  44. #include <rdma/ib_user_verbs.h>
  45. #include <rdma/ib_umem.h>
  46. #include <rdma/ib_addr.h>
  47. #include <rdma/ib_mad.h>
  48. #include <rdma/ib_cache.h>
  49. #include "bnxt_ulp.h"
  50. #include "roce_hsi.h"
  51. #include "qplib_res.h"
  52. #include "qplib_sp.h"
  53. #include "qplib_fp.h"
  54. #include "qplib_rcfw.h"
  55. #include "bnxt_re.h"
  56. #include "ib_verbs.h"
  57. #include <rdma/bnxt_re-abi.h>
  58. static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list,
  59. struct bnxt_qplib_sge *sg_list, int num)
  60. {
  61. int i, total = 0;
  62. for (i = 0; i < num; i++) {
  63. sg_list[i].addr = ib_sg_list[i].addr;
  64. sg_list[i].lkey = ib_sg_list[i].lkey;
  65. sg_list[i].size = ib_sg_list[i].length;
  66. total += sg_list[i].size;
  67. }
  68. return total;
  69. }
  70. /* Device */
  71. struct net_device *bnxt_re_get_netdev(struct ib_device *ibdev, u8 port_num)
  72. {
  73. struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
  74. struct net_device *netdev = NULL;
  75. rcu_read_lock();
  76. if (rdev)
  77. netdev = rdev->netdev;
  78. if (netdev)
  79. dev_hold(netdev);
  80. rcu_read_unlock();
  81. return netdev;
  82. }
  83. int bnxt_re_query_device(struct ib_device *ibdev,
  84. struct ib_device_attr *ib_attr,
  85. struct ib_udata *udata)
  86. {
  87. struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
  88. struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
  89. memset(ib_attr, 0, sizeof(*ib_attr));
  90. ib_attr->fw_ver = (u64)(unsigned long)(dev_attr->fw_ver);
  91. bnxt_qplib_get_guid(rdev->netdev->dev_addr,
  92. (u8 *)&ib_attr->sys_image_guid);
  93. ib_attr->max_mr_size = ~0ull;
  94. ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_4K | BNXT_RE_PAGE_SIZE_8K |
  95. BNXT_RE_PAGE_SIZE_64K | BNXT_RE_PAGE_SIZE_2M |
  96. BNXT_RE_PAGE_SIZE_8M | BNXT_RE_PAGE_SIZE_1G;
  97. ib_attr->vendor_id = rdev->en_dev->pdev->vendor;
  98. ib_attr->vendor_part_id = rdev->en_dev->pdev->device;
  99. ib_attr->hw_ver = rdev->en_dev->pdev->subsystem_device;
  100. ib_attr->max_qp = dev_attr->max_qp;
  101. ib_attr->max_qp_wr = dev_attr->max_qp_wqes;
  102. ib_attr->device_cap_flags =
  103. IB_DEVICE_CURR_QP_STATE_MOD
  104. | IB_DEVICE_RC_RNR_NAK_GEN
  105. | IB_DEVICE_SHUTDOWN_PORT
  106. | IB_DEVICE_SYS_IMAGE_GUID
  107. | IB_DEVICE_LOCAL_DMA_LKEY
  108. | IB_DEVICE_RESIZE_MAX_WR
  109. | IB_DEVICE_PORT_ACTIVE_EVENT
  110. | IB_DEVICE_N_NOTIFY_CQ
  111. | IB_DEVICE_MEM_WINDOW
  112. | IB_DEVICE_MEM_WINDOW_TYPE_2B
  113. | IB_DEVICE_MEM_MGT_EXTENSIONS;
  114. ib_attr->max_sge = dev_attr->max_qp_sges;
  115. ib_attr->max_sge_rd = dev_attr->max_qp_sges;
  116. ib_attr->max_cq = dev_attr->max_cq;
  117. ib_attr->max_cqe = dev_attr->max_cq_wqes;
  118. ib_attr->max_mr = dev_attr->max_mr;
  119. ib_attr->max_pd = dev_attr->max_pd;
  120. ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom;
  121. ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_rd_atom;
  122. ib_attr->atomic_cap = IB_ATOMIC_HCA;
  123. ib_attr->masked_atomic_cap = IB_ATOMIC_HCA;
  124. ib_attr->max_ee_rd_atom = 0;
  125. ib_attr->max_res_rd_atom = 0;
  126. ib_attr->max_ee_init_rd_atom = 0;
  127. ib_attr->max_ee = 0;
  128. ib_attr->max_rdd = 0;
  129. ib_attr->max_mw = dev_attr->max_mw;
  130. ib_attr->max_raw_ipv6_qp = 0;
  131. ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp;
  132. ib_attr->max_mcast_grp = 0;
  133. ib_attr->max_mcast_qp_attach = 0;
  134. ib_attr->max_total_mcast_qp_attach = 0;
  135. ib_attr->max_ah = dev_attr->max_ah;
  136. ib_attr->max_fmr = dev_attr->max_fmr;
  137. ib_attr->max_map_per_fmr = 1; /* ? */
  138. ib_attr->max_srq = dev_attr->max_srq;
  139. ib_attr->max_srq_wr = dev_attr->max_srq_wqes;
  140. ib_attr->max_srq_sge = dev_attr->max_srq_sges;
  141. ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS;
  142. ib_attr->max_pkeys = 1;
  143. ib_attr->local_ca_ack_delay = 0;
  144. return 0;
  145. }
  146. int bnxt_re_modify_device(struct ib_device *ibdev,
  147. int device_modify_mask,
  148. struct ib_device_modify *device_modify)
  149. {
  150. switch (device_modify_mask) {
  151. case IB_DEVICE_MODIFY_SYS_IMAGE_GUID:
  152. /* Modify the GUID requires the modification of the GID table */
  153. /* GUID should be made as READ-ONLY */
  154. break;
  155. case IB_DEVICE_MODIFY_NODE_DESC:
  156. /* Node Desc should be made as READ-ONLY */
  157. break;
  158. default:
  159. break;
  160. }
  161. return 0;
  162. }
  163. static void __to_ib_speed_width(struct net_device *netdev, u8 *speed, u8 *width)
  164. {
  165. struct ethtool_link_ksettings lksettings;
  166. u32 espeed;
  167. if (netdev->ethtool_ops && netdev->ethtool_ops->get_link_ksettings) {
  168. memset(&lksettings, 0, sizeof(lksettings));
  169. rtnl_lock();
  170. netdev->ethtool_ops->get_link_ksettings(netdev, &lksettings);
  171. rtnl_unlock();
  172. espeed = lksettings.base.speed;
  173. } else {
  174. espeed = SPEED_UNKNOWN;
  175. }
  176. switch (espeed) {
  177. case SPEED_1000:
  178. *speed = IB_SPEED_SDR;
  179. *width = IB_WIDTH_1X;
  180. break;
  181. case SPEED_10000:
  182. *speed = IB_SPEED_QDR;
  183. *width = IB_WIDTH_1X;
  184. break;
  185. case SPEED_20000:
  186. *speed = IB_SPEED_DDR;
  187. *width = IB_WIDTH_4X;
  188. break;
  189. case SPEED_25000:
  190. *speed = IB_SPEED_EDR;
  191. *width = IB_WIDTH_1X;
  192. break;
  193. case SPEED_40000:
  194. *speed = IB_SPEED_QDR;
  195. *width = IB_WIDTH_4X;
  196. break;
  197. case SPEED_50000:
  198. break;
  199. default:
  200. *speed = IB_SPEED_SDR;
  201. *width = IB_WIDTH_1X;
  202. break;
  203. }
  204. }
  205. /* Port */
  206. int bnxt_re_query_port(struct ib_device *ibdev, u8 port_num,
  207. struct ib_port_attr *port_attr)
  208. {
  209. struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
  210. struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
  211. memset(port_attr, 0, sizeof(*port_attr));
  212. if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) {
  213. port_attr->state = IB_PORT_ACTIVE;
  214. port_attr->phys_state = 5;
  215. } else {
  216. port_attr->state = IB_PORT_DOWN;
  217. port_attr->phys_state = 3;
  218. }
  219. port_attr->max_mtu = IB_MTU_4096;
  220. port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu);
  221. port_attr->gid_tbl_len = dev_attr->max_sgid;
  222. port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
  223. IB_PORT_DEVICE_MGMT_SUP |
  224. IB_PORT_VENDOR_CLASS_SUP |
  225. IB_PORT_IP_BASED_GIDS;
  226. /* Max MSG size set to 2G for now */
  227. port_attr->max_msg_sz = 0x80000000;
  228. port_attr->bad_pkey_cntr = 0;
  229. port_attr->qkey_viol_cntr = 0;
  230. port_attr->pkey_tbl_len = dev_attr->max_pkey;
  231. port_attr->lid = 0;
  232. port_attr->sm_lid = 0;
  233. port_attr->lmc = 0;
  234. port_attr->max_vl_num = 4;
  235. port_attr->sm_sl = 0;
  236. port_attr->subnet_timeout = 0;
  237. port_attr->init_type_reply = 0;
  238. /* call the underlying netdev's ethtool hooks to query speed settings
  239. * for which we acquire rtnl_lock _only_ if it's registered with
  240. * IB stack to avoid race in the NETDEV_UNREG path
  241. */
  242. if (test_bit(BNXT_RE_FLAG_IBDEV_REGISTERED, &rdev->flags))
  243. __to_ib_speed_width(rdev->netdev, &port_attr->active_speed,
  244. &port_attr->active_width);
  245. return 0;
  246. }
  247. int bnxt_re_modify_port(struct ib_device *ibdev, u8 port_num,
  248. int port_modify_mask,
  249. struct ib_port_modify *port_modify)
  250. {
  251. switch (port_modify_mask) {
  252. case IB_PORT_SHUTDOWN:
  253. break;
  254. case IB_PORT_INIT_TYPE:
  255. break;
  256. case IB_PORT_RESET_QKEY_CNTR:
  257. break;
  258. default:
  259. break;
  260. }
  261. return 0;
  262. }
  263. int bnxt_re_get_port_immutable(struct ib_device *ibdev, u8 port_num,
  264. struct ib_port_immutable *immutable)
  265. {
  266. struct ib_port_attr port_attr;
  267. if (bnxt_re_query_port(ibdev, port_num, &port_attr))
  268. return -EINVAL;
  269. immutable->pkey_tbl_len = port_attr.pkey_tbl_len;
  270. immutable->gid_tbl_len = port_attr.gid_tbl_len;
  271. immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
  272. immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP;
  273. immutable->max_mad_size = IB_MGMT_MAD_SIZE;
  274. return 0;
  275. }
  276. int bnxt_re_query_pkey(struct ib_device *ibdev, u8 port_num,
  277. u16 index, u16 *pkey)
  278. {
  279. struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
  280. /* Ignore port_num */
  281. memset(pkey, 0, sizeof(*pkey));
  282. return bnxt_qplib_get_pkey(&rdev->qplib_res,
  283. &rdev->qplib_res.pkey_tbl, index, pkey);
  284. }
  285. int bnxt_re_query_gid(struct ib_device *ibdev, u8 port_num,
  286. int index, union ib_gid *gid)
  287. {
  288. struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
  289. int rc = 0;
  290. /* Ignore port_num */
  291. memset(gid, 0, sizeof(*gid));
  292. rc = bnxt_qplib_get_sgid(&rdev->qplib_res,
  293. &rdev->qplib_res.sgid_tbl, index,
  294. (struct bnxt_qplib_gid *)gid);
  295. return rc;
  296. }
  297. int bnxt_re_del_gid(struct ib_device *ibdev, u8 port_num,
  298. unsigned int index, void **context)
  299. {
  300. int rc = 0;
  301. struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
  302. struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
  303. struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
  304. /* Delete the entry from the hardware */
  305. ctx = *context;
  306. if (!ctx)
  307. return -EINVAL;
  308. if (sgid_tbl && sgid_tbl->active) {
  309. if (ctx->idx >= sgid_tbl->max)
  310. return -EINVAL;
  311. ctx->refcnt--;
  312. if (!ctx->refcnt) {
  313. rc = bnxt_qplib_del_sgid
  314. (sgid_tbl,
  315. &sgid_tbl->tbl[ctx->idx], true);
  316. if (rc)
  317. dev_err(rdev_to_dev(rdev),
  318. "Failed to remove GID: %#x", rc);
  319. ctx_tbl = sgid_tbl->ctx;
  320. ctx_tbl[ctx->idx] = NULL;
  321. kfree(ctx);
  322. }
  323. } else {
  324. return -EINVAL;
  325. }
  326. return rc;
  327. }
  328. int bnxt_re_add_gid(struct ib_device *ibdev, u8 port_num,
  329. unsigned int index, const union ib_gid *gid,
  330. const struct ib_gid_attr *attr, void **context)
  331. {
  332. int rc;
  333. u32 tbl_idx = 0;
  334. u16 vlan_id = 0xFFFF;
  335. struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
  336. struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
  337. struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
  338. if ((attr->ndev) && is_vlan_dev(attr->ndev))
  339. vlan_id = vlan_dev_vlan_id(attr->ndev);
  340. rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)gid,
  341. rdev->qplib_res.netdev->dev_addr,
  342. vlan_id, true, &tbl_idx);
  343. if (rc == -EALREADY) {
  344. ctx_tbl = sgid_tbl->ctx;
  345. ctx_tbl[tbl_idx]->refcnt++;
  346. *context = ctx_tbl[tbl_idx];
  347. return 0;
  348. }
  349. if (rc < 0) {
  350. dev_err(rdev_to_dev(rdev), "Failed to add GID: %#x", rc);
  351. return rc;
  352. }
  353. ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
  354. if (!ctx)
  355. return -ENOMEM;
  356. ctx_tbl = sgid_tbl->ctx;
  357. ctx->idx = tbl_idx;
  358. ctx->refcnt = 1;
  359. ctx_tbl[tbl_idx] = ctx;
  360. return rc;
  361. }
  362. enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev,
  363. u8 port_num)
  364. {
  365. return IB_LINK_LAYER_ETHERNET;
  366. }
  367. /* Protection Domains */
  368. int bnxt_re_dealloc_pd(struct ib_pd *ib_pd)
  369. {
  370. struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
  371. struct bnxt_re_dev *rdev = pd->rdev;
  372. int rc;
  373. if (ib_pd->uobject && pd->dpi.dbr) {
  374. struct ib_ucontext *ib_uctx = ib_pd->uobject->context;
  375. struct bnxt_re_ucontext *ucntx;
  376. /* Free DPI only if this is the first PD allocated by the
  377. * application and mark the context dpi as NULL
  378. */
  379. ucntx = container_of(ib_uctx, struct bnxt_re_ucontext, ib_uctx);
  380. rc = bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
  381. &rdev->qplib_res.dpi_tbl,
  382. &pd->dpi);
  383. if (rc)
  384. dev_err(rdev_to_dev(rdev), "Failed to deallocate HW DPI");
  385. /* Don't fail, continue*/
  386. ucntx->dpi = NULL;
  387. }
  388. rc = bnxt_qplib_dealloc_pd(&rdev->qplib_res,
  389. &rdev->qplib_res.pd_tbl,
  390. &pd->qplib_pd);
  391. if (rc) {
  392. dev_err(rdev_to_dev(rdev), "Failed to deallocate HW PD");
  393. return rc;
  394. }
  395. kfree(pd);
  396. return 0;
  397. }
  398. struct ib_pd *bnxt_re_alloc_pd(struct ib_device *ibdev,
  399. struct ib_ucontext *ucontext,
  400. struct ib_udata *udata)
  401. {
  402. struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
  403. struct bnxt_re_ucontext *ucntx = container_of(ucontext,
  404. struct bnxt_re_ucontext,
  405. ib_uctx);
  406. struct bnxt_re_pd *pd;
  407. int rc;
  408. pd = kzalloc(sizeof(*pd), GFP_KERNEL);
  409. if (!pd)
  410. return ERR_PTR(-ENOMEM);
  411. pd->rdev = rdev;
  412. if (bnxt_qplib_alloc_pd(&rdev->qplib_res.pd_tbl, &pd->qplib_pd)) {
  413. dev_err(rdev_to_dev(rdev), "Failed to allocate HW PD");
  414. rc = -ENOMEM;
  415. goto fail;
  416. }
  417. if (udata) {
  418. struct bnxt_re_pd_resp resp;
  419. if (!ucntx->dpi) {
  420. /* Allocate DPI in alloc_pd to avoid failing of
  421. * ibv_devinfo and family of application when DPIs
  422. * are depleted.
  423. */
  424. if (bnxt_qplib_alloc_dpi(&rdev->qplib_res.dpi_tbl,
  425. &pd->dpi, ucntx)) {
  426. rc = -ENOMEM;
  427. goto dbfail;
  428. }
  429. ucntx->dpi = &pd->dpi;
  430. }
  431. resp.pdid = pd->qplib_pd.id;
  432. /* Still allow mapping this DBR to the new user PD. */
  433. resp.dpi = ucntx->dpi->dpi;
  434. resp.dbr = (u64)ucntx->dpi->umdbr;
  435. rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
  436. if (rc) {
  437. dev_err(rdev_to_dev(rdev),
  438. "Failed to copy user response\n");
  439. goto dbfail;
  440. }
  441. }
  442. return &pd->ib_pd;
  443. dbfail:
  444. (void)bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl,
  445. &pd->qplib_pd);
  446. fail:
  447. kfree(pd);
  448. return ERR_PTR(rc);
  449. }
  450. /* Address Handles */
  451. int bnxt_re_destroy_ah(struct ib_ah *ib_ah)
  452. {
  453. struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
  454. struct bnxt_re_dev *rdev = ah->rdev;
  455. int rc;
  456. rc = bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah);
  457. if (rc) {
  458. dev_err(rdev_to_dev(rdev), "Failed to destroy HW AH");
  459. return rc;
  460. }
  461. kfree(ah);
  462. return 0;
  463. }
  464. struct ib_ah *bnxt_re_create_ah(struct ib_pd *ib_pd,
  465. struct rdma_ah_attr *ah_attr,
  466. struct ib_udata *udata)
  467. {
  468. struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
  469. struct bnxt_re_dev *rdev = pd->rdev;
  470. struct bnxt_re_ah *ah;
  471. const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr);
  472. int rc;
  473. u16 vlan_tag;
  474. u8 nw_type;
  475. struct ib_gid_attr sgid_attr;
  476. if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) {
  477. dev_err(rdev_to_dev(rdev), "Failed to alloc AH: GRH not set");
  478. return ERR_PTR(-EINVAL);
  479. }
  480. ah = kzalloc(sizeof(*ah), GFP_ATOMIC);
  481. if (!ah)
  482. return ERR_PTR(-ENOMEM);
  483. ah->rdev = rdev;
  484. ah->qplib_ah.pd = &pd->qplib_pd;
  485. /* Supply the configuration for the HW */
  486. memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw,
  487. sizeof(union ib_gid));
  488. /*
  489. * If RoCE V2 is enabled, stack will have two entries for
  490. * each GID entry. Avoiding this duplicte entry in HW. Dividing
  491. * the GID index by 2 for RoCE V2
  492. */
  493. ah->qplib_ah.sgid_index = grh->sgid_index / 2;
  494. ah->qplib_ah.host_sgid_index = grh->sgid_index;
  495. ah->qplib_ah.traffic_class = grh->traffic_class;
  496. ah->qplib_ah.flow_label = grh->flow_label;
  497. ah->qplib_ah.hop_limit = grh->hop_limit;
  498. ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr);
  499. if (ib_pd->uobject &&
  500. !rdma_is_multicast_addr((struct in6_addr *)
  501. grh->dgid.raw) &&
  502. !rdma_link_local_addr((struct in6_addr *)
  503. grh->dgid.raw)) {
  504. union ib_gid sgid;
  505. rc = ib_get_cached_gid(&rdev->ibdev, 1,
  506. grh->sgid_index, &sgid,
  507. &sgid_attr);
  508. if (rc) {
  509. dev_err(rdev_to_dev(rdev),
  510. "Failed to query gid at index %d",
  511. grh->sgid_index);
  512. goto fail;
  513. }
  514. if (sgid_attr.ndev) {
  515. if (is_vlan_dev(sgid_attr.ndev))
  516. vlan_tag = vlan_dev_vlan_id(sgid_attr.ndev);
  517. dev_put(sgid_attr.ndev);
  518. }
  519. /* Get network header type for this GID */
  520. nw_type = ib_gid_to_network_type(sgid_attr.gid_type, &sgid);
  521. switch (nw_type) {
  522. case RDMA_NETWORK_IPV4:
  523. ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4;
  524. break;
  525. case RDMA_NETWORK_IPV6:
  526. ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6;
  527. break;
  528. default:
  529. ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V1;
  530. break;
  531. }
  532. rc = rdma_addr_find_l2_eth_by_grh(&sgid, &grh->dgid,
  533. ah_attr->roce.dmac, &vlan_tag,
  534. &sgid_attr.ndev->ifindex,
  535. NULL);
  536. if (rc) {
  537. dev_err(rdev_to_dev(rdev), "Failed to get dmac\n");
  538. goto fail;
  539. }
  540. }
  541. memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN);
  542. rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah);
  543. if (rc) {
  544. dev_err(rdev_to_dev(rdev), "Failed to allocate HW AH");
  545. goto fail;
  546. }
  547. /* Write AVID to shared page. */
  548. if (ib_pd->uobject) {
  549. struct ib_ucontext *ib_uctx = ib_pd->uobject->context;
  550. struct bnxt_re_ucontext *uctx;
  551. unsigned long flag;
  552. u32 *wrptr;
  553. uctx = container_of(ib_uctx, struct bnxt_re_ucontext, ib_uctx);
  554. spin_lock_irqsave(&uctx->sh_lock, flag);
  555. wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT);
  556. *wrptr = ah->qplib_ah.id;
  557. wmb(); /* make sure cache is updated. */
  558. spin_unlock_irqrestore(&uctx->sh_lock, flag);
  559. }
  560. return &ah->ib_ah;
  561. fail:
  562. kfree(ah);
  563. return ERR_PTR(rc);
  564. }
  565. int bnxt_re_modify_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr)
  566. {
  567. return 0;
  568. }
  569. int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr)
  570. {
  571. struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
  572. ah_attr->type = ib_ah->type;
  573. rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl);
  574. memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN);
  575. rdma_ah_set_grh(ah_attr, NULL, 0,
  576. ah->qplib_ah.host_sgid_index,
  577. 0, ah->qplib_ah.traffic_class);
  578. rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data);
  579. rdma_ah_set_port_num(ah_attr, 1);
  580. rdma_ah_set_static_rate(ah_attr, 0);
  581. return 0;
  582. }
  583. /* Queue Pairs */
  584. int bnxt_re_destroy_qp(struct ib_qp *ib_qp)
  585. {
  586. struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
  587. struct bnxt_re_dev *rdev = qp->rdev;
  588. int rc;
  589. rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
  590. if (rc) {
  591. dev_err(rdev_to_dev(rdev), "Failed to destroy HW QP");
  592. return rc;
  593. }
  594. if (ib_qp->qp_type == IB_QPT_GSI && rdev->qp1_sqp) {
  595. rc = bnxt_qplib_destroy_ah(&rdev->qplib_res,
  596. &rdev->sqp_ah->qplib_ah);
  597. if (rc) {
  598. dev_err(rdev_to_dev(rdev),
  599. "Failed to destroy HW AH for shadow QP");
  600. return rc;
  601. }
  602. rc = bnxt_qplib_destroy_qp(&rdev->qplib_res,
  603. &rdev->qp1_sqp->qplib_qp);
  604. if (rc) {
  605. dev_err(rdev_to_dev(rdev),
  606. "Failed to destroy Shadow QP");
  607. return rc;
  608. }
  609. mutex_lock(&rdev->qp_lock);
  610. list_del(&rdev->qp1_sqp->list);
  611. atomic_dec(&rdev->qp_count);
  612. mutex_unlock(&rdev->qp_lock);
  613. kfree(rdev->sqp_ah);
  614. kfree(rdev->qp1_sqp);
  615. }
  616. if (!IS_ERR_OR_NULL(qp->rumem))
  617. ib_umem_release(qp->rumem);
  618. if (!IS_ERR_OR_NULL(qp->sumem))
  619. ib_umem_release(qp->sumem);
  620. mutex_lock(&rdev->qp_lock);
  621. list_del(&qp->list);
  622. atomic_dec(&rdev->qp_count);
  623. mutex_unlock(&rdev->qp_lock);
  624. kfree(qp);
  625. return 0;
  626. }
  627. static u8 __from_ib_qp_type(enum ib_qp_type type)
  628. {
  629. switch (type) {
  630. case IB_QPT_GSI:
  631. return CMDQ_CREATE_QP1_TYPE_GSI;
  632. case IB_QPT_RC:
  633. return CMDQ_CREATE_QP_TYPE_RC;
  634. case IB_QPT_UD:
  635. return CMDQ_CREATE_QP_TYPE_UD;
  636. default:
  637. return IB_QPT_MAX;
  638. }
  639. }
  640. static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd,
  641. struct bnxt_re_qp *qp, struct ib_udata *udata)
  642. {
  643. struct bnxt_re_qp_req ureq;
  644. struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp;
  645. struct ib_umem *umem;
  646. int bytes = 0;
  647. struct ib_ucontext *context = pd->ib_pd.uobject->context;
  648. struct bnxt_re_ucontext *cntx = container_of(context,
  649. struct bnxt_re_ucontext,
  650. ib_uctx);
  651. if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
  652. return -EFAULT;
  653. bytes = (qplib_qp->sq.max_wqe * BNXT_QPLIB_MAX_SQE_ENTRY_SIZE);
  654. /* Consider mapping PSN search memory only for RC QPs. */
  655. if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC)
  656. bytes += (qplib_qp->sq.max_wqe * sizeof(struct sq_psn_search));
  657. bytes = PAGE_ALIGN(bytes);
  658. umem = ib_umem_get(context, ureq.qpsva, bytes,
  659. IB_ACCESS_LOCAL_WRITE, 1);
  660. if (IS_ERR(umem))
  661. return PTR_ERR(umem);
  662. qp->sumem = umem;
  663. qplib_qp->sq.sglist = umem->sg_head.sgl;
  664. qplib_qp->sq.nmap = umem->nmap;
  665. qplib_qp->qp_handle = ureq.qp_handle;
  666. if (!qp->qplib_qp.srq) {
  667. bytes = (qplib_qp->rq.max_wqe * BNXT_QPLIB_MAX_RQE_ENTRY_SIZE);
  668. bytes = PAGE_ALIGN(bytes);
  669. umem = ib_umem_get(context, ureq.qprva, bytes,
  670. IB_ACCESS_LOCAL_WRITE, 1);
  671. if (IS_ERR(umem))
  672. goto rqfail;
  673. qp->rumem = umem;
  674. qplib_qp->rq.sglist = umem->sg_head.sgl;
  675. qplib_qp->rq.nmap = umem->nmap;
  676. }
  677. qplib_qp->dpi = cntx->dpi;
  678. return 0;
  679. rqfail:
  680. ib_umem_release(qp->sumem);
  681. qp->sumem = NULL;
  682. qplib_qp->sq.sglist = NULL;
  683. qplib_qp->sq.nmap = 0;
  684. return PTR_ERR(umem);
  685. }
  686. static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah
  687. (struct bnxt_re_pd *pd,
  688. struct bnxt_qplib_res *qp1_res,
  689. struct bnxt_qplib_qp *qp1_qp)
  690. {
  691. struct bnxt_re_dev *rdev = pd->rdev;
  692. struct bnxt_re_ah *ah;
  693. union ib_gid sgid;
  694. int rc;
  695. ah = kzalloc(sizeof(*ah), GFP_KERNEL);
  696. if (!ah)
  697. return NULL;
  698. memset(ah, 0, sizeof(*ah));
  699. ah->rdev = rdev;
  700. ah->qplib_ah.pd = &pd->qplib_pd;
  701. rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid);
  702. if (rc)
  703. goto fail;
  704. /* supply the dgid data same as sgid */
  705. memcpy(ah->qplib_ah.dgid.data, &sgid.raw,
  706. sizeof(union ib_gid));
  707. ah->qplib_ah.sgid_index = 0;
  708. ah->qplib_ah.traffic_class = 0;
  709. ah->qplib_ah.flow_label = 0;
  710. ah->qplib_ah.hop_limit = 1;
  711. ah->qplib_ah.sl = 0;
  712. /* Have DMAC same as SMAC */
  713. ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr);
  714. rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah);
  715. if (rc) {
  716. dev_err(rdev_to_dev(rdev),
  717. "Failed to allocate HW AH for Shadow QP");
  718. goto fail;
  719. }
  720. return ah;
  721. fail:
  722. kfree(ah);
  723. return NULL;
  724. }
  725. static struct bnxt_re_qp *bnxt_re_create_shadow_qp
  726. (struct bnxt_re_pd *pd,
  727. struct bnxt_qplib_res *qp1_res,
  728. struct bnxt_qplib_qp *qp1_qp)
  729. {
  730. struct bnxt_re_dev *rdev = pd->rdev;
  731. struct bnxt_re_qp *qp;
  732. int rc;
  733. qp = kzalloc(sizeof(*qp), GFP_KERNEL);
  734. if (!qp)
  735. return NULL;
  736. memset(qp, 0, sizeof(*qp));
  737. qp->rdev = rdev;
  738. /* Initialize the shadow QP structure from the QP1 values */
  739. ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr);
  740. qp->qplib_qp.pd = &pd->qplib_pd;
  741. qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp);
  742. qp->qplib_qp.type = IB_QPT_UD;
  743. qp->qplib_qp.max_inline_data = 0;
  744. qp->qplib_qp.sig_type = true;
  745. /* Shadow QP SQ depth should be same as QP1 RQ depth */
  746. qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe;
  747. qp->qplib_qp.sq.max_sge = 2;
  748. qp->qplib_qp.scq = qp1_qp->scq;
  749. qp->qplib_qp.rcq = qp1_qp->rcq;
  750. qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe;
  751. qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge;
  752. qp->qplib_qp.mtu = qp1_qp->mtu;
  753. qp->qplib_qp.sq_hdr_buf_size = 0;
  754. qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
  755. qp->qplib_qp.dpi = &rdev->dpi_privileged;
  756. rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp);
  757. if (rc)
  758. goto fail;
  759. rdev->sqp_id = qp->qplib_qp.id;
  760. spin_lock_init(&qp->sq_lock);
  761. INIT_LIST_HEAD(&qp->list);
  762. mutex_lock(&rdev->qp_lock);
  763. list_add_tail(&qp->list, &rdev->qp_list);
  764. atomic_inc(&rdev->qp_count);
  765. mutex_unlock(&rdev->qp_lock);
  766. return qp;
  767. fail:
  768. kfree(qp);
  769. return NULL;
  770. }
  771. struct ib_qp *bnxt_re_create_qp(struct ib_pd *ib_pd,
  772. struct ib_qp_init_attr *qp_init_attr,
  773. struct ib_udata *udata)
  774. {
  775. struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
  776. struct bnxt_re_dev *rdev = pd->rdev;
  777. struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
  778. struct bnxt_re_qp *qp;
  779. struct bnxt_re_cq *cq;
  780. int rc, entries;
  781. if ((qp_init_attr->cap.max_send_wr > dev_attr->max_qp_wqes) ||
  782. (qp_init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes) ||
  783. (qp_init_attr->cap.max_send_sge > dev_attr->max_qp_sges) ||
  784. (qp_init_attr->cap.max_recv_sge > dev_attr->max_qp_sges) ||
  785. (qp_init_attr->cap.max_inline_data > dev_attr->max_inline_data))
  786. return ERR_PTR(-EINVAL);
  787. qp = kzalloc(sizeof(*qp), GFP_KERNEL);
  788. if (!qp)
  789. return ERR_PTR(-ENOMEM);
  790. qp->rdev = rdev;
  791. ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr);
  792. qp->qplib_qp.pd = &pd->qplib_pd;
  793. qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp);
  794. qp->qplib_qp.type = __from_ib_qp_type(qp_init_attr->qp_type);
  795. if (qp->qplib_qp.type == IB_QPT_MAX) {
  796. dev_err(rdev_to_dev(rdev), "QP type 0x%x not supported",
  797. qp->qplib_qp.type);
  798. rc = -EINVAL;
  799. goto fail;
  800. }
  801. qp->qplib_qp.max_inline_data = qp_init_attr->cap.max_inline_data;
  802. qp->qplib_qp.sig_type = ((qp_init_attr->sq_sig_type ==
  803. IB_SIGNAL_ALL_WR) ? true : false);
  804. entries = roundup_pow_of_two(qp_init_attr->cap.max_send_wr + 1);
  805. qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
  806. dev_attr->max_qp_wqes + 1);
  807. qp->qplib_qp.sq.max_sge = qp_init_attr->cap.max_send_sge;
  808. if (qp->qplib_qp.sq.max_sge > dev_attr->max_qp_sges)
  809. qp->qplib_qp.sq.max_sge = dev_attr->max_qp_sges;
  810. if (qp_init_attr->send_cq) {
  811. cq = container_of(qp_init_attr->send_cq, struct bnxt_re_cq,
  812. ib_cq);
  813. if (!cq) {
  814. dev_err(rdev_to_dev(rdev), "Send CQ not found");
  815. rc = -EINVAL;
  816. goto fail;
  817. }
  818. qp->qplib_qp.scq = &cq->qplib_cq;
  819. }
  820. if (qp_init_attr->recv_cq) {
  821. cq = container_of(qp_init_attr->recv_cq, struct bnxt_re_cq,
  822. ib_cq);
  823. if (!cq) {
  824. dev_err(rdev_to_dev(rdev), "Receive CQ not found");
  825. rc = -EINVAL;
  826. goto fail;
  827. }
  828. qp->qplib_qp.rcq = &cq->qplib_cq;
  829. }
  830. if (qp_init_attr->srq) {
  831. dev_err(rdev_to_dev(rdev), "SRQ not supported");
  832. rc = -ENOTSUPP;
  833. goto fail;
  834. } else {
  835. /* Allocate 1 more than what's provided so posting max doesn't
  836. * mean empty
  837. */
  838. entries = roundup_pow_of_two(qp_init_attr->cap.max_recv_wr + 1);
  839. qp->qplib_qp.rq.max_wqe = min_t(u32, entries,
  840. dev_attr->max_qp_wqes + 1);
  841. qp->qplib_qp.rq.max_sge = qp_init_attr->cap.max_recv_sge;
  842. if (qp->qplib_qp.rq.max_sge > dev_attr->max_qp_sges)
  843. qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges;
  844. }
  845. qp->qplib_qp.mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
  846. if (qp_init_attr->qp_type == IB_QPT_GSI) {
  847. qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges;
  848. if (qp->qplib_qp.rq.max_sge > dev_attr->max_qp_sges)
  849. qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges;
  850. qp->qplib_qp.sq.max_sge++;
  851. if (qp->qplib_qp.sq.max_sge > dev_attr->max_qp_sges)
  852. qp->qplib_qp.sq.max_sge = dev_attr->max_qp_sges;
  853. qp->qplib_qp.rq_hdr_buf_size =
  854. BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
  855. qp->qplib_qp.sq_hdr_buf_size =
  856. BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2;
  857. qp->qplib_qp.dpi = &rdev->dpi_privileged;
  858. rc = bnxt_qplib_create_qp1(&rdev->qplib_res, &qp->qplib_qp);
  859. if (rc) {
  860. dev_err(rdev_to_dev(rdev), "Failed to create HW QP1");
  861. goto fail;
  862. }
  863. /* Create a shadow QP to handle the QP1 traffic */
  864. rdev->qp1_sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res,
  865. &qp->qplib_qp);
  866. if (!rdev->qp1_sqp) {
  867. rc = -EINVAL;
  868. dev_err(rdev_to_dev(rdev),
  869. "Failed to create Shadow QP for QP1");
  870. goto qp_destroy;
  871. }
  872. rdev->sqp_ah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res,
  873. &qp->qplib_qp);
  874. if (!rdev->sqp_ah) {
  875. bnxt_qplib_destroy_qp(&rdev->qplib_res,
  876. &rdev->qp1_sqp->qplib_qp);
  877. rc = -EINVAL;
  878. dev_err(rdev_to_dev(rdev),
  879. "Failed to create AH entry for ShadowQP");
  880. goto qp_destroy;
  881. }
  882. } else {
  883. qp->qplib_qp.max_rd_atomic = dev_attr->max_qp_rd_atom;
  884. qp->qplib_qp.max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom;
  885. if (udata) {
  886. rc = bnxt_re_init_user_qp(rdev, pd, qp, udata);
  887. if (rc)
  888. goto fail;
  889. } else {
  890. qp->qplib_qp.dpi = &rdev->dpi_privileged;
  891. }
  892. rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp);
  893. if (rc) {
  894. dev_err(rdev_to_dev(rdev), "Failed to create HW QP");
  895. goto fail;
  896. }
  897. }
  898. qp->ib_qp.qp_num = qp->qplib_qp.id;
  899. spin_lock_init(&qp->sq_lock);
  900. if (udata) {
  901. struct bnxt_re_qp_resp resp;
  902. resp.qpid = qp->ib_qp.qp_num;
  903. resp.rsvd = 0;
  904. rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
  905. if (rc) {
  906. dev_err(rdev_to_dev(rdev), "Failed to copy QP udata");
  907. goto qp_destroy;
  908. }
  909. }
  910. INIT_LIST_HEAD(&qp->list);
  911. mutex_lock(&rdev->qp_lock);
  912. list_add_tail(&qp->list, &rdev->qp_list);
  913. atomic_inc(&rdev->qp_count);
  914. mutex_unlock(&rdev->qp_lock);
  915. return &qp->ib_qp;
  916. qp_destroy:
  917. bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
  918. fail:
  919. kfree(qp);
  920. return ERR_PTR(rc);
  921. }
  922. static u8 __from_ib_qp_state(enum ib_qp_state state)
  923. {
  924. switch (state) {
  925. case IB_QPS_RESET:
  926. return CMDQ_MODIFY_QP_NEW_STATE_RESET;
  927. case IB_QPS_INIT:
  928. return CMDQ_MODIFY_QP_NEW_STATE_INIT;
  929. case IB_QPS_RTR:
  930. return CMDQ_MODIFY_QP_NEW_STATE_RTR;
  931. case IB_QPS_RTS:
  932. return CMDQ_MODIFY_QP_NEW_STATE_RTS;
  933. case IB_QPS_SQD:
  934. return CMDQ_MODIFY_QP_NEW_STATE_SQD;
  935. case IB_QPS_SQE:
  936. return CMDQ_MODIFY_QP_NEW_STATE_SQE;
  937. case IB_QPS_ERR:
  938. default:
  939. return CMDQ_MODIFY_QP_NEW_STATE_ERR;
  940. }
  941. }
  942. static enum ib_qp_state __to_ib_qp_state(u8 state)
  943. {
  944. switch (state) {
  945. case CMDQ_MODIFY_QP_NEW_STATE_RESET:
  946. return IB_QPS_RESET;
  947. case CMDQ_MODIFY_QP_NEW_STATE_INIT:
  948. return IB_QPS_INIT;
  949. case CMDQ_MODIFY_QP_NEW_STATE_RTR:
  950. return IB_QPS_RTR;
  951. case CMDQ_MODIFY_QP_NEW_STATE_RTS:
  952. return IB_QPS_RTS;
  953. case CMDQ_MODIFY_QP_NEW_STATE_SQD:
  954. return IB_QPS_SQD;
  955. case CMDQ_MODIFY_QP_NEW_STATE_SQE:
  956. return IB_QPS_SQE;
  957. case CMDQ_MODIFY_QP_NEW_STATE_ERR:
  958. default:
  959. return IB_QPS_ERR;
  960. }
  961. }
  962. static u32 __from_ib_mtu(enum ib_mtu mtu)
  963. {
  964. switch (mtu) {
  965. case IB_MTU_256:
  966. return CMDQ_MODIFY_QP_PATH_MTU_MTU_256;
  967. case IB_MTU_512:
  968. return CMDQ_MODIFY_QP_PATH_MTU_MTU_512;
  969. case IB_MTU_1024:
  970. return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024;
  971. case IB_MTU_2048:
  972. return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
  973. case IB_MTU_4096:
  974. return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096;
  975. default:
  976. return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
  977. }
  978. }
  979. static enum ib_mtu __to_ib_mtu(u32 mtu)
  980. {
  981. switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) {
  982. case CMDQ_MODIFY_QP_PATH_MTU_MTU_256:
  983. return IB_MTU_256;
  984. case CMDQ_MODIFY_QP_PATH_MTU_MTU_512:
  985. return IB_MTU_512;
  986. case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024:
  987. return IB_MTU_1024;
  988. case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048:
  989. return IB_MTU_2048;
  990. case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096:
  991. return IB_MTU_4096;
  992. default:
  993. return IB_MTU_2048;
  994. }
  995. }
  996. static int __from_ib_access_flags(int iflags)
  997. {
  998. int qflags = 0;
  999. if (iflags & IB_ACCESS_LOCAL_WRITE)
  1000. qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
  1001. if (iflags & IB_ACCESS_REMOTE_READ)
  1002. qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ;
  1003. if (iflags & IB_ACCESS_REMOTE_WRITE)
  1004. qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE;
  1005. if (iflags & IB_ACCESS_REMOTE_ATOMIC)
  1006. qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC;
  1007. if (iflags & IB_ACCESS_MW_BIND)
  1008. qflags |= BNXT_QPLIB_ACCESS_MW_BIND;
  1009. if (iflags & IB_ZERO_BASED)
  1010. qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED;
  1011. if (iflags & IB_ACCESS_ON_DEMAND)
  1012. qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND;
  1013. return qflags;
  1014. };
  1015. static enum ib_access_flags __to_ib_access_flags(int qflags)
  1016. {
  1017. enum ib_access_flags iflags = 0;
  1018. if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE)
  1019. iflags |= IB_ACCESS_LOCAL_WRITE;
  1020. if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE)
  1021. iflags |= IB_ACCESS_REMOTE_WRITE;
  1022. if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ)
  1023. iflags |= IB_ACCESS_REMOTE_READ;
  1024. if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC)
  1025. iflags |= IB_ACCESS_REMOTE_ATOMIC;
  1026. if (qflags & BNXT_QPLIB_ACCESS_MW_BIND)
  1027. iflags |= IB_ACCESS_MW_BIND;
  1028. if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED)
  1029. iflags |= IB_ZERO_BASED;
  1030. if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND)
  1031. iflags |= IB_ACCESS_ON_DEMAND;
  1032. return iflags;
  1033. };
  1034. static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev,
  1035. struct bnxt_re_qp *qp1_qp,
  1036. int qp_attr_mask)
  1037. {
  1038. struct bnxt_re_qp *qp = rdev->qp1_sqp;
  1039. int rc = 0;
  1040. if (qp_attr_mask & IB_QP_STATE) {
  1041. qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
  1042. qp->qplib_qp.state = qp1_qp->qplib_qp.state;
  1043. }
  1044. if (qp_attr_mask & IB_QP_PKEY_INDEX) {
  1045. qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
  1046. qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index;
  1047. }
  1048. if (qp_attr_mask & IB_QP_QKEY) {
  1049. qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
  1050. /* Using a Random QKEY */
  1051. qp->qplib_qp.qkey = 0x81818181;
  1052. }
  1053. if (qp_attr_mask & IB_QP_SQ_PSN) {
  1054. qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
  1055. qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn;
  1056. }
  1057. rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
  1058. if (rc)
  1059. dev_err(rdev_to_dev(rdev),
  1060. "Failed to modify Shadow QP for QP1");
  1061. return rc;
  1062. }
  1063. int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
  1064. int qp_attr_mask, struct ib_udata *udata)
  1065. {
  1066. struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
  1067. struct bnxt_re_dev *rdev = qp->rdev;
  1068. struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
  1069. enum ib_qp_state curr_qp_state, new_qp_state;
  1070. int rc, entries;
  1071. int status;
  1072. union ib_gid sgid;
  1073. struct ib_gid_attr sgid_attr;
  1074. u8 nw_type;
  1075. qp->qplib_qp.modify_flags = 0;
  1076. if (qp_attr_mask & IB_QP_STATE) {
  1077. curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state);
  1078. new_qp_state = qp_attr->qp_state;
  1079. if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state,
  1080. ib_qp->qp_type, qp_attr_mask,
  1081. IB_LINK_LAYER_ETHERNET)) {
  1082. dev_err(rdev_to_dev(rdev),
  1083. "Invalid attribute mask: %#x specified ",
  1084. qp_attr_mask);
  1085. dev_err(rdev_to_dev(rdev),
  1086. "for qpn: %#x type: %#x",
  1087. ib_qp->qp_num, ib_qp->qp_type);
  1088. dev_err(rdev_to_dev(rdev),
  1089. "curr_qp_state=0x%x, new_qp_state=0x%x\n",
  1090. curr_qp_state, new_qp_state);
  1091. return -EINVAL;
  1092. }
  1093. qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
  1094. qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state);
  1095. }
  1096. if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) {
  1097. qp->qplib_qp.modify_flags |=
  1098. CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY;
  1099. qp->qplib_qp.en_sqd_async_notify = true;
  1100. }
  1101. if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
  1102. qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS;
  1103. qp->qplib_qp.access =
  1104. __from_ib_access_flags(qp_attr->qp_access_flags);
  1105. /* LOCAL_WRITE access must be set to allow RC receive */
  1106. qp->qplib_qp.access |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
  1107. }
  1108. if (qp_attr_mask & IB_QP_PKEY_INDEX) {
  1109. qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
  1110. qp->qplib_qp.pkey_index = qp_attr->pkey_index;
  1111. }
  1112. if (qp_attr_mask & IB_QP_QKEY) {
  1113. qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
  1114. qp->qplib_qp.qkey = qp_attr->qkey;
  1115. }
  1116. if (qp_attr_mask & IB_QP_AV) {
  1117. const struct ib_global_route *grh =
  1118. rdma_ah_read_grh(&qp_attr->ah_attr);
  1119. qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID |
  1120. CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL |
  1121. CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX |
  1122. CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT |
  1123. CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS |
  1124. CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC |
  1125. CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID;
  1126. memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw,
  1127. sizeof(qp->qplib_qp.ah.dgid.data));
  1128. qp->qplib_qp.ah.flow_label = grh->flow_label;
  1129. /* If RoCE V2 is enabled, stack will have two entries for
  1130. * each GID entry. Avoiding this duplicte entry in HW. Dividing
  1131. * the GID index by 2 for RoCE V2
  1132. */
  1133. qp->qplib_qp.ah.sgid_index = grh->sgid_index / 2;
  1134. qp->qplib_qp.ah.host_sgid_index = grh->sgid_index;
  1135. qp->qplib_qp.ah.hop_limit = grh->hop_limit;
  1136. qp->qplib_qp.ah.traffic_class = grh->traffic_class;
  1137. qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr);
  1138. ether_addr_copy(qp->qplib_qp.ah.dmac,
  1139. qp_attr->ah_attr.roce.dmac);
  1140. status = ib_get_cached_gid(&rdev->ibdev, 1,
  1141. grh->sgid_index,
  1142. &sgid, &sgid_attr);
  1143. if (!status && sgid_attr.ndev) {
  1144. memcpy(qp->qplib_qp.smac, sgid_attr.ndev->dev_addr,
  1145. ETH_ALEN);
  1146. dev_put(sgid_attr.ndev);
  1147. nw_type = ib_gid_to_network_type(sgid_attr.gid_type,
  1148. &sgid);
  1149. switch (nw_type) {
  1150. case RDMA_NETWORK_IPV4:
  1151. qp->qplib_qp.nw_type =
  1152. CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4;
  1153. break;
  1154. case RDMA_NETWORK_IPV6:
  1155. qp->qplib_qp.nw_type =
  1156. CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6;
  1157. break;
  1158. default:
  1159. qp->qplib_qp.nw_type =
  1160. CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1;
  1161. break;
  1162. }
  1163. }
  1164. }
  1165. if (qp_attr_mask & IB_QP_PATH_MTU) {
  1166. qp->qplib_qp.modify_flags |=
  1167. CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
  1168. qp->qplib_qp.path_mtu = __from_ib_mtu(qp_attr->path_mtu);
  1169. } else if (qp_attr->qp_state == IB_QPS_RTR) {
  1170. qp->qplib_qp.modify_flags |=
  1171. CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
  1172. qp->qplib_qp.path_mtu =
  1173. __from_ib_mtu(iboe_get_mtu(rdev->netdev->mtu));
  1174. }
  1175. if (qp_attr_mask & IB_QP_TIMEOUT) {
  1176. qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT;
  1177. qp->qplib_qp.timeout = qp_attr->timeout;
  1178. }
  1179. if (qp_attr_mask & IB_QP_RETRY_CNT) {
  1180. qp->qplib_qp.modify_flags |=
  1181. CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT;
  1182. qp->qplib_qp.retry_cnt = qp_attr->retry_cnt;
  1183. }
  1184. if (qp_attr_mask & IB_QP_RNR_RETRY) {
  1185. qp->qplib_qp.modify_flags |=
  1186. CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY;
  1187. qp->qplib_qp.rnr_retry = qp_attr->rnr_retry;
  1188. }
  1189. if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) {
  1190. qp->qplib_qp.modify_flags |=
  1191. CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER;
  1192. qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer;
  1193. }
  1194. if (qp_attr_mask & IB_QP_RQ_PSN) {
  1195. qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN;
  1196. qp->qplib_qp.rq.psn = qp_attr->rq_psn;
  1197. }
  1198. if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
  1199. qp->qplib_qp.modify_flags |=
  1200. CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC;
  1201. qp->qplib_qp.max_rd_atomic = qp_attr->max_rd_atomic;
  1202. }
  1203. if (qp_attr_mask & IB_QP_SQ_PSN) {
  1204. qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
  1205. qp->qplib_qp.sq.psn = qp_attr->sq_psn;
  1206. }
  1207. if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
  1208. qp->qplib_qp.modify_flags |=
  1209. CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC;
  1210. qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic;
  1211. }
  1212. if (qp_attr_mask & IB_QP_CAP) {
  1213. qp->qplib_qp.modify_flags |=
  1214. CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE |
  1215. CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE |
  1216. CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE |
  1217. CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE |
  1218. CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA;
  1219. if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) ||
  1220. (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) ||
  1221. (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) ||
  1222. (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) ||
  1223. (qp_attr->cap.max_inline_data >=
  1224. dev_attr->max_inline_data)) {
  1225. dev_err(rdev_to_dev(rdev),
  1226. "Create QP failed - max exceeded");
  1227. return -EINVAL;
  1228. }
  1229. entries = roundup_pow_of_two(qp_attr->cap.max_send_wr);
  1230. qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
  1231. dev_attr->max_qp_wqes + 1);
  1232. qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge;
  1233. if (qp->qplib_qp.rq.max_wqe) {
  1234. entries = roundup_pow_of_two(qp_attr->cap.max_recv_wr);
  1235. qp->qplib_qp.rq.max_wqe =
  1236. min_t(u32, entries, dev_attr->max_qp_wqes + 1);
  1237. qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge;
  1238. } else {
  1239. /* SRQ was used prior, just ignore the RQ caps */
  1240. }
  1241. }
  1242. if (qp_attr_mask & IB_QP_DEST_QPN) {
  1243. qp->qplib_qp.modify_flags |=
  1244. CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID;
  1245. qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num;
  1246. }
  1247. rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
  1248. if (rc) {
  1249. dev_err(rdev_to_dev(rdev), "Failed to modify HW QP");
  1250. return rc;
  1251. }
  1252. if (ib_qp->qp_type == IB_QPT_GSI && rdev->qp1_sqp)
  1253. rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask);
  1254. return rc;
  1255. }
  1256. int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
  1257. int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
  1258. {
  1259. struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
  1260. struct bnxt_re_dev *rdev = qp->rdev;
  1261. struct bnxt_qplib_qp qplib_qp;
  1262. int rc;
  1263. memset(&qplib_qp, 0, sizeof(struct bnxt_qplib_qp));
  1264. qplib_qp.id = qp->qplib_qp.id;
  1265. qplib_qp.ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index;
  1266. rc = bnxt_qplib_query_qp(&rdev->qplib_res, &qplib_qp);
  1267. if (rc) {
  1268. dev_err(rdev_to_dev(rdev), "Failed to query HW QP");
  1269. return rc;
  1270. }
  1271. qp_attr->qp_state = __to_ib_qp_state(qplib_qp.state);
  1272. qp_attr->en_sqd_async_notify = qplib_qp.en_sqd_async_notify ? 1 : 0;
  1273. qp_attr->qp_access_flags = __to_ib_access_flags(qplib_qp.access);
  1274. qp_attr->pkey_index = qplib_qp.pkey_index;
  1275. qp_attr->qkey = qplib_qp.qkey;
  1276. qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
  1277. rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp.ah.flow_label,
  1278. qplib_qp.ah.host_sgid_index,
  1279. qplib_qp.ah.hop_limit,
  1280. qplib_qp.ah.traffic_class);
  1281. rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp.ah.dgid.data);
  1282. rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp.ah.sl);
  1283. ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp.ah.dmac);
  1284. qp_attr->path_mtu = __to_ib_mtu(qplib_qp.path_mtu);
  1285. qp_attr->timeout = qplib_qp.timeout;
  1286. qp_attr->retry_cnt = qplib_qp.retry_cnt;
  1287. qp_attr->rnr_retry = qplib_qp.rnr_retry;
  1288. qp_attr->min_rnr_timer = qplib_qp.min_rnr_timer;
  1289. qp_attr->rq_psn = qplib_qp.rq.psn;
  1290. qp_attr->max_rd_atomic = qplib_qp.max_rd_atomic;
  1291. qp_attr->sq_psn = qplib_qp.sq.psn;
  1292. qp_attr->max_dest_rd_atomic = qplib_qp.max_dest_rd_atomic;
  1293. qp_init_attr->sq_sig_type = qplib_qp.sig_type ? IB_SIGNAL_ALL_WR :
  1294. IB_SIGNAL_REQ_WR;
  1295. qp_attr->dest_qp_num = qplib_qp.dest_qpn;
  1296. qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe;
  1297. qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge;
  1298. qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe;
  1299. qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge;
  1300. qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data;
  1301. qp_init_attr->cap = qp_attr->cap;
  1302. return 0;
  1303. }
  1304. /* Routine for sending QP1 packets for RoCE V1 an V2
  1305. */
  1306. static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp,
  1307. struct ib_send_wr *wr,
  1308. struct bnxt_qplib_swqe *wqe,
  1309. int payload_size)
  1310. {
  1311. struct ib_device *ibdev = &qp->rdev->ibdev;
  1312. struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah,
  1313. ib_ah);
  1314. struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah;
  1315. struct bnxt_qplib_sge sge;
  1316. union ib_gid sgid;
  1317. u8 nw_type;
  1318. u16 ether_type;
  1319. struct ib_gid_attr sgid_attr;
  1320. union ib_gid dgid;
  1321. bool is_eth = false;
  1322. bool is_vlan = false;
  1323. bool is_grh = false;
  1324. bool is_udp = false;
  1325. u8 ip_version = 0;
  1326. u16 vlan_id = 0xFFFF;
  1327. void *buf;
  1328. int i, rc = 0, size;
  1329. memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr));
  1330. rc = ib_get_cached_gid(ibdev, 1,
  1331. qplib_ah->host_sgid_index, &sgid,
  1332. &sgid_attr);
  1333. if (rc) {
  1334. dev_err(rdev_to_dev(qp->rdev),
  1335. "Failed to query gid at index %d",
  1336. qplib_ah->host_sgid_index);
  1337. return rc;
  1338. }
  1339. if (sgid_attr.ndev) {
  1340. if (is_vlan_dev(sgid_attr.ndev))
  1341. vlan_id = vlan_dev_vlan_id(sgid_attr.ndev);
  1342. dev_put(sgid_attr.ndev);
  1343. }
  1344. /* Get network header type for this GID */
  1345. nw_type = ib_gid_to_network_type(sgid_attr.gid_type, &sgid);
  1346. switch (nw_type) {
  1347. case RDMA_NETWORK_IPV4:
  1348. nw_type = BNXT_RE_ROCEV2_IPV4_PACKET;
  1349. break;
  1350. case RDMA_NETWORK_IPV6:
  1351. nw_type = BNXT_RE_ROCEV2_IPV6_PACKET;
  1352. break;
  1353. default:
  1354. nw_type = BNXT_RE_ROCE_V1_PACKET;
  1355. break;
  1356. }
  1357. memcpy(&dgid.raw, &qplib_ah->dgid, 16);
  1358. is_udp = sgid_attr.gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
  1359. if (is_udp) {
  1360. if (ipv6_addr_v4mapped((struct in6_addr *)&sgid)) {
  1361. ip_version = 4;
  1362. ether_type = ETH_P_IP;
  1363. } else {
  1364. ip_version = 6;
  1365. ether_type = ETH_P_IPV6;
  1366. }
  1367. is_grh = false;
  1368. } else {
  1369. ether_type = ETH_P_IBOE;
  1370. is_grh = true;
  1371. }
  1372. is_eth = true;
  1373. is_vlan = (vlan_id && (vlan_id < 0x1000)) ? true : false;
  1374. ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh,
  1375. ip_version, is_udp, 0, &qp->qp1_hdr);
  1376. /* ETH */
  1377. ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac);
  1378. ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac);
  1379. /* For vlan, check the sgid for vlan existence */
  1380. if (!is_vlan) {
  1381. qp->qp1_hdr.eth.type = cpu_to_be16(ether_type);
  1382. } else {
  1383. qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type);
  1384. qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id);
  1385. }
  1386. if (is_grh || (ip_version == 6)) {
  1387. memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid.raw, sizeof(sgid));
  1388. memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data,
  1389. sizeof(sgid));
  1390. qp->qp1_hdr.grh.hop_limit = qplib_ah->hop_limit;
  1391. }
  1392. if (ip_version == 4) {
  1393. qp->qp1_hdr.ip4.tos = 0;
  1394. qp->qp1_hdr.ip4.id = 0;
  1395. qp->qp1_hdr.ip4.frag_off = htons(IP_DF);
  1396. qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit;
  1397. memcpy(&qp->qp1_hdr.ip4.saddr, sgid.raw + 12, 4);
  1398. memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4);
  1399. qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr);
  1400. }
  1401. if (is_udp) {
  1402. qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT);
  1403. qp->qp1_hdr.udp.sport = htons(0x8CD1);
  1404. qp->qp1_hdr.udp.csum = 0;
  1405. }
  1406. /* BTH */
  1407. if (wr->opcode == IB_WR_SEND_WITH_IMM) {
  1408. qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
  1409. qp->qp1_hdr.immediate_present = 1;
  1410. } else {
  1411. qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
  1412. }
  1413. if (wr->send_flags & IB_SEND_SOLICITED)
  1414. qp->qp1_hdr.bth.solicited_event = 1;
  1415. /* pad_count */
  1416. qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3;
  1417. /* P_key for QP1 is for all members */
  1418. qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF);
  1419. qp->qp1_hdr.bth.destination_qpn = IB_QP1;
  1420. qp->qp1_hdr.bth.ack_req = 0;
  1421. qp->send_psn++;
  1422. qp->send_psn &= BTH_PSN_MASK;
  1423. qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn);
  1424. /* DETH */
  1425. /* Use the priviledged Q_Key for QP1 */
  1426. qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY);
  1427. qp->qp1_hdr.deth.source_qpn = IB_QP1;
  1428. /* Pack the QP1 to the transmit buffer */
  1429. buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge);
  1430. if (buf) {
  1431. size = ib_ud_header_pack(&qp->qp1_hdr, buf);
  1432. for (i = wqe->num_sge; i; i--) {
  1433. wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr;
  1434. wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey;
  1435. wqe->sg_list[i].size = wqe->sg_list[i - 1].size;
  1436. }
  1437. /*
  1438. * Max Header buf size for IPV6 RoCE V2 is 86,
  1439. * which is same as the QP1 SQ header buffer.
  1440. * Header buf size for IPV4 RoCE V2 can be 66.
  1441. * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20).
  1442. * Subtract 20 bytes from QP1 SQ header buf size
  1443. */
  1444. if (is_udp && ip_version == 4)
  1445. sge.size -= 20;
  1446. /*
  1447. * Max Header buf size for RoCE V1 is 78.
  1448. * ETH(14) + VLAN(4) + GRH(40) + BTH(20).
  1449. * Subtract 8 bytes from QP1 SQ header buf size
  1450. */
  1451. if (!is_udp)
  1452. sge.size -= 8;
  1453. /* Subtract 4 bytes for non vlan packets */
  1454. if (!is_vlan)
  1455. sge.size -= 4;
  1456. wqe->sg_list[0].addr = sge.addr;
  1457. wqe->sg_list[0].lkey = sge.lkey;
  1458. wqe->sg_list[0].size = sge.size;
  1459. wqe->num_sge++;
  1460. } else {
  1461. dev_err(rdev_to_dev(qp->rdev), "QP1 buffer is empty!");
  1462. rc = -ENOMEM;
  1463. }
  1464. return rc;
  1465. }
  1466. /* For the MAD layer, it only provides the recv SGE the size of
  1467. * ib_grh + MAD datagram. No Ethernet headers, Ethertype, BTH, DETH,
  1468. * nor RoCE iCRC. The Cu+ solution must provide buffer for the entire
  1469. * receive packet (334 bytes) with no VLAN and then copy the GRH
  1470. * and the MAD datagram out to the provided SGE.
  1471. */
  1472. static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp,
  1473. struct ib_recv_wr *wr,
  1474. struct bnxt_qplib_swqe *wqe,
  1475. int payload_size)
  1476. {
  1477. struct bnxt_qplib_sge ref, sge;
  1478. u32 rq_prod_index;
  1479. struct bnxt_re_sqp_entries *sqp_entry;
  1480. rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp);
  1481. if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge))
  1482. return -ENOMEM;
  1483. /* Create 1 SGE to receive the entire
  1484. * ethernet packet
  1485. */
  1486. /* Save the reference from ULP */
  1487. ref.addr = wqe->sg_list[0].addr;
  1488. ref.lkey = wqe->sg_list[0].lkey;
  1489. ref.size = wqe->sg_list[0].size;
  1490. sqp_entry = &qp->rdev->sqp_tbl[rq_prod_index];
  1491. /* SGE 1 */
  1492. wqe->sg_list[0].addr = sge.addr;
  1493. wqe->sg_list[0].lkey = sge.lkey;
  1494. wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
  1495. sge.size -= wqe->sg_list[0].size;
  1496. sqp_entry->sge.addr = ref.addr;
  1497. sqp_entry->sge.lkey = ref.lkey;
  1498. sqp_entry->sge.size = ref.size;
  1499. /* Store the wrid for reporting completion */
  1500. sqp_entry->wrid = wqe->wr_id;
  1501. /* change the wqe->wrid to table index */
  1502. wqe->wr_id = rq_prod_index;
  1503. return 0;
  1504. }
  1505. static int is_ud_qp(struct bnxt_re_qp *qp)
  1506. {
  1507. return qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD;
  1508. }
  1509. static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp,
  1510. struct ib_send_wr *wr,
  1511. struct bnxt_qplib_swqe *wqe)
  1512. {
  1513. struct bnxt_re_ah *ah = NULL;
  1514. if (is_ud_qp(qp)) {
  1515. ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah);
  1516. wqe->send.q_key = ud_wr(wr)->remote_qkey;
  1517. wqe->send.dst_qp = ud_wr(wr)->remote_qpn;
  1518. wqe->send.avid = ah->qplib_ah.id;
  1519. }
  1520. switch (wr->opcode) {
  1521. case IB_WR_SEND:
  1522. wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND;
  1523. break;
  1524. case IB_WR_SEND_WITH_IMM:
  1525. wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM;
  1526. wqe->send.imm_data = wr->ex.imm_data;
  1527. break;
  1528. case IB_WR_SEND_WITH_INV:
  1529. wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV;
  1530. wqe->send.inv_key = wr->ex.invalidate_rkey;
  1531. break;
  1532. default:
  1533. return -EINVAL;
  1534. }
  1535. if (wr->send_flags & IB_SEND_SIGNALED)
  1536. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
  1537. if (wr->send_flags & IB_SEND_FENCE)
  1538. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
  1539. if (wr->send_flags & IB_SEND_SOLICITED)
  1540. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
  1541. if (wr->send_flags & IB_SEND_INLINE)
  1542. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
  1543. return 0;
  1544. }
  1545. static int bnxt_re_build_rdma_wqe(struct ib_send_wr *wr,
  1546. struct bnxt_qplib_swqe *wqe)
  1547. {
  1548. switch (wr->opcode) {
  1549. case IB_WR_RDMA_WRITE:
  1550. wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE;
  1551. break;
  1552. case IB_WR_RDMA_WRITE_WITH_IMM:
  1553. wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM;
  1554. wqe->rdma.imm_data = wr->ex.imm_data;
  1555. break;
  1556. case IB_WR_RDMA_READ:
  1557. wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ;
  1558. wqe->rdma.inv_key = wr->ex.invalidate_rkey;
  1559. break;
  1560. default:
  1561. return -EINVAL;
  1562. }
  1563. wqe->rdma.remote_va = rdma_wr(wr)->remote_addr;
  1564. wqe->rdma.r_key = rdma_wr(wr)->rkey;
  1565. if (wr->send_flags & IB_SEND_SIGNALED)
  1566. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
  1567. if (wr->send_flags & IB_SEND_FENCE)
  1568. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
  1569. if (wr->send_flags & IB_SEND_SOLICITED)
  1570. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
  1571. if (wr->send_flags & IB_SEND_INLINE)
  1572. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
  1573. return 0;
  1574. }
  1575. static int bnxt_re_build_atomic_wqe(struct ib_send_wr *wr,
  1576. struct bnxt_qplib_swqe *wqe)
  1577. {
  1578. switch (wr->opcode) {
  1579. case IB_WR_ATOMIC_CMP_AND_SWP:
  1580. wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP;
  1581. wqe->atomic.swap_data = atomic_wr(wr)->swap;
  1582. break;
  1583. case IB_WR_ATOMIC_FETCH_AND_ADD:
  1584. wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD;
  1585. wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
  1586. break;
  1587. default:
  1588. return -EINVAL;
  1589. }
  1590. wqe->atomic.remote_va = atomic_wr(wr)->remote_addr;
  1591. wqe->atomic.r_key = atomic_wr(wr)->rkey;
  1592. if (wr->send_flags & IB_SEND_SIGNALED)
  1593. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
  1594. if (wr->send_flags & IB_SEND_FENCE)
  1595. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
  1596. if (wr->send_flags & IB_SEND_SOLICITED)
  1597. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
  1598. return 0;
  1599. }
  1600. static int bnxt_re_build_inv_wqe(struct ib_send_wr *wr,
  1601. struct bnxt_qplib_swqe *wqe)
  1602. {
  1603. wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV;
  1604. wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey;
  1605. if (wr->send_flags & IB_SEND_SIGNALED)
  1606. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
  1607. if (wr->send_flags & IB_SEND_FENCE)
  1608. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
  1609. if (wr->send_flags & IB_SEND_SOLICITED)
  1610. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
  1611. return 0;
  1612. }
  1613. static int bnxt_re_build_reg_wqe(struct ib_reg_wr *wr,
  1614. struct bnxt_qplib_swqe *wqe)
  1615. {
  1616. struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr);
  1617. struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl;
  1618. int access = wr->access;
  1619. wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0];
  1620. wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0];
  1621. wqe->frmr.page_list = mr->pages;
  1622. wqe->frmr.page_list_len = mr->npages;
  1623. wqe->frmr.levels = qplib_frpl->hwq.level + 1;
  1624. wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR;
  1625. if (wr->wr.send_flags & IB_SEND_FENCE)
  1626. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
  1627. if (wr->wr.send_flags & IB_SEND_SIGNALED)
  1628. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
  1629. if (access & IB_ACCESS_LOCAL_WRITE)
  1630. wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE;
  1631. if (access & IB_ACCESS_REMOTE_READ)
  1632. wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ;
  1633. if (access & IB_ACCESS_REMOTE_WRITE)
  1634. wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE;
  1635. if (access & IB_ACCESS_REMOTE_ATOMIC)
  1636. wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC;
  1637. if (access & IB_ACCESS_MW_BIND)
  1638. wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND;
  1639. wqe->frmr.l_key = wr->key;
  1640. wqe->frmr.length = wr->mr->length;
  1641. wqe->frmr.pbl_pg_sz_log = (wr->mr->page_size >> PAGE_SHIFT_4K) - 1;
  1642. wqe->frmr.va = wr->mr->iova;
  1643. return 0;
  1644. }
  1645. static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev,
  1646. struct ib_send_wr *wr,
  1647. struct bnxt_qplib_swqe *wqe)
  1648. {
  1649. /* Copy the inline data to the data field */
  1650. u8 *in_data;
  1651. u32 i, sge_len;
  1652. void *sge_addr;
  1653. in_data = wqe->inline_data;
  1654. for (i = 0; i < wr->num_sge; i++) {
  1655. sge_addr = (void *)(unsigned long)
  1656. wr->sg_list[i].addr;
  1657. sge_len = wr->sg_list[i].length;
  1658. if ((sge_len + wqe->inline_len) >
  1659. BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) {
  1660. dev_err(rdev_to_dev(rdev),
  1661. "Inline data size requested > supported value");
  1662. return -EINVAL;
  1663. }
  1664. sge_len = wr->sg_list[i].length;
  1665. memcpy(in_data, sge_addr, sge_len);
  1666. in_data += wr->sg_list[i].length;
  1667. wqe->inline_len += wr->sg_list[i].length;
  1668. }
  1669. return wqe->inline_len;
  1670. }
  1671. static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev,
  1672. struct ib_send_wr *wr,
  1673. struct bnxt_qplib_swqe *wqe)
  1674. {
  1675. int payload_sz = 0;
  1676. if (wr->send_flags & IB_SEND_INLINE)
  1677. payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe);
  1678. else
  1679. payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list,
  1680. wqe->num_sge);
  1681. return payload_sz;
  1682. }
  1683. static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev,
  1684. struct bnxt_re_qp *qp,
  1685. struct ib_send_wr *wr)
  1686. {
  1687. struct bnxt_qplib_swqe wqe;
  1688. int rc = 0, payload_sz = 0;
  1689. unsigned long flags;
  1690. spin_lock_irqsave(&qp->sq_lock, flags);
  1691. memset(&wqe, 0, sizeof(wqe));
  1692. while (wr) {
  1693. /* House keeping */
  1694. memset(&wqe, 0, sizeof(wqe));
  1695. /* Common */
  1696. wqe.num_sge = wr->num_sge;
  1697. if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
  1698. dev_err(rdev_to_dev(rdev),
  1699. "Limit exceeded for Send SGEs");
  1700. rc = -EINVAL;
  1701. goto bad;
  1702. }
  1703. payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
  1704. if (payload_sz < 0) {
  1705. rc = -EINVAL;
  1706. goto bad;
  1707. }
  1708. wqe.wr_id = wr->wr_id;
  1709. wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND;
  1710. rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
  1711. if (!rc)
  1712. rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
  1713. bad:
  1714. if (rc) {
  1715. dev_err(rdev_to_dev(rdev),
  1716. "Post send failed opcode = %#x rc = %d",
  1717. wr->opcode, rc);
  1718. break;
  1719. }
  1720. wr = wr->next;
  1721. }
  1722. bnxt_qplib_post_send_db(&qp->qplib_qp);
  1723. spin_unlock_irqrestore(&qp->sq_lock, flags);
  1724. return rc;
  1725. }
  1726. int bnxt_re_post_send(struct ib_qp *ib_qp, struct ib_send_wr *wr,
  1727. struct ib_send_wr **bad_wr)
  1728. {
  1729. struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
  1730. struct bnxt_qplib_swqe wqe;
  1731. int rc = 0, payload_sz = 0;
  1732. unsigned long flags;
  1733. spin_lock_irqsave(&qp->sq_lock, flags);
  1734. while (wr) {
  1735. /* House keeping */
  1736. memset(&wqe, 0, sizeof(wqe));
  1737. /* Common */
  1738. wqe.num_sge = wr->num_sge;
  1739. if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
  1740. dev_err(rdev_to_dev(qp->rdev),
  1741. "Limit exceeded for Send SGEs");
  1742. rc = -EINVAL;
  1743. goto bad;
  1744. }
  1745. payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
  1746. if (payload_sz < 0) {
  1747. rc = -EINVAL;
  1748. goto bad;
  1749. }
  1750. wqe.wr_id = wr->wr_id;
  1751. switch (wr->opcode) {
  1752. case IB_WR_SEND:
  1753. case IB_WR_SEND_WITH_IMM:
  1754. if (ib_qp->qp_type == IB_QPT_GSI) {
  1755. rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe,
  1756. payload_sz);
  1757. if (rc)
  1758. goto bad;
  1759. wqe.rawqp1.lflags |=
  1760. SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC;
  1761. }
  1762. switch (wr->send_flags) {
  1763. case IB_SEND_IP_CSUM:
  1764. wqe.rawqp1.lflags |=
  1765. SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM;
  1766. break;
  1767. default:
  1768. break;
  1769. }
  1770. /* Fall thru to build the wqe */
  1771. case IB_WR_SEND_WITH_INV:
  1772. rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
  1773. break;
  1774. case IB_WR_RDMA_WRITE:
  1775. case IB_WR_RDMA_WRITE_WITH_IMM:
  1776. case IB_WR_RDMA_READ:
  1777. rc = bnxt_re_build_rdma_wqe(wr, &wqe);
  1778. break;
  1779. case IB_WR_ATOMIC_CMP_AND_SWP:
  1780. case IB_WR_ATOMIC_FETCH_AND_ADD:
  1781. rc = bnxt_re_build_atomic_wqe(wr, &wqe);
  1782. break;
  1783. case IB_WR_RDMA_READ_WITH_INV:
  1784. dev_err(rdev_to_dev(qp->rdev),
  1785. "RDMA Read with Invalidate is not supported");
  1786. rc = -EINVAL;
  1787. goto bad;
  1788. case IB_WR_LOCAL_INV:
  1789. rc = bnxt_re_build_inv_wqe(wr, &wqe);
  1790. break;
  1791. case IB_WR_REG_MR:
  1792. rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe);
  1793. break;
  1794. default:
  1795. /* Unsupported WRs */
  1796. dev_err(rdev_to_dev(qp->rdev),
  1797. "WR (%#x) is not supported", wr->opcode);
  1798. rc = -EINVAL;
  1799. goto bad;
  1800. }
  1801. if (!rc)
  1802. rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
  1803. bad:
  1804. if (rc) {
  1805. dev_err(rdev_to_dev(qp->rdev),
  1806. "post_send failed op:%#x qps = %#x rc = %d\n",
  1807. wr->opcode, qp->qplib_qp.state, rc);
  1808. *bad_wr = wr;
  1809. break;
  1810. }
  1811. wr = wr->next;
  1812. }
  1813. bnxt_qplib_post_send_db(&qp->qplib_qp);
  1814. spin_unlock_irqrestore(&qp->sq_lock, flags);
  1815. return rc;
  1816. }
  1817. static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev,
  1818. struct bnxt_re_qp *qp,
  1819. struct ib_recv_wr *wr)
  1820. {
  1821. struct bnxt_qplib_swqe wqe;
  1822. int rc = 0, payload_sz = 0;
  1823. memset(&wqe, 0, sizeof(wqe));
  1824. while (wr) {
  1825. /* House keeping */
  1826. memset(&wqe, 0, sizeof(wqe));
  1827. /* Common */
  1828. wqe.num_sge = wr->num_sge;
  1829. if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
  1830. dev_err(rdev_to_dev(rdev),
  1831. "Limit exceeded for Receive SGEs");
  1832. rc = -EINVAL;
  1833. break;
  1834. }
  1835. payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list,
  1836. wr->num_sge);
  1837. wqe.wr_id = wr->wr_id;
  1838. wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
  1839. rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
  1840. if (rc)
  1841. break;
  1842. wr = wr->next;
  1843. }
  1844. if (!rc)
  1845. bnxt_qplib_post_recv_db(&qp->qplib_qp);
  1846. return rc;
  1847. }
  1848. int bnxt_re_post_recv(struct ib_qp *ib_qp, struct ib_recv_wr *wr,
  1849. struct ib_recv_wr **bad_wr)
  1850. {
  1851. struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
  1852. struct bnxt_qplib_swqe wqe;
  1853. int rc = 0, payload_sz = 0;
  1854. while (wr) {
  1855. /* House keeping */
  1856. memset(&wqe, 0, sizeof(wqe));
  1857. /* Common */
  1858. wqe.num_sge = wr->num_sge;
  1859. if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
  1860. dev_err(rdev_to_dev(qp->rdev),
  1861. "Limit exceeded for Receive SGEs");
  1862. rc = -EINVAL;
  1863. *bad_wr = wr;
  1864. break;
  1865. }
  1866. payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list,
  1867. wr->num_sge);
  1868. wqe.wr_id = wr->wr_id;
  1869. wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
  1870. if (ib_qp->qp_type == IB_QPT_GSI)
  1871. rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe,
  1872. payload_sz);
  1873. if (!rc)
  1874. rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
  1875. if (rc) {
  1876. *bad_wr = wr;
  1877. break;
  1878. }
  1879. wr = wr->next;
  1880. }
  1881. bnxt_qplib_post_recv_db(&qp->qplib_qp);
  1882. return rc;
  1883. }
  1884. /* Completion Queues */
  1885. int bnxt_re_destroy_cq(struct ib_cq *ib_cq)
  1886. {
  1887. struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
  1888. struct bnxt_re_dev *rdev = cq->rdev;
  1889. int rc;
  1890. rc = bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
  1891. if (rc) {
  1892. dev_err(rdev_to_dev(rdev), "Failed to destroy HW CQ");
  1893. return rc;
  1894. }
  1895. if (!IS_ERR_OR_NULL(cq->umem))
  1896. ib_umem_release(cq->umem);
  1897. if (cq) {
  1898. kfree(cq->cql);
  1899. kfree(cq);
  1900. }
  1901. atomic_dec(&rdev->cq_count);
  1902. rdev->nq.budget--;
  1903. return 0;
  1904. }
  1905. struct ib_cq *bnxt_re_create_cq(struct ib_device *ibdev,
  1906. const struct ib_cq_init_attr *attr,
  1907. struct ib_ucontext *context,
  1908. struct ib_udata *udata)
  1909. {
  1910. struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
  1911. struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
  1912. struct bnxt_re_cq *cq = NULL;
  1913. int rc, entries;
  1914. int cqe = attr->cqe;
  1915. /* Validate CQ fields */
  1916. if (cqe < 1 || cqe > dev_attr->max_cq_wqes) {
  1917. dev_err(rdev_to_dev(rdev), "Failed to create CQ -max exceeded");
  1918. return ERR_PTR(-EINVAL);
  1919. }
  1920. cq = kzalloc(sizeof(*cq), GFP_KERNEL);
  1921. if (!cq)
  1922. return ERR_PTR(-ENOMEM);
  1923. cq->rdev = rdev;
  1924. cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq);
  1925. entries = roundup_pow_of_two(cqe + 1);
  1926. if (entries > dev_attr->max_cq_wqes + 1)
  1927. entries = dev_attr->max_cq_wqes + 1;
  1928. if (context) {
  1929. struct bnxt_re_cq_req req;
  1930. struct bnxt_re_ucontext *uctx = container_of
  1931. (context,
  1932. struct bnxt_re_ucontext,
  1933. ib_uctx);
  1934. if (ib_copy_from_udata(&req, udata, sizeof(req))) {
  1935. rc = -EFAULT;
  1936. goto fail;
  1937. }
  1938. cq->umem = ib_umem_get(context, req.cq_va,
  1939. entries * sizeof(struct cq_base),
  1940. IB_ACCESS_LOCAL_WRITE, 1);
  1941. if (IS_ERR(cq->umem)) {
  1942. rc = PTR_ERR(cq->umem);
  1943. goto fail;
  1944. }
  1945. cq->qplib_cq.sghead = cq->umem->sg_head.sgl;
  1946. cq->qplib_cq.nmap = cq->umem->nmap;
  1947. cq->qplib_cq.dpi = uctx->dpi;
  1948. } else {
  1949. cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL);
  1950. cq->cql = kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe),
  1951. GFP_KERNEL);
  1952. if (!cq->cql) {
  1953. rc = -ENOMEM;
  1954. goto fail;
  1955. }
  1956. cq->qplib_cq.dpi = &rdev->dpi_privileged;
  1957. cq->qplib_cq.sghead = NULL;
  1958. cq->qplib_cq.nmap = 0;
  1959. }
  1960. cq->qplib_cq.max_wqe = entries;
  1961. cq->qplib_cq.cnq_hw_ring_id = rdev->nq.ring_id;
  1962. rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq);
  1963. if (rc) {
  1964. dev_err(rdev_to_dev(rdev), "Failed to create HW CQ");
  1965. goto fail;
  1966. }
  1967. cq->ib_cq.cqe = entries;
  1968. cq->cq_period = cq->qplib_cq.period;
  1969. rdev->nq.budget++;
  1970. atomic_inc(&rdev->cq_count);
  1971. if (context) {
  1972. struct bnxt_re_cq_resp resp;
  1973. resp.cqid = cq->qplib_cq.id;
  1974. resp.tail = cq->qplib_cq.hwq.cons;
  1975. resp.phase = cq->qplib_cq.period;
  1976. resp.rsvd = 0;
  1977. rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
  1978. if (rc) {
  1979. dev_err(rdev_to_dev(rdev), "Failed to copy CQ udata");
  1980. bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
  1981. goto c2fail;
  1982. }
  1983. }
  1984. return &cq->ib_cq;
  1985. c2fail:
  1986. if (context)
  1987. ib_umem_release(cq->umem);
  1988. fail:
  1989. kfree(cq->cql);
  1990. kfree(cq);
  1991. return ERR_PTR(rc);
  1992. }
  1993. static u8 __req_to_ib_wc_status(u8 qstatus)
  1994. {
  1995. switch (qstatus) {
  1996. case CQ_REQ_STATUS_OK:
  1997. return IB_WC_SUCCESS;
  1998. case CQ_REQ_STATUS_BAD_RESPONSE_ERR:
  1999. return IB_WC_BAD_RESP_ERR;
  2000. case CQ_REQ_STATUS_LOCAL_LENGTH_ERR:
  2001. return IB_WC_LOC_LEN_ERR;
  2002. case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR:
  2003. return IB_WC_LOC_QP_OP_ERR;
  2004. case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR:
  2005. return IB_WC_LOC_PROT_ERR;
  2006. case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR:
  2007. return IB_WC_GENERAL_ERR;
  2008. case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR:
  2009. return IB_WC_REM_INV_REQ_ERR;
  2010. case CQ_REQ_STATUS_REMOTE_ACCESS_ERR:
  2011. return IB_WC_REM_ACCESS_ERR;
  2012. case CQ_REQ_STATUS_REMOTE_OPERATION_ERR:
  2013. return IB_WC_REM_OP_ERR;
  2014. case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR:
  2015. return IB_WC_RNR_RETRY_EXC_ERR;
  2016. case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR:
  2017. return IB_WC_RETRY_EXC_ERR;
  2018. case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR:
  2019. return IB_WC_WR_FLUSH_ERR;
  2020. default:
  2021. return IB_WC_GENERAL_ERR;
  2022. }
  2023. return 0;
  2024. }
  2025. static u8 __rawqp1_to_ib_wc_status(u8 qstatus)
  2026. {
  2027. switch (qstatus) {
  2028. case CQ_RES_RAWETH_QP1_STATUS_OK:
  2029. return IB_WC_SUCCESS;
  2030. case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR:
  2031. return IB_WC_LOC_ACCESS_ERR;
  2032. case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR:
  2033. return IB_WC_LOC_LEN_ERR;
  2034. case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR:
  2035. return IB_WC_LOC_PROT_ERR;
  2036. case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR:
  2037. return IB_WC_LOC_QP_OP_ERR;
  2038. case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR:
  2039. return IB_WC_GENERAL_ERR;
  2040. case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR:
  2041. return IB_WC_WR_FLUSH_ERR;
  2042. case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR:
  2043. return IB_WC_WR_FLUSH_ERR;
  2044. default:
  2045. return IB_WC_GENERAL_ERR;
  2046. }
  2047. }
  2048. static u8 __rc_to_ib_wc_status(u8 qstatus)
  2049. {
  2050. switch (qstatus) {
  2051. case CQ_RES_RC_STATUS_OK:
  2052. return IB_WC_SUCCESS;
  2053. case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR:
  2054. return IB_WC_LOC_ACCESS_ERR;
  2055. case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR:
  2056. return IB_WC_LOC_LEN_ERR;
  2057. case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR:
  2058. return IB_WC_LOC_PROT_ERR;
  2059. case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR:
  2060. return IB_WC_LOC_QP_OP_ERR;
  2061. case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR:
  2062. return IB_WC_GENERAL_ERR;
  2063. case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR:
  2064. return IB_WC_REM_INV_REQ_ERR;
  2065. case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR:
  2066. return IB_WC_WR_FLUSH_ERR;
  2067. case CQ_RES_RC_STATUS_HW_FLUSH_ERR:
  2068. return IB_WC_WR_FLUSH_ERR;
  2069. default:
  2070. return IB_WC_GENERAL_ERR;
  2071. }
  2072. }
  2073. static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe)
  2074. {
  2075. switch (cqe->type) {
  2076. case BNXT_QPLIB_SWQE_TYPE_SEND:
  2077. wc->opcode = IB_WC_SEND;
  2078. break;
  2079. case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM:
  2080. wc->opcode = IB_WC_SEND;
  2081. wc->wc_flags |= IB_WC_WITH_IMM;
  2082. break;
  2083. case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV:
  2084. wc->opcode = IB_WC_SEND;
  2085. wc->wc_flags |= IB_WC_WITH_INVALIDATE;
  2086. break;
  2087. case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE:
  2088. wc->opcode = IB_WC_RDMA_WRITE;
  2089. break;
  2090. case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM:
  2091. wc->opcode = IB_WC_RDMA_WRITE;
  2092. wc->wc_flags |= IB_WC_WITH_IMM;
  2093. break;
  2094. case BNXT_QPLIB_SWQE_TYPE_RDMA_READ:
  2095. wc->opcode = IB_WC_RDMA_READ;
  2096. break;
  2097. case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP:
  2098. wc->opcode = IB_WC_COMP_SWAP;
  2099. break;
  2100. case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD:
  2101. wc->opcode = IB_WC_FETCH_ADD;
  2102. break;
  2103. case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV:
  2104. wc->opcode = IB_WC_LOCAL_INV;
  2105. break;
  2106. case BNXT_QPLIB_SWQE_TYPE_REG_MR:
  2107. wc->opcode = IB_WC_REG_MR;
  2108. break;
  2109. default:
  2110. wc->opcode = IB_WC_SEND;
  2111. break;
  2112. }
  2113. wc->status = __req_to_ib_wc_status(cqe->status);
  2114. }
  2115. static int bnxt_re_check_packet_type(u16 raweth_qp1_flags,
  2116. u16 raweth_qp1_flags2)
  2117. {
  2118. bool is_udp = false, is_ipv6 = false, is_ipv4 = false;
  2119. /* raweth_qp1_flags Bit 9-6 indicates itype */
  2120. if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
  2121. != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
  2122. return -1;
  2123. if (raweth_qp1_flags2 &
  2124. CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC &&
  2125. raweth_qp1_flags2 &
  2126. CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) {
  2127. is_udp = true;
  2128. /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */
  2129. (raweth_qp1_flags2 &
  2130. CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ?
  2131. (is_ipv6 = true) : (is_ipv4 = true);
  2132. return ((is_ipv6) ?
  2133. BNXT_RE_ROCEV2_IPV6_PACKET :
  2134. BNXT_RE_ROCEV2_IPV4_PACKET);
  2135. } else {
  2136. return BNXT_RE_ROCE_V1_PACKET;
  2137. }
  2138. }
  2139. static int bnxt_re_to_ib_nw_type(int nw_type)
  2140. {
  2141. u8 nw_hdr_type = 0xFF;
  2142. switch (nw_type) {
  2143. case BNXT_RE_ROCE_V1_PACKET:
  2144. nw_hdr_type = RDMA_NETWORK_ROCE_V1;
  2145. break;
  2146. case BNXT_RE_ROCEV2_IPV4_PACKET:
  2147. nw_hdr_type = RDMA_NETWORK_IPV4;
  2148. break;
  2149. case BNXT_RE_ROCEV2_IPV6_PACKET:
  2150. nw_hdr_type = RDMA_NETWORK_IPV6;
  2151. break;
  2152. }
  2153. return nw_hdr_type;
  2154. }
  2155. static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev,
  2156. void *rq_hdr_buf)
  2157. {
  2158. u8 *tmp_buf = NULL;
  2159. struct ethhdr *eth_hdr;
  2160. u16 eth_type;
  2161. bool rc = false;
  2162. tmp_buf = (u8 *)rq_hdr_buf;
  2163. /*
  2164. * If dest mac is not same as I/F mac, this could be a
  2165. * loopback address or multicast address, check whether
  2166. * it is a loopback packet
  2167. */
  2168. if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) {
  2169. tmp_buf += 4;
  2170. /* Check the ether type */
  2171. eth_hdr = (struct ethhdr *)tmp_buf;
  2172. eth_type = ntohs(eth_hdr->h_proto);
  2173. switch (eth_type) {
  2174. case ETH_P_IBOE:
  2175. rc = true;
  2176. break;
  2177. case ETH_P_IP:
  2178. case ETH_P_IPV6: {
  2179. u32 len;
  2180. struct udphdr *udp_hdr;
  2181. len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) :
  2182. sizeof(struct ipv6hdr));
  2183. tmp_buf += sizeof(struct ethhdr) + len;
  2184. udp_hdr = (struct udphdr *)tmp_buf;
  2185. if (ntohs(udp_hdr->dest) ==
  2186. ROCE_V2_UDP_DPORT)
  2187. rc = true;
  2188. break;
  2189. }
  2190. default:
  2191. break;
  2192. }
  2193. }
  2194. return rc;
  2195. }
  2196. static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *qp1_qp,
  2197. struct bnxt_qplib_cqe *cqe)
  2198. {
  2199. struct bnxt_re_dev *rdev = qp1_qp->rdev;
  2200. struct bnxt_re_sqp_entries *sqp_entry = NULL;
  2201. struct bnxt_re_qp *qp = rdev->qp1_sqp;
  2202. struct ib_send_wr *swr;
  2203. struct ib_ud_wr udwr;
  2204. struct ib_recv_wr rwr;
  2205. int pkt_type = 0;
  2206. u32 tbl_idx;
  2207. void *rq_hdr_buf;
  2208. dma_addr_t rq_hdr_buf_map;
  2209. dma_addr_t shrq_hdr_buf_map;
  2210. u32 offset = 0;
  2211. u32 skip_bytes = 0;
  2212. struct ib_sge s_sge[2];
  2213. struct ib_sge r_sge[2];
  2214. int rc;
  2215. memset(&udwr, 0, sizeof(udwr));
  2216. memset(&rwr, 0, sizeof(rwr));
  2217. memset(&s_sge, 0, sizeof(s_sge));
  2218. memset(&r_sge, 0, sizeof(r_sge));
  2219. swr = &udwr.wr;
  2220. tbl_idx = cqe->wr_id;
  2221. rq_hdr_buf = qp1_qp->qplib_qp.rq_hdr_buf +
  2222. (tbl_idx * qp1_qp->qplib_qp.rq_hdr_buf_size);
  2223. rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&qp1_qp->qplib_qp,
  2224. tbl_idx);
  2225. /* Shadow QP header buffer */
  2226. shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&qp->qplib_qp,
  2227. tbl_idx);
  2228. sqp_entry = &rdev->sqp_tbl[tbl_idx];
  2229. /* Store this cqe */
  2230. memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe));
  2231. sqp_entry->qp1_qp = qp1_qp;
  2232. /* Find packet type from the cqe */
  2233. pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags,
  2234. cqe->raweth_qp1_flags2);
  2235. if (pkt_type < 0) {
  2236. dev_err(rdev_to_dev(rdev), "Invalid packet\n");
  2237. return -EINVAL;
  2238. }
  2239. /* Adjust the offset for the user buffer and post in the rq */
  2240. if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET)
  2241. offset = 20;
  2242. /*
  2243. * QP1 loopback packet has 4 bytes of internal header before
  2244. * ether header. Skip these four bytes.
  2245. */
  2246. if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf))
  2247. skip_bytes = 4;
  2248. /* First send SGE . Skip the ether header*/
  2249. s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE
  2250. + skip_bytes;
  2251. s_sge[0].lkey = 0xFFFFFFFF;
  2252. s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 :
  2253. BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
  2254. /* Second Send SGE */
  2255. s_sge[1].addr = s_sge[0].addr + s_sge[0].length +
  2256. BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE;
  2257. if (pkt_type != BNXT_RE_ROCE_V1_PACKET)
  2258. s_sge[1].addr += 8;
  2259. s_sge[1].lkey = 0xFFFFFFFF;
  2260. s_sge[1].length = 256;
  2261. /* First recv SGE */
  2262. r_sge[0].addr = shrq_hdr_buf_map;
  2263. r_sge[0].lkey = 0xFFFFFFFF;
  2264. r_sge[0].length = 40;
  2265. r_sge[1].addr = sqp_entry->sge.addr + offset;
  2266. r_sge[1].lkey = sqp_entry->sge.lkey;
  2267. r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset;
  2268. /* Create receive work request */
  2269. rwr.num_sge = 2;
  2270. rwr.sg_list = r_sge;
  2271. rwr.wr_id = tbl_idx;
  2272. rwr.next = NULL;
  2273. rc = bnxt_re_post_recv_shadow_qp(rdev, qp, &rwr);
  2274. if (rc) {
  2275. dev_err(rdev_to_dev(rdev),
  2276. "Failed to post Rx buffers to shadow QP");
  2277. return -ENOMEM;
  2278. }
  2279. swr->num_sge = 2;
  2280. swr->sg_list = s_sge;
  2281. swr->wr_id = tbl_idx;
  2282. swr->opcode = IB_WR_SEND;
  2283. swr->next = NULL;
  2284. udwr.ah = &rdev->sqp_ah->ib_ah;
  2285. udwr.remote_qpn = rdev->qp1_sqp->qplib_qp.id;
  2286. udwr.remote_qkey = rdev->qp1_sqp->qplib_qp.qkey;
  2287. /* post data received in the send queue */
  2288. rc = bnxt_re_post_send_shadow_qp(rdev, qp, swr);
  2289. return 0;
  2290. }
  2291. static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc,
  2292. struct bnxt_qplib_cqe *cqe)
  2293. {
  2294. wc->opcode = IB_WC_RECV;
  2295. wc->status = __rawqp1_to_ib_wc_status(cqe->status);
  2296. wc->wc_flags |= IB_WC_GRH;
  2297. }
  2298. static void bnxt_re_process_res_rc_wc(struct ib_wc *wc,
  2299. struct bnxt_qplib_cqe *cqe)
  2300. {
  2301. wc->opcode = IB_WC_RECV;
  2302. wc->status = __rc_to_ib_wc_status(cqe->status);
  2303. if (cqe->flags & CQ_RES_RC_FLAGS_IMM)
  2304. wc->wc_flags |= IB_WC_WITH_IMM;
  2305. if (cqe->flags & CQ_RES_RC_FLAGS_INV)
  2306. wc->wc_flags |= IB_WC_WITH_INVALIDATE;
  2307. if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) ==
  2308. (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM))
  2309. wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
  2310. }
  2311. static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *qp,
  2312. struct ib_wc *wc,
  2313. struct bnxt_qplib_cqe *cqe)
  2314. {
  2315. u32 tbl_idx;
  2316. struct bnxt_re_dev *rdev = qp->rdev;
  2317. struct bnxt_re_qp *qp1_qp = NULL;
  2318. struct bnxt_qplib_cqe *orig_cqe = NULL;
  2319. struct bnxt_re_sqp_entries *sqp_entry = NULL;
  2320. int nw_type;
  2321. tbl_idx = cqe->wr_id;
  2322. sqp_entry = &rdev->sqp_tbl[tbl_idx];
  2323. qp1_qp = sqp_entry->qp1_qp;
  2324. orig_cqe = &sqp_entry->cqe;
  2325. wc->wr_id = sqp_entry->wrid;
  2326. wc->byte_len = orig_cqe->length;
  2327. wc->qp = &qp1_qp->ib_qp;
  2328. wc->ex.imm_data = orig_cqe->immdata;
  2329. wc->src_qp = orig_cqe->src_qp;
  2330. memcpy(wc->smac, orig_cqe->smac, ETH_ALEN);
  2331. wc->port_num = 1;
  2332. wc->vendor_err = orig_cqe->status;
  2333. wc->opcode = IB_WC_RECV;
  2334. wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status);
  2335. wc->wc_flags |= IB_WC_GRH;
  2336. nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags,
  2337. orig_cqe->raweth_qp1_flags2);
  2338. if (nw_type >= 0) {
  2339. wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type);
  2340. wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
  2341. }
  2342. }
  2343. static void bnxt_re_process_res_ud_wc(struct ib_wc *wc,
  2344. struct bnxt_qplib_cqe *cqe)
  2345. {
  2346. wc->opcode = IB_WC_RECV;
  2347. wc->status = __rc_to_ib_wc_status(cqe->status);
  2348. if (cqe->flags & CQ_RES_RC_FLAGS_IMM)
  2349. wc->wc_flags |= IB_WC_WITH_IMM;
  2350. if (cqe->flags & CQ_RES_RC_FLAGS_INV)
  2351. wc->wc_flags |= IB_WC_WITH_INVALIDATE;
  2352. if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) ==
  2353. (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM))
  2354. wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
  2355. }
  2356. int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc)
  2357. {
  2358. struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
  2359. struct bnxt_re_qp *qp;
  2360. struct bnxt_qplib_cqe *cqe;
  2361. int i, ncqe, budget;
  2362. u32 tbl_idx;
  2363. struct bnxt_re_sqp_entries *sqp_entry = NULL;
  2364. unsigned long flags;
  2365. spin_lock_irqsave(&cq->cq_lock, flags);
  2366. budget = min_t(u32, num_entries, cq->max_cql);
  2367. if (!cq->cql) {
  2368. dev_err(rdev_to_dev(cq->rdev), "POLL CQ : no CQL to use");
  2369. goto exit;
  2370. }
  2371. cqe = &cq->cql[0];
  2372. while (budget) {
  2373. ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget);
  2374. if (!ncqe)
  2375. break;
  2376. for (i = 0; i < ncqe; i++, cqe++) {
  2377. /* Transcribe each qplib_wqe back to ib_wc */
  2378. memset(wc, 0, sizeof(*wc));
  2379. wc->wr_id = cqe->wr_id;
  2380. wc->byte_len = cqe->length;
  2381. qp = container_of
  2382. ((struct bnxt_qplib_qp *)
  2383. (unsigned long)(cqe->qp_handle),
  2384. struct bnxt_re_qp, qplib_qp);
  2385. if (!qp) {
  2386. dev_err(rdev_to_dev(cq->rdev),
  2387. "POLL CQ : bad QP handle");
  2388. continue;
  2389. }
  2390. wc->qp = &qp->ib_qp;
  2391. wc->ex.imm_data = cqe->immdata;
  2392. wc->src_qp = cqe->src_qp;
  2393. memcpy(wc->smac, cqe->smac, ETH_ALEN);
  2394. wc->port_num = 1;
  2395. wc->vendor_err = cqe->status;
  2396. switch (cqe->opcode) {
  2397. case CQ_BASE_CQE_TYPE_REQ:
  2398. if (qp->qplib_qp.id ==
  2399. qp->rdev->qp1_sqp->qplib_qp.id) {
  2400. /* Handle this completion with
  2401. * the stored completion
  2402. */
  2403. memset(wc, 0, sizeof(*wc));
  2404. continue;
  2405. }
  2406. bnxt_re_process_req_wc(wc, cqe);
  2407. break;
  2408. case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1:
  2409. if (!cqe->status) {
  2410. int rc = 0;
  2411. rc = bnxt_re_process_raw_qp_pkt_rx
  2412. (qp, cqe);
  2413. if (!rc) {
  2414. memset(wc, 0, sizeof(*wc));
  2415. continue;
  2416. }
  2417. cqe->status = -1;
  2418. }
  2419. /* Errors need not be looped back.
  2420. * But change the wr_id to the one
  2421. * stored in the table
  2422. */
  2423. tbl_idx = cqe->wr_id;
  2424. sqp_entry = &cq->rdev->sqp_tbl[tbl_idx];
  2425. wc->wr_id = sqp_entry->wrid;
  2426. bnxt_re_process_res_rawqp1_wc(wc, cqe);
  2427. break;
  2428. case CQ_BASE_CQE_TYPE_RES_RC:
  2429. bnxt_re_process_res_rc_wc(wc, cqe);
  2430. break;
  2431. case CQ_BASE_CQE_TYPE_RES_UD:
  2432. if (qp->qplib_qp.id ==
  2433. qp->rdev->qp1_sqp->qplib_qp.id) {
  2434. /* Handle this completion with
  2435. * the stored completion
  2436. */
  2437. if (cqe->status) {
  2438. continue;
  2439. } else {
  2440. bnxt_re_process_res_shadow_qp_wc
  2441. (qp, wc, cqe);
  2442. break;
  2443. }
  2444. }
  2445. bnxt_re_process_res_ud_wc(wc, cqe);
  2446. break;
  2447. default:
  2448. dev_err(rdev_to_dev(cq->rdev),
  2449. "POLL CQ : type 0x%x not handled",
  2450. cqe->opcode);
  2451. continue;
  2452. }
  2453. wc++;
  2454. budget--;
  2455. }
  2456. }
  2457. exit:
  2458. spin_unlock_irqrestore(&cq->cq_lock, flags);
  2459. return num_entries - budget;
  2460. }
  2461. int bnxt_re_req_notify_cq(struct ib_cq *ib_cq,
  2462. enum ib_cq_notify_flags ib_cqn_flags)
  2463. {
  2464. struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
  2465. int type = 0;
  2466. /* Trigger on the very next completion */
  2467. if (ib_cqn_flags & IB_CQ_NEXT_COMP)
  2468. type = DBR_DBR_TYPE_CQ_ARMALL;
  2469. /* Trigger on the next solicited completion */
  2470. else if (ib_cqn_flags & IB_CQ_SOLICITED)
  2471. type = DBR_DBR_TYPE_CQ_ARMSE;
  2472. bnxt_qplib_req_notify_cq(&cq->qplib_cq, type);
  2473. return 0;
  2474. }
  2475. /* Memory Regions */
  2476. struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags)
  2477. {
  2478. struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
  2479. struct bnxt_re_dev *rdev = pd->rdev;
  2480. struct bnxt_re_mr *mr;
  2481. u64 pbl = 0;
  2482. int rc;
  2483. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  2484. if (!mr)
  2485. return ERR_PTR(-ENOMEM);
  2486. mr->rdev = rdev;
  2487. mr->qplib_mr.pd = &pd->qplib_pd;
  2488. mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
  2489. mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
  2490. /* Allocate and register 0 as the address */
  2491. rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
  2492. if (rc)
  2493. goto fail;
  2494. mr->qplib_mr.hwq.level = PBL_LVL_MAX;
  2495. mr->qplib_mr.total_size = -1; /* Infinte length */
  2496. rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl, 0, false);
  2497. if (rc)
  2498. goto fail_mr;
  2499. mr->ib_mr.lkey = mr->qplib_mr.lkey;
  2500. if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ |
  2501. IB_ACCESS_REMOTE_ATOMIC))
  2502. mr->ib_mr.rkey = mr->ib_mr.lkey;
  2503. atomic_inc(&rdev->mr_count);
  2504. return &mr->ib_mr;
  2505. fail_mr:
  2506. bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
  2507. fail:
  2508. kfree(mr);
  2509. return ERR_PTR(rc);
  2510. }
  2511. int bnxt_re_dereg_mr(struct ib_mr *ib_mr)
  2512. {
  2513. struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
  2514. struct bnxt_re_dev *rdev = mr->rdev;
  2515. int rc;
  2516. if (mr->npages && mr->pages) {
  2517. rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res,
  2518. &mr->qplib_frpl);
  2519. kfree(mr->pages);
  2520. mr->npages = 0;
  2521. mr->pages = NULL;
  2522. }
  2523. rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
  2524. if (!IS_ERR_OR_NULL(mr->ib_umem))
  2525. ib_umem_release(mr->ib_umem);
  2526. kfree(mr);
  2527. atomic_dec(&rdev->mr_count);
  2528. return rc;
  2529. }
  2530. static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr)
  2531. {
  2532. struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
  2533. if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs))
  2534. return -ENOMEM;
  2535. mr->pages[mr->npages++] = addr;
  2536. return 0;
  2537. }
  2538. int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents,
  2539. unsigned int *sg_offset)
  2540. {
  2541. struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
  2542. mr->npages = 0;
  2543. return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page);
  2544. }
  2545. struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type,
  2546. u32 max_num_sg)
  2547. {
  2548. struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
  2549. struct bnxt_re_dev *rdev = pd->rdev;
  2550. struct bnxt_re_mr *mr = NULL;
  2551. int rc;
  2552. if (type != IB_MR_TYPE_MEM_REG) {
  2553. dev_dbg(rdev_to_dev(rdev), "MR type 0x%x not supported", type);
  2554. return ERR_PTR(-EINVAL);
  2555. }
  2556. if (max_num_sg > MAX_PBL_LVL_1_PGS)
  2557. return ERR_PTR(-EINVAL);
  2558. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  2559. if (!mr)
  2560. return ERR_PTR(-ENOMEM);
  2561. mr->rdev = rdev;
  2562. mr->qplib_mr.pd = &pd->qplib_pd;
  2563. mr->qplib_mr.flags = BNXT_QPLIB_FR_PMR;
  2564. mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
  2565. rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
  2566. if (rc)
  2567. goto fail;
  2568. mr->ib_mr.lkey = mr->qplib_mr.lkey;
  2569. mr->ib_mr.rkey = mr->ib_mr.lkey;
  2570. mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL);
  2571. if (!mr->pages) {
  2572. rc = -ENOMEM;
  2573. goto fail;
  2574. }
  2575. rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res,
  2576. &mr->qplib_frpl, max_num_sg);
  2577. if (rc) {
  2578. dev_err(rdev_to_dev(rdev),
  2579. "Failed to allocate HW FR page list");
  2580. goto fail_mr;
  2581. }
  2582. atomic_inc(&rdev->mr_count);
  2583. return &mr->ib_mr;
  2584. fail_mr:
  2585. bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
  2586. fail:
  2587. kfree(mr->pages);
  2588. kfree(mr);
  2589. return ERR_PTR(rc);
  2590. }
  2591. /* Fast Memory Regions */
  2592. struct ib_fmr *bnxt_re_alloc_fmr(struct ib_pd *ib_pd, int mr_access_flags,
  2593. struct ib_fmr_attr *fmr_attr)
  2594. {
  2595. struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
  2596. struct bnxt_re_dev *rdev = pd->rdev;
  2597. struct bnxt_re_fmr *fmr;
  2598. int rc;
  2599. if (fmr_attr->max_pages > MAX_PBL_LVL_2_PGS ||
  2600. fmr_attr->max_maps > rdev->dev_attr.max_map_per_fmr) {
  2601. dev_err(rdev_to_dev(rdev), "Allocate FMR exceeded Max limit");
  2602. return ERR_PTR(-ENOMEM);
  2603. }
  2604. fmr = kzalloc(sizeof(*fmr), GFP_KERNEL);
  2605. if (!fmr)
  2606. return ERR_PTR(-ENOMEM);
  2607. fmr->rdev = rdev;
  2608. fmr->qplib_fmr.pd = &pd->qplib_pd;
  2609. fmr->qplib_fmr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
  2610. rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &fmr->qplib_fmr);
  2611. if (rc)
  2612. goto fail;
  2613. fmr->qplib_fmr.flags = __from_ib_access_flags(mr_access_flags);
  2614. fmr->ib_fmr.lkey = fmr->qplib_fmr.lkey;
  2615. fmr->ib_fmr.rkey = fmr->ib_fmr.lkey;
  2616. atomic_inc(&rdev->mr_count);
  2617. return &fmr->ib_fmr;
  2618. fail:
  2619. kfree(fmr);
  2620. return ERR_PTR(rc);
  2621. }
  2622. int bnxt_re_map_phys_fmr(struct ib_fmr *ib_fmr, u64 *page_list, int list_len,
  2623. u64 iova)
  2624. {
  2625. struct bnxt_re_fmr *fmr = container_of(ib_fmr, struct bnxt_re_fmr,
  2626. ib_fmr);
  2627. struct bnxt_re_dev *rdev = fmr->rdev;
  2628. int rc;
  2629. fmr->qplib_fmr.va = iova;
  2630. fmr->qplib_fmr.total_size = list_len * PAGE_SIZE;
  2631. rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &fmr->qplib_fmr, page_list,
  2632. list_len, true);
  2633. if (rc)
  2634. dev_err(rdev_to_dev(rdev), "Failed to map FMR for lkey = 0x%x!",
  2635. fmr->ib_fmr.lkey);
  2636. return rc;
  2637. }
  2638. int bnxt_re_unmap_fmr(struct list_head *fmr_list)
  2639. {
  2640. struct bnxt_re_dev *rdev;
  2641. struct bnxt_re_fmr *fmr;
  2642. struct ib_fmr *ib_fmr;
  2643. int rc = 0;
  2644. /* Validate each FMRs inside the fmr_list */
  2645. list_for_each_entry(ib_fmr, fmr_list, list) {
  2646. fmr = container_of(ib_fmr, struct bnxt_re_fmr, ib_fmr);
  2647. rdev = fmr->rdev;
  2648. if (rdev) {
  2649. rc = bnxt_qplib_dereg_mrw(&rdev->qplib_res,
  2650. &fmr->qplib_fmr, true);
  2651. if (rc)
  2652. break;
  2653. }
  2654. }
  2655. return rc;
  2656. }
  2657. int bnxt_re_dealloc_fmr(struct ib_fmr *ib_fmr)
  2658. {
  2659. struct bnxt_re_fmr *fmr = container_of(ib_fmr, struct bnxt_re_fmr,
  2660. ib_fmr);
  2661. struct bnxt_re_dev *rdev = fmr->rdev;
  2662. int rc;
  2663. rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &fmr->qplib_fmr);
  2664. if (rc)
  2665. dev_err(rdev_to_dev(rdev), "Failed to free FMR");
  2666. kfree(fmr);
  2667. atomic_dec(&rdev->mr_count);
  2668. return rc;
  2669. }
  2670. /* uverbs */
  2671. struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length,
  2672. u64 virt_addr, int mr_access_flags,
  2673. struct ib_udata *udata)
  2674. {
  2675. struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
  2676. struct bnxt_re_dev *rdev = pd->rdev;
  2677. struct bnxt_re_mr *mr;
  2678. struct ib_umem *umem;
  2679. u64 *pbl_tbl, *pbl_tbl_orig;
  2680. int i, umem_pgs, pages, rc;
  2681. struct scatterlist *sg;
  2682. int entry;
  2683. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  2684. if (!mr)
  2685. return ERR_PTR(-ENOMEM);
  2686. mr->rdev = rdev;
  2687. mr->qplib_mr.pd = &pd->qplib_pd;
  2688. mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
  2689. mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR;
  2690. umem = ib_umem_get(ib_pd->uobject->context, start, length,
  2691. mr_access_flags, 0);
  2692. if (IS_ERR(umem)) {
  2693. dev_err(rdev_to_dev(rdev), "Failed to get umem");
  2694. rc = -EFAULT;
  2695. goto free_mr;
  2696. }
  2697. mr->ib_umem = umem;
  2698. rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
  2699. if (rc) {
  2700. dev_err(rdev_to_dev(rdev), "Failed to allocate MR");
  2701. goto release_umem;
  2702. }
  2703. /* The fixed portion of the rkey is the same as the lkey */
  2704. mr->ib_mr.rkey = mr->qplib_mr.rkey;
  2705. mr->qplib_mr.va = virt_addr;
  2706. umem_pgs = ib_umem_page_count(umem);
  2707. if (!umem_pgs) {
  2708. dev_err(rdev_to_dev(rdev), "umem is invalid!");
  2709. rc = -EINVAL;
  2710. goto free_mrw;
  2711. }
  2712. mr->qplib_mr.total_size = length;
  2713. pbl_tbl = kcalloc(umem_pgs, sizeof(u64 *), GFP_KERNEL);
  2714. if (!pbl_tbl) {
  2715. rc = -EINVAL;
  2716. goto free_mrw;
  2717. }
  2718. pbl_tbl_orig = pbl_tbl;
  2719. if (umem->hugetlb) {
  2720. dev_err(rdev_to_dev(rdev), "umem hugetlb not supported!");
  2721. rc = -EFAULT;
  2722. goto fail;
  2723. }
  2724. if (umem->page_shift != PAGE_SHIFT) {
  2725. dev_err(rdev_to_dev(rdev), "umem page shift unsupported!");
  2726. rc = -EFAULT;
  2727. goto fail;
  2728. }
  2729. /* Map umem buf ptrs to the PBL */
  2730. for_each_sg(umem->sg_head.sgl, sg, umem->nmap, entry) {
  2731. pages = sg_dma_len(sg) >> umem->page_shift;
  2732. for (i = 0; i < pages; i++, pbl_tbl++)
  2733. *pbl_tbl = sg_dma_address(sg) + (i << umem->page_shift);
  2734. }
  2735. rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, pbl_tbl_orig,
  2736. umem_pgs, false);
  2737. if (rc) {
  2738. dev_err(rdev_to_dev(rdev), "Failed to register user MR");
  2739. goto fail;
  2740. }
  2741. kfree(pbl_tbl_orig);
  2742. mr->ib_mr.lkey = mr->qplib_mr.lkey;
  2743. mr->ib_mr.rkey = mr->qplib_mr.lkey;
  2744. atomic_inc(&rdev->mr_count);
  2745. return &mr->ib_mr;
  2746. fail:
  2747. kfree(pbl_tbl_orig);
  2748. free_mrw:
  2749. bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
  2750. release_umem:
  2751. ib_umem_release(umem);
  2752. free_mr:
  2753. kfree(mr);
  2754. return ERR_PTR(rc);
  2755. }
  2756. struct ib_ucontext *bnxt_re_alloc_ucontext(struct ib_device *ibdev,
  2757. struct ib_udata *udata)
  2758. {
  2759. struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
  2760. struct bnxt_re_uctx_resp resp;
  2761. struct bnxt_re_ucontext *uctx;
  2762. struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
  2763. int rc;
  2764. dev_dbg(rdev_to_dev(rdev), "ABI version requested %d",
  2765. ibdev->uverbs_abi_ver);
  2766. if (ibdev->uverbs_abi_ver != BNXT_RE_ABI_VERSION) {
  2767. dev_dbg(rdev_to_dev(rdev), " is different from the device %d ",
  2768. BNXT_RE_ABI_VERSION);
  2769. return ERR_PTR(-EPERM);
  2770. }
  2771. uctx = kzalloc(sizeof(*uctx), GFP_KERNEL);
  2772. if (!uctx)
  2773. return ERR_PTR(-ENOMEM);
  2774. uctx->rdev = rdev;
  2775. uctx->shpg = (void *)__get_free_page(GFP_KERNEL);
  2776. if (!uctx->shpg) {
  2777. rc = -ENOMEM;
  2778. goto fail;
  2779. }
  2780. spin_lock_init(&uctx->sh_lock);
  2781. resp.dev_id = rdev->en_dev->pdev->devfn; /*Temp, Use idr_alloc instead*/
  2782. resp.max_qp = rdev->qplib_ctx.qpc_count;
  2783. resp.pg_size = PAGE_SIZE;
  2784. resp.cqe_sz = sizeof(struct cq_base);
  2785. resp.max_cqd = dev_attr->max_cq_wqes;
  2786. resp.rsvd = 0;
  2787. rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
  2788. if (rc) {
  2789. dev_err(rdev_to_dev(rdev), "Failed to copy user context");
  2790. rc = -EFAULT;
  2791. goto cfail;
  2792. }
  2793. return &uctx->ib_uctx;
  2794. cfail:
  2795. free_page((unsigned long)uctx->shpg);
  2796. uctx->shpg = NULL;
  2797. fail:
  2798. kfree(uctx);
  2799. return ERR_PTR(rc);
  2800. }
  2801. int bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx)
  2802. {
  2803. struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
  2804. struct bnxt_re_ucontext,
  2805. ib_uctx);
  2806. if (uctx->shpg)
  2807. free_page((unsigned long)uctx->shpg);
  2808. kfree(uctx);
  2809. return 0;
  2810. }
  2811. /* Helper function to mmap the virtual memory from user app */
  2812. int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma)
  2813. {
  2814. struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
  2815. struct bnxt_re_ucontext,
  2816. ib_uctx);
  2817. struct bnxt_re_dev *rdev = uctx->rdev;
  2818. u64 pfn;
  2819. if (vma->vm_end - vma->vm_start != PAGE_SIZE)
  2820. return -EINVAL;
  2821. if (vma->vm_pgoff) {
  2822. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  2823. if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
  2824. PAGE_SIZE, vma->vm_page_prot)) {
  2825. dev_err(rdev_to_dev(rdev), "Failed to map DPI");
  2826. return -EAGAIN;
  2827. }
  2828. } else {
  2829. pfn = virt_to_phys(uctx->shpg) >> PAGE_SHIFT;
  2830. if (remap_pfn_range(vma, vma->vm_start,
  2831. pfn, PAGE_SIZE, vma->vm_page_prot)) {
  2832. dev_err(rdev_to_dev(rdev),
  2833. "Failed to map shared page");
  2834. return -EAGAIN;
  2835. }
  2836. }
  2837. return 0;
  2838. }