cl0002.h 2.8 KB

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  1. #ifndef __NVIF_CL0002_H__
  2. #define __NVIF_CL0002_H__
  3. struct nv_dma_v0 {
  4. __u8 version;
  5. #define NV_DMA_V0_TARGET_VM 0x00
  6. #define NV_DMA_V0_TARGET_VRAM 0x01
  7. #define NV_DMA_V0_TARGET_PCI 0x02
  8. #define NV_DMA_V0_TARGET_PCI_US 0x03
  9. #define NV_DMA_V0_TARGET_AGP 0x04
  10. __u8 target;
  11. #define NV_DMA_V0_ACCESS_VM 0x00
  12. #define NV_DMA_V0_ACCESS_RD 0x01
  13. #define NV_DMA_V0_ACCESS_WR 0x02
  14. #define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR)
  15. __u8 access;
  16. __u8 pad03[5];
  17. __u64 start;
  18. __u64 limit;
  19. /* ... chipset-specific class data */
  20. };
  21. struct nv50_dma_v0 {
  22. __u8 version;
  23. #define NV50_DMA_V0_PRIV_VM 0x00
  24. #define NV50_DMA_V0_PRIV_US 0x01
  25. #define NV50_DMA_V0_PRIV__S 0x02
  26. __u8 priv;
  27. #define NV50_DMA_V0_PART_VM 0x00
  28. #define NV50_DMA_V0_PART_256 0x01
  29. #define NV50_DMA_V0_PART_1KB 0x02
  30. __u8 part;
  31. #define NV50_DMA_V0_COMP_NONE 0x00
  32. #define NV50_DMA_V0_COMP_1 0x01
  33. #define NV50_DMA_V0_COMP_2 0x02
  34. #define NV50_DMA_V0_COMP_VM 0x03
  35. __u8 comp;
  36. #define NV50_DMA_V0_KIND_PITCH 0x00
  37. #define NV50_DMA_V0_KIND_VM 0x7f
  38. __u8 kind;
  39. __u8 pad05[3];
  40. };
  41. struct gf100_dma_v0 {
  42. __u8 version;
  43. #define GF100_DMA_V0_PRIV_VM 0x00
  44. #define GF100_DMA_V0_PRIV_US 0x01
  45. #define GF100_DMA_V0_PRIV__S 0x02
  46. __u8 priv;
  47. #define GF100_DMA_V0_KIND_PITCH 0x00
  48. #define GF100_DMA_V0_KIND_VM 0xff
  49. __u8 kind;
  50. __u8 pad03[5];
  51. };
  52. struct gf119_dma_v0 {
  53. __u8 version;
  54. #define GF119_DMA_V0_PAGE_LP 0x00
  55. #define GF119_DMA_V0_PAGE_SP 0x01
  56. __u8 page;
  57. #define GF119_DMA_V0_KIND_PITCH 0x00
  58. #define GF119_DMA_V0_KIND_VM 0xff
  59. __u8 kind;
  60. __u8 pad03[5];
  61. };
  62. #endif