mtk_drm_drv.c 16 KB

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  1. /*
  2. * Copyright (c) 2015 MediaTek Inc.
  3. * Author: YT SHEN <yt.shen@mediatek.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. */
  14. #include <drm/drmP.h>
  15. #include <drm/drm_atomic.h>
  16. #include <drm/drm_atomic_helper.h>
  17. #include <drm/drm_crtc_helper.h>
  18. #include <drm/drm_gem.h>
  19. #include <drm/drm_gem_cma_helper.h>
  20. #include <drm/drm_of.h>
  21. #include <linux/component.h>
  22. #include <linux/iommu.h>
  23. #include <linux/of_address.h>
  24. #include <linux/of_platform.h>
  25. #include <linux/pm_runtime.h>
  26. #include "mtk_drm_crtc.h"
  27. #include "mtk_drm_ddp.h"
  28. #include "mtk_drm_ddp_comp.h"
  29. #include "mtk_drm_drv.h"
  30. #include "mtk_drm_fb.h"
  31. #include "mtk_drm_gem.h"
  32. #define DRIVER_NAME "mediatek"
  33. #define DRIVER_DESC "Mediatek SoC DRM"
  34. #define DRIVER_DATE "20150513"
  35. #define DRIVER_MAJOR 1
  36. #define DRIVER_MINOR 0
  37. static void mtk_atomic_schedule(struct mtk_drm_private *private,
  38. struct drm_atomic_state *state)
  39. {
  40. private->commit.state = state;
  41. schedule_work(&private->commit.work);
  42. }
  43. static void mtk_atomic_wait_for_fences(struct drm_atomic_state *state)
  44. {
  45. struct drm_plane *plane;
  46. struct drm_plane_state *plane_state;
  47. int i;
  48. for_each_plane_in_state(state, plane, plane_state, i)
  49. mtk_fb_wait(plane->state->fb);
  50. }
  51. static void mtk_atomic_complete(struct mtk_drm_private *private,
  52. struct drm_atomic_state *state)
  53. {
  54. struct drm_device *drm = private->drm;
  55. mtk_atomic_wait_for_fences(state);
  56. /*
  57. * Mediatek drm supports runtime PM, so plane registers cannot be
  58. * written when their crtc is disabled.
  59. *
  60. * The comment for drm_atomic_helper_commit states:
  61. * For drivers supporting runtime PM the recommended sequence is
  62. *
  63. * drm_atomic_helper_commit_modeset_disables(dev, state);
  64. * drm_atomic_helper_commit_modeset_enables(dev, state);
  65. * drm_atomic_helper_commit_planes(dev, state,
  66. * DRM_PLANE_COMMIT_ACTIVE_ONLY);
  67. *
  68. * See the kerneldoc entries for these three functions for more details.
  69. */
  70. drm_atomic_helper_commit_modeset_disables(drm, state);
  71. drm_atomic_helper_commit_modeset_enables(drm, state);
  72. drm_atomic_helper_commit_planes(drm, state,
  73. DRM_PLANE_COMMIT_ACTIVE_ONLY);
  74. drm_atomic_helper_wait_for_vblanks(drm, state);
  75. drm_atomic_helper_cleanup_planes(drm, state);
  76. drm_atomic_state_put(state);
  77. }
  78. static void mtk_atomic_work(struct work_struct *work)
  79. {
  80. struct mtk_drm_private *private = container_of(work,
  81. struct mtk_drm_private, commit.work);
  82. mtk_atomic_complete(private, private->commit.state);
  83. }
  84. static int mtk_atomic_commit(struct drm_device *drm,
  85. struct drm_atomic_state *state,
  86. bool async)
  87. {
  88. struct mtk_drm_private *private = drm->dev_private;
  89. int ret;
  90. ret = drm_atomic_helper_prepare_planes(drm, state);
  91. if (ret)
  92. return ret;
  93. mutex_lock(&private->commit.lock);
  94. flush_work(&private->commit.work);
  95. drm_atomic_helper_swap_state(state, true);
  96. drm_atomic_state_get(state);
  97. if (async)
  98. mtk_atomic_schedule(private, state);
  99. else
  100. mtk_atomic_complete(private, state);
  101. mutex_unlock(&private->commit.lock);
  102. return 0;
  103. }
  104. static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = {
  105. .fb_create = mtk_drm_mode_fb_create,
  106. .atomic_check = drm_atomic_helper_check,
  107. .atomic_commit = mtk_atomic_commit,
  108. };
  109. static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
  110. DDP_COMPONENT_OVL0,
  111. DDP_COMPONENT_RDMA0,
  112. DDP_COMPONENT_COLOR0,
  113. DDP_COMPONENT_BLS,
  114. DDP_COMPONENT_DSI0,
  115. };
  116. static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
  117. DDP_COMPONENT_RDMA1,
  118. DDP_COMPONENT_DPI0,
  119. };
  120. static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
  121. DDP_COMPONENT_OVL0,
  122. DDP_COMPONENT_COLOR0,
  123. DDP_COMPONENT_AAL,
  124. DDP_COMPONENT_OD,
  125. DDP_COMPONENT_RDMA0,
  126. DDP_COMPONENT_UFOE,
  127. DDP_COMPONENT_DSI0,
  128. DDP_COMPONENT_PWM0,
  129. };
  130. static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = {
  131. DDP_COMPONENT_OVL1,
  132. DDP_COMPONENT_COLOR1,
  133. DDP_COMPONENT_GAMMA,
  134. DDP_COMPONENT_RDMA1,
  135. DDP_COMPONENT_DPI0,
  136. };
  137. static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
  138. .main_path = mt2701_mtk_ddp_main,
  139. .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
  140. .ext_path = mt2701_mtk_ddp_ext,
  141. .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
  142. .shadow_register = true,
  143. };
  144. static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
  145. .main_path = mt8173_mtk_ddp_main,
  146. .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
  147. .ext_path = mt8173_mtk_ddp_ext,
  148. .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
  149. };
  150. static int mtk_drm_kms_init(struct drm_device *drm)
  151. {
  152. struct mtk_drm_private *private = drm->dev_private;
  153. struct platform_device *pdev;
  154. struct device_node *np;
  155. int ret;
  156. if (!iommu_present(&platform_bus_type))
  157. return -EPROBE_DEFER;
  158. pdev = of_find_device_by_node(private->mutex_node);
  159. if (!pdev) {
  160. dev_err(drm->dev, "Waiting for disp-mutex device %s\n",
  161. private->mutex_node->full_name);
  162. of_node_put(private->mutex_node);
  163. return -EPROBE_DEFER;
  164. }
  165. private->mutex_dev = &pdev->dev;
  166. drm_mode_config_init(drm);
  167. drm->mode_config.min_width = 64;
  168. drm->mode_config.min_height = 64;
  169. /*
  170. * set max width and height as default value(4096x4096).
  171. * this value would be used to check framebuffer size limitation
  172. * at drm_mode_addfb().
  173. */
  174. drm->mode_config.max_width = 4096;
  175. drm->mode_config.max_height = 4096;
  176. drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
  177. ret = component_bind_all(drm->dev, drm);
  178. if (ret)
  179. goto err_config_cleanup;
  180. /*
  181. * We currently support two fixed data streams, each optional,
  182. * and each statically assigned to a crtc:
  183. * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
  184. */
  185. ret = mtk_drm_crtc_create(drm, private->data->main_path,
  186. private->data->main_len);
  187. if (ret < 0)
  188. goto err_component_unbind;
  189. /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */
  190. ret = mtk_drm_crtc_create(drm, private->data->ext_path,
  191. private->data->ext_len);
  192. if (ret < 0)
  193. goto err_component_unbind;
  194. /* Use OVL device for all DMA memory allocations */
  195. np = private->comp_node[private->data->main_path[0]] ?:
  196. private->comp_node[private->data->ext_path[0]];
  197. pdev = of_find_device_by_node(np);
  198. if (!pdev) {
  199. ret = -ENODEV;
  200. dev_err(drm->dev, "Need at least one OVL device\n");
  201. goto err_component_unbind;
  202. }
  203. private->dma_dev = &pdev->dev;
  204. /*
  205. * We don't use the drm_irq_install() helpers provided by the DRM
  206. * core, so we need to set this manually in order to allow the
  207. * DRM_IOCTL_WAIT_VBLANK to operate correctly.
  208. */
  209. drm->irq_enabled = true;
  210. ret = drm_vblank_init(drm, MAX_CRTC);
  211. if (ret < 0)
  212. goto err_component_unbind;
  213. drm_kms_helper_poll_init(drm);
  214. drm_mode_config_reset(drm);
  215. return 0;
  216. err_component_unbind:
  217. component_unbind_all(drm->dev, drm);
  218. err_config_cleanup:
  219. drm_mode_config_cleanup(drm);
  220. return ret;
  221. }
  222. static void mtk_drm_kms_deinit(struct drm_device *drm)
  223. {
  224. drm_kms_helper_poll_fini(drm);
  225. drm_vblank_cleanup(drm);
  226. component_unbind_all(drm->dev, drm);
  227. drm_mode_config_cleanup(drm);
  228. }
  229. static const struct file_operations mtk_drm_fops = {
  230. .owner = THIS_MODULE,
  231. .open = drm_open,
  232. .release = drm_release,
  233. .unlocked_ioctl = drm_ioctl,
  234. .mmap = mtk_drm_gem_mmap,
  235. .poll = drm_poll,
  236. .read = drm_read,
  237. .compat_ioctl = drm_compat_ioctl,
  238. };
  239. static struct drm_driver mtk_drm_driver = {
  240. .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
  241. DRIVER_ATOMIC,
  242. .gem_free_object_unlocked = mtk_drm_gem_free_object,
  243. .gem_vm_ops = &drm_gem_cma_vm_ops,
  244. .dumb_create = mtk_drm_gem_dumb_create,
  245. .dumb_map_offset = mtk_drm_gem_dumb_map_offset,
  246. .dumb_destroy = drm_gem_dumb_destroy,
  247. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  248. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  249. .gem_prime_export = drm_gem_prime_export,
  250. .gem_prime_import = drm_gem_prime_import,
  251. .gem_prime_get_sg_table = mtk_gem_prime_get_sg_table,
  252. .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table,
  253. .gem_prime_mmap = mtk_drm_gem_mmap_buf,
  254. .fops = &mtk_drm_fops,
  255. .name = DRIVER_NAME,
  256. .desc = DRIVER_DESC,
  257. .date = DRIVER_DATE,
  258. .major = DRIVER_MAJOR,
  259. .minor = DRIVER_MINOR,
  260. };
  261. static int compare_of(struct device *dev, void *data)
  262. {
  263. return dev->of_node == data;
  264. }
  265. static int mtk_drm_bind(struct device *dev)
  266. {
  267. struct mtk_drm_private *private = dev_get_drvdata(dev);
  268. struct drm_device *drm;
  269. int ret;
  270. drm = drm_dev_alloc(&mtk_drm_driver, dev);
  271. if (IS_ERR(drm))
  272. return PTR_ERR(drm);
  273. drm->dev_private = private;
  274. private->drm = drm;
  275. ret = mtk_drm_kms_init(drm);
  276. if (ret < 0)
  277. goto err_free;
  278. ret = drm_dev_register(drm, 0);
  279. if (ret < 0)
  280. goto err_deinit;
  281. return 0;
  282. err_deinit:
  283. mtk_drm_kms_deinit(drm);
  284. err_free:
  285. drm_dev_unref(drm);
  286. return ret;
  287. }
  288. static void mtk_drm_unbind(struct device *dev)
  289. {
  290. struct mtk_drm_private *private = dev_get_drvdata(dev);
  291. drm_dev_unregister(private->drm);
  292. drm_dev_unref(private->drm);
  293. private->drm = NULL;
  294. }
  295. static const struct component_master_ops mtk_drm_ops = {
  296. .bind = mtk_drm_bind,
  297. .unbind = mtk_drm_unbind,
  298. };
  299. static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
  300. { .compatible = "mediatek,mt2701-disp-ovl", .data = (void *)MTK_DISP_OVL },
  301. { .compatible = "mediatek,mt8173-disp-ovl", .data = (void *)MTK_DISP_OVL },
  302. { .compatible = "mediatek,mt2701-disp-rdma", .data = (void *)MTK_DISP_RDMA },
  303. { .compatible = "mediatek,mt8173-disp-rdma", .data = (void *)MTK_DISP_RDMA },
  304. { .compatible = "mediatek,mt8173-disp-wdma", .data = (void *)MTK_DISP_WDMA },
  305. { .compatible = "mediatek,mt2701-disp-color", .data = (void *)MTK_DISP_COLOR },
  306. { .compatible = "mediatek,mt8173-disp-color", .data = (void *)MTK_DISP_COLOR },
  307. { .compatible = "mediatek,mt8173-disp-aal", .data = (void *)MTK_DISP_AAL},
  308. { .compatible = "mediatek,mt8173-disp-gamma", .data = (void *)MTK_DISP_GAMMA, },
  309. { .compatible = "mediatek,mt8173-disp-ufoe", .data = (void *)MTK_DISP_UFOE },
  310. { .compatible = "mediatek,mt2701-dsi", .data = (void *)MTK_DSI },
  311. { .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI },
  312. { .compatible = "mediatek,mt8173-dpi", .data = (void *)MTK_DPI },
  313. { .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX },
  314. { .compatible = "mediatek,mt8173-disp-mutex", .data = (void *)MTK_DISP_MUTEX },
  315. { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS },
  316. { .compatible = "mediatek,mt8173-disp-pwm", .data = (void *)MTK_DISP_PWM },
  317. { .compatible = "mediatek,mt8173-disp-od", .data = (void *)MTK_DISP_OD },
  318. { }
  319. };
  320. static int mtk_drm_probe(struct platform_device *pdev)
  321. {
  322. struct device *dev = &pdev->dev;
  323. struct mtk_drm_private *private;
  324. struct resource *mem;
  325. struct device_node *node;
  326. struct component_match *match = NULL;
  327. int ret;
  328. int i;
  329. private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
  330. if (!private)
  331. return -ENOMEM;
  332. mutex_init(&private->commit.lock);
  333. INIT_WORK(&private->commit.work, mtk_atomic_work);
  334. private->data = of_device_get_match_data(dev);
  335. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  336. private->config_regs = devm_ioremap_resource(dev, mem);
  337. if (IS_ERR(private->config_regs)) {
  338. ret = PTR_ERR(private->config_regs);
  339. dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n",
  340. ret);
  341. return ret;
  342. }
  343. /* Iterate over sibling DISP function blocks */
  344. for_each_child_of_node(dev->of_node->parent, node) {
  345. const struct of_device_id *of_id;
  346. enum mtk_ddp_comp_type comp_type;
  347. int comp_id;
  348. of_id = of_match_node(mtk_ddp_comp_dt_ids, node);
  349. if (!of_id)
  350. continue;
  351. if (!of_device_is_available(node)) {
  352. dev_dbg(dev, "Skipping disabled component %s\n",
  353. node->full_name);
  354. continue;
  355. }
  356. comp_type = (enum mtk_ddp_comp_type)of_id->data;
  357. if (comp_type == MTK_DISP_MUTEX) {
  358. private->mutex_node = of_node_get(node);
  359. continue;
  360. }
  361. comp_id = mtk_ddp_comp_get_id(node, comp_type);
  362. if (comp_id < 0) {
  363. dev_warn(dev, "Skipping unknown component %s\n",
  364. node->full_name);
  365. continue;
  366. }
  367. private->comp_node[comp_id] = of_node_get(node);
  368. /*
  369. * Currently only the OVL, RDMA, DSI, and DPI blocks have
  370. * separate component platform drivers and initialize their own
  371. * DDP component structure. The others are initialized here.
  372. */
  373. if (comp_type == MTK_DISP_OVL ||
  374. comp_type == MTK_DISP_RDMA ||
  375. comp_type == MTK_DSI ||
  376. comp_type == MTK_DPI) {
  377. dev_info(dev, "Adding component match for %s\n",
  378. node->full_name);
  379. drm_of_component_match_add(dev, &match, compare_of,
  380. node);
  381. } else {
  382. struct mtk_ddp_comp *comp;
  383. comp = devm_kzalloc(dev, sizeof(*comp), GFP_KERNEL);
  384. if (!comp) {
  385. ret = -ENOMEM;
  386. goto err_node;
  387. }
  388. ret = mtk_ddp_comp_init(dev, node, comp, comp_id, NULL);
  389. if (ret)
  390. goto err_node;
  391. private->ddp_comp[comp_id] = comp;
  392. }
  393. }
  394. if (!private->mutex_node) {
  395. dev_err(dev, "Failed to find disp-mutex node\n");
  396. ret = -ENODEV;
  397. goto err_node;
  398. }
  399. pm_runtime_enable(dev);
  400. platform_set_drvdata(pdev, private);
  401. ret = component_master_add_with_match(dev, &mtk_drm_ops, match);
  402. if (ret)
  403. goto err_pm;
  404. return 0;
  405. err_pm:
  406. pm_runtime_disable(dev);
  407. err_node:
  408. of_node_put(private->mutex_node);
  409. for (i = 0; i < DDP_COMPONENT_ID_MAX; i++)
  410. of_node_put(private->comp_node[i]);
  411. return ret;
  412. }
  413. static int mtk_drm_remove(struct platform_device *pdev)
  414. {
  415. struct mtk_drm_private *private = platform_get_drvdata(pdev);
  416. struct drm_device *drm = private->drm;
  417. int i;
  418. drm_dev_unregister(drm);
  419. mtk_drm_kms_deinit(drm);
  420. drm_dev_unref(drm);
  421. component_master_del(&pdev->dev, &mtk_drm_ops);
  422. pm_runtime_disable(&pdev->dev);
  423. of_node_put(private->mutex_node);
  424. for (i = 0; i < DDP_COMPONENT_ID_MAX; i++)
  425. of_node_put(private->comp_node[i]);
  426. return 0;
  427. }
  428. #ifdef CONFIG_PM_SLEEP
  429. static int mtk_drm_sys_suspend(struct device *dev)
  430. {
  431. struct mtk_drm_private *private = dev_get_drvdata(dev);
  432. struct drm_device *drm = private->drm;
  433. drm_kms_helper_poll_disable(drm);
  434. private->suspend_state = drm_atomic_helper_suspend(drm);
  435. if (IS_ERR(private->suspend_state)) {
  436. drm_kms_helper_poll_enable(drm);
  437. return PTR_ERR(private->suspend_state);
  438. }
  439. DRM_DEBUG_DRIVER("mtk_drm_sys_suspend\n");
  440. return 0;
  441. }
  442. static int mtk_drm_sys_resume(struct device *dev)
  443. {
  444. struct mtk_drm_private *private = dev_get_drvdata(dev);
  445. struct drm_device *drm = private->drm;
  446. drm_atomic_helper_resume(drm, private->suspend_state);
  447. drm_kms_helper_poll_enable(drm);
  448. DRM_DEBUG_DRIVER("mtk_drm_sys_resume\n");
  449. return 0;
  450. }
  451. #endif
  452. static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend,
  453. mtk_drm_sys_resume);
  454. static const struct of_device_id mtk_drm_of_ids[] = {
  455. { .compatible = "mediatek,mt2701-mmsys",
  456. .data = &mt2701_mmsys_driver_data},
  457. { .compatible = "mediatek,mt8173-mmsys",
  458. .data = &mt8173_mmsys_driver_data},
  459. { }
  460. };
  461. static struct platform_driver mtk_drm_platform_driver = {
  462. .probe = mtk_drm_probe,
  463. .remove = mtk_drm_remove,
  464. .driver = {
  465. .name = "mediatek-drm",
  466. .of_match_table = mtk_drm_of_ids,
  467. .pm = &mtk_drm_pm_ops,
  468. },
  469. };
  470. static struct platform_driver * const mtk_drm_drivers[] = {
  471. &mtk_ddp_driver,
  472. &mtk_disp_ovl_driver,
  473. &mtk_disp_rdma_driver,
  474. &mtk_dpi_driver,
  475. &mtk_drm_platform_driver,
  476. &mtk_dsi_driver,
  477. &mtk_mipi_tx_driver,
  478. };
  479. static int __init mtk_drm_init(void)
  480. {
  481. int ret;
  482. int i;
  483. for (i = 0; i < ARRAY_SIZE(mtk_drm_drivers); i++) {
  484. ret = platform_driver_register(mtk_drm_drivers[i]);
  485. if (ret < 0) {
  486. pr_err("Failed to register %s driver: %d\n",
  487. mtk_drm_drivers[i]->driver.name, ret);
  488. goto err;
  489. }
  490. }
  491. return 0;
  492. err:
  493. while (--i >= 0)
  494. platform_driver_unregister(mtk_drm_drivers[i]);
  495. return ret;
  496. }
  497. static void __exit mtk_drm_exit(void)
  498. {
  499. int i;
  500. for (i = ARRAY_SIZE(mtk_drm_drivers) - 1; i >= 0; i--)
  501. platform_driver_unregister(mtk_drm_drivers[i]);
  502. }
  503. module_init(mtk_drm_init);
  504. module_exit(mtk_drm_exit);
  505. MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>");
  506. MODULE_DESCRIPTION("Mediatek SoC DRM driver");
  507. MODULE_LICENSE("GPL v2");