i915_gem_request.c 21 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882
  1. /*
  2. * Copyright © 2016 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. */
  24. #include <linux/prime_numbers.h>
  25. #include "../i915_selftest.h"
  26. #include "mock_context.h"
  27. #include "mock_gem_device.h"
  28. static int igt_add_request(void *arg)
  29. {
  30. struct drm_i915_private *i915 = arg;
  31. struct drm_i915_gem_request *request;
  32. int err = -ENOMEM;
  33. /* Basic preliminary test to create a request and let it loose! */
  34. mutex_lock(&i915->drm.struct_mutex);
  35. request = mock_request(i915->engine[RCS],
  36. i915->kernel_context,
  37. HZ / 10);
  38. if (!request)
  39. goto out_unlock;
  40. i915_add_request(request);
  41. err = 0;
  42. out_unlock:
  43. mutex_unlock(&i915->drm.struct_mutex);
  44. return err;
  45. }
  46. static int igt_wait_request(void *arg)
  47. {
  48. const long T = HZ / 4;
  49. struct drm_i915_private *i915 = arg;
  50. struct drm_i915_gem_request *request;
  51. int err = -EINVAL;
  52. /* Submit a request, then wait upon it */
  53. mutex_lock(&i915->drm.struct_mutex);
  54. request = mock_request(i915->engine[RCS], i915->kernel_context, T);
  55. if (!request) {
  56. err = -ENOMEM;
  57. goto out_unlock;
  58. }
  59. if (i915_wait_request(request, I915_WAIT_LOCKED, 0) != -ETIME) {
  60. pr_err("request wait (busy query) succeeded (expected timeout before submit!)\n");
  61. goto out_unlock;
  62. }
  63. if (i915_wait_request(request, I915_WAIT_LOCKED, T) != -ETIME) {
  64. pr_err("request wait succeeded (expected timeout before submit!)\n");
  65. goto out_unlock;
  66. }
  67. if (i915_gem_request_completed(request)) {
  68. pr_err("request completed before submit!!\n");
  69. goto out_unlock;
  70. }
  71. i915_add_request(request);
  72. if (i915_wait_request(request, I915_WAIT_LOCKED, 0) != -ETIME) {
  73. pr_err("request wait (busy query) succeeded (expected timeout after submit!)\n");
  74. goto out_unlock;
  75. }
  76. if (i915_gem_request_completed(request)) {
  77. pr_err("request completed immediately!\n");
  78. goto out_unlock;
  79. }
  80. if (i915_wait_request(request, I915_WAIT_LOCKED, T / 2) != -ETIME) {
  81. pr_err("request wait succeeded (expected timeout!)\n");
  82. goto out_unlock;
  83. }
  84. if (i915_wait_request(request, I915_WAIT_LOCKED, T) == -ETIME) {
  85. pr_err("request wait timed out!\n");
  86. goto out_unlock;
  87. }
  88. if (!i915_gem_request_completed(request)) {
  89. pr_err("request not complete after waiting!\n");
  90. goto out_unlock;
  91. }
  92. if (i915_wait_request(request, I915_WAIT_LOCKED, T) == -ETIME) {
  93. pr_err("request wait timed out when already complete!\n");
  94. goto out_unlock;
  95. }
  96. err = 0;
  97. out_unlock:
  98. mock_device_flush(i915);
  99. mutex_unlock(&i915->drm.struct_mutex);
  100. return err;
  101. }
  102. static int igt_fence_wait(void *arg)
  103. {
  104. const long T = HZ / 4;
  105. struct drm_i915_private *i915 = arg;
  106. struct drm_i915_gem_request *request;
  107. int err = -EINVAL;
  108. /* Submit a request, treat it as a fence and wait upon it */
  109. mutex_lock(&i915->drm.struct_mutex);
  110. request = mock_request(i915->engine[RCS], i915->kernel_context, T);
  111. if (!request) {
  112. err = -ENOMEM;
  113. goto out_locked;
  114. }
  115. mutex_unlock(&i915->drm.struct_mutex); /* safe as we are single user */
  116. if (dma_fence_wait_timeout(&request->fence, false, T) != -ETIME) {
  117. pr_err("fence wait success before submit (expected timeout)!\n");
  118. goto out_device;
  119. }
  120. mutex_lock(&i915->drm.struct_mutex);
  121. i915_add_request(request);
  122. mutex_unlock(&i915->drm.struct_mutex);
  123. if (dma_fence_is_signaled(&request->fence)) {
  124. pr_err("fence signaled immediately!\n");
  125. goto out_device;
  126. }
  127. if (dma_fence_wait_timeout(&request->fence, false, T / 2) != -ETIME) {
  128. pr_err("fence wait success after submit (expected timeout)!\n");
  129. goto out_device;
  130. }
  131. if (dma_fence_wait_timeout(&request->fence, false, T) <= 0) {
  132. pr_err("fence wait timed out (expected success)!\n");
  133. goto out_device;
  134. }
  135. if (!dma_fence_is_signaled(&request->fence)) {
  136. pr_err("fence unsignaled after waiting!\n");
  137. goto out_device;
  138. }
  139. if (dma_fence_wait_timeout(&request->fence, false, T) <= 0) {
  140. pr_err("fence wait timed out when complete (expected success)!\n");
  141. goto out_device;
  142. }
  143. err = 0;
  144. out_device:
  145. mutex_lock(&i915->drm.struct_mutex);
  146. out_locked:
  147. mock_device_flush(i915);
  148. mutex_unlock(&i915->drm.struct_mutex);
  149. return err;
  150. }
  151. static int igt_request_rewind(void *arg)
  152. {
  153. struct drm_i915_private *i915 = arg;
  154. struct drm_i915_gem_request *request, *vip;
  155. struct i915_gem_context *ctx[2];
  156. int err = -EINVAL;
  157. mutex_lock(&i915->drm.struct_mutex);
  158. ctx[0] = mock_context(i915, "A");
  159. request = mock_request(i915->engine[RCS], ctx[0], 2 * HZ);
  160. if (!request) {
  161. err = -ENOMEM;
  162. goto err_context_0;
  163. }
  164. i915_gem_request_get(request);
  165. i915_add_request(request);
  166. ctx[1] = mock_context(i915, "B");
  167. vip = mock_request(i915->engine[RCS], ctx[1], 0);
  168. if (!vip) {
  169. err = -ENOMEM;
  170. goto err_context_1;
  171. }
  172. /* Simulate preemption by manual reordering */
  173. if (!mock_cancel_request(request)) {
  174. pr_err("failed to cancel request (already executed)!\n");
  175. i915_add_request(vip);
  176. goto err_context_1;
  177. }
  178. i915_gem_request_get(vip);
  179. i915_add_request(vip);
  180. request->engine->submit_request(request);
  181. mutex_unlock(&i915->drm.struct_mutex);
  182. if (i915_wait_request(vip, 0, HZ) == -ETIME) {
  183. pr_err("timed out waiting for high priority request, vip.seqno=%d, current seqno=%d\n",
  184. vip->global_seqno, intel_engine_get_seqno(i915->engine[RCS]));
  185. goto err;
  186. }
  187. if (i915_gem_request_completed(request)) {
  188. pr_err("low priority request already completed\n");
  189. goto err;
  190. }
  191. err = 0;
  192. err:
  193. i915_gem_request_put(vip);
  194. mutex_lock(&i915->drm.struct_mutex);
  195. err_context_1:
  196. mock_context_close(ctx[1]);
  197. i915_gem_request_put(request);
  198. err_context_0:
  199. mock_context_close(ctx[0]);
  200. mock_device_flush(i915);
  201. mutex_unlock(&i915->drm.struct_mutex);
  202. return err;
  203. }
  204. int i915_gem_request_mock_selftests(void)
  205. {
  206. static const struct i915_subtest tests[] = {
  207. SUBTEST(igt_add_request),
  208. SUBTEST(igt_wait_request),
  209. SUBTEST(igt_fence_wait),
  210. SUBTEST(igt_request_rewind),
  211. };
  212. struct drm_i915_private *i915;
  213. int err;
  214. i915 = mock_gem_device();
  215. if (!i915)
  216. return -ENOMEM;
  217. err = i915_subtests(tests, i915);
  218. drm_dev_unref(&i915->drm);
  219. return err;
  220. }
  221. struct live_test {
  222. struct drm_i915_private *i915;
  223. const char *func;
  224. const char *name;
  225. unsigned int reset_count;
  226. };
  227. static int begin_live_test(struct live_test *t,
  228. struct drm_i915_private *i915,
  229. const char *func,
  230. const char *name)
  231. {
  232. int err;
  233. t->i915 = i915;
  234. t->func = func;
  235. t->name = name;
  236. err = i915_gem_wait_for_idle(i915, I915_WAIT_LOCKED);
  237. if (err) {
  238. pr_err("%s(%s): failed to idle before, with err=%d!",
  239. func, name, err);
  240. return err;
  241. }
  242. i915->gpu_error.missed_irq_rings = 0;
  243. t->reset_count = i915_reset_count(&i915->gpu_error);
  244. return 0;
  245. }
  246. static int end_live_test(struct live_test *t)
  247. {
  248. struct drm_i915_private *i915 = t->i915;
  249. i915_gem_retire_requests(i915);
  250. if (wait_for(intel_engines_are_idle(i915), 10)) {
  251. pr_err("%s(%s): GPU not idle\n", t->func, t->name);
  252. return -EIO;
  253. }
  254. if (t->reset_count != i915_reset_count(&i915->gpu_error)) {
  255. pr_err("%s(%s): GPU was reset %d times!\n",
  256. t->func, t->name,
  257. i915_reset_count(&i915->gpu_error) - t->reset_count);
  258. return -EIO;
  259. }
  260. if (i915->gpu_error.missed_irq_rings) {
  261. pr_err("%s(%s): Missed interrupts on engines %lx\n",
  262. t->func, t->name, i915->gpu_error.missed_irq_rings);
  263. return -EIO;
  264. }
  265. return 0;
  266. }
  267. static int live_nop_request(void *arg)
  268. {
  269. struct drm_i915_private *i915 = arg;
  270. struct intel_engine_cs *engine;
  271. struct live_test t;
  272. unsigned int id;
  273. int err;
  274. /* Submit various sized batches of empty requests, to each engine
  275. * (individually), and wait for the batch to complete. We can check
  276. * the overhead of submitting requests to the hardware.
  277. */
  278. mutex_lock(&i915->drm.struct_mutex);
  279. for_each_engine(engine, i915, id) {
  280. IGT_TIMEOUT(end_time);
  281. struct drm_i915_gem_request *request;
  282. unsigned long n, prime;
  283. ktime_t times[2] = {};
  284. err = begin_live_test(&t, i915, __func__, engine->name);
  285. if (err)
  286. goto out_unlock;
  287. for_each_prime_number_from(prime, 1, 8192) {
  288. times[1] = ktime_get_raw();
  289. for (n = 0; n < prime; n++) {
  290. request = i915_gem_request_alloc(engine,
  291. i915->kernel_context);
  292. if (IS_ERR(request)) {
  293. err = PTR_ERR(request);
  294. goto out_unlock;
  295. }
  296. /* This space is left intentionally blank.
  297. *
  298. * We do not actually want to perform any
  299. * action with this request, we just want
  300. * to measure the latency in allocation
  301. * and submission of our breadcrumbs -
  302. * ensuring that the bare request is sufficient
  303. * for the system to work (i.e. proper HEAD
  304. * tracking of the rings, interrupt handling,
  305. * etc). It also gives us the lowest bounds
  306. * for latency.
  307. */
  308. i915_add_request(request);
  309. }
  310. i915_wait_request(request,
  311. I915_WAIT_LOCKED,
  312. MAX_SCHEDULE_TIMEOUT);
  313. times[1] = ktime_sub(ktime_get_raw(), times[1]);
  314. if (prime == 1)
  315. times[0] = times[1];
  316. if (__igt_timeout(end_time, NULL))
  317. break;
  318. }
  319. err = end_live_test(&t);
  320. if (err)
  321. goto out_unlock;
  322. pr_info("Request latencies on %s: 1 = %lluns, %lu = %lluns\n",
  323. engine->name,
  324. ktime_to_ns(times[0]),
  325. prime, div64_u64(ktime_to_ns(times[1]), prime));
  326. }
  327. out_unlock:
  328. mutex_unlock(&i915->drm.struct_mutex);
  329. return err;
  330. }
  331. static struct i915_vma *empty_batch(struct drm_i915_private *i915)
  332. {
  333. struct drm_i915_gem_object *obj;
  334. struct i915_vma *vma;
  335. u32 *cmd;
  336. int err;
  337. obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
  338. if (IS_ERR(obj))
  339. return ERR_CAST(obj);
  340. cmd = i915_gem_object_pin_map(obj, I915_MAP_WB);
  341. if (IS_ERR(cmd)) {
  342. err = PTR_ERR(cmd);
  343. goto err;
  344. }
  345. *cmd = MI_BATCH_BUFFER_END;
  346. i915_gem_object_unpin_map(obj);
  347. err = i915_gem_object_set_to_gtt_domain(obj, false);
  348. if (err)
  349. goto err;
  350. vma = i915_vma_instance(obj, &i915->ggtt.base, NULL);
  351. if (IS_ERR(vma)) {
  352. err = PTR_ERR(vma);
  353. goto err;
  354. }
  355. err = i915_vma_pin(vma, 0, 0, PIN_USER | PIN_GLOBAL);
  356. if (err)
  357. goto err;
  358. return vma;
  359. err:
  360. i915_gem_object_put(obj);
  361. return ERR_PTR(err);
  362. }
  363. static struct drm_i915_gem_request *
  364. empty_request(struct intel_engine_cs *engine,
  365. struct i915_vma *batch)
  366. {
  367. struct drm_i915_gem_request *request;
  368. int err;
  369. request = i915_gem_request_alloc(engine,
  370. engine->i915->kernel_context);
  371. if (IS_ERR(request))
  372. return request;
  373. err = engine->emit_flush(request, EMIT_INVALIDATE);
  374. if (err)
  375. goto out_request;
  376. err = i915_switch_context(request);
  377. if (err)
  378. goto out_request;
  379. err = engine->emit_bb_start(request,
  380. batch->node.start,
  381. batch->node.size,
  382. I915_DISPATCH_SECURE);
  383. if (err)
  384. goto out_request;
  385. out_request:
  386. __i915_add_request(request, err == 0);
  387. return err ? ERR_PTR(err) : request;
  388. }
  389. static int live_empty_request(void *arg)
  390. {
  391. struct drm_i915_private *i915 = arg;
  392. struct intel_engine_cs *engine;
  393. struct live_test t;
  394. struct i915_vma *batch;
  395. unsigned int id;
  396. int err = 0;
  397. /* Submit various sized batches of empty requests, to each engine
  398. * (individually), and wait for the batch to complete. We can check
  399. * the overhead of submitting requests to the hardware.
  400. */
  401. mutex_lock(&i915->drm.struct_mutex);
  402. batch = empty_batch(i915);
  403. if (IS_ERR(batch)) {
  404. err = PTR_ERR(batch);
  405. goto out_unlock;
  406. }
  407. for_each_engine(engine, i915, id) {
  408. IGT_TIMEOUT(end_time);
  409. struct drm_i915_gem_request *request;
  410. unsigned long n, prime;
  411. ktime_t times[2] = {};
  412. err = begin_live_test(&t, i915, __func__, engine->name);
  413. if (err)
  414. goto out_batch;
  415. /* Warmup / preload */
  416. request = empty_request(engine, batch);
  417. if (IS_ERR(request)) {
  418. err = PTR_ERR(request);
  419. goto out_batch;
  420. }
  421. i915_wait_request(request,
  422. I915_WAIT_LOCKED,
  423. MAX_SCHEDULE_TIMEOUT);
  424. for_each_prime_number_from(prime, 1, 8192) {
  425. times[1] = ktime_get_raw();
  426. for (n = 0; n < prime; n++) {
  427. request = empty_request(engine, batch);
  428. if (IS_ERR(request)) {
  429. err = PTR_ERR(request);
  430. goto out_batch;
  431. }
  432. }
  433. i915_wait_request(request,
  434. I915_WAIT_LOCKED,
  435. MAX_SCHEDULE_TIMEOUT);
  436. times[1] = ktime_sub(ktime_get_raw(), times[1]);
  437. if (prime == 1)
  438. times[0] = times[1];
  439. if (__igt_timeout(end_time, NULL))
  440. break;
  441. }
  442. err = end_live_test(&t);
  443. if (err)
  444. goto out_batch;
  445. pr_info("Batch latencies on %s: 1 = %lluns, %lu = %lluns\n",
  446. engine->name,
  447. ktime_to_ns(times[0]),
  448. prime, div64_u64(ktime_to_ns(times[1]), prime));
  449. }
  450. out_batch:
  451. i915_vma_unpin(batch);
  452. i915_vma_put(batch);
  453. out_unlock:
  454. mutex_unlock(&i915->drm.struct_mutex);
  455. return err;
  456. }
  457. static struct i915_vma *recursive_batch(struct drm_i915_private *i915)
  458. {
  459. struct i915_gem_context *ctx = i915->kernel_context;
  460. struct i915_address_space *vm = ctx->ppgtt ? &ctx->ppgtt->base : &i915->ggtt.base;
  461. struct drm_i915_gem_object *obj;
  462. const int gen = INTEL_GEN(i915);
  463. struct i915_vma *vma;
  464. u32 *cmd;
  465. int err;
  466. obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
  467. if (IS_ERR(obj))
  468. return ERR_CAST(obj);
  469. vma = i915_vma_instance(obj, vm, NULL);
  470. if (IS_ERR(vma)) {
  471. err = PTR_ERR(vma);
  472. goto err;
  473. }
  474. err = i915_vma_pin(vma, 0, 0, PIN_USER);
  475. if (err)
  476. goto err;
  477. err = i915_gem_object_set_to_gtt_domain(obj, true);
  478. if (err)
  479. goto err;
  480. cmd = i915_gem_object_pin_map(obj, I915_MAP_WC);
  481. if (IS_ERR(cmd)) {
  482. err = PTR_ERR(cmd);
  483. goto err;
  484. }
  485. if (gen >= 8) {
  486. *cmd++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
  487. *cmd++ = lower_32_bits(vma->node.start);
  488. *cmd++ = upper_32_bits(vma->node.start);
  489. } else if (gen >= 6) {
  490. *cmd++ = MI_BATCH_BUFFER_START | 1 << 8;
  491. *cmd++ = lower_32_bits(vma->node.start);
  492. } else if (gen >= 4) {
  493. *cmd++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
  494. *cmd++ = lower_32_bits(vma->node.start);
  495. } else {
  496. *cmd++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | 1;
  497. *cmd++ = lower_32_bits(vma->node.start);
  498. }
  499. *cmd++ = MI_BATCH_BUFFER_END; /* terminate early in case of error */
  500. wmb();
  501. i915_gem_object_unpin_map(obj);
  502. return vma;
  503. err:
  504. i915_gem_object_put(obj);
  505. return ERR_PTR(err);
  506. }
  507. static int recursive_batch_resolve(struct i915_vma *batch)
  508. {
  509. u32 *cmd;
  510. cmd = i915_gem_object_pin_map(batch->obj, I915_MAP_WC);
  511. if (IS_ERR(cmd))
  512. return PTR_ERR(cmd);
  513. *cmd = MI_BATCH_BUFFER_END;
  514. wmb();
  515. i915_gem_object_unpin_map(batch->obj);
  516. return 0;
  517. }
  518. static int live_all_engines(void *arg)
  519. {
  520. struct drm_i915_private *i915 = arg;
  521. struct intel_engine_cs *engine;
  522. struct drm_i915_gem_request *request[I915_NUM_ENGINES];
  523. struct i915_vma *batch;
  524. struct live_test t;
  525. unsigned int id;
  526. int err;
  527. /* Check we can submit requests to all engines simultaneously. We
  528. * send a recursive batch to each engine - checking that we don't
  529. * block doing so, and that they don't complete too soon.
  530. */
  531. mutex_lock(&i915->drm.struct_mutex);
  532. err = begin_live_test(&t, i915, __func__, "");
  533. if (err)
  534. goto out_unlock;
  535. batch = recursive_batch(i915);
  536. if (IS_ERR(batch)) {
  537. err = PTR_ERR(batch);
  538. pr_err("%s: Unable to create batch, err=%d\n", __func__, err);
  539. goto out_unlock;
  540. }
  541. for_each_engine(engine, i915, id) {
  542. request[id] = i915_gem_request_alloc(engine,
  543. i915->kernel_context);
  544. if (IS_ERR(request[id])) {
  545. err = PTR_ERR(request[id]);
  546. pr_err("%s: Request allocation failed with err=%d\n",
  547. __func__, err);
  548. goto out_request;
  549. }
  550. err = engine->emit_flush(request[id], EMIT_INVALIDATE);
  551. GEM_BUG_ON(err);
  552. err = i915_switch_context(request[id]);
  553. GEM_BUG_ON(err);
  554. err = engine->emit_bb_start(request[id],
  555. batch->node.start,
  556. batch->node.size,
  557. 0);
  558. GEM_BUG_ON(err);
  559. request[id]->batch = batch;
  560. if (!i915_gem_object_has_active_reference(batch->obj)) {
  561. i915_gem_object_get(batch->obj);
  562. i915_gem_object_set_active_reference(batch->obj);
  563. }
  564. i915_vma_move_to_active(batch, request[id], 0);
  565. i915_gem_request_get(request[id]);
  566. i915_add_request(request[id]);
  567. }
  568. for_each_engine(engine, i915, id) {
  569. if (i915_gem_request_completed(request[id])) {
  570. pr_err("%s(%s): request completed too early!\n",
  571. __func__, engine->name);
  572. err = -EINVAL;
  573. goto out_request;
  574. }
  575. }
  576. err = recursive_batch_resolve(batch);
  577. if (err) {
  578. pr_err("%s: failed to resolve batch, err=%d\n", __func__, err);
  579. goto out_request;
  580. }
  581. for_each_engine(engine, i915, id) {
  582. long timeout;
  583. timeout = i915_wait_request(request[id],
  584. I915_WAIT_LOCKED,
  585. MAX_SCHEDULE_TIMEOUT);
  586. if (timeout < 0) {
  587. err = timeout;
  588. pr_err("%s: error waiting for request on %s, err=%d\n",
  589. __func__, engine->name, err);
  590. goto out_request;
  591. }
  592. GEM_BUG_ON(!i915_gem_request_completed(request[id]));
  593. i915_gem_request_put(request[id]);
  594. request[id] = NULL;
  595. }
  596. err = end_live_test(&t);
  597. out_request:
  598. for_each_engine(engine, i915, id)
  599. if (request[id])
  600. i915_gem_request_put(request[id]);
  601. i915_vma_unpin(batch);
  602. i915_vma_put(batch);
  603. out_unlock:
  604. mutex_unlock(&i915->drm.struct_mutex);
  605. return err;
  606. }
  607. static int live_sequential_engines(void *arg)
  608. {
  609. struct drm_i915_private *i915 = arg;
  610. struct drm_i915_gem_request *request[I915_NUM_ENGINES] = {};
  611. struct drm_i915_gem_request *prev = NULL;
  612. struct intel_engine_cs *engine;
  613. struct live_test t;
  614. unsigned int id;
  615. int err;
  616. /* Check we can submit requests to all engines sequentially, such
  617. * that each successive request waits for the earlier ones. This
  618. * tests that we don't execute requests out of order, even though
  619. * they are running on independent engines.
  620. */
  621. mutex_lock(&i915->drm.struct_mutex);
  622. err = begin_live_test(&t, i915, __func__, "");
  623. if (err)
  624. goto out_unlock;
  625. for_each_engine(engine, i915, id) {
  626. struct i915_vma *batch;
  627. batch = recursive_batch(i915);
  628. if (IS_ERR(batch)) {
  629. err = PTR_ERR(batch);
  630. pr_err("%s: Unable to create batch for %s, err=%d\n",
  631. __func__, engine->name, err);
  632. goto out_unlock;
  633. }
  634. request[id] = i915_gem_request_alloc(engine,
  635. i915->kernel_context);
  636. if (IS_ERR(request[id])) {
  637. err = PTR_ERR(request[id]);
  638. pr_err("%s: Request allocation failed for %s with err=%d\n",
  639. __func__, engine->name, err);
  640. goto out_request;
  641. }
  642. if (prev) {
  643. err = i915_gem_request_await_dma_fence(request[id],
  644. &prev->fence);
  645. if (err) {
  646. i915_add_request(request[id]);
  647. pr_err("%s: Request await failed for %s with err=%d\n",
  648. __func__, engine->name, err);
  649. goto out_request;
  650. }
  651. }
  652. err = engine->emit_flush(request[id], EMIT_INVALIDATE);
  653. GEM_BUG_ON(err);
  654. err = i915_switch_context(request[id]);
  655. GEM_BUG_ON(err);
  656. err = engine->emit_bb_start(request[id],
  657. batch->node.start,
  658. batch->node.size,
  659. 0);
  660. GEM_BUG_ON(err);
  661. request[id]->batch = batch;
  662. i915_vma_move_to_active(batch, request[id], 0);
  663. i915_gem_object_set_active_reference(batch->obj);
  664. i915_vma_get(batch);
  665. i915_gem_request_get(request[id]);
  666. i915_add_request(request[id]);
  667. prev = request[id];
  668. }
  669. for_each_engine(engine, i915, id) {
  670. long timeout;
  671. if (i915_gem_request_completed(request[id])) {
  672. pr_err("%s(%s): request completed too early!\n",
  673. __func__, engine->name);
  674. err = -EINVAL;
  675. goto out_request;
  676. }
  677. err = recursive_batch_resolve(request[id]->batch);
  678. if (err) {
  679. pr_err("%s: failed to resolve batch, err=%d\n",
  680. __func__, err);
  681. goto out_request;
  682. }
  683. timeout = i915_wait_request(request[id],
  684. I915_WAIT_LOCKED,
  685. MAX_SCHEDULE_TIMEOUT);
  686. if (timeout < 0) {
  687. err = timeout;
  688. pr_err("%s: error waiting for request on %s, err=%d\n",
  689. __func__, engine->name, err);
  690. goto out_request;
  691. }
  692. GEM_BUG_ON(!i915_gem_request_completed(request[id]));
  693. }
  694. err = end_live_test(&t);
  695. out_request:
  696. for_each_engine(engine, i915, id) {
  697. u32 *cmd;
  698. if (!request[id])
  699. break;
  700. cmd = i915_gem_object_pin_map(request[id]->batch->obj,
  701. I915_MAP_WC);
  702. if (!IS_ERR(cmd)) {
  703. *cmd = MI_BATCH_BUFFER_END;
  704. wmb();
  705. i915_gem_object_unpin_map(request[id]->batch->obj);
  706. }
  707. i915_vma_put(request[id]->batch);
  708. i915_gem_request_put(request[id]);
  709. }
  710. out_unlock:
  711. mutex_unlock(&i915->drm.struct_mutex);
  712. return err;
  713. }
  714. int i915_gem_request_live_selftests(struct drm_i915_private *i915)
  715. {
  716. static const struct i915_subtest tests[] = {
  717. SUBTEST(live_nop_request),
  718. SUBTEST(live_all_engines),
  719. SUBTEST(live_sequential_engines),
  720. SUBTEST(live_empty_request),
  721. };
  722. return i915_subtests(tests, i915);
  723. }