ccp-dmaengine.c 19 KB

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  1. /*
  2. * AMD Cryptographic Coprocessor (CCP) driver
  3. *
  4. * Copyright (C) 2016 Advanced Micro Devices, Inc.
  5. *
  6. * Author: Gary R Hook <gary.hook@amd.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/dmaengine.h>
  15. #include <linux/spinlock.h>
  16. #include <linux/mutex.h>
  17. #include <linux/ccp.h>
  18. #include "ccp-dev.h"
  19. #include "../../dma/dmaengine.h"
  20. #define CCP_DMA_WIDTH(_mask) \
  21. ({ \
  22. u64 mask = _mask + 1; \
  23. (mask == 0) ? 64 : fls64(mask); \
  24. })
  25. /* The CCP as a DMA provider can be configured for public or private
  26. * channels. Default is specified in the vdata for the device (PCI ID).
  27. * This module parameter will override for all channels on all devices:
  28. * dma_chan_attr = 0x2 to force all channels public
  29. * = 0x1 to force all channels private
  30. * = 0x0 to defer to the vdata setting
  31. * = any other value: warning, revert to 0x0
  32. */
  33. static unsigned int dma_chan_attr = CCP_DMA_DFLT;
  34. module_param(dma_chan_attr, uint, 0444);
  35. MODULE_PARM_DESC(dma_chan_attr, "Set DMA channel visibility: 0 (default) = device defaults, 1 = make private, 2 = make public");
  36. unsigned int ccp_get_dma_chan_attr(struct ccp_device *ccp)
  37. {
  38. switch (dma_chan_attr) {
  39. case CCP_DMA_DFLT:
  40. return ccp->vdata->dma_chan_attr;
  41. case CCP_DMA_PRIV:
  42. return DMA_PRIVATE;
  43. case CCP_DMA_PUB:
  44. return 0;
  45. default:
  46. dev_info_once(ccp->dev, "Invalid value for dma_chan_attr: %d\n",
  47. dma_chan_attr);
  48. return ccp->vdata->dma_chan_attr;
  49. }
  50. }
  51. static void ccp_free_cmd_resources(struct ccp_device *ccp,
  52. struct list_head *list)
  53. {
  54. struct ccp_dma_cmd *cmd, *ctmp;
  55. list_for_each_entry_safe(cmd, ctmp, list, entry) {
  56. list_del(&cmd->entry);
  57. kmem_cache_free(ccp->dma_cmd_cache, cmd);
  58. }
  59. }
  60. static void ccp_free_desc_resources(struct ccp_device *ccp,
  61. struct list_head *list)
  62. {
  63. struct ccp_dma_desc *desc, *dtmp;
  64. list_for_each_entry_safe(desc, dtmp, list, entry) {
  65. ccp_free_cmd_resources(ccp, &desc->active);
  66. ccp_free_cmd_resources(ccp, &desc->pending);
  67. list_del(&desc->entry);
  68. kmem_cache_free(ccp->dma_desc_cache, desc);
  69. }
  70. }
  71. static void ccp_free_chan_resources(struct dma_chan *dma_chan)
  72. {
  73. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  74. dma_chan);
  75. unsigned long flags;
  76. dev_dbg(chan->ccp->dev, "%s - chan=%p\n", __func__, chan);
  77. spin_lock_irqsave(&chan->lock, flags);
  78. ccp_free_desc_resources(chan->ccp, &chan->complete);
  79. ccp_free_desc_resources(chan->ccp, &chan->active);
  80. ccp_free_desc_resources(chan->ccp, &chan->pending);
  81. ccp_free_desc_resources(chan->ccp, &chan->created);
  82. spin_unlock_irqrestore(&chan->lock, flags);
  83. }
  84. static void ccp_cleanup_desc_resources(struct ccp_device *ccp,
  85. struct list_head *list)
  86. {
  87. struct ccp_dma_desc *desc, *dtmp;
  88. list_for_each_entry_safe_reverse(desc, dtmp, list, entry) {
  89. if (!async_tx_test_ack(&desc->tx_desc))
  90. continue;
  91. dev_dbg(ccp->dev, "%s - desc=%p\n", __func__, desc);
  92. ccp_free_cmd_resources(ccp, &desc->active);
  93. ccp_free_cmd_resources(ccp, &desc->pending);
  94. list_del(&desc->entry);
  95. kmem_cache_free(ccp->dma_desc_cache, desc);
  96. }
  97. }
  98. static void ccp_do_cleanup(unsigned long data)
  99. {
  100. struct ccp_dma_chan *chan = (struct ccp_dma_chan *)data;
  101. unsigned long flags;
  102. dev_dbg(chan->ccp->dev, "%s - chan=%s\n", __func__,
  103. dma_chan_name(&chan->dma_chan));
  104. spin_lock_irqsave(&chan->lock, flags);
  105. ccp_cleanup_desc_resources(chan->ccp, &chan->complete);
  106. spin_unlock_irqrestore(&chan->lock, flags);
  107. }
  108. static int ccp_issue_next_cmd(struct ccp_dma_desc *desc)
  109. {
  110. struct ccp_dma_cmd *cmd;
  111. int ret;
  112. cmd = list_first_entry(&desc->pending, struct ccp_dma_cmd, entry);
  113. list_move(&cmd->entry, &desc->active);
  114. dev_dbg(desc->ccp->dev, "%s - tx %d, cmd=%p\n", __func__,
  115. desc->tx_desc.cookie, cmd);
  116. ret = ccp_enqueue_cmd(&cmd->ccp_cmd);
  117. if (!ret || (ret == -EINPROGRESS) || (ret == -EBUSY))
  118. return 0;
  119. dev_dbg(desc->ccp->dev, "%s - error: ret=%d, tx %d, cmd=%p\n", __func__,
  120. ret, desc->tx_desc.cookie, cmd);
  121. return ret;
  122. }
  123. static void ccp_free_active_cmd(struct ccp_dma_desc *desc)
  124. {
  125. struct ccp_dma_cmd *cmd;
  126. cmd = list_first_entry_or_null(&desc->active, struct ccp_dma_cmd,
  127. entry);
  128. if (!cmd)
  129. return;
  130. dev_dbg(desc->ccp->dev, "%s - freeing tx %d cmd=%p\n",
  131. __func__, desc->tx_desc.cookie, cmd);
  132. list_del(&cmd->entry);
  133. kmem_cache_free(desc->ccp->dma_cmd_cache, cmd);
  134. }
  135. static struct ccp_dma_desc *__ccp_next_dma_desc(struct ccp_dma_chan *chan,
  136. struct ccp_dma_desc *desc)
  137. {
  138. /* Move current DMA descriptor to the complete list */
  139. if (desc)
  140. list_move(&desc->entry, &chan->complete);
  141. /* Get the next DMA descriptor on the active list */
  142. desc = list_first_entry_or_null(&chan->active, struct ccp_dma_desc,
  143. entry);
  144. return desc;
  145. }
  146. static struct ccp_dma_desc *ccp_handle_active_desc(struct ccp_dma_chan *chan,
  147. struct ccp_dma_desc *desc)
  148. {
  149. struct dma_async_tx_descriptor *tx_desc;
  150. unsigned long flags;
  151. /* Loop over descriptors until one is found with commands */
  152. do {
  153. if (desc) {
  154. /* Remove the DMA command from the list and free it */
  155. ccp_free_active_cmd(desc);
  156. if (!list_empty(&desc->pending)) {
  157. /* No errors, keep going */
  158. if (desc->status != DMA_ERROR)
  159. return desc;
  160. /* Error, free remaining commands and move on */
  161. ccp_free_cmd_resources(desc->ccp,
  162. &desc->pending);
  163. }
  164. tx_desc = &desc->tx_desc;
  165. } else {
  166. tx_desc = NULL;
  167. }
  168. spin_lock_irqsave(&chan->lock, flags);
  169. if (desc) {
  170. if (desc->status != DMA_ERROR)
  171. desc->status = DMA_COMPLETE;
  172. dev_dbg(desc->ccp->dev,
  173. "%s - tx %d complete, status=%u\n", __func__,
  174. desc->tx_desc.cookie, desc->status);
  175. dma_cookie_complete(tx_desc);
  176. }
  177. desc = __ccp_next_dma_desc(chan, desc);
  178. spin_unlock_irqrestore(&chan->lock, flags);
  179. if (tx_desc) {
  180. if (tx_desc->callback &&
  181. (tx_desc->flags & DMA_PREP_INTERRUPT))
  182. tx_desc->callback(tx_desc->callback_param);
  183. dma_run_dependencies(tx_desc);
  184. }
  185. } while (desc);
  186. return NULL;
  187. }
  188. static struct ccp_dma_desc *__ccp_pending_to_active(struct ccp_dma_chan *chan)
  189. {
  190. struct ccp_dma_desc *desc;
  191. if (list_empty(&chan->pending))
  192. return NULL;
  193. desc = list_empty(&chan->active)
  194. ? list_first_entry(&chan->pending, struct ccp_dma_desc, entry)
  195. : NULL;
  196. list_splice_tail_init(&chan->pending, &chan->active);
  197. return desc;
  198. }
  199. static void ccp_cmd_callback(void *data, int err)
  200. {
  201. struct ccp_dma_desc *desc = data;
  202. struct ccp_dma_chan *chan;
  203. int ret;
  204. if (err == -EINPROGRESS)
  205. return;
  206. chan = container_of(desc->tx_desc.chan, struct ccp_dma_chan,
  207. dma_chan);
  208. dev_dbg(chan->ccp->dev, "%s - tx %d callback, err=%d\n",
  209. __func__, desc->tx_desc.cookie, err);
  210. if (err)
  211. desc->status = DMA_ERROR;
  212. while (true) {
  213. /* Check for DMA descriptor completion */
  214. desc = ccp_handle_active_desc(chan, desc);
  215. /* Don't submit cmd if no descriptor or DMA is paused */
  216. if (!desc || (chan->status == DMA_PAUSED))
  217. break;
  218. ret = ccp_issue_next_cmd(desc);
  219. if (!ret)
  220. break;
  221. desc->status = DMA_ERROR;
  222. }
  223. tasklet_schedule(&chan->cleanup_tasklet);
  224. }
  225. static dma_cookie_t ccp_tx_submit(struct dma_async_tx_descriptor *tx_desc)
  226. {
  227. struct ccp_dma_desc *desc = container_of(tx_desc, struct ccp_dma_desc,
  228. tx_desc);
  229. struct ccp_dma_chan *chan;
  230. dma_cookie_t cookie;
  231. unsigned long flags;
  232. chan = container_of(tx_desc->chan, struct ccp_dma_chan, dma_chan);
  233. spin_lock_irqsave(&chan->lock, flags);
  234. cookie = dma_cookie_assign(tx_desc);
  235. list_del(&desc->entry);
  236. list_add_tail(&desc->entry, &chan->pending);
  237. spin_unlock_irqrestore(&chan->lock, flags);
  238. dev_dbg(chan->ccp->dev, "%s - added tx descriptor %d to pending list\n",
  239. __func__, cookie);
  240. return cookie;
  241. }
  242. static struct ccp_dma_cmd *ccp_alloc_dma_cmd(struct ccp_dma_chan *chan)
  243. {
  244. struct ccp_dma_cmd *cmd;
  245. cmd = kmem_cache_alloc(chan->ccp->dma_cmd_cache, GFP_NOWAIT);
  246. if (cmd)
  247. memset(cmd, 0, sizeof(*cmd));
  248. return cmd;
  249. }
  250. static struct ccp_dma_desc *ccp_alloc_dma_desc(struct ccp_dma_chan *chan,
  251. unsigned long flags)
  252. {
  253. struct ccp_dma_desc *desc;
  254. desc = kmem_cache_zalloc(chan->ccp->dma_desc_cache, GFP_NOWAIT);
  255. if (!desc)
  256. return NULL;
  257. dma_async_tx_descriptor_init(&desc->tx_desc, &chan->dma_chan);
  258. desc->tx_desc.flags = flags;
  259. desc->tx_desc.tx_submit = ccp_tx_submit;
  260. desc->ccp = chan->ccp;
  261. INIT_LIST_HEAD(&desc->pending);
  262. INIT_LIST_HEAD(&desc->active);
  263. desc->status = DMA_IN_PROGRESS;
  264. return desc;
  265. }
  266. static struct ccp_dma_desc *ccp_create_desc(struct dma_chan *dma_chan,
  267. struct scatterlist *dst_sg,
  268. unsigned int dst_nents,
  269. struct scatterlist *src_sg,
  270. unsigned int src_nents,
  271. unsigned long flags)
  272. {
  273. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  274. dma_chan);
  275. struct ccp_device *ccp = chan->ccp;
  276. struct ccp_dma_desc *desc;
  277. struct ccp_dma_cmd *cmd;
  278. struct ccp_cmd *ccp_cmd;
  279. struct ccp_passthru_nomap_engine *ccp_pt;
  280. unsigned int src_offset, src_len;
  281. unsigned int dst_offset, dst_len;
  282. unsigned int len;
  283. unsigned long sflags;
  284. size_t total_len;
  285. if (!dst_sg || !src_sg)
  286. return NULL;
  287. if (!dst_nents || !src_nents)
  288. return NULL;
  289. desc = ccp_alloc_dma_desc(chan, flags);
  290. if (!desc)
  291. return NULL;
  292. total_len = 0;
  293. src_len = sg_dma_len(src_sg);
  294. src_offset = 0;
  295. dst_len = sg_dma_len(dst_sg);
  296. dst_offset = 0;
  297. while (true) {
  298. if (!src_len) {
  299. src_nents--;
  300. if (!src_nents)
  301. break;
  302. src_sg = sg_next(src_sg);
  303. if (!src_sg)
  304. break;
  305. src_len = sg_dma_len(src_sg);
  306. src_offset = 0;
  307. continue;
  308. }
  309. if (!dst_len) {
  310. dst_nents--;
  311. if (!dst_nents)
  312. break;
  313. dst_sg = sg_next(dst_sg);
  314. if (!dst_sg)
  315. break;
  316. dst_len = sg_dma_len(dst_sg);
  317. dst_offset = 0;
  318. continue;
  319. }
  320. len = min(dst_len, src_len);
  321. cmd = ccp_alloc_dma_cmd(chan);
  322. if (!cmd)
  323. goto err;
  324. ccp_cmd = &cmd->ccp_cmd;
  325. ccp_cmd->ccp = chan->ccp;
  326. ccp_pt = &ccp_cmd->u.passthru_nomap;
  327. ccp_cmd->flags = CCP_CMD_MAY_BACKLOG;
  328. ccp_cmd->flags |= CCP_CMD_PASSTHRU_NO_DMA_MAP;
  329. ccp_cmd->engine = CCP_ENGINE_PASSTHRU;
  330. ccp_pt->bit_mod = CCP_PASSTHRU_BITWISE_NOOP;
  331. ccp_pt->byte_swap = CCP_PASSTHRU_BYTESWAP_NOOP;
  332. ccp_pt->src_dma = sg_dma_address(src_sg) + src_offset;
  333. ccp_pt->dst_dma = sg_dma_address(dst_sg) + dst_offset;
  334. ccp_pt->src_len = len;
  335. ccp_pt->final = 1;
  336. ccp_cmd->callback = ccp_cmd_callback;
  337. ccp_cmd->data = desc;
  338. list_add_tail(&cmd->entry, &desc->pending);
  339. dev_dbg(ccp->dev,
  340. "%s - cmd=%p, src=%pad, dst=%pad, len=%llu\n", __func__,
  341. cmd, &ccp_pt->src_dma,
  342. &ccp_pt->dst_dma, ccp_pt->src_len);
  343. total_len += len;
  344. src_len -= len;
  345. src_offset += len;
  346. dst_len -= len;
  347. dst_offset += len;
  348. }
  349. desc->len = total_len;
  350. if (list_empty(&desc->pending))
  351. goto err;
  352. dev_dbg(ccp->dev, "%s - desc=%p\n", __func__, desc);
  353. spin_lock_irqsave(&chan->lock, sflags);
  354. list_add_tail(&desc->entry, &chan->created);
  355. spin_unlock_irqrestore(&chan->lock, sflags);
  356. return desc;
  357. err:
  358. ccp_free_cmd_resources(ccp, &desc->pending);
  359. kmem_cache_free(ccp->dma_desc_cache, desc);
  360. return NULL;
  361. }
  362. static struct dma_async_tx_descriptor *ccp_prep_dma_memcpy(
  363. struct dma_chan *dma_chan, dma_addr_t dst, dma_addr_t src, size_t len,
  364. unsigned long flags)
  365. {
  366. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  367. dma_chan);
  368. struct ccp_dma_desc *desc;
  369. struct scatterlist dst_sg, src_sg;
  370. dev_dbg(chan->ccp->dev,
  371. "%s - src=%pad, dst=%pad, len=%zu, flags=%#lx\n",
  372. __func__, &src, &dst, len, flags);
  373. sg_init_table(&dst_sg, 1);
  374. sg_dma_address(&dst_sg) = dst;
  375. sg_dma_len(&dst_sg) = len;
  376. sg_init_table(&src_sg, 1);
  377. sg_dma_address(&src_sg) = src;
  378. sg_dma_len(&src_sg) = len;
  379. desc = ccp_create_desc(dma_chan, &dst_sg, 1, &src_sg, 1, flags);
  380. if (!desc)
  381. return NULL;
  382. return &desc->tx_desc;
  383. }
  384. static struct dma_async_tx_descriptor *ccp_prep_dma_sg(
  385. struct dma_chan *dma_chan, struct scatterlist *dst_sg,
  386. unsigned int dst_nents, struct scatterlist *src_sg,
  387. unsigned int src_nents, unsigned long flags)
  388. {
  389. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  390. dma_chan);
  391. struct ccp_dma_desc *desc;
  392. dev_dbg(chan->ccp->dev,
  393. "%s - src=%p, src_nents=%u dst=%p, dst_nents=%u, flags=%#lx\n",
  394. __func__, src_sg, src_nents, dst_sg, dst_nents, flags);
  395. desc = ccp_create_desc(dma_chan, dst_sg, dst_nents, src_sg, src_nents,
  396. flags);
  397. if (!desc)
  398. return NULL;
  399. return &desc->tx_desc;
  400. }
  401. static struct dma_async_tx_descriptor *ccp_prep_dma_interrupt(
  402. struct dma_chan *dma_chan, unsigned long flags)
  403. {
  404. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  405. dma_chan);
  406. struct ccp_dma_desc *desc;
  407. desc = ccp_alloc_dma_desc(chan, flags);
  408. if (!desc)
  409. return NULL;
  410. return &desc->tx_desc;
  411. }
  412. static void ccp_issue_pending(struct dma_chan *dma_chan)
  413. {
  414. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  415. dma_chan);
  416. struct ccp_dma_desc *desc;
  417. unsigned long flags;
  418. dev_dbg(chan->ccp->dev, "%s\n", __func__);
  419. spin_lock_irqsave(&chan->lock, flags);
  420. desc = __ccp_pending_to_active(chan);
  421. spin_unlock_irqrestore(&chan->lock, flags);
  422. /* If there was nothing active, start processing */
  423. if (desc)
  424. ccp_cmd_callback(desc, 0);
  425. }
  426. static enum dma_status ccp_tx_status(struct dma_chan *dma_chan,
  427. dma_cookie_t cookie,
  428. struct dma_tx_state *state)
  429. {
  430. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  431. dma_chan);
  432. struct ccp_dma_desc *desc;
  433. enum dma_status ret;
  434. unsigned long flags;
  435. if (chan->status == DMA_PAUSED) {
  436. ret = DMA_PAUSED;
  437. goto out;
  438. }
  439. ret = dma_cookie_status(dma_chan, cookie, state);
  440. if (ret == DMA_COMPLETE) {
  441. spin_lock_irqsave(&chan->lock, flags);
  442. /* Get status from complete chain, if still there */
  443. list_for_each_entry(desc, &chan->complete, entry) {
  444. if (desc->tx_desc.cookie != cookie)
  445. continue;
  446. ret = desc->status;
  447. break;
  448. }
  449. spin_unlock_irqrestore(&chan->lock, flags);
  450. }
  451. out:
  452. dev_dbg(chan->ccp->dev, "%s - %u\n", __func__, ret);
  453. return ret;
  454. }
  455. static int ccp_pause(struct dma_chan *dma_chan)
  456. {
  457. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  458. dma_chan);
  459. chan->status = DMA_PAUSED;
  460. /*TODO: Wait for active DMA to complete before returning? */
  461. return 0;
  462. }
  463. static int ccp_resume(struct dma_chan *dma_chan)
  464. {
  465. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  466. dma_chan);
  467. struct ccp_dma_desc *desc;
  468. unsigned long flags;
  469. spin_lock_irqsave(&chan->lock, flags);
  470. desc = list_first_entry_or_null(&chan->active, struct ccp_dma_desc,
  471. entry);
  472. spin_unlock_irqrestore(&chan->lock, flags);
  473. /* Indicate the channel is running again */
  474. chan->status = DMA_IN_PROGRESS;
  475. /* If there was something active, re-start */
  476. if (desc)
  477. ccp_cmd_callback(desc, 0);
  478. return 0;
  479. }
  480. static int ccp_terminate_all(struct dma_chan *dma_chan)
  481. {
  482. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  483. dma_chan);
  484. unsigned long flags;
  485. dev_dbg(chan->ccp->dev, "%s\n", __func__);
  486. /*TODO: Wait for active DMA to complete before continuing */
  487. spin_lock_irqsave(&chan->lock, flags);
  488. /*TODO: Purge the complete list? */
  489. ccp_free_desc_resources(chan->ccp, &chan->active);
  490. ccp_free_desc_resources(chan->ccp, &chan->pending);
  491. ccp_free_desc_resources(chan->ccp, &chan->created);
  492. spin_unlock_irqrestore(&chan->lock, flags);
  493. return 0;
  494. }
  495. int ccp_dmaengine_register(struct ccp_device *ccp)
  496. {
  497. struct ccp_dma_chan *chan;
  498. struct dma_device *dma_dev = &ccp->dma_dev;
  499. struct dma_chan *dma_chan;
  500. char *dma_cmd_cache_name;
  501. char *dma_desc_cache_name;
  502. unsigned int i;
  503. int ret;
  504. ccp->ccp_dma_chan = devm_kcalloc(ccp->dev, ccp->cmd_q_count,
  505. sizeof(*(ccp->ccp_dma_chan)),
  506. GFP_KERNEL);
  507. if (!ccp->ccp_dma_chan)
  508. return -ENOMEM;
  509. dma_cmd_cache_name = devm_kasprintf(ccp->dev, GFP_KERNEL,
  510. "%s-dmaengine-cmd-cache",
  511. ccp->name);
  512. if (!dma_cmd_cache_name)
  513. return -ENOMEM;
  514. ccp->dma_cmd_cache = kmem_cache_create(dma_cmd_cache_name,
  515. sizeof(struct ccp_dma_cmd),
  516. sizeof(void *),
  517. SLAB_HWCACHE_ALIGN, NULL);
  518. if (!ccp->dma_cmd_cache)
  519. return -ENOMEM;
  520. dma_desc_cache_name = devm_kasprintf(ccp->dev, GFP_KERNEL,
  521. "%s-dmaengine-desc-cache",
  522. ccp->name);
  523. if (!dma_desc_cache_name) {
  524. ret = -ENOMEM;
  525. goto err_cache;
  526. }
  527. ccp->dma_desc_cache = kmem_cache_create(dma_desc_cache_name,
  528. sizeof(struct ccp_dma_desc),
  529. sizeof(void *),
  530. SLAB_HWCACHE_ALIGN, NULL);
  531. if (!ccp->dma_desc_cache) {
  532. ret = -ENOMEM;
  533. goto err_cache;
  534. }
  535. dma_dev->dev = ccp->dev;
  536. dma_dev->src_addr_widths = CCP_DMA_WIDTH(dma_get_mask(ccp->dev));
  537. dma_dev->dst_addr_widths = CCP_DMA_WIDTH(dma_get_mask(ccp->dev));
  538. dma_dev->directions = DMA_MEM_TO_MEM;
  539. dma_dev->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
  540. dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
  541. dma_cap_set(DMA_SG, dma_dev->cap_mask);
  542. dma_cap_set(DMA_INTERRUPT, dma_dev->cap_mask);
  543. /* The DMA channels for this device can be set to public or private,
  544. * and overridden by the module parameter dma_chan_attr.
  545. * Default: according to the value in vdata (dma_chan_attr=0)
  546. * dma_chan_attr=0x1: all channels private (override vdata)
  547. * dma_chan_attr=0x2: all channels public (override vdata)
  548. */
  549. if (ccp_get_dma_chan_attr(ccp) == DMA_PRIVATE)
  550. dma_cap_set(DMA_PRIVATE, dma_dev->cap_mask);
  551. INIT_LIST_HEAD(&dma_dev->channels);
  552. for (i = 0; i < ccp->cmd_q_count; i++) {
  553. chan = ccp->ccp_dma_chan + i;
  554. dma_chan = &chan->dma_chan;
  555. chan->ccp = ccp;
  556. spin_lock_init(&chan->lock);
  557. INIT_LIST_HEAD(&chan->created);
  558. INIT_LIST_HEAD(&chan->pending);
  559. INIT_LIST_HEAD(&chan->active);
  560. INIT_LIST_HEAD(&chan->complete);
  561. tasklet_init(&chan->cleanup_tasklet, ccp_do_cleanup,
  562. (unsigned long)chan);
  563. dma_chan->device = dma_dev;
  564. dma_cookie_init(dma_chan);
  565. list_add_tail(&dma_chan->device_node, &dma_dev->channels);
  566. }
  567. dma_dev->device_free_chan_resources = ccp_free_chan_resources;
  568. dma_dev->device_prep_dma_memcpy = ccp_prep_dma_memcpy;
  569. dma_dev->device_prep_dma_sg = ccp_prep_dma_sg;
  570. dma_dev->device_prep_dma_interrupt = ccp_prep_dma_interrupt;
  571. dma_dev->device_issue_pending = ccp_issue_pending;
  572. dma_dev->device_tx_status = ccp_tx_status;
  573. dma_dev->device_pause = ccp_pause;
  574. dma_dev->device_resume = ccp_resume;
  575. dma_dev->device_terminate_all = ccp_terminate_all;
  576. ret = dma_async_device_register(dma_dev);
  577. if (ret)
  578. goto err_reg;
  579. return 0;
  580. err_reg:
  581. kmem_cache_destroy(ccp->dma_desc_cache);
  582. err_cache:
  583. kmem_cache_destroy(ccp->dma_cmd_cache);
  584. return ret;
  585. }
  586. void ccp_dmaengine_unregister(struct ccp_device *ccp)
  587. {
  588. struct dma_device *dma_dev = &ccp->dma_dev;
  589. dma_async_device_unregister(dma_dev);
  590. kmem_cache_destroy(ccp->dma_desc_cache);
  591. kmem_cache_destroy(ccp->dma_cmd_cache);
  592. }