clk-audio-divider.c 4.0 KB

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  1. /*
  2. * Copyright (c) 2017 AmLogic, Inc.
  3. * Author: Jerome Brunet <jbrunet@baylibre.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. /*
  18. * i2s master clock divider: The algorithm of the generic clk-divider used with
  19. * a very precise clock parent such as the mpll tends to select a low divider
  20. * factor. This gives poor results with this particular divider, especially with
  21. * high frequencies (> 100 MHz)
  22. *
  23. * This driver try to select the maximum possible divider with the rate the
  24. * upstream clock can provide.
  25. */
  26. #include <linux/clk-provider.h>
  27. #include "clkc.h"
  28. #define to_meson_clk_audio_divider(_hw) container_of(_hw, \
  29. struct meson_clk_audio_divider, hw)
  30. static int _div_round(unsigned long parent_rate, unsigned long rate,
  31. unsigned long flags)
  32. {
  33. if (flags & CLK_DIVIDER_ROUND_CLOSEST)
  34. return DIV_ROUND_CLOSEST_ULL((u64)parent_rate, rate);
  35. return DIV_ROUND_UP_ULL((u64)parent_rate, rate);
  36. }
  37. static int _get_val(unsigned long parent_rate, unsigned long rate)
  38. {
  39. return DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1;
  40. }
  41. static int _valid_divider(struct clk_hw *hw, int divider)
  42. {
  43. struct meson_clk_audio_divider *adiv =
  44. to_meson_clk_audio_divider(hw);
  45. int max_divider;
  46. u8 width;
  47. width = adiv->div.width;
  48. max_divider = 1 << width;
  49. return clamp(divider, 1, max_divider);
  50. }
  51. static unsigned long audio_divider_recalc_rate(struct clk_hw *hw,
  52. unsigned long parent_rate)
  53. {
  54. struct meson_clk_audio_divider *adiv =
  55. to_meson_clk_audio_divider(hw);
  56. struct parm *p;
  57. unsigned long reg, divider;
  58. p = &adiv->div;
  59. reg = readl(adiv->base + p->reg_off);
  60. divider = PARM_GET(p->width, p->shift, reg) + 1;
  61. return DIV_ROUND_UP_ULL((u64)parent_rate, divider);
  62. }
  63. static long audio_divider_round_rate(struct clk_hw *hw,
  64. unsigned long rate,
  65. unsigned long *parent_rate)
  66. {
  67. struct meson_clk_audio_divider *adiv =
  68. to_meson_clk_audio_divider(hw);
  69. unsigned long max_prate;
  70. int divider;
  71. if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
  72. divider = _div_round(*parent_rate, rate, adiv->flags);
  73. divider = _valid_divider(hw, divider);
  74. return DIV_ROUND_UP_ULL((u64)*parent_rate, divider);
  75. }
  76. /* Get the maximum parent rate */
  77. max_prate = clk_hw_round_rate(clk_hw_get_parent(hw), ULONG_MAX);
  78. /* Get the corresponding rounded down divider */
  79. divider = max_prate / rate;
  80. divider = _valid_divider(hw, divider);
  81. /* Get actual rate of the parent */
  82. *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
  83. divider * rate);
  84. return DIV_ROUND_UP_ULL((u64)*parent_rate, divider);
  85. }
  86. static int audio_divider_set_rate(struct clk_hw *hw,
  87. unsigned long rate,
  88. unsigned long parent_rate)
  89. {
  90. struct meson_clk_audio_divider *adiv =
  91. to_meson_clk_audio_divider(hw);
  92. struct parm *p;
  93. unsigned long reg, flags = 0;
  94. int val;
  95. val = _get_val(parent_rate, rate);
  96. if (adiv->lock)
  97. spin_lock_irqsave(adiv->lock, flags);
  98. else
  99. __acquire(adiv->lock);
  100. p = &adiv->div;
  101. reg = readl(adiv->base + p->reg_off);
  102. reg = PARM_SET(p->width, p->shift, reg, val);
  103. writel(reg, adiv->base + p->reg_off);
  104. if (adiv->lock)
  105. spin_unlock_irqrestore(adiv->lock, flags);
  106. else
  107. __release(adiv->lock);
  108. return 0;
  109. }
  110. const struct clk_ops meson_clk_audio_divider_ro_ops = {
  111. .recalc_rate = audio_divider_recalc_rate,
  112. .round_rate = audio_divider_round_rate,
  113. };
  114. const struct clk_ops meson_clk_audio_divider_ops = {
  115. .recalc_rate = audio_divider_recalc_rate,
  116. .round_rate = audio_divider_round_rate,
  117. .set_rate = audio_divider_set_rate,
  118. };