pcbios.c 10 KB

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  1. /*
  2. * BIOS32 and PCI BIOS handling.
  3. */
  4. #include <linux/pci.h>
  5. #include <linux/init.h>
  6. #include <linux/slab.h>
  7. #include <linux/module.h>
  8. #include <linux/uaccess.h>
  9. #include <asm/pci_x86.h>
  10. #include <asm/e820/types.h>
  11. #include <asm/pci-functions.h>
  12. #include <asm/set_memory.h>
  13. /* BIOS32 signature: "_32_" */
  14. #define BIOS32_SIGNATURE (('_' << 0) + ('3' << 8) + ('2' << 16) + ('_' << 24))
  15. /* PCI signature: "PCI " */
  16. #define PCI_SIGNATURE (('P' << 0) + ('C' << 8) + ('I' << 16) + (' ' << 24))
  17. /* PCI service signature: "$PCI" */
  18. #define PCI_SERVICE (('$' << 0) + ('P' << 8) + ('C' << 16) + ('I' << 24))
  19. /* PCI BIOS hardware mechanism flags */
  20. #define PCIBIOS_HW_TYPE1 0x01
  21. #define PCIBIOS_HW_TYPE2 0x02
  22. #define PCIBIOS_HW_TYPE1_SPEC 0x10
  23. #define PCIBIOS_HW_TYPE2_SPEC 0x20
  24. int pcibios_enabled;
  25. /* According to the BIOS specification at:
  26. * http://members.datafast.net.au/dft0802/specs/bios21.pdf, we could
  27. * restrict the x zone to some pages and make it ro. But this may be
  28. * broken on some bios, complex to handle with static_protections.
  29. * We could make the 0xe0000-0x100000 range rox, but this can break
  30. * some ISA mapping.
  31. *
  32. * So we let's an rw and x hole when pcibios is used. This shouldn't
  33. * happen for modern system with mmconfig, and if you don't want it
  34. * you could disable pcibios...
  35. */
  36. static inline void set_bios_x(void)
  37. {
  38. pcibios_enabled = 1;
  39. set_memory_x(PAGE_OFFSET + BIOS_BEGIN, (BIOS_END - BIOS_BEGIN) >> PAGE_SHIFT);
  40. if (__supported_pte_mask & _PAGE_NX)
  41. printk(KERN_INFO "PCI : PCI BIOS area is rw and x. Use pci=nobios if you want it NX.\n");
  42. }
  43. /*
  44. * This is the standard structure used to identify the entry point
  45. * to the BIOS32 Service Directory, as documented in
  46. * Standard BIOS 32-bit Service Directory Proposal
  47. * Revision 0.4 May 24, 1993
  48. * Phoenix Technologies Ltd.
  49. * Norwood, MA
  50. * and the PCI BIOS specification.
  51. */
  52. union bios32 {
  53. struct {
  54. unsigned long signature; /* _32_ */
  55. unsigned long entry; /* 32 bit physical address */
  56. unsigned char revision; /* Revision level, 0 */
  57. unsigned char length; /* Length in paragraphs should be 01 */
  58. unsigned char checksum; /* All bytes must add up to zero */
  59. unsigned char reserved[5]; /* Must be zero */
  60. } fields;
  61. char chars[16];
  62. };
  63. /*
  64. * Physical address of the service directory. I don't know if we're
  65. * allowed to have more than one of these or not, so just in case
  66. * we'll make pcibios_present() take a memory start parameter and store
  67. * the array there.
  68. */
  69. static struct {
  70. unsigned long address;
  71. unsigned short segment;
  72. } bios32_indirect __initdata = { 0, __KERNEL_CS };
  73. /*
  74. * Returns the entry point for the given service, NULL on error
  75. */
  76. static unsigned long __init bios32_service(unsigned long service)
  77. {
  78. unsigned char return_code; /* %al */
  79. unsigned long address; /* %ebx */
  80. unsigned long length; /* %ecx */
  81. unsigned long entry; /* %edx */
  82. unsigned long flags;
  83. local_irq_save(flags);
  84. __asm__("lcall *(%%edi); cld"
  85. : "=a" (return_code),
  86. "=b" (address),
  87. "=c" (length),
  88. "=d" (entry)
  89. : "0" (service),
  90. "1" (0),
  91. "D" (&bios32_indirect));
  92. local_irq_restore(flags);
  93. switch (return_code) {
  94. case 0:
  95. return address + entry;
  96. case 0x80: /* Not present */
  97. printk(KERN_WARNING "bios32_service(0x%lx): not present\n", service);
  98. return 0;
  99. default: /* Shouldn't happen */
  100. printk(KERN_WARNING "bios32_service(0x%lx): returned 0x%x -- BIOS bug!\n",
  101. service, return_code);
  102. return 0;
  103. }
  104. }
  105. static struct {
  106. unsigned long address;
  107. unsigned short segment;
  108. } pci_indirect __ro_after_init = {
  109. .address = 0,
  110. .segment = __KERNEL_CS,
  111. };
  112. static int pci_bios_present __ro_after_init;
  113. static int __init check_pcibios(void)
  114. {
  115. u32 signature, eax, ebx, ecx;
  116. u8 status, major_ver, minor_ver, hw_mech;
  117. unsigned long flags, pcibios_entry;
  118. if ((pcibios_entry = bios32_service(PCI_SERVICE))) {
  119. pci_indirect.address = pcibios_entry + PAGE_OFFSET;
  120. local_irq_save(flags);
  121. __asm__(
  122. "lcall *(%%edi); cld\n\t"
  123. "jc 1f\n\t"
  124. "xor %%ah, %%ah\n"
  125. "1:"
  126. : "=d" (signature),
  127. "=a" (eax),
  128. "=b" (ebx),
  129. "=c" (ecx)
  130. : "1" (PCIBIOS_PCI_BIOS_PRESENT),
  131. "D" (&pci_indirect)
  132. : "memory");
  133. local_irq_restore(flags);
  134. status = (eax >> 8) & 0xff;
  135. hw_mech = eax & 0xff;
  136. major_ver = (ebx >> 8) & 0xff;
  137. minor_ver = ebx & 0xff;
  138. if (pcibios_last_bus < 0)
  139. pcibios_last_bus = ecx & 0xff;
  140. DBG("PCI: BIOS probe returned s=%02x hw=%02x ver=%02x.%02x l=%02x\n",
  141. status, hw_mech, major_ver, minor_ver, pcibios_last_bus);
  142. if (status || signature != PCI_SIGNATURE) {
  143. printk (KERN_ERR "PCI: BIOS BUG #%x[%08x] found\n",
  144. status, signature);
  145. return 0;
  146. }
  147. printk(KERN_INFO "PCI: PCI BIOS revision %x.%02x entry at 0x%lx, last bus=%d\n",
  148. major_ver, minor_ver, pcibios_entry, pcibios_last_bus);
  149. #ifdef CONFIG_PCI_DIRECT
  150. if (!(hw_mech & PCIBIOS_HW_TYPE1))
  151. pci_probe &= ~PCI_PROBE_CONF1;
  152. if (!(hw_mech & PCIBIOS_HW_TYPE2))
  153. pci_probe &= ~PCI_PROBE_CONF2;
  154. #endif
  155. return 1;
  156. }
  157. return 0;
  158. }
  159. static int pci_bios_read(unsigned int seg, unsigned int bus,
  160. unsigned int devfn, int reg, int len, u32 *value)
  161. {
  162. unsigned long result = 0;
  163. unsigned long flags;
  164. unsigned long bx = (bus << 8) | devfn;
  165. u16 number = 0, mask = 0;
  166. WARN_ON(seg);
  167. if (!value || (bus > 255) || (devfn > 255) || (reg > 255))
  168. return -EINVAL;
  169. raw_spin_lock_irqsave(&pci_config_lock, flags);
  170. switch (len) {
  171. case 1:
  172. number = PCIBIOS_READ_CONFIG_BYTE;
  173. mask = 0xff;
  174. break;
  175. case 2:
  176. number = PCIBIOS_READ_CONFIG_WORD;
  177. mask = 0xffff;
  178. break;
  179. case 4:
  180. number = PCIBIOS_READ_CONFIG_DWORD;
  181. break;
  182. }
  183. __asm__("lcall *(%%esi); cld\n\t"
  184. "jc 1f\n\t"
  185. "xor %%ah, %%ah\n"
  186. "1:"
  187. : "=c" (*value),
  188. "=a" (result)
  189. : "1" (number),
  190. "b" (bx),
  191. "D" ((long)reg),
  192. "S" (&pci_indirect));
  193. /*
  194. * Zero-extend the result beyond 8 or 16 bits, do not trust the
  195. * BIOS having done it:
  196. */
  197. if (mask)
  198. *value &= mask;
  199. raw_spin_unlock_irqrestore(&pci_config_lock, flags);
  200. return (int)((result & 0xff00) >> 8);
  201. }
  202. static int pci_bios_write(unsigned int seg, unsigned int bus,
  203. unsigned int devfn, int reg, int len, u32 value)
  204. {
  205. unsigned long result = 0;
  206. unsigned long flags;
  207. unsigned long bx = (bus << 8) | devfn;
  208. u16 number = 0;
  209. WARN_ON(seg);
  210. if ((bus > 255) || (devfn > 255) || (reg > 255))
  211. return -EINVAL;
  212. raw_spin_lock_irqsave(&pci_config_lock, flags);
  213. switch (len) {
  214. case 1:
  215. number = PCIBIOS_WRITE_CONFIG_BYTE;
  216. break;
  217. case 2:
  218. number = PCIBIOS_WRITE_CONFIG_WORD;
  219. break;
  220. case 4:
  221. number = PCIBIOS_WRITE_CONFIG_DWORD;
  222. break;
  223. }
  224. __asm__("lcall *(%%esi); cld\n\t"
  225. "jc 1f\n\t"
  226. "xor %%ah, %%ah\n"
  227. "1:"
  228. : "=a" (result)
  229. : "0" (number),
  230. "c" (value),
  231. "b" (bx),
  232. "D" ((long)reg),
  233. "S" (&pci_indirect));
  234. raw_spin_unlock_irqrestore(&pci_config_lock, flags);
  235. return (int)((result & 0xff00) >> 8);
  236. }
  237. /*
  238. * Function table for BIOS32 access
  239. */
  240. static const struct pci_raw_ops pci_bios_access = {
  241. .read = pci_bios_read,
  242. .write = pci_bios_write
  243. };
  244. /*
  245. * Try to find PCI BIOS.
  246. */
  247. static const struct pci_raw_ops *__init pci_find_bios(void)
  248. {
  249. union bios32 *check;
  250. unsigned char sum;
  251. int i, length;
  252. /*
  253. * Follow the standard procedure for locating the BIOS32 Service
  254. * directory by scanning the permissible address range from
  255. * 0xe0000 through 0xfffff for a valid BIOS32 structure.
  256. */
  257. for (check = (union bios32 *) __va(0xe0000);
  258. check <= (union bios32 *) __va(0xffff0);
  259. ++check) {
  260. long sig;
  261. if (probe_kernel_address(&check->fields.signature, sig))
  262. continue;
  263. if (check->fields.signature != BIOS32_SIGNATURE)
  264. continue;
  265. length = check->fields.length * 16;
  266. if (!length)
  267. continue;
  268. sum = 0;
  269. for (i = 0; i < length ; ++i)
  270. sum += check->chars[i];
  271. if (sum != 0)
  272. continue;
  273. if (check->fields.revision != 0) {
  274. printk("PCI: unsupported BIOS32 revision %d at 0x%p\n",
  275. check->fields.revision, check);
  276. continue;
  277. }
  278. DBG("PCI: BIOS32 Service Directory structure at 0x%p\n", check);
  279. if (check->fields.entry >= 0x100000) {
  280. printk("PCI: BIOS32 entry (0x%p) in high memory, "
  281. "cannot use.\n", check);
  282. return NULL;
  283. } else {
  284. unsigned long bios32_entry = check->fields.entry;
  285. DBG("PCI: BIOS32 Service Directory entry at 0x%lx\n",
  286. bios32_entry);
  287. bios32_indirect.address = bios32_entry + PAGE_OFFSET;
  288. set_bios_x();
  289. if (check_pcibios())
  290. return &pci_bios_access;
  291. }
  292. break; /* Hopefully more than one BIOS32 cannot happen... */
  293. }
  294. return NULL;
  295. }
  296. /*
  297. * BIOS Functions for IRQ Routing
  298. */
  299. struct irq_routing_options {
  300. u16 size;
  301. struct irq_info *table;
  302. u16 segment;
  303. } __attribute__((packed));
  304. struct irq_routing_table * pcibios_get_irq_routing_table(void)
  305. {
  306. struct irq_routing_options opt;
  307. struct irq_routing_table *rt = NULL;
  308. int ret, map;
  309. unsigned long page;
  310. if (!pci_bios_present)
  311. return NULL;
  312. page = __get_free_page(GFP_KERNEL);
  313. if (!page)
  314. return NULL;
  315. opt.table = (struct irq_info *) page;
  316. opt.size = PAGE_SIZE;
  317. opt.segment = __KERNEL_DS;
  318. DBG("PCI: Fetching IRQ routing table... ");
  319. __asm__("push %%es\n\t"
  320. "push %%ds\n\t"
  321. "pop %%es\n\t"
  322. "lcall *(%%esi); cld\n\t"
  323. "pop %%es\n\t"
  324. "jc 1f\n\t"
  325. "xor %%ah, %%ah\n"
  326. "1:"
  327. : "=a" (ret),
  328. "=b" (map),
  329. "=m" (opt)
  330. : "0" (PCIBIOS_GET_ROUTING_OPTIONS),
  331. "1" (0),
  332. "D" ((long) &opt),
  333. "S" (&pci_indirect),
  334. "m" (opt)
  335. : "memory");
  336. DBG("OK ret=%d, size=%d, map=%x\n", ret, opt.size, map);
  337. if (ret & 0xff00)
  338. printk(KERN_ERR "PCI: Error %02x when fetching IRQ routing table.\n", (ret >> 8) & 0xff);
  339. else if (opt.size) {
  340. rt = kmalloc(sizeof(struct irq_routing_table) + opt.size, GFP_KERNEL);
  341. if (rt) {
  342. memset(rt, 0, sizeof(struct irq_routing_table));
  343. rt->size = opt.size + sizeof(struct irq_routing_table);
  344. rt->exclusive_irqs = map;
  345. memcpy(rt->slots, (void *) page, opt.size);
  346. printk(KERN_INFO "PCI: Using BIOS Interrupt Routing Table\n");
  347. }
  348. }
  349. free_page(page);
  350. return rt;
  351. }
  352. EXPORT_SYMBOL(pcibios_get_irq_routing_table);
  353. int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq)
  354. {
  355. int ret;
  356. __asm__("lcall *(%%esi); cld\n\t"
  357. "jc 1f\n\t"
  358. "xor %%ah, %%ah\n"
  359. "1:"
  360. : "=a" (ret)
  361. : "0" (PCIBIOS_SET_PCI_HW_INT),
  362. "b" ((dev->bus->number << 8) | dev->devfn),
  363. "c" ((irq << 8) | (pin + 10)),
  364. "S" (&pci_indirect));
  365. return !(ret & 0xff00);
  366. }
  367. EXPORT_SYMBOL(pcibios_set_irq_routing);
  368. void __init pci_pcbios_init(void)
  369. {
  370. if ((pci_probe & PCI_PROBE_BIOS)
  371. && ((raw_pci_ops = pci_find_bios()))) {
  372. pci_bios_present = 1;
  373. }
  374. }