smp.c 30 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184
  1. /*
  2. * SMP related functions
  3. *
  4. * Copyright IBM Corp. 1999, 2012
  5. * Author(s): Denis Joseph Barrow,
  6. * Martin Schwidefsky <schwidefsky@de.ibm.com>,
  7. * Heiko Carstens <heiko.carstens@de.ibm.com>,
  8. *
  9. * based on other smp stuff by
  10. * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net>
  11. * (c) 1998 Ingo Molnar
  12. *
  13. * The code outside of smp.c uses logical cpu numbers, only smp.c does
  14. * the translation of logical to physical cpu ids. All new code that
  15. * operates on physical cpu numbers needs to go into smp.c.
  16. */
  17. #define KMSG_COMPONENT "cpu"
  18. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  19. #include <linux/workqueue.h>
  20. #include <linux/bootmem.h>
  21. #include <linux/export.h>
  22. #include <linux/init.h>
  23. #include <linux/mm.h>
  24. #include <linux/err.h>
  25. #include <linux/spinlock.h>
  26. #include <linux/kernel_stat.h>
  27. #include <linux/delay.h>
  28. #include <linux/interrupt.h>
  29. #include <linux/irqflags.h>
  30. #include <linux/cpu.h>
  31. #include <linux/slab.h>
  32. #include <linux/sched/hotplug.h>
  33. #include <linux/sched/task_stack.h>
  34. #include <linux/crash_dump.h>
  35. #include <linux/memblock.h>
  36. #include <asm/asm-offsets.h>
  37. #include <asm/diag.h>
  38. #include <asm/switch_to.h>
  39. #include <asm/facility.h>
  40. #include <asm/ipl.h>
  41. #include <asm/setup.h>
  42. #include <asm/irq.h>
  43. #include <asm/tlbflush.h>
  44. #include <asm/vtimer.h>
  45. #include <asm/lowcore.h>
  46. #include <asm/sclp.h>
  47. #include <asm/vdso.h>
  48. #include <asm/debug.h>
  49. #include <asm/os_info.h>
  50. #include <asm/sigp.h>
  51. #include <asm/idle.h>
  52. #include <asm/nmi.h>
  53. #include "entry.h"
  54. enum {
  55. ec_schedule = 0,
  56. ec_call_function_single,
  57. ec_stop_cpu,
  58. };
  59. enum {
  60. CPU_STATE_STANDBY,
  61. CPU_STATE_CONFIGURED,
  62. };
  63. static DEFINE_PER_CPU(struct cpu *, cpu_device);
  64. struct pcpu {
  65. struct lowcore *lowcore; /* lowcore page(s) for the cpu */
  66. unsigned long ec_mask; /* bit mask for ec_xxx functions */
  67. unsigned long ec_clk; /* sigp timestamp for ec_xxx */
  68. signed char state; /* physical cpu state */
  69. signed char polarization; /* physical polarization */
  70. u16 address; /* physical cpu address */
  71. };
  72. static u8 boot_core_type;
  73. static struct pcpu pcpu_devices[NR_CPUS];
  74. static struct kmem_cache *pcpu_mcesa_cache;
  75. unsigned int smp_cpu_mt_shift;
  76. EXPORT_SYMBOL(smp_cpu_mt_shift);
  77. unsigned int smp_cpu_mtid;
  78. EXPORT_SYMBOL(smp_cpu_mtid);
  79. #ifdef CONFIG_CRASH_DUMP
  80. __vector128 __initdata boot_cpu_vector_save_area[__NUM_VXRS];
  81. #endif
  82. static unsigned int smp_max_threads __initdata = -1U;
  83. static int __init early_nosmt(char *s)
  84. {
  85. smp_max_threads = 1;
  86. return 0;
  87. }
  88. early_param("nosmt", early_nosmt);
  89. static int __init early_smt(char *s)
  90. {
  91. get_option(&s, &smp_max_threads);
  92. return 0;
  93. }
  94. early_param("smt", early_smt);
  95. /*
  96. * The smp_cpu_state_mutex must be held when changing the state or polarization
  97. * member of a pcpu data structure within the pcpu_devices arreay.
  98. */
  99. DEFINE_MUTEX(smp_cpu_state_mutex);
  100. /*
  101. * Signal processor helper functions.
  102. */
  103. static inline int __pcpu_sigp_relax(u16 addr, u8 order, unsigned long parm)
  104. {
  105. int cc;
  106. while (1) {
  107. cc = __pcpu_sigp(addr, order, parm, NULL);
  108. if (cc != SIGP_CC_BUSY)
  109. return cc;
  110. cpu_relax();
  111. }
  112. }
  113. static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm)
  114. {
  115. int cc, retry;
  116. for (retry = 0; ; retry++) {
  117. cc = __pcpu_sigp(pcpu->address, order, parm, NULL);
  118. if (cc != SIGP_CC_BUSY)
  119. break;
  120. if (retry >= 3)
  121. udelay(10);
  122. }
  123. return cc;
  124. }
  125. static inline int pcpu_stopped(struct pcpu *pcpu)
  126. {
  127. u32 uninitialized_var(status);
  128. if (__pcpu_sigp(pcpu->address, SIGP_SENSE,
  129. 0, &status) != SIGP_CC_STATUS_STORED)
  130. return 0;
  131. return !!(status & (SIGP_STATUS_CHECK_STOP|SIGP_STATUS_STOPPED));
  132. }
  133. static inline int pcpu_running(struct pcpu *pcpu)
  134. {
  135. if (__pcpu_sigp(pcpu->address, SIGP_SENSE_RUNNING,
  136. 0, NULL) != SIGP_CC_STATUS_STORED)
  137. return 1;
  138. /* Status stored condition code is equivalent to cpu not running. */
  139. return 0;
  140. }
  141. /*
  142. * Find struct pcpu by cpu address.
  143. */
  144. static struct pcpu *pcpu_find_address(const struct cpumask *mask, u16 address)
  145. {
  146. int cpu;
  147. for_each_cpu(cpu, mask)
  148. if (pcpu_devices[cpu].address == address)
  149. return pcpu_devices + cpu;
  150. return NULL;
  151. }
  152. static void pcpu_ec_call(struct pcpu *pcpu, int ec_bit)
  153. {
  154. int order;
  155. if (test_and_set_bit(ec_bit, &pcpu->ec_mask))
  156. return;
  157. order = pcpu_running(pcpu) ? SIGP_EXTERNAL_CALL : SIGP_EMERGENCY_SIGNAL;
  158. pcpu->ec_clk = get_tod_clock_fast();
  159. pcpu_sigp_retry(pcpu, order, 0);
  160. }
  161. #define ASYNC_FRAME_OFFSET (ASYNC_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE)
  162. #define PANIC_FRAME_OFFSET (PAGE_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE)
  163. static int pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu)
  164. {
  165. unsigned long async_stack, panic_stack;
  166. unsigned long mcesa_origin, mcesa_bits;
  167. struct lowcore *lc;
  168. mcesa_origin = mcesa_bits = 0;
  169. if (pcpu != &pcpu_devices[0]) {
  170. pcpu->lowcore = (struct lowcore *)
  171. __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER);
  172. async_stack = __get_free_pages(GFP_KERNEL, ASYNC_ORDER);
  173. panic_stack = __get_free_page(GFP_KERNEL);
  174. if (!pcpu->lowcore || !panic_stack || !async_stack)
  175. goto out;
  176. if (MACHINE_HAS_VX || MACHINE_HAS_GS) {
  177. mcesa_origin = (unsigned long)
  178. kmem_cache_alloc(pcpu_mcesa_cache, GFP_KERNEL);
  179. if (!mcesa_origin)
  180. goto out;
  181. mcesa_bits = MACHINE_HAS_GS ? 11 : 0;
  182. }
  183. } else {
  184. async_stack = pcpu->lowcore->async_stack - ASYNC_FRAME_OFFSET;
  185. panic_stack = pcpu->lowcore->panic_stack - PANIC_FRAME_OFFSET;
  186. mcesa_origin = pcpu->lowcore->mcesad & MCESA_ORIGIN_MASK;
  187. mcesa_bits = pcpu->lowcore->mcesad & MCESA_LC_MASK;
  188. }
  189. lc = pcpu->lowcore;
  190. memcpy(lc, &S390_lowcore, 512);
  191. memset((char *) lc + 512, 0, sizeof(*lc) - 512);
  192. lc->async_stack = async_stack + ASYNC_FRAME_OFFSET;
  193. lc->panic_stack = panic_stack + PANIC_FRAME_OFFSET;
  194. lc->mcesad = mcesa_origin | mcesa_bits;
  195. lc->cpu_nr = cpu;
  196. lc->spinlock_lockval = arch_spin_lockval(cpu);
  197. if (vdso_alloc_per_cpu(lc))
  198. goto out;
  199. lowcore_ptr[cpu] = lc;
  200. pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, (u32)(unsigned long) lc);
  201. return 0;
  202. out:
  203. if (pcpu != &pcpu_devices[0]) {
  204. if (mcesa_origin)
  205. kmem_cache_free(pcpu_mcesa_cache,
  206. (void *) mcesa_origin);
  207. free_page(panic_stack);
  208. free_pages(async_stack, ASYNC_ORDER);
  209. free_pages((unsigned long) pcpu->lowcore, LC_ORDER);
  210. }
  211. return -ENOMEM;
  212. }
  213. #ifdef CONFIG_HOTPLUG_CPU
  214. static void pcpu_free_lowcore(struct pcpu *pcpu)
  215. {
  216. unsigned long mcesa_origin;
  217. pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, 0);
  218. lowcore_ptr[pcpu - pcpu_devices] = NULL;
  219. vdso_free_per_cpu(pcpu->lowcore);
  220. if (pcpu == &pcpu_devices[0])
  221. return;
  222. if (MACHINE_HAS_VX || MACHINE_HAS_GS) {
  223. mcesa_origin = pcpu->lowcore->mcesad & MCESA_ORIGIN_MASK;
  224. kmem_cache_free(pcpu_mcesa_cache, (void *) mcesa_origin);
  225. }
  226. free_page(pcpu->lowcore->panic_stack-PANIC_FRAME_OFFSET);
  227. free_pages(pcpu->lowcore->async_stack-ASYNC_FRAME_OFFSET, ASYNC_ORDER);
  228. free_pages((unsigned long) pcpu->lowcore, LC_ORDER);
  229. }
  230. #endif /* CONFIG_HOTPLUG_CPU */
  231. static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu)
  232. {
  233. struct lowcore *lc = pcpu->lowcore;
  234. cpumask_set_cpu(cpu, &init_mm.context.cpu_attach_mask);
  235. cpumask_set_cpu(cpu, mm_cpumask(&init_mm));
  236. lc->cpu_nr = cpu;
  237. lc->spinlock_lockval = arch_spin_lockval(cpu);
  238. lc->percpu_offset = __per_cpu_offset[cpu];
  239. lc->kernel_asce = S390_lowcore.kernel_asce;
  240. lc->machine_flags = S390_lowcore.machine_flags;
  241. lc->user_timer = lc->system_timer = lc->steal_timer = 0;
  242. __ctl_store(lc->cregs_save_area, 0, 15);
  243. save_access_regs((unsigned int *) lc->access_regs_save_area);
  244. memcpy(lc->stfle_fac_list, S390_lowcore.stfle_fac_list,
  245. MAX_FACILITY_BIT/8);
  246. }
  247. static void pcpu_attach_task(struct pcpu *pcpu, struct task_struct *tsk)
  248. {
  249. struct lowcore *lc = pcpu->lowcore;
  250. lc->kernel_stack = (unsigned long) task_stack_page(tsk)
  251. + THREAD_SIZE - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs);
  252. lc->current_task = (unsigned long) tsk;
  253. lc->lpp = LPP_MAGIC;
  254. lc->current_pid = tsk->pid;
  255. lc->user_timer = tsk->thread.user_timer;
  256. lc->system_timer = tsk->thread.system_timer;
  257. lc->steal_timer = 0;
  258. }
  259. static void pcpu_start_fn(struct pcpu *pcpu, void (*func)(void *), void *data)
  260. {
  261. struct lowcore *lc = pcpu->lowcore;
  262. lc->restart_stack = lc->kernel_stack;
  263. lc->restart_fn = (unsigned long) func;
  264. lc->restart_data = (unsigned long) data;
  265. lc->restart_source = -1UL;
  266. pcpu_sigp_retry(pcpu, SIGP_RESTART, 0);
  267. }
  268. /*
  269. * Call function via PSW restart on pcpu and stop the current cpu.
  270. */
  271. static void pcpu_delegate(struct pcpu *pcpu, void (*func)(void *),
  272. void *data, unsigned long stack)
  273. {
  274. struct lowcore *lc = lowcore_ptr[pcpu - pcpu_devices];
  275. unsigned long source_cpu = stap();
  276. __load_psw_mask(PSW_KERNEL_BITS);
  277. if (pcpu->address == source_cpu)
  278. func(data); /* should not return */
  279. /* Stop target cpu (if func returns this stops the current cpu). */
  280. pcpu_sigp_retry(pcpu, SIGP_STOP, 0);
  281. /* Restart func on the target cpu and stop the current cpu. */
  282. mem_assign_absolute(lc->restart_stack, stack);
  283. mem_assign_absolute(lc->restart_fn, (unsigned long) func);
  284. mem_assign_absolute(lc->restart_data, (unsigned long) data);
  285. mem_assign_absolute(lc->restart_source, source_cpu);
  286. asm volatile(
  287. "0: sigp 0,%0,%2 # sigp restart to target cpu\n"
  288. " brc 2,0b # busy, try again\n"
  289. "1: sigp 0,%1,%3 # sigp stop to current cpu\n"
  290. " brc 2,1b # busy, try again\n"
  291. : : "d" (pcpu->address), "d" (source_cpu),
  292. "K" (SIGP_RESTART), "K" (SIGP_STOP)
  293. : "0", "1", "cc");
  294. for (;;) ;
  295. }
  296. /*
  297. * Enable additional logical cpus for multi-threading.
  298. */
  299. static int pcpu_set_smt(unsigned int mtid)
  300. {
  301. int cc;
  302. if (smp_cpu_mtid == mtid)
  303. return 0;
  304. cc = __pcpu_sigp(0, SIGP_SET_MULTI_THREADING, mtid, NULL);
  305. if (cc == 0) {
  306. smp_cpu_mtid = mtid;
  307. smp_cpu_mt_shift = 0;
  308. while (smp_cpu_mtid >= (1U << smp_cpu_mt_shift))
  309. smp_cpu_mt_shift++;
  310. pcpu_devices[0].address = stap();
  311. }
  312. return cc;
  313. }
  314. /*
  315. * Call function on an online CPU.
  316. */
  317. void smp_call_online_cpu(void (*func)(void *), void *data)
  318. {
  319. struct pcpu *pcpu;
  320. /* Use the current cpu if it is online. */
  321. pcpu = pcpu_find_address(cpu_online_mask, stap());
  322. if (!pcpu)
  323. /* Use the first online cpu. */
  324. pcpu = pcpu_devices + cpumask_first(cpu_online_mask);
  325. pcpu_delegate(pcpu, func, data, (unsigned long) restart_stack);
  326. }
  327. /*
  328. * Call function on the ipl CPU.
  329. */
  330. void smp_call_ipl_cpu(void (*func)(void *), void *data)
  331. {
  332. pcpu_delegate(&pcpu_devices[0], func, data,
  333. pcpu_devices->lowcore->panic_stack -
  334. PANIC_FRAME_OFFSET + PAGE_SIZE);
  335. }
  336. int smp_find_processor_id(u16 address)
  337. {
  338. int cpu;
  339. for_each_present_cpu(cpu)
  340. if (pcpu_devices[cpu].address == address)
  341. return cpu;
  342. return -1;
  343. }
  344. bool arch_vcpu_is_preempted(int cpu)
  345. {
  346. if (test_cpu_flag_of(CIF_ENABLED_WAIT, cpu))
  347. return false;
  348. if (pcpu_running(pcpu_devices + cpu))
  349. return false;
  350. return true;
  351. }
  352. EXPORT_SYMBOL(arch_vcpu_is_preempted);
  353. void smp_yield_cpu(int cpu)
  354. {
  355. if (MACHINE_HAS_DIAG9C) {
  356. diag_stat_inc_norecursion(DIAG_STAT_X09C);
  357. asm volatile("diag %0,0,0x9c"
  358. : : "d" (pcpu_devices[cpu].address));
  359. } else if (MACHINE_HAS_DIAG44) {
  360. diag_stat_inc_norecursion(DIAG_STAT_X044);
  361. asm volatile("diag 0,0,0x44");
  362. }
  363. }
  364. /*
  365. * Send cpus emergency shutdown signal. This gives the cpus the
  366. * opportunity to complete outstanding interrupts.
  367. */
  368. static void smp_emergency_stop(cpumask_t *cpumask)
  369. {
  370. u64 end;
  371. int cpu;
  372. end = get_tod_clock() + (1000000UL << 12);
  373. for_each_cpu(cpu, cpumask) {
  374. struct pcpu *pcpu = pcpu_devices + cpu;
  375. set_bit(ec_stop_cpu, &pcpu->ec_mask);
  376. while (__pcpu_sigp(pcpu->address, SIGP_EMERGENCY_SIGNAL,
  377. 0, NULL) == SIGP_CC_BUSY &&
  378. get_tod_clock() < end)
  379. cpu_relax();
  380. }
  381. while (get_tod_clock() < end) {
  382. for_each_cpu(cpu, cpumask)
  383. if (pcpu_stopped(pcpu_devices + cpu))
  384. cpumask_clear_cpu(cpu, cpumask);
  385. if (cpumask_empty(cpumask))
  386. break;
  387. cpu_relax();
  388. }
  389. }
  390. /*
  391. * Stop all cpus but the current one.
  392. */
  393. void smp_send_stop(void)
  394. {
  395. cpumask_t cpumask;
  396. int cpu;
  397. /* Disable all interrupts/machine checks */
  398. __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT);
  399. trace_hardirqs_off();
  400. debug_set_critical();
  401. cpumask_copy(&cpumask, cpu_online_mask);
  402. cpumask_clear_cpu(smp_processor_id(), &cpumask);
  403. if (oops_in_progress)
  404. smp_emergency_stop(&cpumask);
  405. /* stop all processors */
  406. for_each_cpu(cpu, &cpumask) {
  407. struct pcpu *pcpu = pcpu_devices + cpu;
  408. pcpu_sigp_retry(pcpu, SIGP_STOP, 0);
  409. while (!pcpu_stopped(pcpu))
  410. cpu_relax();
  411. }
  412. }
  413. /*
  414. * This is the main routine where commands issued by other
  415. * cpus are handled.
  416. */
  417. static void smp_handle_ext_call(void)
  418. {
  419. unsigned long bits;
  420. /* handle bit signal external calls */
  421. bits = xchg(&pcpu_devices[smp_processor_id()].ec_mask, 0);
  422. if (test_bit(ec_stop_cpu, &bits))
  423. smp_stop_cpu();
  424. if (test_bit(ec_schedule, &bits))
  425. scheduler_ipi();
  426. if (test_bit(ec_call_function_single, &bits))
  427. generic_smp_call_function_single_interrupt();
  428. }
  429. static void do_ext_call_interrupt(struct ext_code ext_code,
  430. unsigned int param32, unsigned long param64)
  431. {
  432. inc_irq_stat(ext_code.code == 0x1202 ? IRQEXT_EXC : IRQEXT_EMS);
  433. smp_handle_ext_call();
  434. }
  435. void arch_send_call_function_ipi_mask(const struct cpumask *mask)
  436. {
  437. int cpu;
  438. for_each_cpu(cpu, mask)
  439. pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single);
  440. }
  441. void arch_send_call_function_single_ipi(int cpu)
  442. {
  443. pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single);
  444. }
  445. /*
  446. * this function sends a 'reschedule' IPI to another CPU.
  447. * it goes straight through and wastes no time serializing
  448. * anything. Worst case is that we lose a reschedule ...
  449. */
  450. void smp_send_reschedule(int cpu)
  451. {
  452. pcpu_ec_call(pcpu_devices + cpu, ec_schedule);
  453. }
  454. /*
  455. * parameter area for the set/clear control bit callbacks
  456. */
  457. struct ec_creg_mask_parms {
  458. unsigned long orval;
  459. unsigned long andval;
  460. int cr;
  461. };
  462. /*
  463. * callback for setting/clearing control bits
  464. */
  465. static void smp_ctl_bit_callback(void *info)
  466. {
  467. struct ec_creg_mask_parms *pp = info;
  468. unsigned long cregs[16];
  469. __ctl_store(cregs, 0, 15);
  470. cregs[pp->cr] = (cregs[pp->cr] & pp->andval) | pp->orval;
  471. __ctl_load(cregs, 0, 15);
  472. }
  473. /*
  474. * Set a bit in a control register of all cpus
  475. */
  476. void smp_ctl_set_bit(int cr, int bit)
  477. {
  478. struct ec_creg_mask_parms parms = { 1UL << bit, -1UL, cr };
  479. on_each_cpu(smp_ctl_bit_callback, &parms, 1);
  480. }
  481. EXPORT_SYMBOL(smp_ctl_set_bit);
  482. /*
  483. * Clear a bit in a control register of all cpus
  484. */
  485. void smp_ctl_clear_bit(int cr, int bit)
  486. {
  487. struct ec_creg_mask_parms parms = { 0, ~(1UL << bit), cr };
  488. on_each_cpu(smp_ctl_bit_callback, &parms, 1);
  489. }
  490. EXPORT_SYMBOL(smp_ctl_clear_bit);
  491. #ifdef CONFIG_CRASH_DUMP
  492. int smp_store_status(int cpu)
  493. {
  494. struct pcpu *pcpu = pcpu_devices + cpu;
  495. unsigned long pa;
  496. pa = __pa(&pcpu->lowcore->floating_pt_save_area);
  497. if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_STATUS_AT_ADDRESS,
  498. pa) != SIGP_CC_ORDER_CODE_ACCEPTED)
  499. return -EIO;
  500. if (!MACHINE_HAS_VX && !MACHINE_HAS_GS)
  501. return 0;
  502. pa = __pa(pcpu->lowcore->mcesad & MCESA_ORIGIN_MASK);
  503. if (MACHINE_HAS_GS)
  504. pa |= pcpu->lowcore->mcesad & MCESA_LC_MASK;
  505. if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_ADDITIONAL_STATUS,
  506. pa) != SIGP_CC_ORDER_CODE_ACCEPTED)
  507. return -EIO;
  508. return 0;
  509. }
  510. /*
  511. * Collect CPU state of the previous, crashed system.
  512. * There are four cases:
  513. * 1) standard zfcp dump
  514. * condition: OLDMEM_BASE == NULL && ipl_info.type == IPL_TYPE_FCP_DUMP
  515. * The state for all CPUs except the boot CPU needs to be collected
  516. * with sigp stop-and-store-status. The boot CPU state is located in
  517. * the absolute lowcore of the memory stored in the HSA. The zcore code
  518. * will copy the boot CPU state from the HSA.
  519. * 2) stand-alone kdump for SCSI (zfcp dump with swapped memory)
  520. * condition: OLDMEM_BASE != NULL && ipl_info.type == IPL_TYPE_FCP_DUMP
  521. * The state for all CPUs except the boot CPU needs to be collected
  522. * with sigp stop-and-store-status. The firmware or the boot-loader
  523. * stored the registers of the boot CPU in the absolute lowcore in the
  524. * memory of the old system.
  525. * 3) kdump and the old kernel did not store the CPU state,
  526. * or stand-alone kdump for DASD
  527. * condition: OLDMEM_BASE != NULL && !is_kdump_kernel()
  528. * The state for all CPUs except the boot CPU needs to be collected
  529. * with sigp stop-and-store-status. The kexec code or the boot-loader
  530. * stored the registers of the boot CPU in the memory of the old system.
  531. * 4) kdump and the old kernel stored the CPU state
  532. * condition: OLDMEM_BASE != NULL && is_kdump_kernel()
  533. * This case does not exist for s390 anymore, setup_arch explicitly
  534. * deactivates the elfcorehdr= kernel parameter
  535. */
  536. static __init void smp_save_cpu_vxrs(struct save_area *sa, u16 addr,
  537. bool is_boot_cpu, unsigned long page)
  538. {
  539. __vector128 *vxrs = (__vector128 *) page;
  540. if (is_boot_cpu)
  541. vxrs = boot_cpu_vector_save_area;
  542. else
  543. __pcpu_sigp_relax(addr, SIGP_STORE_ADDITIONAL_STATUS, page);
  544. save_area_add_vxrs(sa, vxrs);
  545. }
  546. static __init void smp_save_cpu_regs(struct save_area *sa, u16 addr,
  547. bool is_boot_cpu, unsigned long page)
  548. {
  549. void *regs = (void *) page;
  550. if (is_boot_cpu)
  551. copy_oldmem_kernel(regs, (void *) __LC_FPREGS_SAVE_AREA, 512);
  552. else
  553. __pcpu_sigp_relax(addr, SIGP_STORE_STATUS_AT_ADDRESS, page);
  554. save_area_add_regs(sa, regs);
  555. }
  556. void __init smp_save_dump_cpus(void)
  557. {
  558. int addr, boot_cpu_addr, max_cpu_addr;
  559. struct save_area *sa;
  560. unsigned long page;
  561. bool is_boot_cpu;
  562. if (!(OLDMEM_BASE || ipl_info.type == IPL_TYPE_FCP_DUMP))
  563. /* No previous system present, normal boot. */
  564. return;
  565. /* Allocate a page as dumping area for the store status sigps */
  566. page = memblock_alloc_base(PAGE_SIZE, PAGE_SIZE, 1UL << 31);
  567. /* Set multi-threading state to the previous system. */
  568. pcpu_set_smt(sclp.mtid_prev);
  569. boot_cpu_addr = stap();
  570. max_cpu_addr = SCLP_MAX_CORES << sclp.mtid_prev;
  571. for (addr = 0; addr <= max_cpu_addr; addr++) {
  572. if (__pcpu_sigp_relax(addr, SIGP_SENSE, 0) ==
  573. SIGP_CC_NOT_OPERATIONAL)
  574. continue;
  575. is_boot_cpu = (addr == boot_cpu_addr);
  576. /* Allocate save area */
  577. sa = save_area_alloc(is_boot_cpu);
  578. if (!sa)
  579. panic("could not allocate memory for save area\n");
  580. if (MACHINE_HAS_VX)
  581. /* Get the vector registers */
  582. smp_save_cpu_vxrs(sa, addr, is_boot_cpu, page);
  583. /*
  584. * For a zfcp dump OLDMEM_BASE == NULL and the registers
  585. * of the boot CPU are stored in the HSA. To retrieve
  586. * these registers an SCLP request is required which is
  587. * done by drivers/s390/char/zcore.c:init_cpu_info()
  588. */
  589. if (!is_boot_cpu || OLDMEM_BASE)
  590. /* Get the CPU registers */
  591. smp_save_cpu_regs(sa, addr, is_boot_cpu, page);
  592. }
  593. memblock_free(page, PAGE_SIZE);
  594. diag308_reset();
  595. pcpu_set_smt(0);
  596. }
  597. #endif /* CONFIG_CRASH_DUMP */
  598. void smp_cpu_set_polarization(int cpu, int val)
  599. {
  600. pcpu_devices[cpu].polarization = val;
  601. }
  602. int smp_cpu_get_polarization(int cpu)
  603. {
  604. return pcpu_devices[cpu].polarization;
  605. }
  606. static void __ref smp_get_core_info(struct sclp_core_info *info, int early)
  607. {
  608. static int use_sigp_detection;
  609. int address;
  610. if (use_sigp_detection || sclp_get_core_info(info, early)) {
  611. use_sigp_detection = 1;
  612. for (address = 0;
  613. address < (SCLP_MAX_CORES << smp_cpu_mt_shift);
  614. address += (1U << smp_cpu_mt_shift)) {
  615. if (__pcpu_sigp_relax(address, SIGP_SENSE, 0) ==
  616. SIGP_CC_NOT_OPERATIONAL)
  617. continue;
  618. info->core[info->configured].core_id =
  619. address >> smp_cpu_mt_shift;
  620. info->configured++;
  621. }
  622. info->combined = info->configured;
  623. }
  624. }
  625. static int smp_add_present_cpu(int cpu);
  626. static int __smp_rescan_cpus(struct sclp_core_info *info, int sysfs_add)
  627. {
  628. struct pcpu *pcpu;
  629. cpumask_t avail;
  630. int cpu, nr, i, j;
  631. u16 address;
  632. nr = 0;
  633. cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask);
  634. cpu = cpumask_first(&avail);
  635. for (i = 0; (i < info->combined) && (cpu < nr_cpu_ids); i++) {
  636. if (sclp.has_core_type && info->core[i].type != boot_core_type)
  637. continue;
  638. address = info->core[i].core_id << smp_cpu_mt_shift;
  639. for (j = 0; j <= smp_cpu_mtid; j++) {
  640. if (pcpu_find_address(cpu_present_mask, address + j))
  641. continue;
  642. pcpu = pcpu_devices + cpu;
  643. pcpu->address = address + j;
  644. pcpu->state =
  645. (cpu >= info->configured*(smp_cpu_mtid + 1)) ?
  646. CPU_STATE_STANDBY : CPU_STATE_CONFIGURED;
  647. smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN);
  648. set_cpu_present(cpu, true);
  649. if (sysfs_add && smp_add_present_cpu(cpu) != 0)
  650. set_cpu_present(cpu, false);
  651. else
  652. nr++;
  653. cpu = cpumask_next(cpu, &avail);
  654. if (cpu >= nr_cpu_ids)
  655. break;
  656. }
  657. }
  658. return nr;
  659. }
  660. void __init smp_detect_cpus(void)
  661. {
  662. unsigned int cpu, mtid, c_cpus, s_cpus;
  663. struct sclp_core_info *info;
  664. u16 address;
  665. /* Get CPU information */
  666. info = memblock_virt_alloc(sizeof(*info), 8);
  667. smp_get_core_info(info, 1);
  668. /* Find boot CPU type */
  669. if (sclp.has_core_type) {
  670. address = stap();
  671. for (cpu = 0; cpu < info->combined; cpu++)
  672. if (info->core[cpu].core_id == address) {
  673. /* The boot cpu dictates the cpu type. */
  674. boot_core_type = info->core[cpu].type;
  675. break;
  676. }
  677. if (cpu >= info->combined)
  678. panic("Could not find boot CPU type");
  679. }
  680. /* Set multi-threading state for the current system */
  681. mtid = boot_core_type ? sclp.mtid : sclp.mtid_cp;
  682. mtid = (mtid < smp_max_threads) ? mtid : smp_max_threads - 1;
  683. pcpu_set_smt(mtid);
  684. /* Print number of CPUs */
  685. c_cpus = s_cpus = 0;
  686. for (cpu = 0; cpu < info->combined; cpu++) {
  687. if (sclp.has_core_type &&
  688. info->core[cpu].type != boot_core_type)
  689. continue;
  690. if (cpu < info->configured)
  691. c_cpus += smp_cpu_mtid + 1;
  692. else
  693. s_cpus += smp_cpu_mtid + 1;
  694. }
  695. pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus);
  696. /* Add CPUs present at boot */
  697. get_online_cpus();
  698. __smp_rescan_cpus(info, 0);
  699. put_online_cpus();
  700. memblock_free_early((unsigned long)info, sizeof(*info));
  701. }
  702. /*
  703. * Activate a secondary processor.
  704. */
  705. static void smp_start_secondary(void *cpuvoid)
  706. {
  707. S390_lowcore.last_update_clock = get_tod_clock();
  708. S390_lowcore.restart_stack = (unsigned long) restart_stack;
  709. S390_lowcore.restart_fn = (unsigned long) do_restart;
  710. S390_lowcore.restart_data = 0;
  711. S390_lowcore.restart_source = -1UL;
  712. restore_access_regs(S390_lowcore.access_regs_save_area);
  713. __ctl_load(S390_lowcore.cregs_save_area, 0, 15);
  714. __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT);
  715. cpu_init();
  716. preempt_disable();
  717. init_cpu_timer();
  718. vtime_init();
  719. pfault_init();
  720. notify_cpu_starting(smp_processor_id());
  721. set_cpu_online(smp_processor_id(), true);
  722. inc_irq_stat(CPU_RST);
  723. local_irq_enable();
  724. cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
  725. }
  726. /* Upping and downing of CPUs */
  727. int __cpu_up(unsigned int cpu, struct task_struct *tidle)
  728. {
  729. struct pcpu *pcpu;
  730. int base, i, rc;
  731. pcpu = pcpu_devices + cpu;
  732. if (pcpu->state != CPU_STATE_CONFIGURED)
  733. return -EIO;
  734. base = smp_get_base_cpu(cpu);
  735. for (i = 0; i <= smp_cpu_mtid; i++) {
  736. if (base + i < nr_cpu_ids)
  737. if (cpu_online(base + i))
  738. break;
  739. }
  740. /*
  741. * If this is the first CPU of the core to get online
  742. * do an initial CPU reset.
  743. */
  744. if (i > smp_cpu_mtid &&
  745. pcpu_sigp_retry(pcpu_devices + base, SIGP_INITIAL_CPU_RESET, 0) !=
  746. SIGP_CC_ORDER_CODE_ACCEPTED)
  747. return -EIO;
  748. rc = pcpu_alloc_lowcore(pcpu, cpu);
  749. if (rc)
  750. return rc;
  751. pcpu_prepare_secondary(pcpu, cpu);
  752. pcpu_attach_task(pcpu, tidle);
  753. pcpu_start_fn(pcpu, smp_start_secondary, NULL);
  754. /* Wait until cpu puts itself in the online & active maps */
  755. while (!cpu_online(cpu))
  756. cpu_relax();
  757. return 0;
  758. }
  759. static unsigned int setup_possible_cpus __initdata;
  760. static int __init _setup_possible_cpus(char *s)
  761. {
  762. get_option(&s, &setup_possible_cpus);
  763. return 0;
  764. }
  765. early_param("possible_cpus", _setup_possible_cpus);
  766. #ifdef CONFIG_HOTPLUG_CPU
  767. int __cpu_disable(void)
  768. {
  769. unsigned long cregs[16];
  770. /* Handle possible pending IPIs */
  771. smp_handle_ext_call();
  772. set_cpu_online(smp_processor_id(), false);
  773. /* Disable pseudo page faults on this cpu. */
  774. pfault_fini();
  775. /* Disable interrupt sources via control register. */
  776. __ctl_store(cregs, 0, 15);
  777. cregs[0] &= ~0x0000ee70UL; /* disable all external interrupts */
  778. cregs[6] &= ~0xff000000UL; /* disable all I/O interrupts */
  779. cregs[14] &= ~0x1f000000UL; /* disable most machine checks */
  780. __ctl_load(cregs, 0, 15);
  781. clear_cpu_flag(CIF_NOHZ_DELAY);
  782. return 0;
  783. }
  784. void __cpu_die(unsigned int cpu)
  785. {
  786. struct pcpu *pcpu;
  787. /* Wait until target cpu is down */
  788. pcpu = pcpu_devices + cpu;
  789. while (!pcpu_stopped(pcpu))
  790. cpu_relax();
  791. pcpu_free_lowcore(pcpu);
  792. cpumask_clear_cpu(cpu, mm_cpumask(&init_mm));
  793. cpumask_clear_cpu(cpu, &init_mm.context.cpu_attach_mask);
  794. }
  795. void __noreturn cpu_die(void)
  796. {
  797. idle_task_exit();
  798. pcpu_sigp_retry(pcpu_devices + smp_processor_id(), SIGP_STOP, 0);
  799. for (;;) ;
  800. }
  801. #endif /* CONFIG_HOTPLUG_CPU */
  802. void __init smp_fill_possible_mask(void)
  803. {
  804. unsigned int possible, sclp_max, cpu;
  805. sclp_max = max(sclp.mtid, sclp.mtid_cp) + 1;
  806. sclp_max = min(smp_max_threads, sclp_max);
  807. sclp_max = (sclp.max_cores * sclp_max) ?: nr_cpu_ids;
  808. possible = setup_possible_cpus ?: nr_cpu_ids;
  809. possible = min(possible, sclp_max);
  810. for (cpu = 0; cpu < possible && cpu < nr_cpu_ids; cpu++)
  811. set_cpu_possible(cpu, true);
  812. }
  813. void __init smp_prepare_cpus(unsigned int max_cpus)
  814. {
  815. unsigned long size;
  816. /* request the 0x1201 emergency signal external interrupt */
  817. if (register_external_irq(EXT_IRQ_EMERGENCY_SIG, do_ext_call_interrupt))
  818. panic("Couldn't request external interrupt 0x1201");
  819. /* request the 0x1202 external call external interrupt */
  820. if (register_external_irq(EXT_IRQ_EXTERNAL_CALL, do_ext_call_interrupt))
  821. panic("Couldn't request external interrupt 0x1202");
  822. /* create slab cache for the machine-check-extended-save-areas */
  823. if (MACHINE_HAS_VX || MACHINE_HAS_GS) {
  824. size = 1UL << (MACHINE_HAS_GS ? 11 : 10);
  825. pcpu_mcesa_cache = kmem_cache_create("nmi_save_areas",
  826. size, size, 0, NULL);
  827. if (!pcpu_mcesa_cache)
  828. panic("Couldn't create nmi save area cache");
  829. }
  830. }
  831. void __init smp_prepare_boot_cpu(void)
  832. {
  833. struct pcpu *pcpu = pcpu_devices;
  834. WARN_ON(!cpu_present(0) || !cpu_online(0));
  835. pcpu->state = CPU_STATE_CONFIGURED;
  836. pcpu->lowcore = (struct lowcore *)(unsigned long) store_prefix();
  837. S390_lowcore.percpu_offset = __per_cpu_offset[0];
  838. smp_cpu_set_polarization(0, POLARIZATION_UNKNOWN);
  839. }
  840. void __init smp_cpus_done(unsigned int max_cpus)
  841. {
  842. }
  843. void __init smp_setup_processor_id(void)
  844. {
  845. pcpu_devices[0].address = stap();
  846. S390_lowcore.cpu_nr = 0;
  847. S390_lowcore.spinlock_lockval = arch_spin_lockval(0);
  848. }
  849. /*
  850. * the frequency of the profiling timer can be changed
  851. * by writing a multiplier value into /proc/profile.
  852. *
  853. * usually you want to run this on all CPUs ;)
  854. */
  855. int setup_profiling_timer(unsigned int multiplier)
  856. {
  857. return 0;
  858. }
  859. #ifdef CONFIG_HOTPLUG_CPU
  860. static ssize_t cpu_configure_show(struct device *dev,
  861. struct device_attribute *attr, char *buf)
  862. {
  863. ssize_t count;
  864. mutex_lock(&smp_cpu_state_mutex);
  865. count = sprintf(buf, "%d\n", pcpu_devices[dev->id].state);
  866. mutex_unlock(&smp_cpu_state_mutex);
  867. return count;
  868. }
  869. static ssize_t cpu_configure_store(struct device *dev,
  870. struct device_attribute *attr,
  871. const char *buf, size_t count)
  872. {
  873. struct pcpu *pcpu;
  874. int cpu, val, rc, i;
  875. char delim;
  876. if (sscanf(buf, "%d %c", &val, &delim) != 1)
  877. return -EINVAL;
  878. if (val != 0 && val != 1)
  879. return -EINVAL;
  880. get_online_cpus();
  881. mutex_lock(&smp_cpu_state_mutex);
  882. rc = -EBUSY;
  883. /* disallow configuration changes of online cpus and cpu 0 */
  884. cpu = dev->id;
  885. cpu = smp_get_base_cpu(cpu);
  886. if (cpu == 0)
  887. goto out;
  888. for (i = 0; i <= smp_cpu_mtid; i++)
  889. if (cpu_online(cpu + i))
  890. goto out;
  891. pcpu = pcpu_devices + cpu;
  892. rc = 0;
  893. switch (val) {
  894. case 0:
  895. if (pcpu->state != CPU_STATE_CONFIGURED)
  896. break;
  897. rc = sclp_core_deconfigure(pcpu->address >> smp_cpu_mt_shift);
  898. if (rc)
  899. break;
  900. for (i = 0; i <= smp_cpu_mtid; i++) {
  901. if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i))
  902. continue;
  903. pcpu[i].state = CPU_STATE_STANDBY;
  904. smp_cpu_set_polarization(cpu + i,
  905. POLARIZATION_UNKNOWN);
  906. }
  907. topology_expect_change();
  908. break;
  909. case 1:
  910. if (pcpu->state != CPU_STATE_STANDBY)
  911. break;
  912. rc = sclp_core_configure(pcpu->address >> smp_cpu_mt_shift);
  913. if (rc)
  914. break;
  915. for (i = 0; i <= smp_cpu_mtid; i++) {
  916. if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i))
  917. continue;
  918. pcpu[i].state = CPU_STATE_CONFIGURED;
  919. smp_cpu_set_polarization(cpu + i,
  920. POLARIZATION_UNKNOWN);
  921. }
  922. topology_expect_change();
  923. break;
  924. default:
  925. break;
  926. }
  927. out:
  928. mutex_unlock(&smp_cpu_state_mutex);
  929. put_online_cpus();
  930. return rc ? rc : count;
  931. }
  932. static DEVICE_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store);
  933. #endif /* CONFIG_HOTPLUG_CPU */
  934. static ssize_t show_cpu_address(struct device *dev,
  935. struct device_attribute *attr, char *buf)
  936. {
  937. return sprintf(buf, "%d\n", pcpu_devices[dev->id].address);
  938. }
  939. static DEVICE_ATTR(address, 0444, show_cpu_address, NULL);
  940. static struct attribute *cpu_common_attrs[] = {
  941. #ifdef CONFIG_HOTPLUG_CPU
  942. &dev_attr_configure.attr,
  943. #endif
  944. &dev_attr_address.attr,
  945. NULL,
  946. };
  947. static struct attribute_group cpu_common_attr_group = {
  948. .attrs = cpu_common_attrs,
  949. };
  950. static struct attribute *cpu_online_attrs[] = {
  951. &dev_attr_idle_count.attr,
  952. &dev_attr_idle_time_us.attr,
  953. NULL,
  954. };
  955. static struct attribute_group cpu_online_attr_group = {
  956. .attrs = cpu_online_attrs,
  957. };
  958. static int smp_cpu_online(unsigned int cpu)
  959. {
  960. struct device *s = &per_cpu(cpu_device, cpu)->dev;
  961. return sysfs_create_group(&s->kobj, &cpu_online_attr_group);
  962. }
  963. static int smp_cpu_pre_down(unsigned int cpu)
  964. {
  965. struct device *s = &per_cpu(cpu_device, cpu)->dev;
  966. sysfs_remove_group(&s->kobj, &cpu_online_attr_group);
  967. return 0;
  968. }
  969. static int smp_add_present_cpu(int cpu)
  970. {
  971. struct device *s;
  972. struct cpu *c;
  973. int rc;
  974. c = kzalloc(sizeof(*c), GFP_KERNEL);
  975. if (!c)
  976. return -ENOMEM;
  977. per_cpu(cpu_device, cpu) = c;
  978. s = &c->dev;
  979. c->hotpluggable = 1;
  980. rc = register_cpu(c, cpu);
  981. if (rc)
  982. goto out;
  983. rc = sysfs_create_group(&s->kobj, &cpu_common_attr_group);
  984. if (rc)
  985. goto out_cpu;
  986. rc = topology_cpu_init(c);
  987. if (rc)
  988. goto out_topology;
  989. return 0;
  990. out_topology:
  991. sysfs_remove_group(&s->kobj, &cpu_common_attr_group);
  992. out_cpu:
  993. #ifdef CONFIG_HOTPLUG_CPU
  994. unregister_cpu(c);
  995. #endif
  996. out:
  997. return rc;
  998. }
  999. #ifdef CONFIG_HOTPLUG_CPU
  1000. int __ref smp_rescan_cpus(void)
  1001. {
  1002. struct sclp_core_info *info;
  1003. int nr;
  1004. info = kzalloc(sizeof(*info), GFP_KERNEL);
  1005. if (!info)
  1006. return -ENOMEM;
  1007. smp_get_core_info(info, 0);
  1008. get_online_cpus();
  1009. mutex_lock(&smp_cpu_state_mutex);
  1010. nr = __smp_rescan_cpus(info, 1);
  1011. mutex_unlock(&smp_cpu_state_mutex);
  1012. put_online_cpus();
  1013. kfree(info);
  1014. if (nr)
  1015. topology_schedule_update();
  1016. return 0;
  1017. }
  1018. static ssize_t __ref rescan_store(struct device *dev,
  1019. struct device_attribute *attr,
  1020. const char *buf,
  1021. size_t count)
  1022. {
  1023. int rc;
  1024. rc = smp_rescan_cpus();
  1025. return rc ? rc : count;
  1026. }
  1027. static DEVICE_ATTR(rescan, 0200, NULL, rescan_store);
  1028. #endif /* CONFIG_HOTPLUG_CPU */
  1029. static int __init s390_smp_init(void)
  1030. {
  1031. int cpu, rc = 0;
  1032. #ifdef CONFIG_HOTPLUG_CPU
  1033. rc = device_create_file(cpu_subsys.dev_root, &dev_attr_rescan);
  1034. if (rc)
  1035. return rc;
  1036. #endif
  1037. for_each_present_cpu(cpu) {
  1038. rc = smp_add_present_cpu(cpu);
  1039. if (rc)
  1040. goto out;
  1041. }
  1042. rc = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "s390/smp:online",
  1043. smp_cpu_online, smp_cpu_pre_down);
  1044. out:
  1045. return rc;
  1046. }
  1047. subsys_initcall(s390_smp_init);