amdgpu_sched.c 4.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157
  1. /*
  2. * Copyright 2015 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. *
  23. */
  24. #include <linux/kthread.h>
  25. #include <linux/wait.h>
  26. #include <linux/sched.h>
  27. #include <drm/drmP.h>
  28. #include "amdgpu.h"
  29. static int amdgpu_sched_prepare_job(struct amd_gpu_scheduler *sched,
  30. struct amd_context_entity *c_entity,
  31. void *job)
  32. {
  33. int r = 0;
  34. struct amdgpu_cs_parser *sched_job = (struct amdgpu_cs_parser *)job;
  35. if (sched_job->prepare_job) {
  36. r = sched_job->prepare_job(sched_job);
  37. if (r) {
  38. DRM_ERROR("Prepare job error\n");
  39. schedule_work(&sched_job->job_work);
  40. }
  41. }
  42. return r;
  43. }
  44. static void amdgpu_fence_sched_cb(struct fence *f, struct fence_cb *cb)
  45. {
  46. struct amd_sched_job *sched_job =
  47. container_of(cb, struct amd_sched_job, cb);
  48. amd_sched_process_job(sched_job);
  49. }
  50. static void amdgpu_sched_run_job(struct amd_gpu_scheduler *sched,
  51. struct amd_context_entity *c_entity,
  52. struct amd_sched_job *job)
  53. {
  54. int r = 0;
  55. struct amdgpu_cs_parser *sched_job;
  56. struct amdgpu_fence *fence;
  57. if (!job || !job->job) {
  58. DRM_ERROR("job is null\n");
  59. return;
  60. }
  61. sched_job = (struct amdgpu_cs_parser *)job->job;
  62. mutex_lock(&sched_job->job_lock);
  63. r = amdgpu_ib_schedule(sched_job->adev,
  64. sched_job->num_ibs,
  65. sched_job->ibs,
  66. sched_job->filp);
  67. if (r)
  68. goto err;
  69. fence = sched_job->ibs[sched_job->num_ibs - 1].fence;
  70. if (fence_add_callback(&fence->base,
  71. &job->cb, amdgpu_fence_sched_cb)) {
  72. DRM_ERROR("fence add callback failed\n");
  73. goto err;
  74. }
  75. if (sched_job->run_job) {
  76. r = sched_job->run_job(sched_job);
  77. if (r)
  78. goto err;
  79. }
  80. amd_sched_emit(c_entity, sched_job->ibs[sched_job->num_ibs - 1].sequence);
  81. mutex_unlock(&sched_job->job_lock);
  82. return;
  83. err:
  84. DRM_ERROR("Run job error\n");
  85. mutex_unlock(&sched_job->job_lock);
  86. schedule_work(&sched_job->job_work);
  87. }
  88. static void amdgpu_sched_process_job(struct amd_gpu_scheduler *sched, void *job)
  89. {
  90. struct amdgpu_cs_parser *sched_job = NULL;
  91. struct amdgpu_fence *fence = NULL;
  92. struct amdgpu_ring *ring = NULL;
  93. struct amdgpu_device *adev = NULL;
  94. if (!job)
  95. return;
  96. sched_job = (struct amdgpu_cs_parser *)job;
  97. fence = sched_job->ibs[sched_job->num_ibs - 1].fence;
  98. if (!fence)
  99. return;
  100. ring = fence->ring;
  101. adev = ring->adev;
  102. schedule_work(&sched_job->job_work);
  103. }
  104. struct amd_sched_backend_ops amdgpu_sched_ops = {
  105. .prepare_job = amdgpu_sched_prepare_job,
  106. .run_job = amdgpu_sched_run_job,
  107. .process_job = amdgpu_sched_process_job
  108. };
  109. int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev,
  110. struct amdgpu_ring *ring,
  111. struct amdgpu_ib *ibs,
  112. unsigned num_ibs,
  113. int (*free_job)(struct amdgpu_cs_parser *),
  114. void *owner,
  115. struct fence **f)
  116. {
  117. int r = 0;
  118. if (amdgpu_enable_scheduler) {
  119. uint64_t v_seq;
  120. struct amdgpu_cs_parser *sched_job =
  121. amdgpu_cs_parser_create(adev, owner, &adev->kernel_ctx,
  122. ibs, 1);
  123. if(!sched_job) {
  124. return -ENOMEM;
  125. }
  126. sched_job->free_job = free_job;
  127. v_seq = atomic64_inc_return(&adev->kernel_ctx.rings[ring->idx].c_entity.last_queued_v_seq);
  128. ibs[num_ibs - 1].sequence = v_seq;
  129. amd_sched_push_job(ring->scheduler,
  130. &adev->kernel_ctx.rings[ring->idx].c_entity,
  131. sched_job);
  132. r = amd_sched_wait_emit(
  133. &adev->kernel_ctx.rings[ring->idx].c_entity,
  134. v_seq,
  135. false,
  136. -1);
  137. if (r)
  138. WARN(true, "emit timeout\n");
  139. } else
  140. r = amdgpu_ib_schedule(adev, 1, ibs, owner);
  141. if (r)
  142. return r;
  143. *f = &ibs[num_ibs - 1].fence->base;
  144. return 0;
  145. }