amdgpu_psp.c 14 KB

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  1. /*
  2. * Copyright 2016 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Author: Huang Rui
  23. *
  24. */
  25. #include <linux/firmware.h>
  26. #include <drm/drmP.h>
  27. #include "amdgpu.h"
  28. #include "amdgpu_psp.h"
  29. #include "amdgpu_ucode.h"
  30. #include "soc15_common.h"
  31. #include "psp_v3_1.h"
  32. #include "psp_v10_0.h"
  33. static void psp_set_funcs(struct amdgpu_device *adev);
  34. static int psp_early_init(void *handle)
  35. {
  36. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  37. psp_set_funcs(adev);
  38. return 0;
  39. }
  40. static int psp_sw_init(void *handle)
  41. {
  42. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  43. struct psp_context *psp = &adev->psp;
  44. int ret;
  45. switch (adev->asic_type) {
  46. case CHIP_VEGA10:
  47. psp->init_microcode = psp_v3_1_init_microcode;
  48. psp->bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv;
  49. psp->bootloader_load_sos = psp_v3_1_bootloader_load_sos;
  50. psp->prep_cmd_buf = psp_v3_1_prep_cmd_buf;
  51. psp->ring_init = psp_v3_1_ring_init;
  52. psp->ring_create = psp_v3_1_ring_create;
  53. psp->ring_stop = psp_v3_1_ring_stop;
  54. psp->ring_destroy = psp_v3_1_ring_destroy;
  55. psp->cmd_submit = psp_v3_1_cmd_submit;
  56. psp->compare_sram_data = psp_v3_1_compare_sram_data;
  57. psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk;
  58. psp->mode1_reset = psp_v3_1_mode1_reset;
  59. break;
  60. case CHIP_RAVEN:
  61. psp->init_microcode = psp_v10_0_init_microcode;
  62. psp->prep_cmd_buf = psp_v10_0_prep_cmd_buf;
  63. psp->ring_init = psp_v10_0_ring_init;
  64. psp->ring_create = psp_v10_0_ring_create;
  65. psp->ring_stop = psp_v10_0_ring_stop;
  66. psp->ring_destroy = psp_v10_0_ring_destroy;
  67. psp->cmd_submit = psp_v10_0_cmd_submit;
  68. psp->compare_sram_data = psp_v10_0_compare_sram_data;
  69. psp->mode1_reset = psp_v10_0_mode1_reset;
  70. break;
  71. default:
  72. return -EINVAL;
  73. }
  74. psp->adev = adev;
  75. ret = psp_init_microcode(psp);
  76. if (ret) {
  77. DRM_ERROR("Failed to load psp firmware!\n");
  78. return ret;
  79. }
  80. return 0;
  81. }
  82. static int psp_sw_fini(void *handle)
  83. {
  84. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  85. release_firmware(adev->psp.sos_fw);
  86. adev->psp.sos_fw = NULL;
  87. release_firmware(adev->psp.asd_fw);
  88. adev->psp.asd_fw = NULL;
  89. return 0;
  90. }
  91. int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
  92. uint32_t reg_val, uint32_t mask, bool check_changed)
  93. {
  94. uint32_t val;
  95. int i;
  96. struct amdgpu_device *adev = psp->adev;
  97. for (i = 0; i < adev->usec_timeout; i++) {
  98. val = RREG32(reg_index);
  99. if (check_changed) {
  100. if (val != reg_val)
  101. return 0;
  102. } else {
  103. if ((val & mask) == reg_val)
  104. return 0;
  105. }
  106. udelay(1);
  107. }
  108. return -ETIME;
  109. }
  110. static int
  111. psp_cmd_submit_buf(struct psp_context *psp,
  112. struct amdgpu_firmware_info *ucode,
  113. struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr,
  114. int index)
  115. {
  116. int ret;
  117. memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
  118. memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
  119. ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr,
  120. fence_mc_addr, index);
  121. while (*((unsigned int *)psp->fence_buf) != index) {
  122. msleep(1);
  123. }
  124. return ret;
  125. }
  126. static void psp_prep_tmr_cmd_buf(struct psp_gfx_cmd_resp *cmd,
  127. uint64_t tmr_mc, uint32_t size)
  128. {
  129. cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
  130. cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
  131. cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
  132. cmd->cmd.cmd_setup_tmr.buf_size = size;
  133. }
  134. /* Set up Trusted Memory Region */
  135. static int psp_tmr_init(struct psp_context *psp)
  136. {
  137. int ret;
  138. /*
  139. * Allocate 3M memory aligned to 1M from Frame Buffer (local
  140. * physical).
  141. *
  142. * Note: this memory need be reserved till the driver
  143. * uninitializes.
  144. */
  145. ret = amdgpu_bo_create_kernel(psp->adev, 0x300000, 0x100000,
  146. AMDGPU_GEM_DOMAIN_VRAM,
  147. &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
  148. return ret;
  149. }
  150. static int psp_tmr_load(struct psp_context *psp)
  151. {
  152. int ret;
  153. struct psp_gfx_cmd_resp *cmd;
  154. cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
  155. if (!cmd)
  156. return -ENOMEM;
  157. psp_prep_tmr_cmd_buf(cmd, psp->tmr_mc_addr, 0x300000);
  158. ret = psp_cmd_submit_buf(psp, NULL, cmd,
  159. psp->fence_buf_mc_addr, 1);
  160. if (ret)
  161. goto failed;
  162. kfree(cmd);
  163. return 0;
  164. failed:
  165. kfree(cmd);
  166. return ret;
  167. }
  168. static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
  169. uint64_t asd_mc, uint64_t asd_mc_shared,
  170. uint32_t size, uint32_t shared_size)
  171. {
  172. cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
  173. cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
  174. cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
  175. cmd->cmd.cmd_load_ta.app_len = size;
  176. cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
  177. cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
  178. cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
  179. }
  180. static int psp_asd_init(struct psp_context *psp)
  181. {
  182. int ret;
  183. /*
  184. * Allocate 16k memory aligned to 4k from Frame Buffer (local
  185. * physical) for shared ASD <-> Driver
  186. */
  187. ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE,
  188. PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
  189. &psp->asd_shared_bo,
  190. &psp->asd_shared_mc_addr,
  191. &psp->asd_shared_buf);
  192. return ret;
  193. }
  194. static int psp_asd_load(struct psp_context *psp)
  195. {
  196. int ret;
  197. struct psp_gfx_cmd_resp *cmd;
  198. /* If PSP version doesn't match ASD version, asd loading will be failed.
  199. * add workaround to bypass it for sriov now.
  200. * TODO: add version check to make it common
  201. */
  202. if (amdgpu_sriov_vf(psp->adev))
  203. return 0;
  204. cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
  205. if (!cmd)
  206. return -ENOMEM;
  207. memset(psp->fw_pri_buf, 0, PSP_1_MEG);
  208. memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
  209. psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr,
  210. psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
  211. ret = psp_cmd_submit_buf(psp, NULL, cmd,
  212. psp->fence_buf_mc_addr, 2);
  213. kfree(cmd);
  214. return ret;
  215. }
  216. static int psp_hw_start(struct psp_context *psp)
  217. {
  218. struct amdgpu_device *adev = psp->adev;
  219. int ret;
  220. if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) {
  221. ret = psp_bootloader_load_sysdrv(psp);
  222. if (ret)
  223. return ret;
  224. ret = psp_bootloader_load_sos(psp);
  225. if (ret)
  226. return ret;
  227. }
  228. ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
  229. if (ret)
  230. return ret;
  231. ret = psp_tmr_load(psp);
  232. if (ret)
  233. return ret;
  234. ret = psp_asd_load(psp);
  235. if (ret)
  236. return ret;
  237. return 0;
  238. }
  239. static int psp_np_fw_load(struct psp_context *psp)
  240. {
  241. int i, ret;
  242. struct amdgpu_firmware_info *ucode;
  243. struct amdgpu_device* adev = psp->adev;
  244. for (i = 0; i < adev->firmware.max_ucodes; i++) {
  245. ucode = &adev->firmware.ucode[i];
  246. if (!ucode->fw)
  247. continue;
  248. if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
  249. psp_smu_reload_quirk(psp))
  250. continue;
  251. if (amdgpu_sriov_vf(adev) &&
  252. (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
  253. || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
  254. || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G))
  255. /*skip ucode loading in SRIOV VF */
  256. continue;
  257. ret = psp_prep_cmd_buf(ucode, psp->cmd);
  258. if (ret)
  259. return ret;
  260. ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
  261. psp->fence_buf_mc_addr, i + 3);
  262. if (ret)
  263. return ret;
  264. #if 0
  265. /* check if firmware loaded sucessfully */
  266. if (!amdgpu_psp_check_fw_loading_status(adev, i))
  267. return -EINVAL;
  268. #endif
  269. }
  270. return 0;
  271. }
  272. static int psp_load_fw(struct amdgpu_device *adev)
  273. {
  274. int ret;
  275. struct psp_context *psp = &adev->psp;
  276. if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset != 0)
  277. goto skip_memalloc;
  278. psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
  279. if (!psp->cmd)
  280. return -ENOMEM;
  281. ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
  282. AMDGPU_GEM_DOMAIN_GTT,
  283. &psp->fw_pri_bo,
  284. &psp->fw_pri_mc_addr,
  285. &psp->fw_pri_buf);
  286. if (ret)
  287. goto failed;
  288. ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
  289. AMDGPU_GEM_DOMAIN_VRAM,
  290. &psp->fence_buf_bo,
  291. &psp->fence_buf_mc_addr,
  292. &psp->fence_buf);
  293. if (ret)
  294. goto failed_mem2;
  295. ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
  296. AMDGPU_GEM_DOMAIN_VRAM,
  297. &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
  298. (void **)&psp->cmd_buf_mem);
  299. if (ret)
  300. goto failed_mem1;
  301. memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
  302. ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
  303. if (ret)
  304. goto failed_mem;
  305. ret = psp_tmr_init(psp);
  306. if (ret)
  307. goto failed_mem;
  308. ret = psp_asd_init(psp);
  309. if (ret)
  310. goto failed_mem;
  311. skip_memalloc:
  312. ret = psp_hw_start(psp);
  313. if (ret)
  314. goto failed_mem;
  315. ret = psp_np_fw_load(psp);
  316. if (ret)
  317. goto failed_mem;
  318. return 0;
  319. failed_mem:
  320. amdgpu_bo_free_kernel(&psp->cmd_buf_bo,
  321. &psp->cmd_buf_mc_addr,
  322. (void **)&psp->cmd_buf_mem);
  323. failed_mem1:
  324. amdgpu_bo_free_kernel(&psp->fence_buf_bo,
  325. &psp->fence_buf_mc_addr, &psp->fence_buf);
  326. failed_mem2:
  327. amdgpu_bo_free_kernel(&psp->fw_pri_bo,
  328. &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
  329. failed:
  330. kfree(psp->cmd);
  331. psp->cmd = NULL;
  332. return ret;
  333. }
  334. static int psp_hw_init(void *handle)
  335. {
  336. int ret;
  337. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  338. if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
  339. return 0;
  340. mutex_lock(&adev->firmware.mutex);
  341. /*
  342. * This sequence is just used on hw_init only once, no need on
  343. * resume.
  344. */
  345. ret = amdgpu_ucode_init_bo(adev);
  346. if (ret)
  347. goto failed;
  348. ret = psp_load_fw(adev);
  349. if (ret) {
  350. DRM_ERROR("PSP firmware loading failed\n");
  351. goto failed;
  352. }
  353. mutex_unlock(&adev->firmware.mutex);
  354. return 0;
  355. failed:
  356. adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
  357. mutex_unlock(&adev->firmware.mutex);
  358. return -EINVAL;
  359. }
  360. static int psp_hw_fini(void *handle)
  361. {
  362. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  363. struct psp_context *psp = &adev->psp;
  364. if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
  365. return 0;
  366. amdgpu_ucode_fini_bo(adev);
  367. psp_ring_destroy(psp, PSP_RING_TYPE__KM);
  368. amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
  369. amdgpu_bo_free_kernel(&psp->fw_pri_bo,
  370. &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
  371. amdgpu_bo_free_kernel(&psp->fence_buf_bo,
  372. &psp->fence_buf_mc_addr, &psp->fence_buf);
  373. amdgpu_bo_free_kernel(&psp->asd_shared_bo, &psp->asd_shared_mc_addr,
  374. &psp->asd_shared_buf);
  375. amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
  376. (void **)&psp->cmd_buf_mem);
  377. kfree(psp->cmd);
  378. psp->cmd = NULL;
  379. return 0;
  380. }
  381. static int psp_suspend(void *handle)
  382. {
  383. int ret;
  384. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  385. struct psp_context *psp = &adev->psp;
  386. ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
  387. if (ret) {
  388. DRM_ERROR("PSP ring stop failed\n");
  389. return ret;
  390. }
  391. return 0;
  392. }
  393. static int psp_resume(void *handle)
  394. {
  395. int ret;
  396. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  397. struct psp_context *psp = &adev->psp;
  398. if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
  399. return 0;
  400. DRM_INFO("PSP is resuming...\n");
  401. mutex_lock(&adev->firmware.mutex);
  402. ret = psp_hw_start(psp);
  403. if (ret)
  404. goto failed;
  405. ret = psp_np_fw_load(psp);
  406. if (ret)
  407. goto failed;
  408. mutex_unlock(&adev->firmware.mutex);
  409. return 0;
  410. failed:
  411. DRM_ERROR("PSP resume failed\n");
  412. mutex_unlock(&adev->firmware.mutex);
  413. return ret;
  414. }
  415. static bool psp_check_reset(void* handle)
  416. {
  417. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  418. if (adev->flags & AMD_IS_APU)
  419. return true;
  420. return false;
  421. }
  422. static int psp_reset(void* handle)
  423. {
  424. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  425. return psp_mode1_reset(&adev->psp);
  426. }
  427. static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
  428. enum AMDGPU_UCODE_ID ucode_type)
  429. {
  430. struct amdgpu_firmware_info *ucode = NULL;
  431. if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
  432. DRM_INFO("firmware is not loaded by PSP\n");
  433. return true;
  434. }
  435. if (!adev->firmware.fw_size)
  436. return false;
  437. ucode = &adev->firmware.ucode[ucode_type];
  438. if (!ucode->fw || !ucode->ucode_size)
  439. return false;
  440. return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
  441. }
  442. static int psp_set_clockgating_state(void *handle,
  443. enum amd_clockgating_state state)
  444. {
  445. return 0;
  446. }
  447. static int psp_set_powergating_state(void *handle,
  448. enum amd_powergating_state state)
  449. {
  450. return 0;
  451. }
  452. const struct amd_ip_funcs psp_ip_funcs = {
  453. .name = "psp",
  454. .early_init = psp_early_init,
  455. .late_init = NULL,
  456. .sw_init = psp_sw_init,
  457. .sw_fini = psp_sw_fini,
  458. .hw_init = psp_hw_init,
  459. .hw_fini = psp_hw_fini,
  460. .suspend = psp_suspend,
  461. .resume = psp_resume,
  462. .is_idle = NULL,
  463. .check_soft_reset = psp_check_reset,
  464. .wait_for_idle = NULL,
  465. .soft_reset = psp_reset,
  466. .set_clockgating_state = psp_set_clockgating_state,
  467. .set_powergating_state = psp_set_powergating_state,
  468. };
  469. static const struct amdgpu_psp_funcs psp_funcs = {
  470. .check_fw_loading_status = psp_check_fw_loading_status,
  471. };
  472. static void psp_set_funcs(struct amdgpu_device *adev)
  473. {
  474. if (NULL == adev->firmware.funcs)
  475. adev->firmware.funcs = &psp_funcs;
  476. }
  477. const struct amdgpu_ip_block_version psp_v3_1_ip_block =
  478. {
  479. .type = AMD_IP_BLOCK_TYPE_PSP,
  480. .major = 3,
  481. .minor = 1,
  482. .rev = 0,
  483. .funcs = &psp_ip_funcs,
  484. };
  485. const struct amdgpu_ip_block_version psp_v10_0_ip_block =
  486. {
  487. .type = AMD_IP_BLOCK_TYPE_PSP,
  488. .major = 10,
  489. .minor = 0,
  490. .rev = 0,
  491. .funcs = &psp_ip_funcs,
  492. };