chip.c 36 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452
  1. /*
  2. * linux/kernel/irq/chip.c
  3. *
  4. * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
  5. * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
  6. *
  7. * This file contains the core interrupt handling code, for irq-chip
  8. * based architectures.
  9. *
  10. * Detailed information is available in Documentation/core-api/genericirq.rst
  11. */
  12. #include <linux/irq.h>
  13. #include <linux/msi.h>
  14. #include <linux/module.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/kernel_stat.h>
  17. #include <linux/irqdomain.h>
  18. #include <trace/events/irq.h>
  19. #include "internals.h"
  20. static irqreturn_t bad_chained_irq(int irq, void *dev_id)
  21. {
  22. WARN_ONCE(1, "Chained irq %d should not call an action\n", irq);
  23. return IRQ_NONE;
  24. }
  25. /*
  26. * Chained handlers should never call action on their IRQ. This default
  27. * action will emit warning if such thing happens.
  28. */
  29. struct irqaction chained_action = {
  30. .handler = bad_chained_irq,
  31. };
  32. /**
  33. * irq_set_chip - set the irq chip for an irq
  34. * @irq: irq number
  35. * @chip: pointer to irq chip description structure
  36. */
  37. int irq_set_chip(unsigned int irq, struct irq_chip *chip)
  38. {
  39. unsigned long flags;
  40. struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
  41. if (!desc)
  42. return -EINVAL;
  43. if (!chip)
  44. chip = &no_irq_chip;
  45. desc->irq_data.chip = chip;
  46. irq_put_desc_unlock(desc, flags);
  47. /*
  48. * For !CONFIG_SPARSE_IRQ make the irq show up in
  49. * allocated_irqs.
  50. */
  51. irq_mark_irq(irq);
  52. return 0;
  53. }
  54. EXPORT_SYMBOL(irq_set_chip);
  55. /**
  56. * irq_set_type - set the irq trigger type for an irq
  57. * @irq: irq number
  58. * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
  59. */
  60. int irq_set_irq_type(unsigned int irq, unsigned int type)
  61. {
  62. unsigned long flags;
  63. struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
  64. int ret = 0;
  65. if (!desc)
  66. return -EINVAL;
  67. ret = __irq_set_trigger(desc, type);
  68. irq_put_desc_busunlock(desc, flags);
  69. return ret;
  70. }
  71. EXPORT_SYMBOL(irq_set_irq_type);
  72. /**
  73. * irq_set_handler_data - set irq handler data for an irq
  74. * @irq: Interrupt number
  75. * @data: Pointer to interrupt specific data
  76. *
  77. * Set the hardware irq controller data for an irq
  78. */
  79. int irq_set_handler_data(unsigned int irq, void *data)
  80. {
  81. unsigned long flags;
  82. struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
  83. if (!desc)
  84. return -EINVAL;
  85. desc->irq_common_data.handler_data = data;
  86. irq_put_desc_unlock(desc, flags);
  87. return 0;
  88. }
  89. EXPORT_SYMBOL(irq_set_handler_data);
  90. /**
  91. * irq_set_msi_desc_off - set MSI descriptor data for an irq at offset
  92. * @irq_base: Interrupt number base
  93. * @irq_offset: Interrupt number offset
  94. * @entry: Pointer to MSI descriptor data
  95. *
  96. * Set the MSI descriptor entry for an irq at offset
  97. */
  98. int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
  99. struct msi_desc *entry)
  100. {
  101. unsigned long flags;
  102. struct irq_desc *desc = irq_get_desc_lock(irq_base + irq_offset, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
  103. if (!desc)
  104. return -EINVAL;
  105. desc->irq_common_data.msi_desc = entry;
  106. if (entry && !irq_offset)
  107. entry->irq = irq_base;
  108. irq_put_desc_unlock(desc, flags);
  109. return 0;
  110. }
  111. /**
  112. * irq_set_msi_desc - set MSI descriptor data for an irq
  113. * @irq: Interrupt number
  114. * @entry: Pointer to MSI descriptor data
  115. *
  116. * Set the MSI descriptor entry for an irq
  117. */
  118. int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry)
  119. {
  120. return irq_set_msi_desc_off(irq, 0, entry);
  121. }
  122. /**
  123. * irq_set_chip_data - set irq chip data for an irq
  124. * @irq: Interrupt number
  125. * @data: Pointer to chip specific data
  126. *
  127. * Set the hardware irq chip data for an irq
  128. */
  129. int irq_set_chip_data(unsigned int irq, void *data)
  130. {
  131. unsigned long flags;
  132. struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
  133. if (!desc)
  134. return -EINVAL;
  135. desc->irq_data.chip_data = data;
  136. irq_put_desc_unlock(desc, flags);
  137. return 0;
  138. }
  139. EXPORT_SYMBOL(irq_set_chip_data);
  140. struct irq_data *irq_get_irq_data(unsigned int irq)
  141. {
  142. struct irq_desc *desc = irq_to_desc(irq);
  143. return desc ? &desc->irq_data : NULL;
  144. }
  145. EXPORT_SYMBOL_GPL(irq_get_irq_data);
  146. static void irq_state_clr_disabled(struct irq_desc *desc)
  147. {
  148. irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED);
  149. }
  150. static void irq_state_clr_masked(struct irq_desc *desc)
  151. {
  152. irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED);
  153. }
  154. static void irq_state_clr_started(struct irq_desc *desc)
  155. {
  156. irqd_clear(&desc->irq_data, IRQD_IRQ_STARTED);
  157. }
  158. static void irq_state_set_started(struct irq_desc *desc)
  159. {
  160. irqd_set(&desc->irq_data, IRQD_IRQ_STARTED);
  161. }
  162. enum {
  163. IRQ_STARTUP_NORMAL,
  164. IRQ_STARTUP_MANAGED,
  165. IRQ_STARTUP_ABORT,
  166. };
  167. #ifdef CONFIG_SMP
  168. static int
  169. __irq_startup_managed(struct irq_desc *desc, struct cpumask *aff, bool force)
  170. {
  171. struct irq_data *d = irq_desc_get_irq_data(desc);
  172. if (!irqd_affinity_is_managed(d))
  173. return IRQ_STARTUP_NORMAL;
  174. irqd_clr_managed_shutdown(d);
  175. if (cpumask_any_and(aff, cpu_online_mask) >= nr_cpu_ids) {
  176. /*
  177. * Catch code which fiddles with enable_irq() on a managed
  178. * and potentially shutdown IRQ. Chained interrupt
  179. * installment or irq auto probing should not happen on
  180. * managed irqs either.
  181. */
  182. if (WARN_ON_ONCE(force))
  183. return IRQ_STARTUP_ABORT;
  184. /*
  185. * The interrupt was requested, but there is no online CPU
  186. * in it's affinity mask. Put it into managed shutdown
  187. * state and let the cpu hotplug mechanism start it up once
  188. * a CPU in the mask becomes available.
  189. */
  190. return IRQ_STARTUP_ABORT;
  191. }
  192. /*
  193. * Managed interrupts have reserved resources, so this should not
  194. * happen.
  195. */
  196. if (WARN_ON(irq_domain_activate_irq(d, false)))
  197. return IRQ_STARTUP_ABORT;
  198. return IRQ_STARTUP_MANAGED;
  199. }
  200. #else
  201. static __always_inline int
  202. __irq_startup_managed(struct irq_desc *desc, struct cpumask *aff, bool force)
  203. {
  204. return IRQ_STARTUP_NORMAL;
  205. }
  206. #endif
  207. static int __irq_startup(struct irq_desc *desc)
  208. {
  209. struct irq_data *d = irq_desc_get_irq_data(desc);
  210. int ret = 0;
  211. /* Warn if this interrupt is not activated but try nevertheless */
  212. WARN_ON_ONCE(!irqd_is_activated(d));
  213. if (d->chip->irq_startup) {
  214. ret = d->chip->irq_startup(d);
  215. irq_state_clr_disabled(desc);
  216. irq_state_clr_masked(desc);
  217. } else {
  218. irq_enable(desc);
  219. }
  220. irq_state_set_started(desc);
  221. return ret;
  222. }
  223. int irq_startup(struct irq_desc *desc, bool resend, bool force)
  224. {
  225. struct irq_data *d = irq_desc_get_irq_data(desc);
  226. struct cpumask *aff = irq_data_get_affinity_mask(d);
  227. int ret = 0;
  228. desc->depth = 0;
  229. if (irqd_is_started(d)) {
  230. irq_enable(desc);
  231. } else {
  232. switch (__irq_startup_managed(desc, aff, force)) {
  233. case IRQ_STARTUP_NORMAL:
  234. ret = __irq_startup(desc);
  235. irq_setup_affinity(desc);
  236. break;
  237. case IRQ_STARTUP_MANAGED:
  238. irq_do_set_affinity(d, aff, false);
  239. ret = __irq_startup(desc);
  240. break;
  241. case IRQ_STARTUP_ABORT:
  242. irqd_set_managed_shutdown(d);
  243. return 0;
  244. }
  245. }
  246. if (resend)
  247. check_irq_resend(desc);
  248. return ret;
  249. }
  250. int irq_activate(struct irq_desc *desc)
  251. {
  252. struct irq_data *d = irq_desc_get_irq_data(desc);
  253. if (!irqd_affinity_is_managed(d))
  254. return irq_domain_activate_irq(d, false);
  255. return 0;
  256. }
  257. void irq_activate_and_startup(struct irq_desc *desc, bool resend)
  258. {
  259. if (WARN_ON(irq_activate(desc)))
  260. return;
  261. irq_startup(desc, resend, IRQ_START_FORCE);
  262. }
  263. static void __irq_disable(struct irq_desc *desc, bool mask);
  264. void irq_shutdown(struct irq_desc *desc)
  265. {
  266. if (irqd_is_started(&desc->irq_data)) {
  267. desc->depth = 1;
  268. if (desc->irq_data.chip->irq_shutdown) {
  269. desc->irq_data.chip->irq_shutdown(&desc->irq_data);
  270. irq_state_set_disabled(desc);
  271. irq_state_set_masked(desc);
  272. } else {
  273. __irq_disable(desc, true);
  274. }
  275. irq_state_clr_started(desc);
  276. }
  277. /*
  278. * This must be called even if the interrupt was never started up,
  279. * because the activation can happen before the interrupt is
  280. * available for request/startup. It has it's own state tracking so
  281. * it's safe to call it unconditionally.
  282. */
  283. irq_domain_deactivate_irq(&desc->irq_data);
  284. }
  285. void irq_enable(struct irq_desc *desc)
  286. {
  287. if (!irqd_irq_disabled(&desc->irq_data)) {
  288. unmask_irq(desc);
  289. } else {
  290. irq_state_clr_disabled(desc);
  291. if (desc->irq_data.chip->irq_enable) {
  292. desc->irq_data.chip->irq_enable(&desc->irq_data);
  293. irq_state_clr_masked(desc);
  294. } else {
  295. unmask_irq(desc);
  296. }
  297. }
  298. }
  299. static void __irq_disable(struct irq_desc *desc, bool mask)
  300. {
  301. if (irqd_irq_disabled(&desc->irq_data)) {
  302. if (mask)
  303. mask_irq(desc);
  304. } else {
  305. irq_state_set_disabled(desc);
  306. if (desc->irq_data.chip->irq_disable) {
  307. desc->irq_data.chip->irq_disable(&desc->irq_data);
  308. irq_state_set_masked(desc);
  309. } else if (mask) {
  310. mask_irq(desc);
  311. }
  312. }
  313. }
  314. /**
  315. * irq_disable - Mark interrupt disabled
  316. * @desc: irq descriptor which should be disabled
  317. *
  318. * If the chip does not implement the irq_disable callback, we
  319. * use a lazy disable approach. That means we mark the interrupt
  320. * disabled, but leave the hardware unmasked. That's an
  321. * optimization because we avoid the hardware access for the
  322. * common case where no interrupt happens after we marked it
  323. * disabled. If an interrupt happens, then the interrupt flow
  324. * handler masks the line at the hardware level and marks it
  325. * pending.
  326. *
  327. * If the interrupt chip does not implement the irq_disable callback,
  328. * a driver can disable the lazy approach for a particular irq line by
  329. * calling 'irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY)'. This can
  330. * be used for devices which cannot disable the interrupt at the
  331. * device level under certain circumstances and have to use
  332. * disable_irq[_nosync] instead.
  333. */
  334. void irq_disable(struct irq_desc *desc)
  335. {
  336. __irq_disable(desc, irq_settings_disable_unlazy(desc));
  337. }
  338. void irq_percpu_enable(struct irq_desc *desc, unsigned int cpu)
  339. {
  340. if (desc->irq_data.chip->irq_enable)
  341. desc->irq_data.chip->irq_enable(&desc->irq_data);
  342. else
  343. desc->irq_data.chip->irq_unmask(&desc->irq_data);
  344. cpumask_set_cpu(cpu, desc->percpu_enabled);
  345. }
  346. void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu)
  347. {
  348. if (desc->irq_data.chip->irq_disable)
  349. desc->irq_data.chip->irq_disable(&desc->irq_data);
  350. else
  351. desc->irq_data.chip->irq_mask(&desc->irq_data);
  352. cpumask_clear_cpu(cpu, desc->percpu_enabled);
  353. }
  354. static inline void mask_ack_irq(struct irq_desc *desc)
  355. {
  356. if (desc->irq_data.chip->irq_mask_ack) {
  357. desc->irq_data.chip->irq_mask_ack(&desc->irq_data);
  358. irq_state_set_masked(desc);
  359. } else {
  360. mask_irq(desc);
  361. if (desc->irq_data.chip->irq_ack)
  362. desc->irq_data.chip->irq_ack(&desc->irq_data);
  363. }
  364. }
  365. void mask_irq(struct irq_desc *desc)
  366. {
  367. if (irqd_irq_masked(&desc->irq_data))
  368. return;
  369. if (desc->irq_data.chip->irq_mask) {
  370. desc->irq_data.chip->irq_mask(&desc->irq_data);
  371. irq_state_set_masked(desc);
  372. }
  373. }
  374. void unmask_irq(struct irq_desc *desc)
  375. {
  376. if (!irqd_irq_masked(&desc->irq_data))
  377. return;
  378. if (desc->irq_data.chip->irq_unmask) {
  379. desc->irq_data.chip->irq_unmask(&desc->irq_data);
  380. irq_state_clr_masked(desc);
  381. }
  382. }
  383. void unmask_threaded_irq(struct irq_desc *desc)
  384. {
  385. struct irq_chip *chip = desc->irq_data.chip;
  386. if (chip->flags & IRQCHIP_EOI_THREADED)
  387. chip->irq_eoi(&desc->irq_data);
  388. unmask_irq(desc);
  389. }
  390. /*
  391. * handle_nested_irq - Handle a nested irq from a irq thread
  392. * @irq: the interrupt number
  393. *
  394. * Handle interrupts which are nested into a threaded interrupt
  395. * handler. The handler function is called inside the calling
  396. * threads context.
  397. */
  398. void handle_nested_irq(unsigned int irq)
  399. {
  400. struct irq_desc *desc = irq_to_desc(irq);
  401. struct irqaction *action;
  402. irqreturn_t action_ret;
  403. might_sleep();
  404. raw_spin_lock_irq(&desc->lock);
  405. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  406. action = desc->action;
  407. if (unlikely(!action || irqd_irq_disabled(&desc->irq_data))) {
  408. desc->istate |= IRQS_PENDING;
  409. goto out_unlock;
  410. }
  411. kstat_incr_irqs_this_cpu(desc);
  412. irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS);
  413. raw_spin_unlock_irq(&desc->lock);
  414. action_ret = IRQ_NONE;
  415. for_each_action_of_desc(desc, action)
  416. action_ret |= action->thread_fn(action->irq, action->dev_id);
  417. if (!noirqdebug)
  418. note_interrupt(desc, action_ret);
  419. raw_spin_lock_irq(&desc->lock);
  420. irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
  421. out_unlock:
  422. raw_spin_unlock_irq(&desc->lock);
  423. }
  424. EXPORT_SYMBOL_GPL(handle_nested_irq);
  425. static bool irq_check_poll(struct irq_desc *desc)
  426. {
  427. if (!(desc->istate & IRQS_POLL_INPROGRESS))
  428. return false;
  429. return irq_wait_for_poll(desc);
  430. }
  431. static bool irq_may_run(struct irq_desc *desc)
  432. {
  433. unsigned int mask = IRQD_IRQ_INPROGRESS | IRQD_WAKEUP_ARMED;
  434. /*
  435. * If the interrupt is not in progress and is not an armed
  436. * wakeup interrupt, proceed.
  437. */
  438. if (!irqd_has_set(&desc->irq_data, mask))
  439. return true;
  440. /*
  441. * If the interrupt is an armed wakeup source, mark it pending
  442. * and suspended, disable it and notify the pm core about the
  443. * event.
  444. */
  445. if (irq_pm_check_wakeup(desc))
  446. return false;
  447. /*
  448. * Handle a potential concurrent poll on a different core.
  449. */
  450. return irq_check_poll(desc);
  451. }
  452. /**
  453. * handle_simple_irq - Simple and software-decoded IRQs.
  454. * @desc: the interrupt description structure for this irq
  455. *
  456. * Simple interrupts are either sent from a demultiplexing interrupt
  457. * handler or come from hardware, where no interrupt hardware control
  458. * is necessary.
  459. *
  460. * Note: The caller is expected to handle the ack, clear, mask and
  461. * unmask issues if necessary.
  462. */
  463. void handle_simple_irq(struct irq_desc *desc)
  464. {
  465. raw_spin_lock(&desc->lock);
  466. if (!irq_may_run(desc))
  467. goto out_unlock;
  468. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  469. if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
  470. desc->istate |= IRQS_PENDING;
  471. goto out_unlock;
  472. }
  473. kstat_incr_irqs_this_cpu(desc);
  474. handle_irq_event(desc);
  475. out_unlock:
  476. raw_spin_unlock(&desc->lock);
  477. }
  478. EXPORT_SYMBOL_GPL(handle_simple_irq);
  479. /**
  480. * handle_untracked_irq - Simple and software-decoded IRQs.
  481. * @desc: the interrupt description structure for this irq
  482. *
  483. * Untracked interrupts are sent from a demultiplexing interrupt
  484. * handler when the demultiplexer does not know which device it its
  485. * multiplexed irq domain generated the interrupt. IRQ's handled
  486. * through here are not subjected to stats tracking, randomness, or
  487. * spurious interrupt detection.
  488. *
  489. * Note: Like handle_simple_irq, the caller is expected to handle
  490. * the ack, clear, mask and unmask issues if necessary.
  491. */
  492. void handle_untracked_irq(struct irq_desc *desc)
  493. {
  494. unsigned int flags = 0;
  495. raw_spin_lock(&desc->lock);
  496. if (!irq_may_run(desc))
  497. goto out_unlock;
  498. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  499. if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
  500. desc->istate |= IRQS_PENDING;
  501. goto out_unlock;
  502. }
  503. desc->istate &= ~IRQS_PENDING;
  504. irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS);
  505. raw_spin_unlock(&desc->lock);
  506. __handle_irq_event_percpu(desc, &flags);
  507. raw_spin_lock(&desc->lock);
  508. irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
  509. out_unlock:
  510. raw_spin_unlock(&desc->lock);
  511. }
  512. EXPORT_SYMBOL_GPL(handle_untracked_irq);
  513. /*
  514. * Called unconditionally from handle_level_irq() and only for oneshot
  515. * interrupts from handle_fasteoi_irq()
  516. */
  517. static void cond_unmask_irq(struct irq_desc *desc)
  518. {
  519. /*
  520. * We need to unmask in the following cases:
  521. * - Standard level irq (IRQF_ONESHOT is not set)
  522. * - Oneshot irq which did not wake the thread (caused by a
  523. * spurious interrupt or a primary handler handling it
  524. * completely).
  525. */
  526. if (!irqd_irq_disabled(&desc->irq_data) &&
  527. irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot)
  528. unmask_irq(desc);
  529. }
  530. /**
  531. * handle_level_irq - Level type irq handler
  532. * @desc: the interrupt description structure for this irq
  533. *
  534. * Level type interrupts are active as long as the hardware line has
  535. * the active level. This may require to mask the interrupt and unmask
  536. * it after the associated handler has acknowledged the device, so the
  537. * interrupt line is back to inactive.
  538. */
  539. void handle_level_irq(struct irq_desc *desc)
  540. {
  541. raw_spin_lock(&desc->lock);
  542. mask_ack_irq(desc);
  543. if (!irq_may_run(desc))
  544. goto out_unlock;
  545. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  546. /*
  547. * If its disabled or no action available
  548. * keep it masked and get out of here
  549. */
  550. if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
  551. desc->istate |= IRQS_PENDING;
  552. goto out_unlock;
  553. }
  554. kstat_incr_irqs_this_cpu(desc);
  555. handle_irq_event(desc);
  556. cond_unmask_irq(desc);
  557. out_unlock:
  558. raw_spin_unlock(&desc->lock);
  559. }
  560. EXPORT_SYMBOL_GPL(handle_level_irq);
  561. #ifdef CONFIG_IRQ_PREFLOW_FASTEOI
  562. static inline void preflow_handler(struct irq_desc *desc)
  563. {
  564. if (desc->preflow_handler)
  565. desc->preflow_handler(&desc->irq_data);
  566. }
  567. #else
  568. static inline void preflow_handler(struct irq_desc *desc) { }
  569. #endif
  570. static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip)
  571. {
  572. if (!(desc->istate & IRQS_ONESHOT)) {
  573. chip->irq_eoi(&desc->irq_data);
  574. return;
  575. }
  576. /*
  577. * We need to unmask in the following cases:
  578. * - Oneshot irq which did not wake the thread (caused by a
  579. * spurious interrupt or a primary handler handling it
  580. * completely).
  581. */
  582. if (!irqd_irq_disabled(&desc->irq_data) &&
  583. irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) {
  584. chip->irq_eoi(&desc->irq_data);
  585. unmask_irq(desc);
  586. } else if (!(chip->flags & IRQCHIP_EOI_THREADED)) {
  587. chip->irq_eoi(&desc->irq_data);
  588. }
  589. }
  590. /**
  591. * handle_fasteoi_irq - irq handler for transparent controllers
  592. * @desc: the interrupt description structure for this irq
  593. *
  594. * Only a single callback will be issued to the chip: an ->eoi()
  595. * call when the interrupt has been serviced. This enables support
  596. * for modern forms of interrupt handlers, which handle the flow
  597. * details in hardware, transparently.
  598. */
  599. void handle_fasteoi_irq(struct irq_desc *desc)
  600. {
  601. struct irq_chip *chip = desc->irq_data.chip;
  602. raw_spin_lock(&desc->lock);
  603. if (!irq_may_run(desc))
  604. goto out;
  605. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  606. /*
  607. * If its disabled or no action available
  608. * then mask it and get out of here:
  609. */
  610. if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
  611. desc->istate |= IRQS_PENDING;
  612. mask_irq(desc);
  613. goto out;
  614. }
  615. kstat_incr_irqs_this_cpu(desc);
  616. if (desc->istate & IRQS_ONESHOT)
  617. mask_irq(desc);
  618. preflow_handler(desc);
  619. handle_irq_event(desc);
  620. cond_unmask_eoi_irq(desc, chip);
  621. raw_spin_unlock(&desc->lock);
  622. return;
  623. out:
  624. if (!(chip->flags & IRQCHIP_EOI_IF_HANDLED))
  625. chip->irq_eoi(&desc->irq_data);
  626. raw_spin_unlock(&desc->lock);
  627. }
  628. EXPORT_SYMBOL_GPL(handle_fasteoi_irq);
  629. /**
  630. * handle_edge_irq - edge type IRQ handler
  631. * @desc: the interrupt description structure for this irq
  632. *
  633. * Interrupt occures on the falling and/or rising edge of a hardware
  634. * signal. The occurrence is latched into the irq controller hardware
  635. * and must be acked in order to be reenabled. After the ack another
  636. * interrupt can happen on the same source even before the first one
  637. * is handled by the associated event handler. If this happens it
  638. * might be necessary to disable (mask) the interrupt depending on the
  639. * controller hardware. This requires to reenable the interrupt inside
  640. * of the loop which handles the interrupts which have arrived while
  641. * the handler was running. If all pending interrupts are handled, the
  642. * loop is left.
  643. */
  644. void handle_edge_irq(struct irq_desc *desc)
  645. {
  646. raw_spin_lock(&desc->lock);
  647. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  648. if (!irq_may_run(desc)) {
  649. desc->istate |= IRQS_PENDING;
  650. mask_ack_irq(desc);
  651. goto out_unlock;
  652. }
  653. /*
  654. * If its disabled or no action available then mask it and get
  655. * out of here.
  656. */
  657. if (irqd_irq_disabled(&desc->irq_data) || !desc->action) {
  658. desc->istate |= IRQS_PENDING;
  659. mask_ack_irq(desc);
  660. goto out_unlock;
  661. }
  662. kstat_incr_irqs_this_cpu(desc);
  663. /* Start handling the irq */
  664. desc->irq_data.chip->irq_ack(&desc->irq_data);
  665. do {
  666. if (unlikely(!desc->action)) {
  667. mask_irq(desc);
  668. goto out_unlock;
  669. }
  670. /*
  671. * When another irq arrived while we were handling
  672. * one, we could have masked the irq.
  673. * Renable it, if it was not disabled in meantime.
  674. */
  675. if (unlikely(desc->istate & IRQS_PENDING)) {
  676. if (!irqd_irq_disabled(&desc->irq_data) &&
  677. irqd_irq_masked(&desc->irq_data))
  678. unmask_irq(desc);
  679. }
  680. handle_irq_event(desc);
  681. } while ((desc->istate & IRQS_PENDING) &&
  682. !irqd_irq_disabled(&desc->irq_data));
  683. out_unlock:
  684. raw_spin_unlock(&desc->lock);
  685. }
  686. EXPORT_SYMBOL(handle_edge_irq);
  687. #ifdef CONFIG_IRQ_EDGE_EOI_HANDLER
  688. /**
  689. * handle_edge_eoi_irq - edge eoi type IRQ handler
  690. * @desc: the interrupt description structure for this irq
  691. *
  692. * Similar as the above handle_edge_irq, but using eoi and w/o the
  693. * mask/unmask logic.
  694. */
  695. void handle_edge_eoi_irq(struct irq_desc *desc)
  696. {
  697. struct irq_chip *chip = irq_desc_get_chip(desc);
  698. raw_spin_lock(&desc->lock);
  699. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  700. if (!irq_may_run(desc)) {
  701. desc->istate |= IRQS_PENDING;
  702. goto out_eoi;
  703. }
  704. /*
  705. * If its disabled or no action available then mask it and get
  706. * out of here.
  707. */
  708. if (irqd_irq_disabled(&desc->irq_data) || !desc->action) {
  709. desc->istate |= IRQS_PENDING;
  710. goto out_eoi;
  711. }
  712. kstat_incr_irqs_this_cpu(desc);
  713. do {
  714. if (unlikely(!desc->action))
  715. goto out_eoi;
  716. handle_irq_event(desc);
  717. } while ((desc->istate & IRQS_PENDING) &&
  718. !irqd_irq_disabled(&desc->irq_data));
  719. out_eoi:
  720. chip->irq_eoi(&desc->irq_data);
  721. raw_spin_unlock(&desc->lock);
  722. }
  723. #endif
  724. /**
  725. * handle_percpu_irq - Per CPU local irq handler
  726. * @desc: the interrupt description structure for this irq
  727. *
  728. * Per CPU interrupts on SMP machines without locking requirements
  729. */
  730. void handle_percpu_irq(struct irq_desc *desc)
  731. {
  732. struct irq_chip *chip = irq_desc_get_chip(desc);
  733. kstat_incr_irqs_this_cpu(desc);
  734. if (chip->irq_ack)
  735. chip->irq_ack(&desc->irq_data);
  736. handle_irq_event_percpu(desc);
  737. if (chip->irq_eoi)
  738. chip->irq_eoi(&desc->irq_data);
  739. }
  740. /**
  741. * handle_percpu_devid_irq - Per CPU local irq handler with per cpu dev ids
  742. * @desc: the interrupt description structure for this irq
  743. *
  744. * Per CPU interrupts on SMP machines without locking requirements. Same as
  745. * handle_percpu_irq() above but with the following extras:
  746. *
  747. * action->percpu_dev_id is a pointer to percpu variables which
  748. * contain the real device id for the cpu on which this handler is
  749. * called
  750. */
  751. void handle_percpu_devid_irq(struct irq_desc *desc)
  752. {
  753. struct irq_chip *chip = irq_desc_get_chip(desc);
  754. struct irqaction *action = desc->action;
  755. unsigned int irq = irq_desc_get_irq(desc);
  756. irqreturn_t res;
  757. kstat_incr_irqs_this_cpu(desc);
  758. if (chip->irq_ack)
  759. chip->irq_ack(&desc->irq_data);
  760. if (likely(action)) {
  761. trace_irq_handler_entry(irq, action);
  762. res = action->handler(irq, raw_cpu_ptr(action->percpu_dev_id));
  763. trace_irq_handler_exit(irq, action, res);
  764. } else {
  765. unsigned int cpu = smp_processor_id();
  766. bool enabled = cpumask_test_cpu(cpu, desc->percpu_enabled);
  767. if (enabled)
  768. irq_percpu_disable(desc, cpu);
  769. pr_err_once("Spurious%s percpu IRQ%u on CPU%u\n",
  770. enabled ? " and unmasked" : "", irq, cpu);
  771. }
  772. if (chip->irq_eoi)
  773. chip->irq_eoi(&desc->irq_data);
  774. }
  775. static void
  776. __irq_do_set_handler(struct irq_desc *desc, irq_flow_handler_t handle,
  777. int is_chained, const char *name)
  778. {
  779. if (!handle) {
  780. handle = handle_bad_irq;
  781. } else {
  782. struct irq_data *irq_data = &desc->irq_data;
  783. #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
  784. /*
  785. * With hierarchical domains we might run into a
  786. * situation where the outermost chip is not yet set
  787. * up, but the inner chips are there. Instead of
  788. * bailing we install the handler, but obviously we
  789. * cannot enable/startup the interrupt at this point.
  790. */
  791. while (irq_data) {
  792. if (irq_data->chip != &no_irq_chip)
  793. break;
  794. /*
  795. * Bail out if the outer chip is not set up
  796. * and the interrrupt supposed to be started
  797. * right away.
  798. */
  799. if (WARN_ON(is_chained))
  800. return;
  801. /* Try the parent */
  802. irq_data = irq_data->parent_data;
  803. }
  804. #endif
  805. if (WARN_ON(!irq_data || irq_data->chip == &no_irq_chip))
  806. return;
  807. }
  808. /* Uninstall? */
  809. if (handle == handle_bad_irq) {
  810. if (desc->irq_data.chip != &no_irq_chip)
  811. mask_ack_irq(desc);
  812. irq_state_set_disabled(desc);
  813. if (is_chained)
  814. desc->action = NULL;
  815. desc->depth = 1;
  816. }
  817. desc->handle_irq = handle;
  818. desc->name = name;
  819. if (handle != handle_bad_irq && is_chained) {
  820. unsigned int type = irqd_get_trigger_type(&desc->irq_data);
  821. /*
  822. * We're about to start this interrupt immediately,
  823. * hence the need to set the trigger configuration.
  824. * But the .set_type callback may have overridden the
  825. * flow handler, ignoring that we're dealing with a
  826. * chained interrupt. Reset it immediately because we
  827. * do know better.
  828. */
  829. if (type != IRQ_TYPE_NONE) {
  830. __irq_set_trigger(desc, type);
  831. desc->handle_irq = handle;
  832. }
  833. irq_settings_set_noprobe(desc);
  834. irq_settings_set_norequest(desc);
  835. irq_settings_set_nothread(desc);
  836. desc->action = &chained_action;
  837. irq_activate_and_startup(desc, IRQ_RESEND);
  838. }
  839. }
  840. void
  841. __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
  842. const char *name)
  843. {
  844. unsigned long flags;
  845. struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0);
  846. if (!desc)
  847. return;
  848. __irq_do_set_handler(desc, handle, is_chained, name);
  849. irq_put_desc_busunlock(desc, flags);
  850. }
  851. EXPORT_SYMBOL_GPL(__irq_set_handler);
  852. void
  853. irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle,
  854. void *data)
  855. {
  856. unsigned long flags;
  857. struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0);
  858. if (!desc)
  859. return;
  860. desc->irq_common_data.handler_data = data;
  861. __irq_do_set_handler(desc, handle, 1, NULL);
  862. irq_put_desc_busunlock(desc, flags);
  863. }
  864. EXPORT_SYMBOL_GPL(irq_set_chained_handler_and_data);
  865. void
  866. irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
  867. irq_flow_handler_t handle, const char *name)
  868. {
  869. irq_set_chip(irq, chip);
  870. __irq_set_handler(irq, handle, 0, name);
  871. }
  872. EXPORT_SYMBOL_GPL(irq_set_chip_and_handler_name);
  873. void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set)
  874. {
  875. unsigned long flags, trigger, tmp;
  876. struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
  877. if (!desc)
  878. return;
  879. /*
  880. * Warn when a driver sets the no autoenable flag on an already
  881. * active interrupt.
  882. */
  883. WARN_ON_ONCE(!desc->depth && (set & _IRQ_NOAUTOEN));
  884. irq_settings_clr_and_set(desc, clr, set);
  885. trigger = irqd_get_trigger_type(&desc->irq_data);
  886. irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU |
  887. IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT);
  888. if (irq_settings_has_no_balance_set(desc))
  889. irqd_set(&desc->irq_data, IRQD_NO_BALANCING);
  890. if (irq_settings_is_per_cpu(desc))
  891. irqd_set(&desc->irq_data, IRQD_PER_CPU);
  892. if (irq_settings_can_move_pcntxt(desc))
  893. irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT);
  894. if (irq_settings_is_level(desc))
  895. irqd_set(&desc->irq_data, IRQD_LEVEL);
  896. tmp = irq_settings_get_trigger_mask(desc);
  897. if (tmp != IRQ_TYPE_NONE)
  898. trigger = tmp;
  899. irqd_set(&desc->irq_data, trigger);
  900. irq_put_desc_unlock(desc, flags);
  901. }
  902. EXPORT_SYMBOL_GPL(irq_modify_status);
  903. /**
  904. * irq_cpu_online - Invoke all irq_cpu_online functions.
  905. *
  906. * Iterate through all irqs and invoke the chip.irq_cpu_online()
  907. * for each.
  908. */
  909. void irq_cpu_online(void)
  910. {
  911. struct irq_desc *desc;
  912. struct irq_chip *chip;
  913. unsigned long flags;
  914. unsigned int irq;
  915. for_each_active_irq(irq) {
  916. desc = irq_to_desc(irq);
  917. if (!desc)
  918. continue;
  919. raw_spin_lock_irqsave(&desc->lock, flags);
  920. chip = irq_data_get_irq_chip(&desc->irq_data);
  921. if (chip && chip->irq_cpu_online &&
  922. (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
  923. !irqd_irq_disabled(&desc->irq_data)))
  924. chip->irq_cpu_online(&desc->irq_data);
  925. raw_spin_unlock_irqrestore(&desc->lock, flags);
  926. }
  927. }
  928. /**
  929. * irq_cpu_offline - Invoke all irq_cpu_offline functions.
  930. *
  931. * Iterate through all irqs and invoke the chip.irq_cpu_offline()
  932. * for each.
  933. */
  934. void irq_cpu_offline(void)
  935. {
  936. struct irq_desc *desc;
  937. struct irq_chip *chip;
  938. unsigned long flags;
  939. unsigned int irq;
  940. for_each_active_irq(irq) {
  941. desc = irq_to_desc(irq);
  942. if (!desc)
  943. continue;
  944. raw_spin_lock_irqsave(&desc->lock, flags);
  945. chip = irq_data_get_irq_chip(&desc->irq_data);
  946. if (chip && chip->irq_cpu_offline &&
  947. (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
  948. !irqd_irq_disabled(&desc->irq_data)))
  949. chip->irq_cpu_offline(&desc->irq_data);
  950. raw_spin_unlock_irqrestore(&desc->lock, flags);
  951. }
  952. }
  953. #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
  954. #ifdef CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS
  955. /**
  956. * handle_fasteoi_ack_irq - irq handler for edge hierarchy
  957. * stacked on transparent controllers
  958. *
  959. * @desc: the interrupt description structure for this irq
  960. *
  961. * Like handle_fasteoi_irq(), but for use with hierarchy where
  962. * the irq_chip also needs to have its ->irq_ack() function
  963. * called.
  964. */
  965. void handle_fasteoi_ack_irq(struct irq_desc *desc)
  966. {
  967. struct irq_chip *chip = desc->irq_data.chip;
  968. raw_spin_lock(&desc->lock);
  969. if (!irq_may_run(desc))
  970. goto out;
  971. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  972. /*
  973. * If its disabled or no action available
  974. * then mask it and get out of here:
  975. */
  976. if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
  977. desc->istate |= IRQS_PENDING;
  978. mask_irq(desc);
  979. goto out;
  980. }
  981. kstat_incr_irqs_this_cpu(desc);
  982. if (desc->istate & IRQS_ONESHOT)
  983. mask_irq(desc);
  984. /* Start handling the irq */
  985. desc->irq_data.chip->irq_ack(&desc->irq_data);
  986. preflow_handler(desc);
  987. handle_irq_event(desc);
  988. cond_unmask_eoi_irq(desc, chip);
  989. raw_spin_unlock(&desc->lock);
  990. return;
  991. out:
  992. if (!(chip->flags & IRQCHIP_EOI_IF_HANDLED))
  993. chip->irq_eoi(&desc->irq_data);
  994. raw_spin_unlock(&desc->lock);
  995. }
  996. EXPORT_SYMBOL_GPL(handle_fasteoi_ack_irq);
  997. /**
  998. * handle_fasteoi_mask_irq - irq handler for level hierarchy
  999. * stacked on transparent controllers
  1000. *
  1001. * @desc: the interrupt description structure for this irq
  1002. *
  1003. * Like handle_fasteoi_irq(), but for use with hierarchy where
  1004. * the irq_chip also needs to have its ->irq_mask_ack() function
  1005. * called.
  1006. */
  1007. void handle_fasteoi_mask_irq(struct irq_desc *desc)
  1008. {
  1009. struct irq_chip *chip = desc->irq_data.chip;
  1010. raw_spin_lock(&desc->lock);
  1011. mask_ack_irq(desc);
  1012. if (!irq_may_run(desc))
  1013. goto out;
  1014. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  1015. /*
  1016. * If its disabled or no action available
  1017. * then mask it and get out of here:
  1018. */
  1019. if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
  1020. desc->istate |= IRQS_PENDING;
  1021. mask_irq(desc);
  1022. goto out;
  1023. }
  1024. kstat_incr_irqs_this_cpu(desc);
  1025. if (desc->istate & IRQS_ONESHOT)
  1026. mask_irq(desc);
  1027. preflow_handler(desc);
  1028. handle_irq_event(desc);
  1029. cond_unmask_eoi_irq(desc, chip);
  1030. raw_spin_unlock(&desc->lock);
  1031. return;
  1032. out:
  1033. if (!(chip->flags & IRQCHIP_EOI_IF_HANDLED))
  1034. chip->irq_eoi(&desc->irq_data);
  1035. raw_spin_unlock(&desc->lock);
  1036. }
  1037. EXPORT_SYMBOL_GPL(handle_fasteoi_mask_irq);
  1038. #endif /* CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS */
  1039. /**
  1040. * irq_chip_enable_parent - Enable the parent interrupt (defaults to unmask if
  1041. * NULL)
  1042. * @data: Pointer to interrupt specific data
  1043. */
  1044. void irq_chip_enable_parent(struct irq_data *data)
  1045. {
  1046. data = data->parent_data;
  1047. if (data->chip->irq_enable)
  1048. data->chip->irq_enable(data);
  1049. else
  1050. data->chip->irq_unmask(data);
  1051. }
  1052. EXPORT_SYMBOL_GPL(irq_chip_enable_parent);
  1053. /**
  1054. * irq_chip_disable_parent - Disable the parent interrupt (defaults to mask if
  1055. * NULL)
  1056. * @data: Pointer to interrupt specific data
  1057. */
  1058. void irq_chip_disable_parent(struct irq_data *data)
  1059. {
  1060. data = data->parent_data;
  1061. if (data->chip->irq_disable)
  1062. data->chip->irq_disable(data);
  1063. else
  1064. data->chip->irq_mask(data);
  1065. }
  1066. EXPORT_SYMBOL_GPL(irq_chip_disable_parent);
  1067. /**
  1068. * irq_chip_ack_parent - Acknowledge the parent interrupt
  1069. * @data: Pointer to interrupt specific data
  1070. */
  1071. void irq_chip_ack_parent(struct irq_data *data)
  1072. {
  1073. data = data->parent_data;
  1074. data->chip->irq_ack(data);
  1075. }
  1076. EXPORT_SYMBOL_GPL(irq_chip_ack_parent);
  1077. /**
  1078. * irq_chip_mask_parent - Mask the parent interrupt
  1079. * @data: Pointer to interrupt specific data
  1080. */
  1081. void irq_chip_mask_parent(struct irq_data *data)
  1082. {
  1083. data = data->parent_data;
  1084. data->chip->irq_mask(data);
  1085. }
  1086. EXPORT_SYMBOL_GPL(irq_chip_mask_parent);
  1087. /**
  1088. * irq_chip_unmask_parent - Unmask the parent interrupt
  1089. * @data: Pointer to interrupt specific data
  1090. */
  1091. void irq_chip_unmask_parent(struct irq_data *data)
  1092. {
  1093. data = data->parent_data;
  1094. data->chip->irq_unmask(data);
  1095. }
  1096. EXPORT_SYMBOL_GPL(irq_chip_unmask_parent);
  1097. /**
  1098. * irq_chip_eoi_parent - Invoke EOI on the parent interrupt
  1099. * @data: Pointer to interrupt specific data
  1100. */
  1101. void irq_chip_eoi_parent(struct irq_data *data)
  1102. {
  1103. data = data->parent_data;
  1104. data->chip->irq_eoi(data);
  1105. }
  1106. EXPORT_SYMBOL_GPL(irq_chip_eoi_parent);
  1107. /**
  1108. * irq_chip_set_affinity_parent - Set affinity on the parent interrupt
  1109. * @data: Pointer to interrupt specific data
  1110. * @dest: The affinity mask to set
  1111. * @force: Flag to enforce setting (disable online checks)
  1112. *
  1113. * Conditinal, as the underlying parent chip might not implement it.
  1114. */
  1115. int irq_chip_set_affinity_parent(struct irq_data *data,
  1116. const struct cpumask *dest, bool force)
  1117. {
  1118. data = data->parent_data;
  1119. if (data->chip->irq_set_affinity)
  1120. return data->chip->irq_set_affinity(data, dest, force);
  1121. return -ENOSYS;
  1122. }
  1123. EXPORT_SYMBOL_GPL(irq_chip_set_affinity_parent);
  1124. /**
  1125. * irq_chip_set_type_parent - Set IRQ type on the parent interrupt
  1126. * @data: Pointer to interrupt specific data
  1127. * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
  1128. *
  1129. * Conditional, as the underlying parent chip might not implement it.
  1130. */
  1131. int irq_chip_set_type_parent(struct irq_data *data, unsigned int type)
  1132. {
  1133. data = data->parent_data;
  1134. if (data->chip->irq_set_type)
  1135. return data->chip->irq_set_type(data, type);
  1136. return -ENOSYS;
  1137. }
  1138. EXPORT_SYMBOL_GPL(irq_chip_set_type_parent);
  1139. /**
  1140. * irq_chip_retrigger_hierarchy - Retrigger an interrupt in hardware
  1141. * @data: Pointer to interrupt specific data
  1142. *
  1143. * Iterate through the domain hierarchy of the interrupt and check
  1144. * whether a hw retrigger function exists. If yes, invoke it.
  1145. */
  1146. int irq_chip_retrigger_hierarchy(struct irq_data *data)
  1147. {
  1148. for (data = data->parent_data; data; data = data->parent_data)
  1149. if (data->chip && data->chip->irq_retrigger)
  1150. return data->chip->irq_retrigger(data);
  1151. return 0;
  1152. }
  1153. /**
  1154. * irq_chip_set_vcpu_affinity_parent - Set vcpu affinity on the parent interrupt
  1155. * @data: Pointer to interrupt specific data
  1156. * @vcpu_info: The vcpu affinity information
  1157. */
  1158. int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, void *vcpu_info)
  1159. {
  1160. data = data->parent_data;
  1161. if (data->chip->irq_set_vcpu_affinity)
  1162. return data->chip->irq_set_vcpu_affinity(data, vcpu_info);
  1163. return -ENOSYS;
  1164. }
  1165. /**
  1166. * irq_chip_set_wake_parent - Set/reset wake-up on the parent interrupt
  1167. * @data: Pointer to interrupt specific data
  1168. * @on: Whether to set or reset the wake-up capability of this irq
  1169. *
  1170. * Conditional, as the underlying parent chip might not implement it.
  1171. */
  1172. int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on)
  1173. {
  1174. data = data->parent_data;
  1175. if (data->chip->irq_set_wake)
  1176. return data->chip->irq_set_wake(data, on);
  1177. return -ENOSYS;
  1178. }
  1179. #endif
  1180. /**
  1181. * irq_chip_compose_msi_msg - Componse msi message for a irq chip
  1182. * @data: Pointer to interrupt specific data
  1183. * @msg: Pointer to the MSI message
  1184. *
  1185. * For hierarchical domains we find the first chip in the hierarchy
  1186. * which implements the irq_compose_msi_msg callback. For non
  1187. * hierarchical we use the top level chip.
  1188. */
  1189. int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
  1190. {
  1191. struct irq_data *pos = NULL;
  1192. #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
  1193. for (; data; data = data->parent_data)
  1194. #endif
  1195. if (data->chip && data->chip->irq_compose_msi_msg)
  1196. pos = data;
  1197. if (!pos)
  1198. return -ENOSYS;
  1199. pos->chip->irq_compose_msi_msg(pos, msg);
  1200. return 0;
  1201. }
  1202. /**
  1203. * irq_chip_pm_get - Enable power for an IRQ chip
  1204. * @data: Pointer to interrupt specific data
  1205. *
  1206. * Enable the power to the IRQ chip referenced by the interrupt data
  1207. * structure.
  1208. */
  1209. int irq_chip_pm_get(struct irq_data *data)
  1210. {
  1211. int retval;
  1212. if (IS_ENABLED(CONFIG_PM) && data->chip->parent_device) {
  1213. retval = pm_runtime_get_sync(data->chip->parent_device);
  1214. if (retval < 0) {
  1215. pm_runtime_put_noidle(data->chip->parent_device);
  1216. return retval;
  1217. }
  1218. }
  1219. return 0;
  1220. }
  1221. /**
  1222. * irq_chip_pm_put - Disable power for an IRQ chip
  1223. * @data: Pointer to interrupt specific data
  1224. *
  1225. * Disable the power to the IRQ chip referenced by the interrupt data
  1226. * structure, belongs. Note that power will only be disabled, once this
  1227. * function has been called for all IRQs that have called irq_chip_pm_get().
  1228. */
  1229. int irq_chip_pm_put(struct irq_data *data)
  1230. {
  1231. int retval = 0;
  1232. if (IS_ENABLED(CONFIG_PM) && data->chip->parent_device)
  1233. retval = pm_runtime_put(data->chip->parent_device);
  1234. return (retval < 0) ? retval : 0;
  1235. }