arch_timer.c 14 KB

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  1. /*
  2. * Copyright (C) 2012 ARM Ltd.
  3. * Author: Marc Zyngier <marc.zyngier@arm.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  17. */
  18. #include <linux/cpu.h>
  19. #include <linux/kvm.h>
  20. #include <linux/kvm_host.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/irq.h>
  23. #include <clocksource/arm_arch_timer.h>
  24. #include <asm/arch_timer.h>
  25. #include <asm/kvm_hyp.h>
  26. #include <kvm/arm_vgic.h>
  27. #include <kvm/arm_arch_timer.h>
  28. #include "trace.h"
  29. static struct timecounter *timecounter;
  30. static unsigned int host_vtimer_irq;
  31. static u32 host_vtimer_irq_flags;
  32. void kvm_timer_vcpu_put(struct kvm_vcpu *vcpu)
  33. {
  34. vcpu->arch.timer_cpu.active_cleared_last = false;
  35. }
  36. static u64 kvm_phys_timer_read(void)
  37. {
  38. return timecounter->cc->read(timecounter->cc);
  39. }
  40. static bool timer_is_armed(struct arch_timer_cpu *timer)
  41. {
  42. return timer->armed;
  43. }
  44. /* timer_arm: as in "arm the timer", not as in ARM the company */
  45. static void timer_arm(struct arch_timer_cpu *timer, u64 ns)
  46. {
  47. timer->armed = true;
  48. hrtimer_start(&timer->timer, ktime_add_ns(ktime_get(), ns),
  49. HRTIMER_MODE_ABS);
  50. }
  51. static void timer_disarm(struct arch_timer_cpu *timer)
  52. {
  53. if (timer_is_armed(timer)) {
  54. hrtimer_cancel(&timer->timer);
  55. cancel_work_sync(&timer->expired);
  56. timer->armed = false;
  57. }
  58. }
  59. static irqreturn_t kvm_arch_timer_handler(int irq, void *dev_id)
  60. {
  61. struct kvm_vcpu *vcpu = *(struct kvm_vcpu **)dev_id;
  62. /*
  63. * We disable the timer in the world switch and let it be
  64. * handled by kvm_timer_sync_hwstate(). Getting a timer
  65. * interrupt at this point is a sure sign of some major
  66. * breakage.
  67. */
  68. pr_warn("Unexpected interrupt %d on vcpu %p\n", irq, vcpu);
  69. return IRQ_HANDLED;
  70. }
  71. /*
  72. * Work function for handling the backup timer that we schedule when a vcpu is
  73. * no longer running, but had a timer programmed to fire in the future.
  74. */
  75. static void kvm_timer_inject_irq_work(struct work_struct *work)
  76. {
  77. struct kvm_vcpu *vcpu;
  78. vcpu = container_of(work, struct kvm_vcpu, arch.timer_cpu.expired);
  79. /*
  80. * If the vcpu is blocked we want to wake it up so that it will see
  81. * the timer has expired when entering the guest.
  82. */
  83. kvm_vcpu_kick(vcpu);
  84. }
  85. static u64 kvm_timer_compute_delta(struct kvm_vcpu *vcpu)
  86. {
  87. u64 cval, now;
  88. cval = vcpu->arch.timer_cpu.cntv_cval;
  89. now = kvm_phys_timer_read() - vcpu->kvm->arch.timer.cntvoff;
  90. if (now < cval) {
  91. u64 ns;
  92. ns = cyclecounter_cyc2ns(timecounter->cc,
  93. cval - now,
  94. timecounter->mask,
  95. &timecounter->frac);
  96. return ns;
  97. }
  98. return 0;
  99. }
  100. static enum hrtimer_restart kvm_timer_expire(struct hrtimer *hrt)
  101. {
  102. struct arch_timer_cpu *timer;
  103. struct kvm_vcpu *vcpu;
  104. u64 ns;
  105. timer = container_of(hrt, struct arch_timer_cpu, timer);
  106. vcpu = container_of(timer, struct kvm_vcpu, arch.timer_cpu);
  107. /*
  108. * Check that the timer has really expired from the guest's
  109. * PoV (NTP on the host may have forced it to expire
  110. * early). If we should have slept longer, restart it.
  111. */
  112. ns = kvm_timer_compute_delta(vcpu);
  113. if (unlikely(ns)) {
  114. hrtimer_forward_now(hrt, ns_to_ktime(ns));
  115. return HRTIMER_RESTART;
  116. }
  117. schedule_work(&timer->expired);
  118. return HRTIMER_NORESTART;
  119. }
  120. static bool kvm_timer_irq_can_fire(struct kvm_vcpu *vcpu)
  121. {
  122. struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
  123. return !(timer->cntv_ctl & ARCH_TIMER_CTRL_IT_MASK) &&
  124. (timer->cntv_ctl & ARCH_TIMER_CTRL_ENABLE);
  125. }
  126. bool kvm_timer_should_fire(struct kvm_vcpu *vcpu)
  127. {
  128. struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
  129. u64 cval, now;
  130. if (!kvm_timer_irq_can_fire(vcpu))
  131. return false;
  132. cval = timer->cntv_cval;
  133. now = kvm_phys_timer_read() - vcpu->kvm->arch.timer.cntvoff;
  134. return cval <= now;
  135. }
  136. static void kvm_timer_update_irq(struct kvm_vcpu *vcpu, bool new_level)
  137. {
  138. int ret;
  139. struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
  140. BUG_ON(!vgic_initialized(vcpu->kvm));
  141. timer->active_cleared_last = false;
  142. timer->irq.level = new_level;
  143. trace_kvm_timer_update_irq(vcpu->vcpu_id, timer->irq.irq,
  144. timer->irq.level);
  145. ret = kvm_vgic_inject_mapped_irq(vcpu->kvm, vcpu->vcpu_id,
  146. timer->irq.irq,
  147. timer->irq.level);
  148. WARN_ON(ret);
  149. }
  150. /*
  151. * Check if there was a change in the timer state (should we raise or lower
  152. * the line level to the GIC).
  153. */
  154. static int kvm_timer_update_state(struct kvm_vcpu *vcpu)
  155. {
  156. struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
  157. /*
  158. * If userspace modified the timer registers via SET_ONE_REG before
  159. * the vgic was initialized, we mustn't set the timer->irq.level value
  160. * because the guest would never see the interrupt. Instead wait
  161. * until we call this function from kvm_timer_flush_hwstate.
  162. */
  163. if (!vgic_initialized(vcpu->kvm) || !timer->enabled)
  164. return -ENODEV;
  165. if (kvm_timer_should_fire(vcpu) != timer->irq.level)
  166. kvm_timer_update_irq(vcpu, !timer->irq.level);
  167. return 0;
  168. }
  169. /*
  170. * Schedule the background timer before calling kvm_vcpu_block, so that this
  171. * thread is removed from its waitqueue and made runnable when there's a timer
  172. * interrupt to handle.
  173. */
  174. void kvm_timer_schedule(struct kvm_vcpu *vcpu)
  175. {
  176. struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
  177. BUG_ON(timer_is_armed(timer));
  178. /*
  179. * No need to schedule a background timer if the guest timer has
  180. * already expired, because kvm_vcpu_block will return before putting
  181. * the thread to sleep.
  182. */
  183. if (kvm_timer_should_fire(vcpu))
  184. return;
  185. /*
  186. * If the timer is not capable of raising interrupts (disabled or
  187. * masked), then there's no more work for us to do.
  188. */
  189. if (!kvm_timer_irq_can_fire(vcpu))
  190. return;
  191. /* The timer has not yet expired, schedule a background timer */
  192. timer_arm(timer, kvm_timer_compute_delta(vcpu));
  193. }
  194. void kvm_timer_unschedule(struct kvm_vcpu *vcpu)
  195. {
  196. struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
  197. timer_disarm(timer);
  198. }
  199. /**
  200. * kvm_timer_flush_hwstate - prepare to move the virt timer to the cpu
  201. * @vcpu: The vcpu pointer
  202. *
  203. * Check if the virtual timer has expired while we were running in the host,
  204. * and inject an interrupt if that was the case.
  205. */
  206. void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu)
  207. {
  208. struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
  209. bool phys_active;
  210. int ret;
  211. if (kvm_timer_update_state(vcpu))
  212. return;
  213. /*
  214. * If we enter the guest with the virtual input level to the VGIC
  215. * asserted, then we have already told the VGIC what we need to, and
  216. * we don't need to exit from the guest until the guest deactivates
  217. * the already injected interrupt, so therefore we should set the
  218. * hardware active state to prevent unnecessary exits from the guest.
  219. *
  220. * Also, if we enter the guest with the virtual timer interrupt active,
  221. * then it must be active on the physical distributor, because we set
  222. * the HW bit and the guest must be able to deactivate the virtual and
  223. * physical interrupt at the same time.
  224. *
  225. * Conversely, if the virtual input level is deasserted and the virtual
  226. * interrupt is not active, then always clear the hardware active state
  227. * to ensure that hardware interrupts from the timer triggers a guest
  228. * exit.
  229. */
  230. phys_active = timer->irq.level ||
  231. kvm_vgic_map_is_active(vcpu, timer->irq.irq);
  232. /*
  233. * We want to avoid hitting the (re)distributor as much as
  234. * possible, as this is a potentially expensive MMIO access
  235. * (not to mention locks in the irq layer), and a solution for
  236. * this is to cache the "active" state in memory.
  237. *
  238. * Things to consider: we cannot cache an "active set" state,
  239. * because the HW can change this behind our back (it becomes
  240. * "clear" in the HW). We must then restrict the caching to
  241. * the "clear" state.
  242. *
  243. * The cache is invalidated on:
  244. * - vcpu put, indicating that the HW cannot be trusted to be
  245. * in a sane state on the next vcpu load,
  246. * - any change in the interrupt state
  247. *
  248. * Usage conditions:
  249. * - cached value is "active clear"
  250. * - value to be programmed is "active clear"
  251. */
  252. if (timer->active_cleared_last && !phys_active)
  253. return;
  254. ret = irq_set_irqchip_state(host_vtimer_irq,
  255. IRQCHIP_STATE_ACTIVE,
  256. phys_active);
  257. WARN_ON(ret);
  258. timer->active_cleared_last = !phys_active;
  259. }
  260. /**
  261. * kvm_timer_sync_hwstate - sync timer state from cpu
  262. * @vcpu: The vcpu pointer
  263. *
  264. * Check if the virtual timer has expired while we were running in the guest,
  265. * and inject an interrupt if that was the case.
  266. */
  267. void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu)
  268. {
  269. struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
  270. BUG_ON(timer_is_armed(timer));
  271. /*
  272. * The guest could have modified the timer registers or the timer
  273. * could have expired, update the timer state.
  274. */
  275. kvm_timer_update_state(vcpu);
  276. }
  277. int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu,
  278. const struct kvm_irq_level *irq)
  279. {
  280. struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
  281. /*
  282. * The vcpu timer irq number cannot be determined in
  283. * kvm_timer_vcpu_init() because it is called much before
  284. * kvm_vcpu_set_target(). To handle this, we determine
  285. * vcpu timer irq number when the vcpu is reset.
  286. */
  287. timer->irq.irq = irq->irq;
  288. /*
  289. * The bits in CNTV_CTL are architecturally reset to UNKNOWN for ARMv8
  290. * and to 0 for ARMv7. We provide an implementation that always
  291. * resets the timer to be disabled and unmasked and is compliant with
  292. * the ARMv7 architecture.
  293. */
  294. timer->cntv_ctl = 0;
  295. kvm_timer_update_state(vcpu);
  296. return 0;
  297. }
  298. void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu)
  299. {
  300. struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
  301. INIT_WORK(&timer->expired, kvm_timer_inject_irq_work);
  302. hrtimer_init(&timer->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
  303. timer->timer.function = kvm_timer_expire;
  304. }
  305. static void kvm_timer_init_interrupt(void *info)
  306. {
  307. enable_percpu_irq(host_vtimer_irq, host_vtimer_irq_flags);
  308. }
  309. int kvm_arm_timer_set_reg(struct kvm_vcpu *vcpu, u64 regid, u64 value)
  310. {
  311. struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
  312. switch (regid) {
  313. case KVM_REG_ARM_TIMER_CTL:
  314. timer->cntv_ctl = value;
  315. break;
  316. case KVM_REG_ARM_TIMER_CNT:
  317. vcpu->kvm->arch.timer.cntvoff = kvm_phys_timer_read() - value;
  318. break;
  319. case KVM_REG_ARM_TIMER_CVAL:
  320. timer->cntv_cval = value;
  321. break;
  322. default:
  323. return -1;
  324. }
  325. kvm_timer_update_state(vcpu);
  326. return 0;
  327. }
  328. u64 kvm_arm_timer_get_reg(struct kvm_vcpu *vcpu, u64 regid)
  329. {
  330. struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
  331. switch (regid) {
  332. case KVM_REG_ARM_TIMER_CTL:
  333. return timer->cntv_ctl;
  334. case KVM_REG_ARM_TIMER_CNT:
  335. return kvm_phys_timer_read() - vcpu->kvm->arch.timer.cntvoff;
  336. case KVM_REG_ARM_TIMER_CVAL:
  337. return timer->cntv_cval;
  338. }
  339. return (u64)-1;
  340. }
  341. static int kvm_timer_starting_cpu(unsigned int cpu)
  342. {
  343. kvm_timer_init_interrupt(NULL);
  344. return 0;
  345. }
  346. static int kvm_timer_dying_cpu(unsigned int cpu)
  347. {
  348. disable_percpu_irq(host_vtimer_irq);
  349. return 0;
  350. }
  351. int kvm_timer_hyp_init(void)
  352. {
  353. struct arch_timer_kvm_info *info;
  354. int err;
  355. info = arch_timer_get_kvm_info();
  356. timecounter = &info->timecounter;
  357. if (!timecounter->cc) {
  358. kvm_err("kvm_arch_timer: uninitialized timecounter\n");
  359. return -ENODEV;
  360. }
  361. if (info->virtual_irq <= 0) {
  362. kvm_err("kvm_arch_timer: invalid virtual timer IRQ: %d\n",
  363. info->virtual_irq);
  364. return -ENODEV;
  365. }
  366. host_vtimer_irq = info->virtual_irq;
  367. host_vtimer_irq_flags = irq_get_trigger_type(host_vtimer_irq);
  368. if (host_vtimer_irq_flags != IRQF_TRIGGER_HIGH &&
  369. host_vtimer_irq_flags != IRQF_TRIGGER_LOW) {
  370. kvm_err("Invalid trigger for IRQ%d, assuming level low\n",
  371. host_vtimer_irq);
  372. host_vtimer_irq_flags = IRQF_TRIGGER_LOW;
  373. }
  374. err = request_percpu_irq(host_vtimer_irq, kvm_arch_timer_handler,
  375. "kvm guest timer", kvm_get_running_vcpus());
  376. if (err) {
  377. kvm_err("kvm_arch_timer: can't request interrupt %d (%d)\n",
  378. host_vtimer_irq, err);
  379. return err;
  380. }
  381. kvm_info("virtual timer IRQ%d\n", host_vtimer_irq);
  382. cpuhp_setup_state(CPUHP_AP_KVM_ARM_TIMER_STARTING,
  383. "kvm/arm/timer:starting", kvm_timer_starting_cpu,
  384. kvm_timer_dying_cpu);
  385. return err;
  386. }
  387. void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu)
  388. {
  389. struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
  390. timer_disarm(timer);
  391. kvm_vgic_unmap_phys_irq(vcpu, timer->irq.irq);
  392. }
  393. int kvm_timer_enable(struct kvm_vcpu *vcpu)
  394. {
  395. struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
  396. struct irq_desc *desc;
  397. struct irq_data *data;
  398. int phys_irq;
  399. int ret;
  400. if (timer->enabled)
  401. return 0;
  402. /*
  403. * Find the physical IRQ number corresponding to the host_vtimer_irq
  404. */
  405. desc = irq_to_desc(host_vtimer_irq);
  406. if (!desc) {
  407. kvm_err("%s: no interrupt descriptor\n", __func__);
  408. return -EINVAL;
  409. }
  410. data = irq_desc_get_irq_data(desc);
  411. while (data->parent_data)
  412. data = data->parent_data;
  413. phys_irq = data->hwirq;
  414. /*
  415. * Tell the VGIC that the virtual interrupt is tied to a
  416. * physical interrupt. We do that once per VCPU.
  417. */
  418. ret = kvm_vgic_map_phys_irq(vcpu, timer->irq.irq, phys_irq);
  419. if (ret)
  420. return ret;
  421. timer->enabled = 1;
  422. return 0;
  423. }
  424. void kvm_timer_init(struct kvm *kvm)
  425. {
  426. kvm->arch.timer.cntvoff = kvm_phys_timer_read();
  427. }
  428. /*
  429. * On VHE system, we only need to configure trap on physical timer and counter
  430. * accesses in EL0 and EL1 once, not for every world switch.
  431. * The host kernel runs at EL2 with HCR_EL2.TGE == 1,
  432. * and this makes those bits have no effect for the host kernel execution.
  433. */
  434. void kvm_timer_init_vhe(void)
  435. {
  436. /* When HCR_EL2.E2H ==1, EL1PCEN and EL1PCTEN are shifted by 10 */
  437. u32 cnthctl_shift = 10;
  438. u64 val;
  439. /*
  440. * Disallow physical timer access for the guest.
  441. * Physical counter access is allowed.
  442. */
  443. val = read_sysreg(cnthctl_el2);
  444. val &= ~(CNTHCTL_EL1PCEN << cnthctl_shift);
  445. val |= (CNTHCTL_EL1PCTEN << cnthctl_shift);
  446. write_sysreg(val, cnthctl_el2);
  447. }