smc_wr.c 18 KB

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  1. /*
  2. * Shared Memory Communications over RDMA (SMC-R) and RoCE
  3. *
  4. * Work Requests exploiting Infiniband API
  5. *
  6. * Work requests (WR) of type ib_post_send or ib_post_recv respectively
  7. * are submitted to either RC SQ or RC RQ respectively
  8. * (reliably connected send/receive queue)
  9. * and become work queue entries (WQEs).
  10. * While an SQ WR/WQE is pending, we track it until transmission completion.
  11. * Through a send or receive completion queue (CQ) respectively,
  12. * we get completion queue entries (CQEs) [aka work completions (WCs)].
  13. * Since the CQ callback is called from IRQ context, we split work by using
  14. * bottom halves implemented by tasklets.
  15. *
  16. * SMC uses this to exchange LLC (link layer control)
  17. * and CDC (connection data control) messages.
  18. *
  19. * Copyright IBM Corp. 2016
  20. *
  21. * Author(s): Steffen Maier <maier@linux.vnet.ibm.com>
  22. */
  23. #include <linux/atomic.h>
  24. #include <linux/hashtable.h>
  25. #include <linux/wait.h>
  26. #include <rdma/ib_verbs.h>
  27. #include <asm/div64.h>
  28. #include "smc.h"
  29. #include "smc_wr.h"
  30. #define SMC_WR_MAX_POLL_CQE 10 /* max. # of compl. queue elements in 1 poll */
  31. #define SMC_WR_RX_HASH_BITS 4
  32. static DEFINE_HASHTABLE(smc_wr_rx_hash, SMC_WR_RX_HASH_BITS);
  33. static DEFINE_SPINLOCK(smc_wr_rx_hash_lock);
  34. struct smc_wr_tx_pend { /* control data for a pending send request */
  35. u64 wr_id; /* work request id sent */
  36. smc_wr_tx_handler handler;
  37. enum ib_wc_status wc_status; /* CQE status */
  38. struct smc_link *link;
  39. u32 idx;
  40. struct smc_wr_tx_pend_priv priv;
  41. };
  42. /******************************** send queue *********************************/
  43. /*------------------------------- completion --------------------------------*/
  44. static inline int smc_wr_tx_find_pending_index(struct smc_link *link, u64 wr_id)
  45. {
  46. u32 i;
  47. for (i = 0; i < link->wr_tx_cnt; i++) {
  48. if (link->wr_tx_pends[i].wr_id == wr_id)
  49. return i;
  50. }
  51. return link->wr_tx_cnt;
  52. }
  53. static inline void smc_wr_tx_process_cqe(struct ib_wc *wc)
  54. {
  55. struct smc_wr_tx_pend pnd_snd;
  56. struct smc_link *link;
  57. u32 pnd_snd_idx;
  58. int i;
  59. link = wc->qp->qp_context;
  60. if (wc->opcode == IB_WC_REG_MR) {
  61. if (wc->status)
  62. link->wr_reg_state = FAILED;
  63. else
  64. link->wr_reg_state = CONFIRMED;
  65. wake_up(&link->wr_reg_wait);
  66. return;
  67. }
  68. pnd_snd_idx = smc_wr_tx_find_pending_index(link, wc->wr_id);
  69. if (pnd_snd_idx == link->wr_tx_cnt)
  70. return;
  71. link->wr_tx_pends[pnd_snd_idx].wc_status = wc->status;
  72. memcpy(&pnd_snd, &link->wr_tx_pends[pnd_snd_idx], sizeof(pnd_snd));
  73. /* clear the full struct smc_wr_tx_pend including .priv */
  74. memset(&link->wr_tx_pends[pnd_snd_idx], 0,
  75. sizeof(link->wr_tx_pends[pnd_snd_idx]));
  76. memset(&link->wr_tx_bufs[pnd_snd_idx], 0,
  77. sizeof(link->wr_tx_bufs[pnd_snd_idx]));
  78. if (!test_and_clear_bit(pnd_snd_idx, link->wr_tx_mask))
  79. return;
  80. if (wc->status) {
  81. struct smc_link_group *lgr;
  82. for_each_set_bit(i, link->wr_tx_mask, link->wr_tx_cnt) {
  83. /* clear full struct smc_wr_tx_pend including .priv */
  84. memset(&link->wr_tx_pends[i], 0,
  85. sizeof(link->wr_tx_pends[i]));
  86. memset(&link->wr_tx_bufs[i], 0,
  87. sizeof(link->wr_tx_bufs[i]));
  88. clear_bit(i, link->wr_tx_mask);
  89. }
  90. /* terminate connections of this link group abnormally */
  91. lgr = container_of(link, struct smc_link_group,
  92. lnk[SMC_SINGLE_LINK]);
  93. smc_lgr_terminate(lgr);
  94. }
  95. if (pnd_snd.handler)
  96. pnd_snd.handler(&pnd_snd.priv, link, wc->status);
  97. wake_up(&link->wr_tx_wait);
  98. }
  99. static void smc_wr_tx_tasklet_fn(unsigned long data)
  100. {
  101. struct smc_ib_device *dev = (struct smc_ib_device *)data;
  102. struct ib_wc wc[SMC_WR_MAX_POLL_CQE];
  103. int i = 0, rc;
  104. int polled = 0;
  105. again:
  106. polled++;
  107. do {
  108. rc = ib_poll_cq(dev->roce_cq_send, SMC_WR_MAX_POLL_CQE, wc);
  109. if (polled == 1) {
  110. ib_req_notify_cq(dev->roce_cq_send,
  111. IB_CQ_NEXT_COMP |
  112. IB_CQ_REPORT_MISSED_EVENTS);
  113. }
  114. if (!rc)
  115. break;
  116. for (i = 0; i < rc; i++)
  117. smc_wr_tx_process_cqe(&wc[i]);
  118. } while (rc > 0);
  119. if (polled == 1)
  120. goto again;
  121. }
  122. void smc_wr_tx_cq_handler(struct ib_cq *ib_cq, void *cq_context)
  123. {
  124. struct smc_ib_device *dev = (struct smc_ib_device *)cq_context;
  125. tasklet_schedule(&dev->send_tasklet);
  126. }
  127. /*---------------------------- request submission ---------------------------*/
  128. static inline int smc_wr_tx_get_free_slot_index(struct smc_link *link, u32 *idx)
  129. {
  130. *idx = link->wr_tx_cnt;
  131. for_each_clear_bit(*idx, link->wr_tx_mask, link->wr_tx_cnt) {
  132. if (!test_and_set_bit(*idx, link->wr_tx_mask))
  133. return 0;
  134. }
  135. *idx = link->wr_tx_cnt;
  136. return -EBUSY;
  137. }
  138. /**
  139. * smc_wr_tx_get_free_slot() - returns buffer for message assembly,
  140. * and sets info for pending transmit tracking
  141. * @link: Pointer to smc_link used to later send the message.
  142. * @handler: Send completion handler function pointer.
  143. * @wr_buf: Out value returns pointer to message buffer.
  144. * @wr_pend_priv: Out value returns pointer serving as handler context.
  145. *
  146. * Return: 0 on success, or -errno on error.
  147. */
  148. int smc_wr_tx_get_free_slot(struct smc_link *link,
  149. smc_wr_tx_handler handler,
  150. struct smc_wr_buf **wr_buf,
  151. struct smc_wr_tx_pend_priv **wr_pend_priv)
  152. {
  153. struct smc_wr_tx_pend *wr_pend;
  154. struct ib_send_wr *wr_ib;
  155. u64 wr_id;
  156. u32 idx;
  157. int rc;
  158. *wr_buf = NULL;
  159. *wr_pend_priv = NULL;
  160. if (in_softirq()) {
  161. rc = smc_wr_tx_get_free_slot_index(link, &idx);
  162. if (rc)
  163. return rc;
  164. } else {
  165. rc = wait_event_interruptible_timeout(
  166. link->wr_tx_wait,
  167. (smc_wr_tx_get_free_slot_index(link, &idx) != -EBUSY),
  168. SMC_WR_TX_WAIT_FREE_SLOT_TIME);
  169. if (!rc) {
  170. /* timeout - terminate connections */
  171. struct smc_link_group *lgr;
  172. lgr = container_of(link, struct smc_link_group,
  173. lnk[SMC_SINGLE_LINK]);
  174. smc_lgr_terminate(lgr);
  175. return -EPIPE;
  176. }
  177. if (rc == -ERESTARTSYS)
  178. return -EINTR;
  179. if (idx == link->wr_tx_cnt)
  180. return -EPIPE;
  181. }
  182. wr_id = smc_wr_tx_get_next_wr_id(link);
  183. wr_pend = &link->wr_tx_pends[idx];
  184. wr_pend->wr_id = wr_id;
  185. wr_pend->handler = handler;
  186. wr_pend->link = link;
  187. wr_pend->idx = idx;
  188. wr_ib = &link->wr_tx_ibs[idx];
  189. wr_ib->wr_id = wr_id;
  190. *wr_buf = &link->wr_tx_bufs[idx];
  191. *wr_pend_priv = &wr_pend->priv;
  192. return 0;
  193. }
  194. int smc_wr_tx_put_slot(struct smc_link *link,
  195. struct smc_wr_tx_pend_priv *wr_pend_priv)
  196. {
  197. struct smc_wr_tx_pend *pend;
  198. pend = container_of(wr_pend_priv, struct smc_wr_tx_pend, priv);
  199. if (pend->idx < link->wr_tx_cnt) {
  200. /* clear the full struct smc_wr_tx_pend including .priv */
  201. memset(&link->wr_tx_pends[pend->idx], 0,
  202. sizeof(link->wr_tx_pends[pend->idx]));
  203. memset(&link->wr_tx_bufs[pend->idx], 0,
  204. sizeof(link->wr_tx_bufs[pend->idx]));
  205. test_and_clear_bit(pend->idx, link->wr_tx_mask);
  206. return 1;
  207. }
  208. return 0;
  209. }
  210. /* Send prepared WR slot via ib_post_send.
  211. * @priv: pointer to smc_wr_tx_pend_priv identifying prepared message buffer
  212. */
  213. int smc_wr_tx_send(struct smc_link *link, struct smc_wr_tx_pend_priv *priv)
  214. {
  215. struct ib_send_wr *failed_wr = NULL;
  216. struct smc_wr_tx_pend *pend;
  217. int rc;
  218. ib_req_notify_cq(link->smcibdev->roce_cq_send,
  219. IB_CQ_SOLICITED_MASK | IB_CQ_REPORT_MISSED_EVENTS);
  220. pend = container_of(priv, struct smc_wr_tx_pend, priv);
  221. rc = ib_post_send(link->roce_qp, &link->wr_tx_ibs[pend->idx],
  222. &failed_wr);
  223. if (rc)
  224. smc_wr_tx_put_slot(link, priv);
  225. return rc;
  226. }
  227. /* Register a memory region and wait for result. */
  228. int smc_wr_reg_send(struct smc_link *link, struct ib_mr *mr)
  229. {
  230. struct ib_send_wr *failed_wr = NULL;
  231. int rc;
  232. ib_req_notify_cq(link->smcibdev->roce_cq_send,
  233. IB_CQ_NEXT_COMP | IB_CQ_REPORT_MISSED_EVENTS);
  234. link->wr_reg_state = POSTED;
  235. link->wr_reg.wr.wr_id = (u64)(uintptr_t)mr;
  236. link->wr_reg.mr = mr;
  237. link->wr_reg.key = mr->rkey;
  238. failed_wr = &link->wr_reg.wr;
  239. rc = ib_post_send(link->roce_qp, &link->wr_reg.wr, &failed_wr);
  240. WARN_ON(failed_wr != &link->wr_reg.wr);
  241. if (rc)
  242. return rc;
  243. rc = wait_event_interruptible_timeout(link->wr_reg_wait,
  244. (link->wr_reg_state != POSTED),
  245. SMC_WR_REG_MR_WAIT_TIME);
  246. if (!rc) {
  247. /* timeout - terminate connections */
  248. struct smc_link_group *lgr;
  249. lgr = container_of(link, struct smc_link_group,
  250. lnk[SMC_SINGLE_LINK]);
  251. smc_lgr_terminate(lgr);
  252. return -EPIPE;
  253. }
  254. if (rc == -ERESTARTSYS)
  255. return -EINTR;
  256. switch (link->wr_reg_state) {
  257. case CONFIRMED:
  258. rc = 0;
  259. break;
  260. case FAILED:
  261. rc = -EIO;
  262. break;
  263. case POSTED:
  264. rc = -EPIPE;
  265. break;
  266. }
  267. return rc;
  268. }
  269. void smc_wr_tx_dismiss_slots(struct smc_link *link, u8 wr_rx_hdr_type,
  270. smc_wr_tx_filter filter,
  271. smc_wr_tx_dismisser dismisser,
  272. unsigned long data)
  273. {
  274. struct smc_wr_tx_pend_priv *tx_pend;
  275. struct smc_wr_rx_hdr *wr_rx;
  276. int i;
  277. for_each_set_bit(i, link->wr_tx_mask, link->wr_tx_cnt) {
  278. wr_rx = (struct smc_wr_rx_hdr *)&link->wr_rx_bufs[i];
  279. if (wr_rx->type != wr_rx_hdr_type)
  280. continue;
  281. tx_pend = &link->wr_tx_pends[i].priv;
  282. if (filter(tx_pend, data))
  283. dismisser(tx_pend);
  284. }
  285. }
  286. bool smc_wr_tx_has_pending(struct smc_link *link, u8 wr_rx_hdr_type,
  287. smc_wr_tx_filter filter, unsigned long data)
  288. {
  289. struct smc_wr_tx_pend_priv *tx_pend;
  290. struct smc_wr_rx_hdr *wr_rx;
  291. int i;
  292. for_each_set_bit(i, link->wr_tx_mask, link->wr_tx_cnt) {
  293. wr_rx = (struct smc_wr_rx_hdr *)&link->wr_rx_bufs[i];
  294. if (wr_rx->type != wr_rx_hdr_type)
  295. continue;
  296. tx_pend = &link->wr_tx_pends[i].priv;
  297. if (filter(tx_pend, data))
  298. return true;
  299. }
  300. return false;
  301. }
  302. /****************************** receive queue ********************************/
  303. int smc_wr_rx_register_handler(struct smc_wr_rx_handler *handler)
  304. {
  305. struct smc_wr_rx_handler *h_iter;
  306. int rc = 0;
  307. spin_lock(&smc_wr_rx_hash_lock);
  308. hash_for_each_possible(smc_wr_rx_hash, h_iter, list, handler->type) {
  309. if (h_iter->type == handler->type) {
  310. rc = -EEXIST;
  311. goto out_unlock;
  312. }
  313. }
  314. hash_add(smc_wr_rx_hash, &handler->list, handler->type);
  315. out_unlock:
  316. spin_unlock(&smc_wr_rx_hash_lock);
  317. return rc;
  318. }
  319. /* Demultiplex a received work request based on the message type to its handler.
  320. * Relies on smc_wr_rx_hash having been completely filled before any IB WRs,
  321. * and not being modified any more afterwards so we don't need to lock it.
  322. */
  323. static inline void smc_wr_rx_demultiplex(struct ib_wc *wc)
  324. {
  325. struct smc_link *link = (struct smc_link *)wc->qp->qp_context;
  326. struct smc_wr_rx_handler *handler;
  327. struct smc_wr_rx_hdr *wr_rx;
  328. u64 temp_wr_id;
  329. u32 index;
  330. if (wc->byte_len < sizeof(*wr_rx))
  331. return; /* short message */
  332. temp_wr_id = wc->wr_id;
  333. index = do_div(temp_wr_id, link->wr_rx_cnt);
  334. wr_rx = (struct smc_wr_rx_hdr *)&link->wr_rx_bufs[index];
  335. hash_for_each_possible(smc_wr_rx_hash, handler, list, wr_rx->type) {
  336. if (handler->type == wr_rx->type)
  337. handler->handler(wc, wr_rx);
  338. }
  339. }
  340. static inline void smc_wr_rx_process_cqes(struct ib_wc wc[], int num)
  341. {
  342. struct smc_link *link;
  343. int i;
  344. for (i = 0; i < num; i++) {
  345. link = wc[i].qp->qp_context;
  346. if (wc[i].status == IB_WC_SUCCESS) {
  347. smc_wr_rx_demultiplex(&wc[i]);
  348. smc_wr_rx_post(link); /* refill WR RX */
  349. } else {
  350. struct smc_link_group *lgr;
  351. /* handle status errors */
  352. switch (wc[i].status) {
  353. case IB_WC_RETRY_EXC_ERR:
  354. case IB_WC_RNR_RETRY_EXC_ERR:
  355. case IB_WC_WR_FLUSH_ERR:
  356. /* terminate connections of this link group
  357. * abnormally
  358. */
  359. lgr = container_of(link, struct smc_link_group,
  360. lnk[SMC_SINGLE_LINK]);
  361. smc_lgr_terminate(lgr);
  362. break;
  363. default:
  364. smc_wr_rx_post(link); /* refill WR RX */
  365. break;
  366. }
  367. }
  368. }
  369. }
  370. static void smc_wr_rx_tasklet_fn(unsigned long data)
  371. {
  372. struct smc_ib_device *dev = (struct smc_ib_device *)data;
  373. struct ib_wc wc[SMC_WR_MAX_POLL_CQE];
  374. int polled = 0;
  375. int rc;
  376. again:
  377. polled++;
  378. do {
  379. memset(&wc, 0, sizeof(wc));
  380. rc = ib_poll_cq(dev->roce_cq_recv, SMC_WR_MAX_POLL_CQE, wc);
  381. if (polled == 1) {
  382. ib_req_notify_cq(dev->roce_cq_recv,
  383. IB_CQ_SOLICITED_MASK
  384. | IB_CQ_REPORT_MISSED_EVENTS);
  385. }
  386. if (!rc)
  387. break;
  388. smc_wr_rx_process_cqes(&wc[0], rc);
  389. } while (rc > 0);
  390. if (polled == 1)
  391. goto again;
  392. }
  393. void smc_wr_rx_cq_handler(struct ib_cq *ib_cq, void *cq_context)
  394. {
  395. struct smc_ib_device *dev = (struct smc_ib_device *)cq_context;
  396. tasklet_schedule(&dev->recv_tasklet);
  397. }
  398. int smc_wr_rx_post_init(struct smc_link *link)
  399. {
  400. u32 i;
  401. int rc = 0;
  402. for (i = 0; i < link->wr_rx_cnt; i++)
  403. rc = smc_wr_rx_post(link);
  404. return rc;
  405. }
  406. /***************************** init, exit, misc ******************************/
  407. void smc_wr_remember_qp_attr(struct smc_link *lnk)
  408. {
  409. struct ib_qp_attr *attr = &lnk->qp_attr;
  410. struct ib_qp_init_attr init_attr;
  411. memset(attr, 0, sizeof(*attr));
  412. memset(&init_attr, 0, sizeof(init_attr));
  413. ib_query_qp(lnk->roce_qp, attr,
  414. IB_QP_STATE |
  415. IB_QP_CUR_STATE |
  416. IB_QP_PKEY_INDEX |
  417. IB_QP_PORT |
  418. IB_QP_QKEY |
  419. IB_QP_AV |
  420. IB_QP_PATH_MTU |
  421. IB_QP_TIMEOUT |
  422. IB_QP_RETRY_CNT |
  423. IB_QP_RNR_RETRY |
  424. IB_QP_RQ_PSN |
  425. IB_QP_ALT_PATH |
  426. IB_QP_MIN_RNR_TIMER |
  427. IB_QP_SQ_PSN |
  428. IB_QP_PATH_MIG_STATE |
  429. IB_QP_CAP |
  430. IB_QP_DEST_QPN,
  431. &init_attr);
  432. lnk->wr_tx_cnt = min_t(size_t, SMC_WR_BUF_CNT,
  433. lnk->qp_attr.cap.max_send_wr);
  434. lnk->wr_rx_cnt = min_t(size_t, SMC_WR_BUF_CNT * 3,
  435. lnk->qp_attr.cap.max_recv_wr);
  436. }
  437. static void smc_wr_init_sge(struct smc_link *lnk)
  438. {
  439. u32 i;
  440. for (i = 0; i < lnk->wr_tx_cnt; i++) {
  441. lnk->wr_tx_sges[i].addr =
  442. lnk->wr_tx_dma_addr + i * SMC_WR_BUF_SIZE;
  443. lnk->wr_tx_sges[i].length = SMC_WR_TX_SIZE;
  444. lnk->wr_tx_sges[i].lkey = lnk->roce_pd->local_dma_lkey;
  445. lnk->wr_tx_ibs[i].next = NULL;
  446. lnk->wr_tx_ibs[i].sg_list = &lnk->wr_tx_sges[i];
  447. lnk->wr_tx_ibs[i].num_sge = 1;
  448. lnk->wr_tx_ibs[i].opcode = IB_WR_SEND;
  449. lnk->wr_tx_ibs[i].send_flags =
  450. IB_SEND_SIGNALED | IB_SEND_SOLICITED;
  451. }
  452. for (i = 0; i < lnk->wr_rx_cnt; i++) {
  453. lnk->wr_rx_sges[i].addr =
  454. lnk->wr_rx_dma_addr + i * SMC_WR_BUF_SIZE;
  455. lnk->wr_rx_sges[i].length = SMC_WR_BUF_SIZE;
  456. lnk->wr_rx_sges[i].lkey = lnk->roce_pd->local_dma_lkey;
  457. lnk->wr_rx_ibs[i].next = NULL;
  458. lnk->wr_rx_ibs[i].sg_list = &lnk->wr_rx_sges[i];
  459. lnk->wr_rx_ibs[i].num_sge = 1;
  460. }
  461. lnk->wr_reg.wr.next = NULL;
  462. lnk->wr_reg.wr.num_sge = 0;
  463. lnk->wr_reg.wr.send_flags = IB_SEND_SIGNALED;
  464. lnk->wr_reg.wr.opcode = IB_WR_REG_MR;
  465. lnk->wr_reg.access = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_REMOTE_WRITE;
  466. }
  467. void smc_wr_free_link(struct smc_link *lnk)
  468. {
  469. struct ib_device *ibdev;
  470. memset(lnk->wr_tx_mask, 0,
  471. BITS_TO_LONGS(SMC_WR_BUF_CNT) * sizeof(*lnk->wr_tx_mask));
  472. if (!lnk->smcibdev)
  473. return;
  474. ibdev = lnk->smcibdev->ibdev;
  475. if (lnk->wr_rx_dma_addr) {
  476. ib_dma_unmap_single(ibdev, lnk->wr_rx_dma_addr,
  477. SMC_WR_BUF_SIZE * lnk->wr_rx_cnt,
  478. DMA_FROM_DEVICE);
  479. lnk->wr_rx_dma_addr = 0;
  480. }
  481. if (lnk->wr_tx_dma_addr) {
  482. ib_dma_unmap_single(ibdev, lnk->wr_tx_dma_addr,
  483. SMC_WR_BUF_SIZE * lnk->wr_tx_cnt,
  484. DMA_TO_DEVICE);
  485. lnk->wr_tx_dma_addr = 0;
  486. }
  487. }
  488. void smc_wr_free_link_mem(struct smc_link *lnk)
  489. {
  490. kfree(lnk->wr_tx_pends);
  491. lnk->wr_tx_pends = NULL;
  492. kfree(lnk->wr_tx_mask);
  493. lnk->wr_tx_mask = NULL;
  494. kfree(lnk->wr_tx_sges);
  495. lnk->wr_tx_sges = NULL;
  496. kfree(lnk->wr_rx_sges);
  497. lnk->wr_rx_sges = NULL;
  498. kfree(lnk->wr_rx_ibs);
  499. lnk->wr_rx_ibs = NULL;
  500. kfree(lnk->wr_tx_ibs);
  501. lnk->wr_tx_ibs = NULL;
  502. kfree(lnk->wr_tx_bufs);
  503. lnk->wr_tx_bufs = NULL;
  504. kfree(lnk->wr_rx_bufs);
  505. lnk->wr_rx_bufs = NULL;
  506. }
  507. int smc_wr_alloc_link_mem(struct smc_link *link)
  508. {
  509. /* allocate link related memory */
  510. link->wr_tx_bufs = kcalloc(SMC_WR_BUF_CNT, SMC_WR_BUF_SIZE, GFP_KERNEL);
  511. if (!link->wr_tx_bufs)
  512. goto no_mem;
  513. link->wr_rx_bufs = kcalloc(SMC_WR_BUF_CNT * 3, SMC_WR_BUF_SIZE,
  514. GFP_KERNEL);
  515. if (!link->wr_rx_bufs)
  516. goto no_mem_wr_tx_bufs;
  517. link->wr_tx_ibs = kcalloc(SMC_WR_BUF_CNT, sizeof(link->wr_tx_ibs[0]),
  518. GFP_KERNEL);
  519. if (!link->wr_tx_ibs)
  520. goto no_mem_wr_rx_bufs;
  521. link->wr_rx_ibs = kcalloc(SMC_WR_BUF_CNT * 3,
  522. sizeof(link->wr_rx_ibs[0]),
  523. GFP_KERNEL);
  524. if (!link->wr_rx_ibs)
  525. goto no_mem_wr_tx_ibs;
  526. link->wr_tx_sges = kcalloc(SMC_WR_BUF_CNT, sizeof(link->wr_tx_sges[0]),
  527. GFP_KERNEL);
  528. if (!link->wr_tx_sges)
  529. goto no_mem_wr_rx_ibs;
  530. link->wr_rx_sges = kcalloc(SMC_WR_BUF_CNT * 3,
  531. sizeof(link->wr_rx_sges[0]),
  532. GFP_KERNEL);
  533. if (!link->wr_rx_sges)
  534. goto no_mem_wr_tx_sges;
  535. link->wr_tx_mask = kzalloc(
  536. BITS_TO_LONGS(SMC_WR_BUF_CNT) * sizeof(*link->wr_tx_mask),
  537. GFP_KERNEL);
  538. if (!link->wr_tx_mask)
  539. goto no_mem_wr_rx_sges;
  540. link->wr_tx_pends = kcalloc(SMC_WR_BUF_CNT,
  541. sizeof(link->wr_tx_pends[0]),
  542. GFP_KERNEL);
  543. if (!link->wr_tx_pends)
  544. goto no_mem_wr_tx_mask;
  545. return 0;
  546. no_mem_wr_tx_mask:
  547. kfree(link->wr_tx_mask);
  548. no_mem_wr_rx_sges:
  549. kfree(link->wr_rx_sges);
  550. no_mem_wr_tx_sges:
  551. kfree(link->wr_tx_sges);
  552. no_mem_wr_rx_ibs:
  553. kfree(link->wr_rx_ibs);
  554. no_mem_wr_tx_ibs:
  555. kfree(link->wr_tx_ibs);
  556. no_mem_wr_rx_bufs:
  557. kfree(link->wr_rx_bufs);
  558. no_mem_wr_tx_bufs:
  559. kfree(link->wr_tx_bufs);
  560. no_mem:
  561. return -ENOMEM;
  562. }
  563. void smc_wr_remove_dev(struct smc_ib_device *smcibdev)
  564. {
  565. tasklet_kill(&smcibdev->recv_tasklet);
  566. tasklet_kill(&smcibdev->send_tasklet);
  567. }
  568. void smc_wr_add_dev(struct smc_ib_device *smcibdev)
  569. {
  570. tasklet_init(&smcibdev->recv_tasklet, smc_wr_rx_tasklet_fn,
  571. (unsigned long)smcibdev);
  572. tasklet_init(&smcibdev->send_tasklet, smc_wr_tx_tasklet_fn,
  573. (unsigned long)smcibdev);
  574. }
  575. int smc_wr_create_link(struct smc_link *lnk)
  576. {
  577. struct ib_device *ibdev = lnk->smcibdev->ibdev;
  578. int rc = 0;
  579. smc_wr_tx_set_wr_id(&lnk->wr_tx_id, 0);
  580. lnk->wr_rx_id = 0;
  581. lnk->wr_rx_dma_addr = ib_dma_map_single(
  582. ibdev, lnk->wr_rx_bufs, SMC_WR_BUF_SIZE * lnk->wr_rx_cnt,
  583. DMA_FROM_DEVICE);
  584. if (ib_dma_mapping_error(ibdev, lnk->wr_rx_dma_addr)) {
  585. lnk->wr_rx_dma_addr = 0;
  586. rc = -EIO;
  587. goto out;
  588. }
  589. lnk->wr_tx_dma_addr = ib_dma_map_single(
  590. ibdev, lnk->wr_tx_bufs, SMC_WR_BUF_SIZE * lnk->wr_tx_cnt,
  591. DMA_TO_DEVICE);
  592. if (ib_dma_mapping_error(ibdev, lnk->wr_tx_dma_addr)) {
  593. rc = -EIO;
  594. goto dma_unmap;
  595. }
  596. smc_wr_init_sge(lnk);
  597. memset(lnk->wr_tx_mask, 0,
  598. BITS_TO_LONGS(SMC_WR_BUF_CNT) * sizeof(*lnk->wr_tx_mask));
  599. init_waitqueue_head(&lnk->wr_tx_wait);
  600. init_waitqueue_head(&lnk->wr_reg_wait);
  601. return rc;
  602. dma_unmap:
  603. ib_dma_unmap_single(ibdev, lnk->wr_rx_dma_addr,
  604. SMC_WR_BUF_SIZE * lnk->wr_rx_cnt,
  605. DMA_FROM_DEVICE);
  606. lnk->wr_rx_dma_addr = 0;
  607. out:
  608. return rc;
  609. }