dma.c 7.5 KB

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  1. /*
  2. * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. /*
  9. * DMA Coherent API Notes
  10. *
  11. * I/O is inherently non-coherent on ARC. So a coherent DMA buffer is
  12. * implemented by accessing it using a kernel virtual address, with
  13. * Cache bit off in the TLB entry.
  14. *
  15. * The default DMA address == Phy address which is 0x8000_0000 based.
  16. */
  17. #include <linux/dma-mapping.h>
  18. #include <asm/cache.h>
  19. #include <asm/cacheflush.h>
  20. static void *arc_dma_alloc(struct device *dev, size_t size,
  21. dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
  22. {
  23. unsigned long order = get_order(size);
  24. struct page *page;
  25. phys_addr_t paddr;
  26. void *kvaddr;
  27. int need_coh = 1, need_kvaddr = 0;
  28. page = alloc_pages(gfp, order);
  29. if (!page)
  30. return NULL;
  31. /*
  32. * IOC relies on all data (even coherent DMA data) being in cache
  33. * Thus allocate normal cached memory
  34. *
  35. * The gains with IOC are two pronged:
  36. * -For streaming data, elides need for cache maintenance, saving
  37. * cycles in flush code, and bus bandwidth as all the lines of a
  38. * buffer need to be flushed out to memory
  39. * -For coherent data, Read/Write to buffers terminate early in cache
  40. * (vs. always going to memory - thus are faster)
  41. */
  42. if ((is_isa_arcv2() && ioc_enable) ||
  43. (attrs & DMA_ATTR_NON_CONSISTENT))
  44. need_coh = 0;
  45. /*
  46. * - A coherent buffer needs MMU mapping to enforce non-cachability
  47. * - A highmem page needs a virtual handle (hence MMU mapping)
  48. * independent of cachability
  49. */
  50. if (PageHighMem(page) || need_coh)
  51. need_kvaddr = 1;
  52. /* This is linear addr (0x8000_0000 based) */
  53. paddr = page_to_phys(page);
  54. *dma_handle = paddr;
  55. /* This is kernel Virtual address (0x7000_0000 based) */
  56. if (need_kvaddr) {
  57. kvaddr = ioremap_nocache(paddr, size);
  58. if (kvaddr == NULL) {
  59. __free_pages(page, order);
  60. return NULL;
  61. }
  62. } else {
  63. kvaddr = (void *)(u32)paddr;
  64. }
  65. /*
  66. * Evict any existing L1 and/or L2 lines for the backing page
  67. * in case it was used earlier as a normal "cached" page.
  68. * Yeah this bit us - STAR 9000898266
  69. *
  70. * Although core does call flush_cache_vmap(), it gets kvaddr hence
  71. * can't be used to efficiently flush L1 and/or L2 which need paddr
  72. * Currently flush_cache_vmap nukes the L1 cache completely which
  73. * will be optimized as a separate commit
  74. */
  75. if (need_coh)
  76. dma_cache_wback_inv(paddr, size);
  77. return kvaddr;
  78. }
  79. static void arc_dma_free(struct device *dev, size_t size, void *vaddr,
  80. dma_addr_t dma_handle, unsigned long attrs)
  81. {
  82. phys_addr_t paddr = dma_handle;
  83. struct page *page = virt_to_page(paddr);
  84. int is_non_coh = 1;
  85. is_non_coh = (attrs & DMA_ATTR_NON_CONSISTENT) ||
  86. (is_isa_arcv2() && ioc_enable);
  87. if (PageHighMem(page) || !is_non_coh)
  88. iounmap((void __force __iomem *)vaddr);
  89. __free_pages(page, get_order(size));
  90. }
  91. static int arc_dma_mmap(struct device *dev, struct vm_area_struct *vma,
  92. void *cpu_addr, dma_addr_t dma_addr, size_t size,
  93. unsigned long attrs)
  94. {
  95. unsigned long user_count = vma_pages(vma);
  96. unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
  97. unsigned long pfn = __phys_to_pfn(dma_addr);
  98. unsigned long off = vma->vm_pgoff;
  99. int ret = -ENXIO;
  100. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  101. if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
  102. return ret;
  103. if (off < count && user_count <= (count - off)) {
  104. ret = remap_pfn_range(vma, vma->vm_start,
  105. pfn + off,
  106. user_count << PAGE_SHIFT,
  107. vma->vm_page_prot);
  108. }
  109. return ret;
  110. }
  111. /*
  112. * streaming DMA Mapping API...
  113. * CPU accesses page via normal paddr, thus needs to explicitly made
  114. * consistent before each use
  115. */
  116. static void _dma_cache_sync(phys_addr_t paddr, size_t size,
  117. enum dma_data_direction dir)
  118. {
  119. switch (dir) {
  120. case DMA_FROM_DEVICE:
  121. dma_cache_inv(paddr, size);
  122. break;
  123. case DMA_TO_DEVICE:
  124. dma_cache_wback(paddr, size);
  125. break;
  126. case DMA_BIDIRECTIONAL:
  127. dma_cache_wback_inv(paddr, size);
  128. break;
  129. default:
  130. pr_err("Invalid DMA dir [%d] for OP @ %pa[p]\n", dir, &paddr);
  131. }
  132. }
  133. /*
  134. * arc_dma_map_page - map a portion of a page for streaming DMA
  135. *
  136. * Ensure that any data held in the cache is appropriately discarded
  137. * or written back.
  138. *
  139. * The device owns this memory once this call has completed. The CPU
  140. * can regain ownership by calling dma_unmap_page().
  141. *
  142. * Note: while it takes struct page as arg, caller can "abuse" it to pass
  143. * a region larger than PAGE_SIZE, provided it is physically contiguous
  144. * and this still works correctly
  145. */
  146. static dma_addr_t arc_dma_map_page(struct device *dev, struct page *page,
  147. unsigned long offset, size_t size, enum dma_data_direction dir,
  148. unsigned long attrs)
  149. {
  150. phys_addr_t paddr = page_to_phys(page) + offset;
  151. if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
  152. _dma_cache_sync(paddr, size, dir);
  153. return paddr;
  154. }
  155. /*
  156. * arc_dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
  157. *
  158. * After this call, reads by the CPU to the buffer are guaranteed to see
  159. * whatever the device wrote there.
  160. *
  161. * Note: historically this routine was not implemented for ARC
  162. */
  163. static void arc_dma_unmap_page(struct device *dev, dma_addr_t handle,
  164. size_t size, enum dma_data_direction dir,
  165. unsigned long attrs)
  166. {
  167. phys_addr_t paddr = handle;
  168. if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
  169. _dma_cache_sync(paddr, size, dir);
  170. }
  171. static int arc_dma_map_sg(struct device *dev, struct scatterlist *sg,
  172. int nents, enum dma_data_direction dir, unsigned long attrs)
  173. {
  174. struct scatterlist *s;
  175. int i;
  176. for_each_sg(sg, s, nents, i)
  177. s->dma_address = dma_map_page(dev, sg_page(s), s->offset,
  178. s->length, dir);
  179. return nents;
  180. }
  181. static void arc_dma_unmap_sg(struct device *dev, struct scatterlist *sg,
  182. int nents, enum dma_data_direction dir,
  183. unsigned long attrs)
  184. {
  185. struct scatterlist *s;
  186. int i;
  187. for_each_sg(sg, s, nents, i)
  188. arc_dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir,
  189. attrs);
  190. }
  191. static void arc_dma_sync_single_for_cpu(struct device *dev,
  192. dma_addr_t dma_handle, size_t size, enum dma_data_direction dir)
  193. {
  194. _dma_cache_sync(dma_handle, size, DMA_FROM_DEVICE);
  195. }
  196. static void arc_dma_sync_single_for_device(struct device *dev,
  197. dma_addr_t dma_handle, size_t size, enum dma_data_direction dir)
  198. {
  199. _dma_cache_sync(dma_handle, size, DMA_TO_DEVICE);
  200. }
  201. static void arc_dma_sync_sg_for_cpu(struct device *dev,
  202. struct scatterlist *sglist, int nelems,
  203. enum dma_data_direction dir)
  204. {
  205. int i;
  206. struct scatterlist *sg;
  207. for_each_sg(sglist, sg, nelems, i)
  208. _dma_cache_sync(sg_phys(sg), sg->length, dir);
  209. }
  210. static void arc_dma_sync_sg_for_device(struct device *dev,
  211. struct scatterlist *sglist, int nelems,
  212. enum dma_data_direction dir)
  213. {
  214. int i;
  215. struct scatterlist *sg;
  216. for_each_sg(sglist, sg, nelems, i)
  217. _dma_cache_sync(sg_phys(sg), sg->length, dir);
  218. }
  219. static int arc_dma_supported(struct device *dev, u64 dma_mask)
  220. {
  221. /* Support 32 bit DMA mask exclusively */
  222. return dma_mask == DMA_BIT_MASK(32);
  223. }
  224. const struct dma_map_ops arc_dma_ops = {
  225. .alloc = arc_dma_alloc,
  226. .free = arc_dma_free,
  227. .mmap = arc_dma_mmap,
  228. .map_page = arc_dma_map_page,
  229. .unmap_page = arc_dma_unmap_page,
  230. .map_sg = arc_dma_map_sg,
  231. .unmap_sg = arc_dma_unmap_sg,
  232. .sync_single_for_device = arc_dma_sync_single_for_device,
  233. .sync_single_for_cpu = arc_dma_sync_single_for_cpu,
  234. .sync_sg_for_cpu = arc_dma_sync_sg_for_cpu,
  235. .sync_sg_for_device = arc_dma_sync_sg_for_device,
  236. .dma_supported = arc_dma_supported,
  237. };
  238. EXPORT_SYMBOL(arc_dma_ops);