iosf_mbi.h 2.9 KB

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  1. /*
  2. * Intel OnChip System Fabric MailBox access support
  3. */
  4. #ifndef IOSF_MBI_SYMS_H
  5. #define IOSF_MBI_SYMS_H
  6. #define MBI_MCR_OFFSET 0xD0
  7. #define MBI_MDR_OFFSET 0xD4
  8. #define MBI_MCRX_OFFSET 0xD8
  9. #define MBI_RD_MASK 0xFEFFFFFF
  10. #define MBI_WR_MASK 0X01000000
  11. #define MBI_MASK_HI 0xFFFFFF00
  12. #define MBI_MASK_LO 0x000000FF
  13. #define MBI_ENABLE 0xF0
  14. /* IOSF SB read/write opcodes */
  15. #define MBI_MMIO_READ 0x00
  16. #define MBI_MMIO_WRITE 0x01
  17. #define MBI_CR_READ 0x06
  18. #define MBI_CR_WRITE 0x07
  19. #define MBI_REG_READ 0x10
  20. #define MBI_REG_WRITE 0x11
  21. #define MBI_ESRAM_READ 0x12
  22. #define MBI_ESRAM_WRITE 0x13
  23. /* Baytrail available units */
  24. #define BT_MBI_UNIT_AUNIT 0x00
  25. #define BT_MBI_UNIT_SMC 0x01
  26. #define BT_MBI_UNIT_CPU 0x02
  27. #define BT_MBI_UNIT_BUNIT 0x03
  28. #define BT_MBI_UNIT_PMC 0x04
  29. #define BT_MBI_UNIT_GFX 0x06
  30. #define BT_MBI_UNIT_SMI 0x0C
  31. #define BT_MBI_UNIT_USB 0x43
  32. #define BT_MBI_UNIT_SATA 0xA3
  33. #define BT_MBI_UNIT_PCIE 0xA6
  34. /* Quark available units */
  35. #define QRK_MBI_UNIT_HBA 0x00
  36. #define QRK_MBI_UNIT_HB 0x03
  37. #define QRK_MBI_UNIT_RMU 0x04
  38. #define QRK_MBI_UNIT_MM 0x05
  39. #define QRK_MBI_UNIT_SOC 0x31
  40. #if IS_ENABLED(CONFIG_IOSF_MBI)
  41. bool iosf_mbi_available(void);
  42. /**
  43. * iosf_mbi_read() - MailBox Interface read command
  44. * @port: port indicating subunit being accessed
  45. * @opcode: port specific read or write opcode
  46. * @offset: register address offset
  47. * @mdr: register data to be read
  48. *
  49. * Locking is handled by spinlock - cannot sleep.
  50. * Return: Nonzero on error
  51. */
  52. int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr);
  53. /**
  54. * iosf_mbi_write() - MailBox unmasked write command
  55. * @port: port indicating subunit being accessed
  56. * @opcode: port specific read or write opcode
  57. * @offset: register address offset
  58. * @mdr: register data to be written
  59. *
  60. * Locking is handled by spinlock - cannot sleep.
  61. * Return: Nonzero on error
  62. */
  63. int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr);
  64. /**
  65. * iosf_mbi_modify() - MailBox masked write command
  66. * @port: port indicating subunit being accessed
  67. * @opcode: port specific read or write opcode
  68. * @offset: register address offset
  69. * @mdr: register data being modified
  70. * @mask: mask indicating bits in mdr to be modified
  71. *
  72. * Locking is handled by spinlock - cannot sleep.
  73. * Return: Nonzero on error
  74. */
  75. int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask);
  76. #else /* CONFIG_IOSF_MBI is not enabled */
  77. static inline
  78. bool iosf_mbi_available(void)
  79. {
  80. return false;
  81. }
  82. static inline
  83. int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr)
  84. {
  85. WARN(1, "IOSF_MBI driver not available");
  86. return -EPERM;
  87. }
  88. static inline
  89. int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr)
  90. {
  91. WARN(1, "IOSF_MBI driver not available");
  92. return -EPERM;
  93. }
  94. static inline
  95. int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask)
  96. {
  97. WARN(1, "IOSF_MBI driver not available");
  98. return -EPERM;
  99. }
  100. #endif /* CONFIG_IOSF_MBI */
  101. #endif /* IOSF_MBI_SYMS_H */