setup.c 26 KB

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  1. /*
  2. * linux/arch/arm/kernel/setup.c
  3. *
  4. * Copyright (C) 1995-2001 Russell King
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/export.h>
  11. #include <linux/kernel.h>
  12. #include <linux/stddef.h>
  13. #include <linux/ioport.h>
  14. #include <linux/delay.h>
  15. #include <linux/utsname.h>
  16. #include <linux/initrd.h>
  17. #include <linux/console.h>
  18. #include <linux/bootmem.h>
  19. #include <linux/seq_file.h>
  20. #include <linux/screen_info.h>
  21. #include <linux/of_iommu.h>
  22. #include <linux/of_platform.h>
  23. #include <linux/init.h>
  24. #include <linux/kexec.h>
  25. #include <linux/of_fdt.h>
  26. #include <linux/cpu.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/smp.h>
  29. #include <linux/proc_fs.h>
  30. #include <linux/memblock.h>
  31. #include <linux/bug.h>
  32. #include <linux/compiler.h>
  33. #include <linux/sort.h>
  34. #include <asm/unified.h>
  35. #include <asm/cp15.h>
  36. #include <asm/cpu.h>
  37. #include <asm/cputype.h>
  38. #include <asm/elf.h>
  39. #include <asm/procinfo.h>
  40. #include <asm/psci.h>
  41. #include <asm/sections.h>
  42. #include <asm/setup.h>
  43. #include <asm/smp_plat.h>
  44. #include <asm/mach-types.h>
  45. #include <asm/cacheflush.h>
  46. #include <asm/cachetype.h>
  47. #include <asm/tlbflush.h>
  48. #include <asm/prom.h>
  49. #include <asm/mach/arch.h>
  50. #include <asm/mach/irq.h>
  51. #include <asm/mach/time.h>
  52. #include <asm/system_info.h>
  53. #include <asm/system_misc.h>
  54. #include <asm/traps.h>
  55. #include <asm/unwind.h>
  56. #include <asm/memblock.h>
  57. #include <asm/virt.h>
  58. #include "atags.h"
  59. #if defined(CONFIG_FPE_NWFPE) || defined(CONFIG_FPE_FASTFPE)
  60. char fpe_type[8];
  61. static int __init fpe_setup(char *line)
  62. {
  63. memcpy(fpe_type, line, 8);
  64. return 1;
  65. }
  66. __setup("fpe=", fpe_setup);
  67. #endif
  68. extern void init_default_cache_policy(unsigned long);
  69. extern void paging_init(const struct machine_desc *desc);
  70. extern void early_paging_init(const struct machine_desc *,
  71. struct proc_info_list *);
  72. extern void sanity_check_meminfo(void);
  73. extern enum reboot_mode reboot_mode;
  74. extern void setup_dma_zone(const struct machine_desc *desc);
  75. unsigned int processor_id;
  76. EXPORT_SYMBOL(processor_id);
  77. unsigned int __machine_arch_type __read_mostly;
  78. EXPORT_SYMBOL(__machine_arch_type);
  79. unsigned int cacheid __read_mostly;
  80. EXPORT_SYMBOL(cacheid);
  81. unsigned int __atags_pointer __initdata;
  82. unsigned int system_rev;
  83. EXPORT_SYMBOL(system_rev);
  84. unsigned int system_serial_low;
  85. EXPORT_SYMBOL(system_serial_low);
  86. unsigned int system_serial_high;
  87. EXPORT_SYMBOL(system_serial_high);
  88. unsigned int elf_hwcap __read_mostly;
  89. EXPORT_SYMBOL(elf_hwcap);
  90. unsigned int elf_hwcap2 __read_mostly;
  91. EXPORT_SYMBOL(elf_hwcap2);
  92. #ifdef MULTI_CPU
  93. struct processor processor __read_mostly;
  94. #endif
  95. #ifdef MULTI_TLB
  96. struct cpu_tlb_fns cpu_tlb __read_mostly;
  97. #endif
  98. #ifdef MULTI_USER
  99. struct cpu_user_fns cpu_user __read_mostly;
  100. #endif
  101. #ifdef MULTI_CACHE
  102. struct cpu_cache_fns cpu_cache __read_mostly;
  103. #endif
  104. #ifdef CONFIG_OUTER_CACHE
  105. struct outer_cache_fns outer_cache __read_mostly;
  106. EXPORT_SYMBOL(outer_cache);
  107. #endif
  108. /*
  109. * Cached cpu_architecture() result for use by assembler code.
  110. * C code should use the cpu_architecture() function instead of accessing this
  111. * variable directly.
  112. */
  113. int __cpu_architecture __read_mostly = CPU_ARCH_UNKNOWN;
  114. struct stack {
  115. u32 irq[3];
  116. u32 abt[3];
  117. u32 und[3];
  118. u32 fiq[3];
  119. } ____cacheline_aligned;
  120. #ifndef CONFIG_CPU_V7M
  121. static struct stack stacks[NR_CPUS];
  122. #endif
  123. char elf_platform[ELF_PLATFORM_SIZE];
  124. EXPORT_SYMBOL(elf_platform);
  125. static const char *cpu_name;
  126. static const char *machine_name;
  127. static char __initdata cmd_line[COMMAND_LINE_SIZE];
  128. const struct machine_desc *machine_desc __initdata;
  129. static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } };
  130. #define ENDIANNESS ((char)endian_test.l)
  131. DEFINE_PER_CPU(struct cpuinfo_arm, cpu_data);
  132. /*
  133. * Standard memory resources
  134. */
  135. static struct resource mem_res[] = {
  136. {
  137. .name = "Video RAM",
  138. .start = 0,
  139. .end = 0,
  140. .flags = IORESOURCE_MEM
  141. },
  142. {
  143. .name = "Kernel code",
  144. .start = 0,
  145. .end = 0,
  146. .flags = IORESOURCE_MEM
  147. },
  148. {
  149. .name = "Kernel data",
  150. .start = 0,
  151. .end = 0,
  152. .flags = IORESOURCE_MEM
  153. }
  154. };
  155. #define video_ram mem_res[0]
  156. #define kernel_code mem_res[1]
  157. #define kernel_data mem_res[2]
  158. static struct resource io_res[] = {
  159. {
  160. .name = "reserved",
  161. .start = 0x3bc,
  162. .end = 0x3be,
  163. .flags = IORESOURCE_IO | IORESOURCE_BUSY
  164. },
  165. {
  166. .name = "reserved",
  167. .start = 0x378,
  168. .end = 0x37f,
  169. .flags = IORESOURCE_IO | IORESOURCE_BUSY
  170. },
  171. {
  172. .name = "reserved",
  173. .start = 0x278,
  174. .end = 0x27f,
  175. .flags = IORESOURCE_IO | IORESOURCE_BUSY
  176. }
  177. };
  178. #define lp0 io_res[0]
  179. #define lp1 io_res[1]
  180. #define lp2 io_res[2]
  181. static const char *proc_arch[] = {
  182. "undefined/unknown",
  183. "3",
  184. "4",
  185. "4T",
  186. "5",
  187. "5T",
  188. "5TE",
  189. "5TEJ",
  190. "6TEJ",
  191. "7",
  192. "7M",
  193. "?(12)",
  194. "?(13)",
  195. "?(14)",
  196. "?(15)",
  197. "?(16)",
  198. "?(17)",
  199. };
  200. #ifdef CONFIG_CPU_V7M
  201. static int __get_cpu_architecture(void)
  202. {
  203. return CPU_ARCH_ARMv7M;
  204. }
  205. #else
  206. static int __get_cpu_architecture(void)
  207. {
  208. int cpu_arch;
  209. if ((read_cpuid_id() & 0x0008f000) == 0) {
  210. cpu_arch = CPU_ARCH_UNKNOWN;
  211. } else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
  212. cpu_arch = (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
  213. } else if ((read_cpuid_id() & 0x00080000) == 0x00000000) {
  214. cpu_arch = (read_cpuid_id() >> 16) & 7;
  215. if (cpu_arch)
  216. cpu_arch += CPU_ARCH_ARMv3;
  217. } else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
  218. /* Revised CPUID format. Read the Memory Model Feature
  219. * Register 0 and check for VMSAv7 or PMSAv7 */
  220. unsigned int mmfr0 = read_cpuid_ext(CPUID_EXT_MMFR0);
  221. if ((mmfr0 & 0x0000000f) >= 0x00000003 ||
  222. (mmfr0 & 0x000000f0) >= 0x00000030)
  223. cpu_arch = CPU_ARCH_ARMv7;
  224. else if ((mmfr0 & 0x0000000f) == 0x00000002 ||
  225. (mmfr0 & 0x000000f0) == 0x00000020)
  226. cpu_arch = CPU_ARCH_ARMv6;
  227. else
  228. cpu_arch = CPU_ARCH_UNKNOWN;
  229. } else
  230. cpu_arch = CPU_ARCH_UNKNOWN;
  231. return cpu_arch;
  232. }
  233. #endif
  234. int __pure cpu_architecture(void)
  235. {
  236. BUG_ON(__cpu_architecture == CPU_ARCH_UNKNOWN);
  237. return __cpu_architecture;
  238. }
  239. static int cpu_has_aliasing_icache(unsigned int arch)
  240. {
  241. int aliasing_icache;
  242. unsigned int id_reg, num_sets, line_size;
  243. /* PIPT caches never alias. */
  244. if (icache_is_pipt())
  245. return 0;
  246. /* arch specifies the register format */
  247. switch (arch) {
  248. case CPU_ARCH_ARMv7:
  249. asm("mcr p15, 2, %0, c0, c0, 0 @ set CSSELR"
  250. : /* No output operands */
  251. : "r" (1));
  252. isb();
  253. asm("mrc p15, 1, %0, c0, c0, 0 @ read CCSIDR"
  254. : "=r" (id_reg));
  255. line_size = 4 << ((id_reg & 0x7) + 2);
  256. num_sets = ((id_reg >> 13) & 0x7fff) + 1;
  257. aliasing_icache = (line_size * num_sets) > PAGE_SIZE;
  258. break;
  259. case CPU_ARCH_ARMv6:
  260. aliasing_icache = read_cpuid_cachetype() & (1 << 11);
  261. break;
  262. default:
  263. /* I-cache aliases will be handled by D-cache aliasing code */
  264. aliasing_icache = 0;
  265. }
  266. return aliasing_icache;
  267. }
  268. static void __init cacheid_init(void)
  269. {
  270. unsigned int arch = cpu_architecture();
  271. if (arch == CPU_ARCH_ARMv7M) {
  272. cacheid = 0;
  273. } else if (arch >= CPU_ARCH_ARMv6) {
  274. unsigned int cachetype = read_cpuid_cachetype();
  275. if ((cachetype & (7 << 29)) == 4 << 29) {
  276. /* ARMv7 register format */
  277. arch = CPU_ARCH_ARMv7;
  278. cacheid = CACHEID_VIPT_NONALIASING;
  279. switch (cachetype & (3 << 14)) {
  280. case (1 << 14):
  281. cacheid |= CACHEID_ASID_TAGGED;
  282. break;
  283. case (3 << 14):
  284. cacheid |= CACHEID_PIPT;
  285. break;
  286. }
  287. } else {
  288. arch = CPU_ARCH_ARMv6;
  289. if (cachetype & (1 << 23))
  290. cacheid = CACHEID_VIPT_ALIASING;
  291. else
  292. cacheid = CACHEID_VIPT_NONALIASING;
  293. }
  294. if (cpu_has_aliasing_icache(arch))
  295. cacheid |= CACHEID_VIPT_I_ALIASING;
  296. } else {
  297. cacheid = CACHEID_VIVT;
  298. }
  299. pr_info("CPU: %s data cache, %s instruction cache\n",
  300. cache_is_vivt() ? "VIVT" :
  301. cache_is_vipt_aliasing() ? "VIPT aliasing" :
  302. cache_is_vipt_nonaliasing() ? "PIPT / VIPT nonaliasing" : "unknown",
  303. cache_is_vivt() ? "VIVT" :
  304. icache_is_vivt_asid_tagged() ? "VIVT ASID tagged" :
  305. icache_is_vipt_aliasing() ? "VIPT aliasing" :
  306. icache_is_pipt() ? "PIPT" :
  307. cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown");
  308. }
  309. /*
  310. * These functions re-use the assembly code in head.S, which
  311. * already provide the required functionality.
  312. */
  313. extern struct proc_info_list *lookup_processor_type(unsigned int);
  314. void __init early_print(const char *str, ...)
  315. {
  316. extern void printascii(const char *);
  317. char buf[256];
  318. va_list ap;
  319. va_start(ap, str);
  320. vsnprintf(buf, sizeof(buf), str, ap);
  321. va_end(ap);
  322. #ifdef CONFIG_DEBUG_LL
  323. printascii(buf);
  324. #endif
  325. printk("%s", buf);
  326. }
  327. static void __init cpuid_init_hwcaps(void)
  328. {
  329. unsigned int divide_instrs, vmsa;
  330. if (cpu_architecture() < CPU_ARCH_ARMv7)
  331. return;
  332. divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24;
  333. switch (divide_instrs) {
  334. case 2:
  335. elf_hwcap |= HWCAP_IDIVA;
  336. case 1:
  337. elf_hwcap |= HWCAP_IDIVT;
  338. }
  339. /* LPAE implies atomic ldrd/strd instructions */
  340. vmsa = (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xf) >> 0;
  341. if (vmsa >= 5)
  342. elf_hwcap |= HWCAP_LPAE;
  343. }
  344. static void __init elf_hwcap_fixup(void)
  345. {
  346. unsigned id = read_cpuid_id();
  347. unsigned sync_prim;
  348. /*
  349. * HWCAP_TLS is available only on 1136 r1p0 and later,
  350. * see also kuser_get_tls_init.
  351. */
  352. if (read_cpuid_part() == ARM_CPU_PART_ARM1136 &&
  353. ((id >> 20) & 3) == 0) {
  354. elf_hwcap &= ~HWCAP_TLS;
  355. return;
  356. }
  357. /* Verify if CPUID scheme is implemented */
  358. if ((id & 0x000f0000) != 0x000f0000)
  359. return;
  360. /*
  361. * If the CPU supports LDREX/STREX and LDREXB/STREXB,
  362. * avoid advertising SWP; it may not be atomic with
  363. * multiprocessing cores.
  364. */
  365. sync_prim = ((read_cpuid_ext(CPUID_EXT_ISAR3) >> 8) & 0xf0) |
  366. ((read_cpuid_ext(CPUID_EXT_ISAR4) >> 20) & 0x0f);
  367. if (sync_prim >= 0x13)
  368. elf_hwcap &= ~HWCAP_SWP;
  369. }
  370. /*
  371. * cpu_init - initialise one CPU.
  372. *
  373. * cpu_init sets up the per-CPU stacks.
  374. */
  375. void notrace cpu_init(void)
  376. {
  377. #ifndef CONFIG_CPU_V7M
  378. unsigned int cpu = smp_processor_id();
  379. struct stack *stk = &stacks[cpu];
  380. if (cpu >= NR_CPUS) {
  381. pr_crit("CPU%u: bad primary CPU number\n", cpu);
  382. BUG();
  383. }
  384. /*
  385. * This only works on resume and secondary cores. For booting on the
  386. * boot cpu, smp_prepare_boot_cpu is called after percpu area setup.
  387. */
  388. set_my_cpu_offset(per_cpu_offset(cpu));
  389. cpu_proc_init();
  390. /*
  391. * Define the placement constraint for the inline asm directive below.
  392. * In Thumb-2, msr with an immediate value is not allowed.
  393. */
  394. #ifdef CONFIG_THUMB2_KERNEL
  395. #define PLC "r"
  396. #else
  397. #define PLC "I"
  398. #endif
  399. /*
  400. * setup stacks for re-entrant exception handlers
  401. */
  402. __asm__ (
  403. "msr cpsr_c, %1\n\t"
  404. "add r14, %0, %2\n\t"
  405. "mov sp, r14\n\t"
  406. "msr cpsr_c, %3\n\t"
  407. "add r14, %0, %4\n\t"
  408. "mov sp, r14\n\t"
  409. "msr cpsr_c, %5\n\t"
  410. "add r14, %0, %6\n\t"
  411. "mov sp, r14\n\t"
  412. "msr cpsr_c, %7\n\t"
  413. "add r14, %0, %8\n\t"
  414. "mov sp, r14\n\t"
  415. "msr cpsr_c, %9"
  416. :
  417. : "r" (stk),
  418. PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
  419. "I" (offsetof(struct stack, irq[0])),
  420. PLC (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
  421. "I" (offsetof(struct stack, abt[0])),
  422. PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE),
  423. "I" (offsetof(struct stack, und[0])),
  424. PLC (PSR_F_BIT | PSR_I_BIT | FIQ_MODE),
  425. "I" (offsetof(struct stack, fiq[0])),
  426. PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
  427. : "r14");
  428. #endif
  429. }
  430. u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
  431. void __init smp_setup_processor_id(void)
  432. {
  433. int i;
  434. u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
  435. u32 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
  436. cpu_logical_map(0) = cpu;
  437. for (i = 1; i < nr_cpu_ids; ++i)
  438. cpu_logical_map(i) = i == cpu ? 0 : i;
  439. /*
  440. * clear __my_cpu_offset on boot CPU to avoid hang caused by
  441. * using percpu variable early, for example, lockdep will
  442. * access percpu variable inside lock_release
  443. */
  444. set_my_cpu_offset(0);
  445. pr_info("Booting Linux on physical CPU 0x%x\n", mpidr);
  446. }
  447. struct mpidr_hash mpidr_hash;
  448. #ifdef CONFIG_SMP
  449. /**
  450. * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
  451. * level in order to build a linear index from an
  452. * MPIDR value. Resulting algorithm is a collision
  453. * free hash carried out through shifting and ORing
  454. */
  455. static void __init smp_build_mpidr_hash(void)
  456. {
  457. u32 i, affinity;
  458. u32 fs[3], bits[3], ls, mask = 0;
  459. /*
  460. * Pre-scan the list of MPIDRS and filter out bits that do
  461. * not contribute to affinity levels, ie they never toggle.
  462. */
  463. for_each_possible_cpu(i)
  464. mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
  465. pr_debug("mask of set bits 0x%x\n", mask);
  466. /*
  467. * Find and stash the last and first bit set at all affinity levels to
  468. * check how many bits are required to represent them.
  469. */
  470. for (i = 0; i < 3; i++) {
  471. affinity = MPIDR_AFFINITY_LEVEL(mask, i);
  472. /*
  473. * Find the MSB bit and LSB bits position
  474. * to determine how many bits are required
  475. * to express the affinity level.
  476. */
  477. ls = fls(affinity);
  478. fs[i] = affinity ? ffs(affinity) - 1 : 0;
  479. bits[i] = ls - fs[i];
  480. }
  481. /*
  482. * An index can be created from the MPIDR by isolating the
  483. * significant bits at each affinity level and by shifting
  484. * them in order to compress the 24 bits values space to a
  485. * compressed set of values. This is equivalent to hashing
  486. * the MPIDR through shifting and ORing. It is a collision free
  487. * hash though not minimal since some levels might contain a number
  488. * of CPUs that is not an exact power of 2 and their bit
  489. * representation might contain holes, eg MPIDR[7:0] = {0x2, 0x80}.
  490. */
  491. mpidr_hash.shift_aff[0] = fs[0];
  492. mpidr_hash.shift_aff[1] = MPIDR_LEVEL_BITS + fs[1] - bits[0];
  493. mpidr_hash.shift_aff[2] = 2*MPIDR_LEVEL_BITS + fs[2] -
  494. (bits[1] + bits[0]);
  495. mpidr_hash.mask = mask;
  496. mpidr_hash.bits = bits[2] + bits[1] + bits[0];
  497. pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] mask[0x%x] bits[%u]\n",
  498. mpidr_hash.shift_aff[0],
  499. mpidr_hash.shift_aff[1],
  500. mpidr_hash.shift_aff[2],
  501. mpidr_hash.mask,
  502. mpidr_hash.bits);
  503. /*
  504. * 4x is an arbitrary value used to warn on a hash table much bigger
  505. * than expected on most systems.
  506. */
  507. if (mpidr_hash_size() > 4 * num_possible_cpus())
  508. pr_warn("Large number of MPIDR hash buckets detected\n");
  509. sync_cache_w(&mpidr_hash);
  510. }
  511. #endif
  512. static void __init setup_processor(void)
  513. {
  514. struct proc_info_list *list;
  515. /*
  516. * locate processor in the list of supported processor
  517. * types. The linker builds this table for us from the
  518. * entries in arch/arm/mm/proc-*.S
  519. */
  520. list = lookup_processor_type(read_cpuid_id());
  521. if (!list) {
  522. pr_err("CPU configuration botched (ID %08x), unable to continue.\n",
  523. read_cpuid_id());
  524. while (1);
  525. }
  526. cpu_name = list->cpu_name;
  527. __cpu_architecture = __get_cpu_architecture();
  528. #ifdef MULTI_CPU
  529. processor = *list->proc;
  530. #endif
  531. #ifdef MULTI_TLB
  532. cpu_tlb = *list->tlb;
  533. #endif
  534. #ifdef MULTI_USER
  535. cpu_user = *list->user;
  536. #endif
  537. #ifdef MULTI_CACHE
  538. cpu_cache = *list->cache;
  539. #endif
  540. pr_info("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
  541. cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
  542. proc_arch[cpu_architecture()], get_cr());
  543. snprintf(init_utsname()->machine, __NEW_UTS_LEN + 1, "%s%c",
  544. list->arch_name, ENDIANNESS);
  545. snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c",
  546. list->elf_name, ENDIANNESS);
  547. elf_hwcap = list->elf_hwcap;
  548. cpuid_init_hwcaps();
  549. #ifndef CONFIG_ARM_THUMB
  550. elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT);
  551. #endif
  552. #ifdef CONFIG_MMU
  553. init_default_cache_policy(list->__cpu_mm_mmu_flags);
  554. #endif
  555. erratum_a15_798181_init();
  556. elf_hwcap_fixup();
  557. cacheid_init();
  558. cpu_init();
  559. }
  560. void __init dump_machine_table(void)
  561. {
  562. const struct machine_desc *p;
  563. early_print("Available machine support:\n\nID (hex)\tNAME\n");
  564. for_each_machine_desc(p)
  565. early_print("%08x\t%s\n", p->nr, p->name);
  566. early_print("\nPlease check your kernel config and/or bootloader.\n");
  567. while (true)
  568. /* can't use cpu_relax() here as it may require MMU setup */;
  569. }
  570. int __init arm_add_memory(u64 start, u64 size)
  571. {
  572. u64 aligned_start;
  573. /*
  574. * Ensure that start/size are aligned to a page boundary.
  575. * Size is rounded down, start is rounded up.
  576. */
  577. aligned_start = PAGE_ALIGN(start);
  578. if (aligned_start > start + size)
  579. size = 0;
  580. else
  581. size -= aligned_start - start;
  582. #ifndef CONFIG_ARCH_PHYS_ADDR_T_64BIT
  583. if (aligned_start > ULONG_MAX) {
  584. pr_crit("Ignoring memory at 0x%08llx outside 32-bit physical address space\n",
  585. (long long)start);
  586. return -EINVAL;
  587. }
  588. if (aligned_start + size > ULONG_MAX) {
  589. pr_crit("Truncating memory at 0x%08llx to fit in 32-bit physical address space\n",
  590. (long long)start);
  591. /*
  592. * To ensure bank->start + bank->size is representable in
  593. * 32 bits, we use ULONG_MAX as the upper limit rather than 4GB.
  594. * This means we lose a page after masking.
  595. */
  596. size = ULONG_MAX - aligned_start;
  597. }
  598. #endif
  599. if (aligned_start < PHYS_OFFSET) {
  600. if (aligned_start + size <= PHYS_OFFSET) {
  601. pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
  602. aligned_start, aligned_start + size);
  603. return -EINVAL;
  604. }
  605. pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
  606. aligned_start, (u64)PHYS_OFFSET);
  607. size -= PHYS_OFFSET - aligned_start;
  608. aligned_start = PHYS_OFFSET;
  609. }
  610. start = aligned_start;
  611. size = size & ~(phys_addr_t)(PAGE_SIZE - 1);
  612. /*
  613. * Check whether this memory region has non-zero size or
  614. * invalid node number.
  615. */
  616. if (size == 0)
  617. return -EINVAL;
  618. memblock_add(start, size);
  619. return 0;
  620. }
  621. /*
  622. * Pick out the memory size. We look for mem=size@start,
  623. * where start and size are "size[KkMm]"
  624. */
  625. static int __init early_mem(char *p)
  626. {
  627. static int usermem __initdata = 0;
  628. u64 size;
  629. u64 start;
  630. char *endp;
  631. /*
  632. * If the user specifies memory size, we
  633. * blow away any automatically generated
  634. * size.
  635. */
  636. if (usermem == 0) {
  637. usermem = 1;
  638. memblock_remove(memblock_start_of_DRAM(),
  639. memblock_end_of_DRAM() - memblock_start_of_DRAM());
  640. }
  641. start = PHYS_OFFSET;
  642. size = memparse(p, &endp);
  643. if (*endp == '@')
  644. start = memparse(endp + 1, NULL);
  645. arm_add_memory(start, size);
  646. return 0;
  647. }
  648. early_param("mem", early_mem);
  649. static void __init request_standard_resources(const struct machine_desc *mdesc)
  650. {
  651. struct memblock_region *region;
  652. struct resource *res;
  653. kernel_code.start = virt_to_phys(_text);
  654. kernel_code.end = virt_to_phys(_etext - 1);
  655. kernel_data.start = virt_to_phys(_sdata);
  656. kernel_data.end = virt_to_phys(_end - 1);
  657. for_each_memblock(memory, region) {
  658. res = memblock_virt_alloc(sizeof(*res), 0);
  659. res->name = "System RAM";
  660. res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
  661. res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
  662. res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
  663. request_resource(&iomem_resource, res);
  664. if (kernel_code.start >= res->start &&
  665. kernel_code.end <= res->end)
  666. request_resource(res, &kernel_code);
  667. if (kernel_data.start >= res->start &&
  668. kernel_data.end <= res->end)
  669. request_resource(res, &kernel_data);
  670. }
  671. if (mdesc->video_start) {
  672. video_ram.start = mdesc->video_start;
  673. video_ram.end = mdesc->video_end;
  674. request_resource(&iomem_resource, &video_ram);
  675. }
  676. /*
  677. * Some machines don't have the possibility of ever
  678. * possessing lp0, lp1 or lp2
  679. */
  680. if (mdesc->reserve_lp0)
  681. request_resource(&ioport_resource, &lp0);
  682. if (mdesc->reserve_lp1)
  683. request_resource(&ioport_resource, &lp1);
  684. if (mdesc->reserve_lp2)
  685. request_resource(&ioport_resource, &lp2);
  686. }
  687. #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
  688. struct screen_info screen_info = {
  689. .orig_video_lines = 30,
  690. .orig_video_cols = 80,
  691. .orig_video_mode = 0,
  692. .orig_video_ega_bx = 0,
  693. .orig_video_isVGA = 1,
  694. .orig_video_points = 8
  695. };
  696. #endif
  697. static int __init customize_machine(void)
  698. {
  699. /*
  700. * customizes platform devices, or adds new ones
  701. * On DT based machines, we fall back to populating the
  702. * machine from the device tree, if no callback is provided,
  703. * otherwise we would always need an init_machine callback.
  704. */
  705. of_iommu_init();
  706. if (machine_desc->init_machine)
  707. machine_desc->init_machine();
  708. #ifdef CONFIG_OF
  709. else
  710. of_platform_populate(NULL, of_default_bus_match_table,
  711. NULL, NULL);
  712. #endif
  713. return 0;
  714. }
  715. arch_initcall(customize_machine);
  716. static int __init init_machine_late(void)
  717. {
  718. if (machine_desc->init_late)
  719. machine_desc->init_late();
  720. return 0;
  721. }
  722. late_initcall(init_machine_late);
  723. #ifdef CONFIG_KEXEC
  724. static inline unsigned long long get_total_mem(void)
  725. {
  726. unsigned long total;
  727. total = max_low_pfn - min_low_pfn;
  728. return total << PAGE_SHIFT;
  729. }
  730. /**
  731. * reserve_crashkernel() - reserves memory are for crash kernel
  732. *
  733. * This function reserves memory area given in "crashkernel=" kernel command
  734. * line parameter. The memory reserved is used by a dump capture kernel when
  735. * primary kernel is crashing.
  736. */
  737. static void __init reserve_crashkernel(void)
  738. {
  739. unsigned long long crash_size, crash_base;
  740. unsigned long long total_mem;
  741. int ret;
  742. total_mem = get_total_mem();
  743. ret = parse_crashkernel(boot_command_line, total_mem,
  744. &crash_size, &crash_base);
  745. if (ret)
  746. return;
  747. ret = memblock_reserve(crash_base, crash_size);
  748. if (ret < 0) {
  749. pr_warn("crashkernel reservation failed - memory is in use (0x%lx)\n",
  750. (unsigned long)crash_base);
  751. return;
  752. }
  753. pr_info("Reserving %ldMB of memory at %ldMB for crashkernel (System RAM: %ldMB)\n",
  754. (unsigned long)(crash_size >> 20),
  755. (unsigned long)(crash_base >> 20),
  756. (unsigned long)(total_mem >> 20));
  757. crashk_res.start = crash_base;
  758. crashk_res.end = crash_base + crash_size - 1;
  759. insert_resource(&iomem_resource, &crashk_res);
  760. }
  761. #else
  762. static inline void reserve_crashkernel(void) {}
  763. #endif /* CONFIG_KEXEC */
  764. void __init hyp_mode_check(void)
  765. {
  766. #ifdef CONFIG_ARM_VIRT_EXT
  767. sync_boot_mode();
  768. if (is_hyp_mode_available()) {
  769. pr_info("CPU: All CPU(s) started in HYP mode.\n");
  770. pr_info("CPU: Virtualization extensions available.\n");
  771. } else if (is_hyp_mode_mismatched()) {
  772. pr_warn("CPU: WARNING: CPU(s) started in wrong/inconsistent modes (primary CPU mode 0x%x)\n",
  773. __boot_cpu_mode & MODE_MASK);
  774. pr_warn("CPU: This may indicate a broken bootloader or firmware.\n");
  775. } else
  776. pr_info("CPU: All CPU(s) started in SVC mode.\n");
  777. #endif
  778. }
  779. void __init setup_arch(char **cmdline_p)
  780. {
  781. const struct machine_desc *mdesc;
  782. setup_processor();
  783. mdesc = setup_machine_fdt(__atags_pointer);
  784. if (!mdesc)
  785. mdesc = setup_machine_tags(__atags_pointer, __machine_arch_type);
  786. machine_desc = mdesc;
  787. machine_name = mdesc->name;
  788. dump_stack_set_arch_desc("%s", mdesc->name);
  789. if (mdesc->reboot_mode != REBOOT_HARD)
  790. reboot_mode = mdesc->reboot_mode;
  791. init_mm.start_code = (unsigned long) _text;
  792. init_mm.end_code = (unsigned long) _etext;
  793. init_mm.end_data = (unsigned long) _edata;
  794. init_mm.brk = (unsigned long) _end;
  795. /* populate cmd_line too for later use, preserving boot_command_line */
  796. strlcpy(cmd_line, boot_command_line, COMMAND_LINE_SIZE);
  797. *cmdline_p = cmd_line;
  798. parse_early_param();
  799. early_paging_init(mdesc, lookup_processor_type(read_cpuid_id()));
  800. setup_dma_zone(mdesc);
  801. sanity_check_meminfo();
  802. arm_memblock_init(mdesc);
  803. paging_init(mdesc);
  804. request_standard_resources(mdesc);
  805. if (mdesc->restart)
  806. arm_pm_restart = mdesc->restart;
  807. unflatten_device_tree();
  808. arm_dt_init_cpu_maps();
  809. psci_init();
  810. #ifdef CONFIG_SMP
  811. if (is_smp()) {
  812. if (!mdesc->smp_init || !mdesc->smp_init()) {
  813. if (psci_smp_available())
  814. smp_set_ops(&psci_smp_ops);
  815. else if (mdesc->smp)
  816. smp_set_ops(mdesc->smp);
  817. }
  818. smp_init_cpus();
  819. smp_build_mpidr_hash();
  820. }
  821. #endif
  822. if (!is_smp())
  823. hyp_mode_check();
  824. reserve_crashkernel();
  825. #ifdef CONFIG_MULTI_IRQ_HANDLER
  826. handle_arch_irq = mdesc->handle_irq;
  827. #endif
  828. #ifdef CONFIG_VT
  829. #if defined(CONFIG_VGA_CONSOLE)
  830. conswitchp = &vga_con;
  831. #elif defined(CONFIG_DUMMY_CONSOLE)
  832. conswitchp = &dummy_con;
  833. #endif
  834. #endif
  835. if (mdesc->init_early)
  836. mdesc->init_early();
  837. }
  838. static int __init topology_init(void)
  839. {
  840. int cpu;
  841. for_each_possible_cpu(cpu) {
  842. struct cpuinfo_arm *cpuinfo = &per_cpu(cpu_data, cpu);
  843. cpuinfo->cpu.hotpluggable = 1;
  844. register_cpu(&cpuinfo->cpu, cpu);
  845. }
  846. return 0;
  847. }
  848. subsys_initcall(topology_init);
  849. #ifdef CONFIG_HAVE_PROC_CPU
  850. static int __init proc_cpu_init(void)
  851. {
  852. struct proc_dir_entry *res;
  853. res = proc_mkdir("cpu", NULL);
  854. if (!res)
  855. return -ENOMEM;
  856. return 0;
  857. }
  858. fs_initcall(proc_cpu_init);
  859. #endif
  860. static const char *hwcap_str[] = {
  861. "swp",
  862. "half",
  863. "thumb",
  864. "26bit",
  865. "fastmult",
  866. "fpa",
  867. "vfp",
  868. "edsp",
  869. "java",
  870. "iwmmxt",
  871. "crunch",
  872. "thumbee",
  873. "neon",
  874. "vfpv3",
  875. "vfpv3d16",
  876. "tls",
  877. "vfpv4",
  878. "idiva",
  879. "idivt",
  880. "vfpd32",
  881. "lpae",
  882. "evtstrm",
  883. NULL
  884. };
  885. static const char *hwcap2_str[] = {
  886. "aes",
  887. "pmull",
  888. "sha1",
  889. "sha2",
  890. "crc32",
  891. NULL
  892. };
  893. static int c_show(struct seq_file *m, void *v)
  894. {
  895. int i, j;
  896. u32 cpuid;
  897. for_each_online_cpu(i) {
  898. /*
  899. * glibc reads /proc/cpuinfo to determine the number of
  900. * online processors, looking for lines beginning with
  901. * "processor". Give glibc what it expects.
  902. */
  903. seq_printf(m, "processor\t: %d\n", i);
  904. cpuid = is_smp() ? per_cpu(cpu_data, i).cpuid : read_cpuid_id();
  905. seq_printf(m, "model name\t: %s rev %d (%s)\n",
  906. cpu_name, cpuid & 15, elf_platform);
  907. #if defined(CONFIG_SMP)
  908. seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
  909. per_cpu(cpu_data, i).loops_per_jiffy / (500000UL/HZ),
  910. (per_cpu(cpu_data, i).loops_per_jiffy / (5000UL/HZ)) % 100);
  911. #else
  912. seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
  913. loops_per_jiffy / (500000/HZ),
  914. (loops_per_jiffy / (5000/HZ)) % 100);
  915. #endif
  916. /* dump out the processor features */
  917. seq_puts(m, "Features\t: ");
  918. for (j = 0; hwcap_str[j]; j++)
  919. if (elf_hwcap & (1 << j))
  920. seq_printf(m, "%s ", hwcap_str[j]);
  921. for (j = 0; hwcap2_str[j]; j++)
  922. if (elf_hwcap2 & (1 << j))
  923. seq_printf(m, "%s ", hwcap2_str[j]);
  924. seq_printf(m, "\nCPU implementer\t: 0x%02x\n", cpuid >> 24);
  925. seq_printf(m, "CPU architecture: %s\n",
  926. proc_arch[cpu_architecture()]);
  927. if ((cpuid & 0x0008f000) == 0x00000000) {
  928. /* pre-ARM7 */
  929. seq_printf(m, "CPU part\t: %07x\n", cpuid >> 4);
  930. } else {
  931. if ((cpuid & 0x0008f000) == 0x00007000) {
  932. /* ARM7 */
  933. seq_printf(m, "CPU variant\t: 0x%02x\n",
  934. (cpuid >> 16) & 127);
  935. } else {
  936. /* post-ARM7 */
  937. seq_printf(m, "CPU variant\t: 0x%x\n",
  938. (cpuid >> 20) & 15);
  939. }
  940. seq_printf(m, "CPU part\t: 0x%03x\n",
  941. (cpuid >> 4) & 0xfff);
  942. }
  943. seq_printf(m, "CPU revision\t: %d\n\n", cpuid & 15);
  944. }
  945. seq_printf(m, "Hardware\t: %s\n", machine_name);
  946. seq_printf(m, "Revision\t: %04x\n", system_rev);
  947. seq_printf(m, "Serial\t\t: %08x%08x\n",
  948. system_serial_high, system_serial_low);
  949. return 0;
  950. }
  951. static void *c_start(struct seq_file *m, loff_t *pos)
  952. {
  953. return *pos < 1 ? (void *)1 : NULL;
  954. }
  955. static void *c_next(struct seq_file *m, void *v, loff_t *pos)
  956. {
  957. ++*pos;
  958. return NULL;
  959. }
  960. static void c_stop(struct seq_file *m, void *v)
  961. {
  962. }
  963. const struct seq_operations cpuinfo_op = {
  964. .start = c_start,
  965. .next = c_next,
  966. .stop = c_stop,
  967. .show = c_show
  968. };