low_i2c.c 36 KB

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  1. /*
  2. * arch/powerpc/platforms/powermac/low_i2c.c
  3. *
  4. * Copyright (C) 2003-2005 Ben. Herrenschmidt (benh@kernel.crashing.org)
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version
  9. * 2 of the License, or (at your option) any later version.
  10. *
  11. * The linux i2c layer isn't completely suitable for our needs for various
  12. * reasons ranging from too late initialisation to semantics not perfectly
  13. * matching some requirements of the apple platform functions etc...
  14. *
  15. * This file thus provides a simple low level unified i2c interface for
  16. * powermac that covers the various types of i2c busses used in Apple machines.
  17. * For now, keywest, PMU and SMU, though we could add Cuda, or other bit
  18. * banging busses found on older chipsets in earlier machines if we ever need
  19. * one of them.
  20. *
  21. * The drivers in this file are synchronous/blocking. In addition, the
  22. * keywest one is fairly slow due to the use of msleep instead of interrupts
  23. * as the interrupt is currently used by i2c-keywest. In the long run, we
  24. * might want to get rid of those high-level interfaces to linux i2c layer
  25. * either completely (converting all drivers) or replacing them all with a
  26. * single stub driver on top of this one. Once done, the interrupt will be
  27. * available for our use.
  28. */
  29. #undef DEBUG
  30. #undef DEBUG_LOW
  31. #include <linux/types.h>
  32. #include <linux/sched.h>
  33. #include <linux/init.h>
  34. #include <linux/export.h>
  35. #include <linux/adb.h>
  36. #include <linux/pmu.h>
  37. #include <linux/delay.h>
  38. #include <linux/completion.h>
  39. #include <linux/platform_device.h>
  40. #include <linux/interrupt.h>
  41. #include <linux/timer.h>
  42. #include <linux/mutex.h>
  43. #include <linux/i2c.h>
  44. #include <linux/slab.h>
  45. #include <asm/keylargo.h>
  46. #include <asm/uninorth.h>
  47. #include <asm/io.h>
  48. #include <asm/prom.h>
  49. #include <asm/machdep.h>
  50. #include <asm/smu.h>
  51. #include <asm/pmac_pfunc.h>
  52. #include <asm/pmac_low_i2c.h>
  53. #ifdef DEBUG
  54. #define DBG(x...) do {\
  55. printk(KERN_DEBUG "low_i2c:" x); \
  56. } while(0)
  57. #else
  58. #define DBG(x...)
  59. #endif
  60. #ifdef DEBUG_LOW
  61. #define DBG_LOW(x...) do {\
  62. printk(KERN_DEBUG "low_i2c:" x); \
  63. } while(0)
  64. #else
  65. #define DBG_LOW(x...)
  66. #endif
  67. static int pmac_i2c_force_poll = 1;
  68. /*
  69. * A bus structure. Each bus in the system has such a structure associated.
  70. */
  71. struct pmac_i2c_bus
  72. {
  73. struct list_head link;
  74. struct device_node *controller;
  75. struct device_node *busnode;
  76. int type;
  77. int flags;
  78. struct i2c_adapter adapter;
  79. void *hostdata;
  80. int channel; /* some hosts have multiple */
  81. int mode; /* current mode */
  82. struct mutex mutex;
  83. int opened;
  84. int polled; /* open mode */
  85. struct platform_device *platform_dev;
  86. struct lock_class_key lock_key;
  87. /* ops */
  88. int (*open)(struct pmac_i2c_bus *bus);
  89. void (*close)(struct pmac_i2c_bus *bus);
  90. int (*xfer)(struct pmac_i2c_bus *bus, u8 addrdir, int subsize,
  91. u32 subaddr, u8 *data, int len);
  92. };
  93. static LIST_HEAD(pmac_i2c_busses);
  94. /*
  95. * Keywest implementation
  96. */
  97. struct pmac_i2c_host_kw
  98. {
  99. struct mutex mutex; /* Access mutex for use by
  100. * i2c-keywest */
  101. void __iomem *base; /* register base address */
  102. int bsteps; /* register stepping */
  103. int speed; /* speed */
  104. int irq;
  105. u8 *data;
  106. unsigned len;
  107. int state;
  108. int rw;
  109. int polled;
  110. int result;
  111. struct completion complete;
  112. spinlock_t lock;
  113. struct timer_list timeout_timer;
  114. };
  115. /* Register indices */
  116. typedef enum {
  117. reg_mode = 0,
  118. reg_control,
  119. reg_status,
  120. reg_isr,
  121. reg_ier,
  122. reg_addr,
  123. reg_subaddr,
  124. reg_data
  125. } reg_t;
  126. /* The Tumbler audio equalizer can be really slow sometimes */
  127. #define KW_POLL_TIMEOUT (2*HZ)
  128. /* Mode register */
  129. #define KW_I2C_MODE_100KHZ 0x00
  130. #define KW_I2C_MODE_50KHZ 0x01
  131. #define KW_I2C_MODE_25KHZ 0x02
  132. #define KW_I2C_MODE_DUMB 0x00
  133. #define KW_I2C_MODE_STANDARD 0x04
  134. #define KW_I2C_MODE_STANDARDSUB 0x08
  135. #define KW_I2C_MODE_COMBINED 0x0C
  136. #define KW_I2C_MODE_MODE_MASK 0x0C
  137. #define KW_I2C_MODE_CHAN_MASK 0xF0
  138. /* Control register */
  139. #define KW_I2C_CTL_AAK 0x01
  140. #define KW_I2C_CTL_XADDR 0x02
  141. #define KW_I2C_CTL_STOP 0x04
  142. #define KW_I2C_CTL_START 0x08
  143. /* Status register */
  144. #define KW_I2C_STAT_BUSY 0x01
  145. #define KW_I2C_STAT_LAST_AAK 0x02
  146. #define KW_I2C_STAT_LAST_RW 0x04
  147. #define KW_I2C_STAT_SDA 0x08
  148. #define KW_I2C_STAT_SCL 0x10
  149. /* IER & ISR registers */
  150. #define KW_I2C_IRQ_DATA 0x01
  151. #define KW_I2C_IRQ_ADDR 0x02
  152. #define KW_I2C_IRQ_STOP 0x04
  153. #define KW_I2C_IRQ_START 0x08
  154. #define KW_I2C_IRQ_MASK 0x0F
  155. /* State machine states */
  156. enum {
  157. state_idle,
  158. state_addr,
  159. state_read,
  160. state_write,
  161. state_stop,
  162. state_dead
  163. };
  164. #define WRONG_STATE(name) do {\
  165. printk(KERN_DEBUG "KW: wrong state. Got %s, state: %s " \
  166. "(isr: %02x)\n", \
  167. name, __kw_state_names[host->state], isr); \
  168. } while(0)
  169. static const char *__kw_state_names[] = {
  170. "state_idle",
  171. "state_addr",
  172. "state_read",
  173. "state_write",
  174. "state_stop",
  175. "state_dead"
  176. };
  177. static inline u8 __kw_read_reg(struct pmac_i2c_host_kw *host, reg_t reg)
  178. {
  179. return readb(host->base + (((unsigned int)reg) << host->bsteps));
  180. }
  181. static inline void __kw_write_reg(struct pmac_i2c_host_kw *host,
  182. reg_t reg, u8 val)
  183. {
  184. writeb(val, host->base + (((unsigned)reg) << host->bsteps));
  185. (void)__kw_read_reg(host, reg_subaddr);
  186. }
  187. #define kw_write_reg(reg, val) __kw_write_reg(host, reg, val)
  188. #define kw_read_reg(reg) __kw_read_reg(host, reg)
  189. static u8 kw_i2c_wait_interrupt(struct pmac_i2c_host_kw *host)
  190. {
  191. int i, j;
  192. u8 isr;
  193. for (i = 0; i < 1000; i++) {
  194. isr = kw_read_reg(reg_isr) & KW_I2C_IRQ_MASK;
  195. if (isr != 0)
  196. return isr;
  197. /* This code is used with the timebase frozen, we cannot rely
  198. * on udelay nor schedule when in polled mode !
  199. * For now, just use a bogus loop....
  200. */
  201. if (host->polled) {
  202. for (j = 1; j < 100000; j++)
  203. mb();
  204. } else
  205. msleep(1);
  206. }
  207. return isr;
  208. }
  209. static void kw_i2c_do_stop(struct pmac_i2c_host_kw *host, int result)
  210. {
  211. kw_write_reg(reg_control, KW_I2C_CTL_STOP);
  212. host->state = state_stop;
  213. host->result = result;
  214. }
  215. static void kw_i2c_handle_interrupt(struct pmac_i2c_host_kw *host, u8 isr)
  216. {
  217. u8 ack;
  218. DBG_LOW("kw_handle_interrupt(%s, isr: %x)\n",
  219. __kw_state_names[host->state], isr);
  220. if (host->state == state_idle) {
  221. printk(KERN_WARNING "low_i2c: Keywest got an out of state"
  222. " interrupt, ignoring\n");
  223. kw_write_reg(reg_isr, isr);
  224. return;
  225. }
  226. if (isr == 0) {
  227. printk(KERN_WARNING "low_i2c: Timeout in i2c transfer"
  228. " on keywest !\n");
  229. if (host->state != state_stop) {
  230. kw_i2c_do_stop(host, -EIO);
  231. return;
  232. }
  233. ack = kw_read_reg(reg_status);
  234. if (ack & KW_I2C_STAT_BUSY)
  235. kw_write_reg(reg_status, 0);
  236. host->state = state_idle;
  237. kw_write_reg(reg_ier, 0x00);
  238. if (!host->polled)
  239. complete(&host->complete);
  240. return;
  241. }
  242. if (isr & KW_I2C_IRQ_ADDR) {
  243. ack = kw_read_reg(reg_status);
  244. if (host->state != state_addr) {
  245. WRONG_STATE("KW_I2C_IRQ_ADDR");
  246. kw_i2c_do_stop(host, -EIO);
  247. }
  248. if ((ack & KW_I2C_STAT_LAST_AAK) == 0) {
  249. host->result = -ENXIO;
  250. host->state = state_stop;
  251. DBG_LOW("KW: NAK on address\n");
  252. } else {
  253. if (host->len == 0)
  254. kw_i2c_do_stop(host, 0);
  255. else if (host->rw) {
  256. host->state = state_read;
  257. if (host->len > 1)
  258. kw_write_reg(reg_control,
  259. KW_I2C_CTL_AAK);
  260. } else {
  261. host->state = state_write;
  262. kw_write_reg(reg_data, *(host->data++));
  263. host->len--;
  264. }
  265. }
  266. kw_write_reg(reg_isr, KW_I2C_IRQ_ADDR);
  267. }
  268. if (isr & KW_I2C_IRQ_DATA) {
  269. if (host->state == state_read) {
  270. *(host->data++) = kw_read_reg(reg_data);
  271. host->len--;
  272. kw_write_reg(reg_isr, KW_I2C_IRQ_DATA);
  273. if (host->len == 0)
  274. host->state = state_stop;
  275. else if (host->len == 1)
  276. kw_write_reg(reg_control, 0);
  277. } else if (host->state == state_write) {
  278. ack = kw_read_reg(reg_status);
  279. if ((ack & KW_I2C_STAT_LAST_AAK) == 0) {
  280. DBG_LOW("KW: nack on data write\n");
  281. host->result = -EFBIG;
  282. host->state = state_stop;
  283. } else if (host->len) {
  284. kw_write_reg(reg_data, *(host->data++));
  285. host->len--;
  286. } else
  287. kw_i2c_do_stop(host, 0);
  288. } else {
  289. WRONG_STATE("KW_I2C_IRQ_DATA");
  290. if (host->state != state_stop)
  291. kw_i2c_do_stop(host, -EIO);
  292. }
  293. kw_write_reg(reg_isr, KW_I2C_IRQ_DATA);
  294. }
  295. if (isr & KW_I2C_IRQ_STOP) {
  296. kw_write_reg(reg_isr, KW_I2C_IRQ_STOP);
  297. if (host->state != state_stop) {
  298. WRONG_STATE("KW_I2C_IRQ_STOP");
  299. host->result = -EIO;
  300. }
  301. host->state = state_idle;
  302. if (!host->polled)
  303. complete(&host->complete);
  304. }
  305. /* Below should only happen in manual mode which we don't use ... */
  306. if (isr & KW_I2C_IRQ_START)
  307. kw_write_reg(reg_isr, KW_I2C_IRQ_START);
  308. }
  309. /* Interrupt handler */
  310. static irqreturn_t kw_i2c_irq(int irq, void *dev_id)
  311. {
  312. struct pmac_i2c_host_kw *host = dev_id;
  313. unsigned long flags;
  314. spin_lock_irqsave(&host->lock, flags);
  315. del_timer(&host->timeout_timer);
  316. kw_i2c_handle_interrupt(host, kw_read_reg(reg_isr));
  317. if (host->state != state_idle) {
  318. host->timeout_timer.expires = jiffies + KW_POLL_TIMEOUT;
  319. add_timer(&host->timeout_timer);
  320. }
  321. spin_unlock_irqrestore(&host->lock, flags);
  322. return IRQ_HANDLED;
  323. }
  324. static void kw_i2c_timeout(struct timer_list *t)
  325. {
  326. struct pmac_i2c_host_kw *host = from_timer(host, t, timeout_timer);
  327. unsigned long flags;
  328. spin_lock_irqsave(&host->lock, flags);
  329. /*
  330. * If the timer is pending, that means we raced with the
  331. * irq, in which case we just return
  332. */
  333. if (timer_pending(&host->timeout_timer))
  334. goto skip;
  335. kw_i2c_handle_interrupt(host, kw_read_reg(reg_isr));
  336. if (host->state != state_idle) {
  337. host->timeout_timer.expires = jiffies + KW_POLL_TIMEOUT;
  338. add_timer(&host->timeout_timer);
  339. }
  340. skip:
  341. spin_unlock_irqrestore(&host->lock, flags);
  342. }
  343. static int kw_i2c_open(struct pmac_i2c_bus *bus)
  344. {
  345. struct pmac_i2c_host_kw *host = bus->hostdata;
  346. mutex_lock(&host->mutex);
  347. return 0;
  348. }
  349. static void kw_i2c_close(struct pmac_i2c_bus *bus)
  350. {
  351. struct pmac_i2c_host_kw *host = bus->hostdata;
  352. mutex_unlock(&host->mutex);
  353. }
  354. static int kw_i2c_xfer(struct pmac_i2c_bus *bus, u8 addrdir, int subsize,
  355. u32 subaddr, u8 *data, int len)
  356. {
  357. struct pmac_i2c_host_kw *host = bus->hostdata;
  358. u8 mode_reg = host->speed;
  359. int use_irq = host->irq && !bus->polled;
  360. /* Setup mode & subaddress if any */
  361. switch(bus->mode) {
  362. case pmac_i2c_mode_dumb:
  363. return -EINVAL;
  364. case pmac_i2c_mode_std:
  365. mode_reg |= KW_I2C_MODE_STANDARD;
  366. if (subsize != 0)
  367. return -EINVAL;
  368. break;
  369. case pmac_i2c_mode_stdsub:
  370. mode_reg |= KW_I2C_MODE_STANDARDSUB;
  371. if (subsize != 1)
  372. return -EINVAL;
  373. break;
  374. case pmac_i2c_mode_combined:
  375. mode_reg |= KW_I2C_MODE_COMBINED;
  376. if (subsize != 1)
  377. return -EINVAL;
  378. break;
  379. }
  380. /* Setup channel & clear pending irqs */
  381. kw_write_reg(reg_isr, kw_read_reg(reg_isr));
  382. kw_write_reg(reg_mode, mode_reg | (bus->channel << 4));
  383. kw_write_reg(reg_status, 0);
  384. /* Set up address and r/w bit, strip possible stale bus number from
  385. * address top bits
  386. */
  387. kw_write_reg(reg_addr, addrdir & 0xff);
  388. /* Set up the sub address */
  389. if ((mode_reg & KW_I2C_MODE_MODE_MASK) == KW_I2C_MODE_STANDARDSUB
  390. || (mode_reg & KW_I2C_MODE_MODE_MASK) == KW_I2C_MODE_COMBINED)
  391. kw_write_reg(reg_subaddr, subaddr);
  392. /* Prepare for async operations */
  393. host->data = data;
  394. host->len = len;
  395. host->state = state_addr;
  396. host->result = 0;
  397. host->rw = (addrdir & 1);
  398. host->polled = bus->polled;
  399. /* Enable interrupt if not using polled mode and interrupt is
  400. * available
  401. */
  402. if (use_irq) {
  403. /* Clear completion */
  404. reinit_completion(&host->complete);
  405. /* Ack stale interrupts */
  406. kw_write_reg(reg_isr, kw_read_reg(reg_isr));
  407. /* Arm timeout */
  408. host->timeout_timer.expires = jiffies + KW_POLL_TIMEOUT;
  409. add_timer(&host->timeout_timer);
  410. /* Enable emission */
  411. kw_write_reg(reg_ier, KW_I2C_IRQ_MASK);
  412. }
  413. /* Start sending address */
  414. kw_write_reg(reg_control, KW_I2C_CTL_XADDR);
  415. /* Wait for completion */
  416. if (use_irq)
  417. wait_for_completion(&host->complete);
  418. else {
  419. while(host->state != state_idle) {
  420. unsigned long flags;
  421. u8 isr = kw_i2c_wait_interrupt(host);
  422. spin_lock_irqsave(&host->lock, flags);
  423. kw_i2c_handle_interrupt(host, isr);
  424. spin_unlock_irqrestore(&host->lock, flags);
  425. }
  426. }
  427. /* Disable emission */
  428. kw_write_reg(reg_ier, 0);
  429. return host->result;
  430. }
  431. static struct pmac_i2c_host_kw *__init kw_i2c_host_init(struct device_node *np)
  432. {
  433. struct pmac_i2c_host_kw *host;
  434. const u32 *psteps, *prate, *addrp;
  435. u32 steps;
  436. host = kzalloc(sizeof(*host), GFP_KERNEL);
  437. if (host == NULL) {
  438. printk(KERN_ERR "low_i2c: Can't allocate host for %pOF\n",
  439. np);
  440. return NULL;
  441. }
  442. /* Apple is kind enough to provide a valid AAPL,address property
  443. * on all i2c keywest nodes so far ... we would have to fallback
  444. * to macio parsing if that wasn't the case
  445. */
  446. addrp = of_get_property(np, "AAPL,address", NULL);
  447. if (addrp == NULL) {
  448. printk(KERN_ERR "low_i2c: Can't find address for %pOF\n",
  449. np);
  450. kfree(host);
  451. return NULL;
  452. }
  453. mutex_init(&host->mutex);
  454. init_completion(&host->complete);
  455. spin_lock_init(&host->lock);
  456. timer_setup(&host->timeout_timer, kw_i2c_timeout, 0);
  457. psteps = of_get_property(np, "AAPL,address-step", NULL);
  458. steps = psteps ? (*psteps) : 0x10;
  459. for (host->bsteps = 0; (steps & 0x01) == 0; host->bsteps++)
  460. steps >>= 1;
  461. /* Select interface rate */
  462. host->speed = KW_I2C_MODE_25KHZ;
  463. prate = of_get_property(np, "AAPL,i2c-rate", NULL);
  464. if (prate) switch(*prate) {
  465. case 100:
  466. host->speed = KW_I2C_MODE_100KHZ;
  467. break;
  468. case 50:
  469. host->speed = KW_I2C_MODE_50KHZ;
  470. break;
  471. case 25:
  472. host->speed = KW_I2C_MODE_25KHZ;
  473. break;
  474. }
  475. host->irq = irq_of_parse_and_map(np, 0);
  476. if (!host->irq)
  477. printk(KERN_WARNING
  478. "low_i2c: Failed to map interrupt for %pOF\n",
  479. np);
  480. host->base = ioremap((*addrp), 0x1000);
  481. if (host->base == NULL) {
  482. printk(KERN_ERR "low_i2c: Can't map registers for %pOF\n",
  483. np);
  484. kfree(host);
  485. return NULL;
  486. }
  487. /* Make sure IRQ is disabled */
  488. kw_write_reg(reg_ier, 0);
  489. /* Request chip interrupt. We set IRQF_NO_SUSPEND because we don't
  490. * want that interrupt disabled between the 2 passes of driver
  491. * suspend or we'll have issues running the pfuncs
  492. */
  493. if (request_irq(host->irq, kw_i2c_irq, IRQF_NO_SUSPEND,
  494. "keywest i2c", host))
  495. host->irq = 0;
  496. printk(KERN_INFO "KeyWest i2c @0x%08x irq %d %pOF\n",
  497. *addrp, host->irq, np);
  498. return host;
  499. }
  500. static void __init kw_i2c_add(struct pmac_i2c_host_kw *host,
  501. struct device_node *controller,
  502. struct device_node *busnode,
  503. int channel)
  504. {
  505. struct pmac_i2c_bus *bus;
  506. bus = kzalloc(sizeof(struct pmac_i2c_bus), GFP_KERNEL);
  507. if (bus == NULL)
  508. return;
  509. bus->controller = of_node_get(controller);
  510. bus->busnode = of_node_get(busnode);
  511. bus->type = pmac_i2c_bus_keywest;
  512. bus->hostdata = host;
  513. bus->channel = channel;
  514. bus->mode = pmac_i2c_mode_std;
  515. bus->open = kw_i2c_open;
  516. bus->close = kw_i2c_close;
  517. bus->xfer = kw_i2c_xfer;
  518. mutex_init(&bus->mutex);
  519. lockdep_set_class(&bus->mutex, &bus->lock_key);
  520. if (controller == busnode)
  521. bus->flags = pmac_i2c_multibus;
  522. list_add(&bus->link, &pmac_i2c_busses);
  523. printk(KERN_INFO " channel %d bus %s\n", channel,
  524. (controller == busnode) ? "<multibus>" : busnode->full_name);
  525. }
  526. static void __init kw_i2c_probe(void)
  527. {
  528. struct device_node *np, *child, *parent;
  529. /* Probe keywest-i2c busses */
  530. for_each_compatible_node(np, "i2c","keywest-i2c") {
  531. struct pmac_i2c_host_kw *host;
  532. int multibus;
  533. /* Found one, init a host structure */
  534. host = kw_i2c_host_init(np);
  535. if (host == NULL)
  536. continue;
  537. /* Now check if we have a multibus setup (old style) or if we
  538. * have proper bus nodes. Note that the "new" way (proper bus
  539. * nodes) might cause us to not create some busses that are
  540. * kept hidden in the device-tree. In the future, we might
  541. * want to work around that by creating busses without a node
  542. * but not for now
  543. */
  544. child = of_get_next_child(np, NULL);
  545. multibus = !child || strcmp(child->name, "i2c-bus");
  546. of_node_put(child);
  547. /* For a multibus setup, we get the bus count based on the
  548. * parent type
  549. */
  550. if (multibus) {
  551. int chans, i;
  552. parent = of_get_parent(np);
  553. if (parent == NULL)
  554. continue;
  555. chans = parent->name[0] == 'u' ? 2 : 1;
  556. for (i = 0; i < chans; i++)
  557. kw_i2c_add(host, np, np, i);
  558. } else {
  559. for (child = NULL;
  560. (child = of_get_next_child(np, child)) != NULL;) {
  561. const u32 *reg = of_get_property(child,
  562. "reg", NULL);
  563. if (reg == NULL)
  564. continue;
  565. kw_i2c_add(host, np, child, *reg);
  566. }
  567. }
  568. }
  569. }
  570. /*
  571. *
  572. * PMU implementation
  573. *
  574. */
  575. #ifdef CONFIG_ADB_PMU
  576. /*
  577. * i2c command block to the PMU
  578. */
  579. struct pmu_i2c_hdr {
  580. u8 bus;
  581. u8 mode;
  582. u8 bus2;
  583. u8 address;
  584. u8 sub_addr;
  585. u8 comb_addr;
  586. u8 count;
  587. u8 data[];
  588. };
  589. static void pmu_i2c_complete(struct adb_request *req)
  590. {
  591. complete(req->arg);
  592. }
  593. static int pmu_i2c_xfer(struct pmac_i2c_bus *bus, u8 addrdir, int subsize,
  594. u32 subaddr, u8 *data, int len)
  595. {
  596. struct adb_request *req = bus->hostdata;
  597. struct pmu_i2c_hdr *hdr = (struct pmu_i2c_hdr *)&req->data[1];
  598. struct completion comp;
  599. int read = addrdir & 1;
  600. int retry;
  601. int rc = 0;
  602. /* For now, limit ourselves to 16 bytes transfers */
  603. if (len > 16)
  604. return -EINVAL;
  605. init_completion(&comp);
  606. for (retry = 0; retry < 16; retry++) {
  607. memset(req, 0, sizeof(struct adb_request));
  608. hdr->bus = bus->channel;
  609. hdr->count = len;
  610. switch(bus->mode) {
  611. case pmac_i2c_mode_std:
  612. if (subsize != 0)
  613. return -EINVAL;
  614. hdr->address = addrdir;
  615. hdr->mode = PMU_I2C_MODE_SIMPLE;
  616. break;
  617. case pmac_i2c_mode_stdsub:
  618. case pmac_i2c_mode_combined:
  619. if (subsize != 1)
  620. return -EINVAL;
  621. hdr->address = addrdir & 0xfe;
  622. hdr->comb_addr = addrdir;
  623. hdr->sub_addr = subaddr;
  624. if (bus->mode == pmac_i2c_mode_stdsub)
  625. hdr->mode = PMU_I2C_MODE_STDSUB;
  626. else
  627. hdr->mode = PMU_I2C_MODE_COMBINED;
  628. break;
  629. default:
  630. return -EINVAL;
  631. }
  632. reinit_completion(&comp);
  633. req->data[0] = PMU_I2C_CMD;
  634. req->reply[0] = 0xff;
  635. req->nbytes = sizeof(struct pmu_i2c_hdr) + 1;
  636. req->done = pmu_i2c_complete;
  637. req->arg = &comp;
  638. if (!read && len) {
  639. memcpy(hdr->data, data, len);
  640. req->nbytes += len;
  641. }
  642. rc = pmu_queue_request(req);
  643. if (rc)
  644. return rc;
  645. wait_for_completion(&comp);
  646. if (req->reply[0] == PMU_I2C_STATUS_OK)
  647. break;
  648. msleep(15);
  649. }
  650. if (req->reply[0] != PMU_I2C_STATUS_OK)
  651. return -EIO;
  652. for (retry = 0; retry < 16; retry++) {
  653. memset(req, 0, sizeof(struct adb_request));
  654. /* I know that looks like a lot, slow as hell, but darwin
  655. * does it so let's be on the safe side for now
  656. */
  657. msleep(15);
  658. hdr->bus = PMU_I2C_BUS_STATUS;
  659. reinit_completion(&comp);
  660. req->data[0] = PMU_I2C_CMD;
  661. req->reply[0] = 0xff;
  662. req->nbytes = 2;
  663. req->done = pmu_i2c_complete;
  664. req->arg = &comp;
  665. rc = pmu_queue_request(req);
  666. if (rc)
  667. return rc;
  668. wait_for_completion(&comp);
  669. if (req->reply[0] == PMU_I2C_STATUS_OK && !read)
  670. return 0;
  671. if (req->reply[0] == PMU_I2C_STATUS_DATAREAD && read) {
  672. int rlen = req->reply_len - 1;
  673. if (rlen != len) {
  674. printk(KERN_WARNING "low_i2c: PMU returned %d"
  675. " bytes, expected %d !\n", rlen, len);
  676. return -EIO;
  677. }
  678. if (len)
  679. memcpy(data, &req->reply[1], len);
  680. return 0;
  681. }
  682. }
  683. return -EIO;
  684. }
  685. static void __init pmu_i2c_probe(void)
  686. {
  687. struct pmac_i2c_bus *bus;
  688. struct device_node *busnode;
  689. int channel, sz;
  690. if (!pmu_present())
  691. return;
  692. /* There might or might not be a "pmu-i2c" node, we use that
  693. * or via-pmu itself, whatever we find. I haven't seen a machine
  694. * with separate bus nodes, so we assume a multibus setup
  695. */
  696. busnode = of_find_node_by_name(NULL, "pmu-i2c");
  697. if (busnode == NULL)
  698. busnode = of_find_node_by_name(NULL, "via-pmu");
  699. if (busnode == NULL)
  700. return;
  701. printk(KERN_INFO "PMU i2c %pOF\n", busnode);
  702. /*
  703. * We add bus 1 and 2 only for now, bus 0 is "special"
  704. */
  705. for (channel = 1; channel <= 2; channel++) {
  706. sz = sizeof(struct pmac_i2c_bus) + sizeof(struct adb_request);
  707. bus = kzalloc(sz, GFP_KERNEL);
  708. if (bus == NULL)
  709. return;
  710. bus->controller = busnode;
  711. bus->busnode = busnode;
  712. bus->type = pmac_i2c_bus_pmu;
  713. bus->channel = channel;
  714. bus->mode = pmac_i2c_mode_std;
  715. bus->hostdata = bus + 1;
  716. bus->xfer = pmu_i2c_xfer;
  717. mutex_init(&bus->mutex);
  718. lockdep_set_class(&bus->mutex, &bus->lock_key);
  719. bus->flags = pmac_i2c_multibus;
  720. list_add(&bus->link, &pmac_i2c_busses);
  721. printk(KERN_INFO " channel %d bus <multibus>\n", channel);
  722. }
  723. }
  724. #endif /* CONFIG_ADB_PMU */
  725. /*
  726. *
  727. * SMU implementation
  728. *
  729. */
  730. #ifdef CONFIG_PMAC_SMU
  731. static void smu_i2c_complete(struct smu_i2c_cmd *cmd, void *misc)
  732. {
  733. complete(misc);
  734. }
  735. static int smu_i2c_xfer(struct pmac_i2c_bus *bus, u8 addrdir, int subsize,
  736. u32 subaddr, u8 *data, int len)
  737. {
  738. struct smu_i2c_cmd *cmd = bus->hostdata;
  739. struct completion comp;
  740. int read = addrdir & 1;
  741. int rc = 0;
  742. if ((read && len > SMU_I2C_READ_MAX) ||
  743. ((!read) && len > SMU_I2C_WRITE_MAX))
  744. return -EINVAL;
  745. memset(cmd, 0, sizeof(struct smu_i2c_cmd));
  746. cmd->info.bus = bus->channel;
  747. cmd->info.devaddr = addrdir;
  748. cmd->info.datalen = len;
  749. switch(bus->mode) {
  750. case pmac_i2c_mode_std:
  751. if (subsize != 0)
  752. return -EINVAL;
  753. cmd->info.type = SMU_I2C_TRANSFER_SIMPLE;
  754. break;
  755. case pmac_i2c_mode_stdsub:
  756. case pmac_i2c_mode_combined:
  757. if (subsize > 3 || subsize < 1)
  758. return -EINVAL;
  759. cmd->info.sublen = subsize;
  760. /* that's big-endian only but heh ! */
  761. memcpy(&cmd->info.subaddr, ((char *)&subaddr) + (4 - subsize),
  762. subsize);
  763. if (bus->mode == pmac_i2c_mode_stdsub)
  764. cmd->info.type = SMU_I2C_TRANSFER_STDSUB;
  765. else
  766. cmd->info.type = SMU_I2C_TRANSFER_COMBINED;
  767. break;
  768. default:
  769. return -EINVAL;
  770. }
  771. if (!read && len)
  772. memcpy(cmd->info.data, data, len);
  773. init_completion(&comp);
  774. cmd->done = smu_i2c_complete;
  775. cmd->misc = &comp;
  776. rc = smu_queue_i2c(cmd);
  777. if (rc < 0)
  778. return rc;
  779. wait_for_completion(&comp);
  780. rc = cmd->status;
  781. if (read && len)
  782. memcpy(data, cmd->info.data, len);
  783. return rc < 0 ? rc : 0;
  784. }
  785. static void __init smu_i2c_probe(void)
  786. {
  787. struct device_node *controller, *busnode;
  788. struct pmac_i2c_bus *bus;
  789. const u32 *reg;
  790. int sz;
  791. if (!smu_present())
  792. return;
  793. controller = of_find_node_by_name(NULL, "smu-i2c-control");
  794. if (controller == NULL)
  795. controller = of_find_node_by_name(NULL, "smu");
  796. if (controller == NULL)
  797. return;
  798. printk(KERN_INFO "SMU i2c %pOF\n", controller);
  799. /* Look for childs, note that they might not be of the right
  800. * type as older device trees mix i2c busses and other things
  801. * at the same level
  802. */
  803. for (busnode = NULL;
  804. (busnode = of_get_next_child(controller, busnode)) != NULL;) {
  805. if (strcmp(busnode->type, "i2c") &&
  806. strcmp(busnode->type, "i2c-bus"))
  807. continue;
  808. reg = of_get_property(busnode, "reg", NULL);
  809. if (reg == NULL)
  810. continue;
  811. sz = sizeof(struct pmac_i2c_bus) + sizeof(struct smu_i2c_cmd);
  812. bus = kzalloc(sz, GFP_KERNEL);
  813. if (bus == NULL)
  814. return;
  815. bus->controller = controller;
  816. bus->busnode = of_node_get(busnode);
  817. bus->type = pmac_i2c_bus_smu;
  818. bus->channel = *reg;
  819. bus->mode = pmac_i2c_mode_std;
  820. bus->hostdata = bus + 1;
  821. bus->xfer = smu_i2c_xfer;
  822. mutex_init(&bus->mutex);
  823. lockdep_set_class(&bus->mutex, &bus->lock_key);
  824. bus->flags = 0;
  825. list_add(&bus->link, &pmac_i2c_busses);
  826. printk(KERN_INFO " channel %x bus %pOF\n",
  827. bus->channel, busnode);
  828. }
  829. }
  830. #endif /* CONFIG_PMAC_SMU */
  831. /*
  832. *
  833. * Core code
  834. *
  835. */
  836. struct pmac_i2c_bus *pmac_i2c_find_bus(struct device_node *node)
  837. {
  838. struct device_node *p = of_node_get(node);
  839. struct device_node *prev = NULL;
  840. struct pmac_i2c_bus *bus;
  841. while(p) {
  842. list_for_each_entry(bus, &pmac_i2c_busses, link) {
  843. if (p == bus->busnode) {
  844. if (prev && bus->flags & pmac_i2c_multibus) {
  845. const u32 *reg;
  846. reg = of_get_property(prev, "reg",
  847. NULL);
  848. if (!reg)
  849. continue;
  850. if (((*reg) >> 8) != bus->channel)
  851. continue;
  852. }
  853. of_node_put(p);
  854. of_node_put(prev);
  855. return bus;
  856. }
  857. }
  858. of_node_put(prev);
  859. prev = p;
  860. p = of_get_parent(p);
  861. }
  862. return NULL;
  863. }
  864. EXPORT_SYMBOL_GPL(pmac_i2c_find_bus);
  865. u8 pmac_i2c_get_dev_addr(struct device_node *device)
  866. {
  867. const u32 *reg = of_get_property(device, "reg", NULL);
  868. if (reg == NULL)
  869. return 0;
  870. return (*reg) & 0xff;
  871. }
  872. EXPORT_SYMBOL_GPL(pmac_i2c_get_dev_addr);
  873. struct device_node *pmac_i2c_get_controller(struct pmac_i2c_bus *bus)
  874. {
  875. return bus->controller;
  876. }
  877. EXPORT_SYMBOL_GPL(pmac_i2c_get_controller);
  878. struct device_node *pmac_i2c_get_bus_node(struct pmac_i2c_bus *bus)
  879. {
  880. return bus->busnode;
  881. }
  882. EXPORT_SYMBOL_GPL(pmac_i2c_get_bus_node);
  883. int pmac_i2c_get_type(struct pmac_i2c_bus *bus)
  884. {
  885. return bus->type;
  886. }
  887. EXPORT_SYMBOL_GPL(pmac_i2c_get_type);
  888. int pmac_i2c_get_flags(struct pmac_i2c_bus *bus)
  889. {
  890. return bus->flags;
  891. }
  892. EXPORT_SYMBOL_GPL(pmac_i2c_get_flags);
  893. int pmac_i2c_get_channel(struct pmac_i2c_bus *bus)
  894. {
  895. return bus->channel;
  896. }
  897. EXPORT_SYMBOL_GPL(pmac_i2c_get_channel);
  898. struct i2c_adapter *pmac_i2c_get_adapter(struct pmac_i2c_bus *bus)
  899. {
  900. return &bus->adapter;
  901. }
  902. EXPORT_SYMBOL_GPL(pmac_i2c_get_adapter);
  903. struct pmac_i2c_bus *pmac_i2c_adapter_to_bus(struct i2c_adapter *adapter)
  904. {
  905. struct pmac_i2c_bus *bus;
  906. list_for_each_entry(bus, &pmac_i2c_busses, link)
  907. if (&bus->adapter == adapter)
  908. return bus;
  909. return NULL;
  910. }
  911. EXPORT_SYMBOL_GPL(pmac_i2c_adapter_to_bus);
  912. int pmac_i2c_match_adapter(struct device_node *dev, struct i2c_adapter *adapter)
  913. {
  914. struct pmac_i2c_bus *bus = pmac_i2c_find_bus(dev);
  915. if (bus == NULL)
  916. return 0;
  917. return (&bus->adapter == adapter);
  918. }
  919. EXPORT_SYMBOL_GPL(pmac_i2c_match_adapter);
  920. int pmac_low_i2c_lock(struct device_node *np)
  921. {
  922. struct pmac_i2c_bus *bus, *found = NULL;
  923. list_for_each_entry(bus, &pmac_i2c_busses, link) {
  924. if (np == bus->controller) {
  925. found = bus;
  926. break;
  927. }
  928. }
  929. if (!found)
  930. return -ENODEV;
  931. return pmac_i2c_open(bus, 0);
  932. }
  933. EXPORT_SYMBOL_GPL(pmac_low_i2c_lock);
  934. int pmac_low_i2c_unlock(struct device_node *np)
  935. {
  936. struct pmac_i2c_bus *bus, *found = NULL;
  937. list_for_each_entry(bus, &pmac_i2c_busses, link) {
  938. if (np == bus->controller) {
  939. found = bus;
  940. break;
  941. }
  942. }
  943. if (!found)
  944. return -ENODEV;
  945. pmac_i2c_close(bus);
  946. return 0;
  947. }
  948. EXPORT_SYMBOL_GPL(pmac_low_i2c_unlock);
  949. int pmac_i2c_open(struct pmac_i2c_bus *bus, int polled)
  950. {
  951. int rc;
  952. mutex_lock(&bus->mutex);
  953. bus->polled = polled || pmac_i2c_force_poll;
  954. bus->opened = 1;
  955. bus->mode = pmac_i2c_mode_std;
  956. if (bus->open && (rc = bus->open(bus)) != 0) {
  957. bus->opened = 0;
  958. mutex_unlock(&bus->mutex);
  959. return rc;
  960. }
  961. return 0;
  962. }
  963. EXPORT_SYMBOL_GPL(pmac_i2c_open);
  964. void pmac_i2c_close(struct pmac_i2c_bus *bus)
  965. {
  966. WARN_ON(!bus->opened);
  967. if (bus->close)
  968. bus->close(bus);
  969. bus->opened = 0;
  970. mutex_unlock(&bus->mutex);
  971. }
  972. EXPORT_SYMBOL_GPL(pmac_i2c_close);
  973. int pmac_i2c_setmode(struct pmac_i2c_bus *bus, int mode)
  974. {
  975. WARN_ON(!bus->opened);
  976. /* Report me if you see the error below as there might be a new
  977. * "combined4" mode that I need to implement for the SMU bus
  978. */
  979. if (mode < pmac_i2c_mode_dumb || mode > pmac_i2c_mode_combined) {
  980. printk(KERN_ERR "low_i2c: Invalid mode %d requested on"
  981. " bus %pOF !\n", mode, bus->busnode);
  982. return -EINVAL;
  983. }
  984. bus->mode = mode;
  985. return 0;
  986. }
  987. EXPORT_SYMBOL_GPL(pmac_i2c_setmode);
  988. int pmac_i2c_xfer(struct pmac_i2c_bus *bus, u8 addrdir, int subsize,
  989. u32 subaddr, u8 *data, int len)
  990. {
  991. int rc;
  992. WARN_ON(!bus->opened);
  993. DBG("xfer() chan=%d, addrdir=0x%x, mode=%d, subsize=%d, subaddr=0x%x,"
  994. " %d bytes, bus %pOF\n", bus->channel, addrdir, bus->mode, subsize,
  995. subaddr, len, bus->busnode);
  996. rc = bus->xfer(bus, addrdir, subsize, subaddr, data, len);
  997. #ifdef DEBUG
  998. if (rc)
  999. DBG("xfer error %d\n", rc);
  1000. #endif
  1001. return rc;
  1002. }
  1003. EXPORT_SYMBOL_GPL(pmac_i2c_xfer);
  1004. /* some quirks for platform function decoding */
  1005. enum {
  1006. pmac_i2c_quirk_invmask = 0x00000001u,
  1007. pmac_i2c_quirk_skip = 0x00000002u,
  1008. };
  1009. static void pmac_i2c_devscan(void (*callback)(struct device_node *dev,
  1010. int quirks))
  1011. {
  1012. struct pmac_i2c_bus *bus;
  1013. struct device_node *np;
  1014. static struct whitelist_ent {
  1015. char *name;
  1016. char *compatible;
  1017. int quirks;
  1018. } whitelist[] = {
  1019. /* XXX Study device-tree's & apple drivers are get the quirks
  1020. * right !
  1021. */
  1022. /* Workaround: It seems that running the clockspreading
  1023. * properties on the eMac will cause lockups during boot.
  1024. * The machine seems to work fine without that. So for now,
  1025. * let's make sure i2c-hwclock doesn't match about "imic"
  1026. * clocks and we'll figure out if we really need to do
  1027. * something special about those later.
  1028. */
  1029. { "i2c-hwclock", "imic5002", pmac_i2c_quirk_skip },
  1030. { "i2c-hwclock", "imic5003", pmac_i2c_quirk_skip },
  1031. { "i2c-hwclock", NULL, pmac_i2c_quirk_invmask },
  1032. { "i2c-cpu-voltage", NULL, 0},
  1033. { "temp-monitor", NULL, 0 },
  1034. { "supply-monitor", NULL, 0 },
  1035. { NULL, NULL, 0 },
  1036. };
  1037. /* Only some devices need to have platform functions instantiated
  1038. * here. For now, we have a table. Others, like 9554 i2c GPIOs used
  1039. * on Xserve, if we ever do a driver for them, will use their own
  1040. * platform function instance
  1041. */
  1042. list_for_each_entry(bus, &pmac_i2c_busses, link) {
  1043. for (np = NULL;
  1044. (np = of_get_next_child(bus->busnode, np)) != NULL;) {
  1045. struct whitelist_ent *p;
  1046. /* If multibus, check if device is on that bus */
  1047. if (bus->flags & pmac_i2c_multibus)
  1048. if (bus != pmac_i2c_find_bus(np))
  1049. continue;
  1050. for (p = whitelist; p->name != NULL; p++) {
  1051. if (strcmp(np->name, p->name))
  1052. continue;
  1053. if (p->compatible &&
  1054. !of_device_is_compatible(np, p->compatible))
  1055. continue;
  1056. if (p->quirks & pmac_i2c_quirk_skip)
  1057. break;
  1058. callback(np, p->quirks);
  1059. break;
  1060. }
  1061. }
  1062. }
  1063. }
  1064. #define MAX_I2C_DATA 64
  1065. struct pmac_i2c_pf_inst
  1066. {
  1067. struct pmac_i2c_bus *bus;
  1068. u8 addr;
  1069. u8 buffer[MAX_I2C_DATA];
  1070. u8 scratch[MAX_I2C_DATA];
  1071. int bytes;
  1072. int quirks;
  1073. };
  1074. static void* pmac_i2c_do_begin(struct pmf_function *func, struct pmf_args *args)
  1075. {
  1076. struct pmac_i2c_pf_inst *inst;
  1077. struct pmac_i2c_bus *bus;
  1078. bus = pmac_i2c_find_bus(func->node);
  1079. if (bus == NULL) {
  1080. printk(KERN_ERR "low_i2c: Can't find bus for %pOF (pfunc)\n",
  1081. func->node);
  1082. return NULL;
  1083. }
  1084. if (pmac_i2c_open(bus, 0)) {
  1085. printk(KERN_ERR "low_i2c: Can't open i2c bus for %pOF (pfunc)\n",
  1086. func->node);
  1087. return NULL;
  1088. }
  1089. /* XXX might need GFP_ATOMIC when called during the suspend process,
  1090. * but then, there are already lots of issues with suspending when
  1091. * near OOM that need to be resolved, the allocator itself should
  1092. * probably make GFP_NOIO implicit during suspend
  1093. */
  1094. inst = kzalloc(sizeof(struct pmac_i2c_pf_inst), GFP_KERNEL);
  1095. if (inst == NULL) {
  1096. pmac_i2c_close(bus);
  1097. return NULL;
  1098. }
  1099. inst->bus = bus;
  1100. inst->addr = pmac_i2c_get_dev_addr(func->node);
  1101. inst->quirks = (int)(long)func->driver_data;
  1102. return inst;
  1103. }
  1104. static void pmac_i2c_do_end(struct pmf_function *func, void *instdata)
  1105. {
  1106. struct pmac_i2c_pf_inst *inst = instdata;
  1107. if (inst == NULL)
  1108. return;
  1109. pmac_i2c_close(inst->bus);
  1110. kfree(inst);
  1111. }
  1112. static int pmac_i2c_do_read(PMF_STD_ARGS, u32 len)
  1113. {
  1114. struct pmac_i2c_pf_inst *inst = instdata;
  1115. inst->bytes = len;
  1116. return pmac_i2c_xfer(inst->bus, inst->addr | pmac_i2c_read, 0, 0,
  1117. inst->buffer, len);
  1118. }
  1119. static int pmac_i2c_do_write(PMF_STD_ARGS, u32 len, const u8 *data)
  1120. {
  1121. struct pmac_i2c_pf_inst *inst = instdata;
  1122. return pmac_i2c_xfer(inst->bus, inst->addr | pmac_i2c_write, 0, 0,
  1123. (u8 *)data, len);
  1124. }
  1125. /* This function is used to do the masking & OR'ing for the "rmw" type
  1126. * callbacks. Ze should apply the mask and OR in the values in the
  1127. * buffer before writing back. The problem is that it seems that
  1128. * various darwin drivers implement the mask/or differently, thus
  1129. * we need to check the quirks first
  1130. */
  1131. static void pmac_i2c_do_apply_rmw(struct pmac_i2c_pf_inst *inst,
  1132. u32 len, const u8 *mask, const u8 *val)
  1133. {
  1134. int i;
  1135. if (inst->quirks & pmac_i2c_quirk_invmask) {
  1136. for (i = 0; i < len; i ++)
  1137. inst->scratch[i] = (inst->buffer[i] & mask[i]) | val[i];
  1138. } else {
  1139. for (i = 0; i < len; i ++)
  1140. inst->scratch[i] = (inst->buffer[i] & ~mask[i])
  1141. | (val[i] & mask[i]);
  1142. }
  1143. }
  1144. static int pmac_i2c_do_rmw(PMF_STD_ARGS, u32 masklen, u32 valuelen,
  1145. u32 totallen, const u8 *maskdata,
  1146. const u8 *valuedata)
  1147. {
  1148. struct pmac_i2c_pf_inst *inst = instdata;
  1149. if (masklen > inst->bytes || valuelen > inst->bytes ||
  1150. totallen > inst->bytes || valuelen > masklen)
  1151. return -EINVAL;
  1152. pmac_i2c_do_apply_rmw(inst, masklen, maskdata, valuedata);
  1153. return pmac_i2c_xfer(inst->bus, inst->addr | pmac_i2c_write, 0, 0,
  1154. inst->scratch, totallen);
  1155. }
  1156. static int pmac_i2c_do_read_sub(PMF_STD_ARGS, u8 subaddr, u32 len)
  1157. {
  1158. struct pmac_i2c_pf_inst *inst = instdata;
  1159. inst->bytes = len;
  1160. return pmac_i2c_xfer(inst->bus, inst->addr | pmac_i2c_read, 1, subaddr,
  1161. inst->buffer, len);
  1162. }
  1163. static int pmac_i2c_do_write_sub(PMF_STD_ARGS, u8 subaddr, u32 len,
  1164. const u8 *data)
  1165. {
  1166. struct pmac_i2c_pf_inst *inst = instdata;
  1167. return pmac_i2c_xfer(inst->bus, inst->addr | pmac_i2c_write, 1,
  1168. subaddr, (u8 *)data, len);
  1169. }
  1170. static int pmac_i2c_do_set_mode(PMF_STD_ARGS, int mode)
  1171. {
  1172. struct pmac_i2c_pf_inst *inst = instdata;
  1173. return pmac_i2c_setmode(inst->bus, mode);
  1174. }
  1175. static int pmac_i2c_do_rmw_sub(PMF_STD_ARGS, u8 subaddr, u32 masklen,
  1176. u32 valuelen, u32 totallen, const u8 *maskdata,
  1177. const u8 *valuedata)
  1178. {
  1179. struct pmac_i2c_pf_inst *inst = instdata;
  1180. if (masklen > inst->bytes || valuelen > inst->bytes ||
  1181. totallen > inst->bytes || valuelen > masklen)
  1182. return -EINVAL;
  1183. pmac_i2c_do_apply_rmw(inst, masklen, maskdata, valuedata);
  1184. return pmac_i2c_xfer(inst->bus, inst->addr | pmac_i2c_write, 1,
  1185. subaddr, inst->scratch, totallen);
  1186. }
  1187. static int pmac_i2c_do_mask_and_comp(PMF_STD_ARGS, u32 len,
  1188. const u8 *maskdata,
  1189. const u8 *valuedata)
  1190. {
  1191. struct pmac_i2c_pf_inst *inst = instdata;
  1192. int i, match;
  1193. /* Get return value pointer, it's assumed to be a u32 */
  1194. if (!args || !args->count || !args->u[0].p)
  1195. return -EINVAL;
  1196. /* Check buffer */
  1197. if (len > inst->bytes)
  1198. return -EINVAL;
  1199. for (i = 0, match = 1; match && i < len; i ++)
  1200. if ((inst->buffer[i] & maskdata[i]) != valuedata[i])
  1201. match = 0;
  1202. *args->u[0].p = match;
  1203. return 0;
  1204. }
  1205. static int pmac_i2c_do_delay(PMF_STD_ARGS, u32 duration)
  1206. {
  1207. msleep((duration + 999) / 1000);
  1208. return 0;
  1209. }
  1210. static struct pmf_handlers pmac_i2c_pfunc_handlers = {
  1211. .begin = pmac_i2c_do_begin,
  1212. .end = pmac_i2c_do_end,
  1213. .read_i2c = pmac_i2c_do_read,
  1214. .write_i2c = pmac_i2c_do_write,
  1215. .rmw_i2c = pmac_i2c_do_rmw,
  1216. .read_i2c_sub = pmac_i2c_do_read_sub,
  1217. .write_i2c_sub = pmac_i2c_do_write_sub,
  1218. .rmw_i2c_sub = pmac_i2c_do_rmw_sub,
  1219. .set_i2c_mode = pmac_i2c_do_set_mode,
  1220. .mask_and_compare = pmac_i2c_do_mask_and_comp,
  1221. .delay = pmac_i2c_do_delay,
  1222. };
  1223. static void __init pmac_i2c_dev_create(struct device_node *np, int quirks)
  1224. {
  1225. DBG("dev_create(%pOF)\n", np);
  1226. pmf_register_driver(np, &pmac_i2c_pfunc_handlers,
  1227. (void *)(long)quirks);
  1228. }
  1229. static void __init pmac_i2c_dev_init(struct device_node *np, int quirks)
  1230. {
  1231. DBG("dev_create(%pOF)\n", np);
  1232. pmf_do_functions(np, NULL, 0, PMF_FLAGS_ON_INIT, NULL);
  1233. }
  1234. static void pmac_i2c_dev_suspend(struct device_node *np, int quirks)
  1235. {
  1236. DBG("dev_suspend(%pOF)\n", np);
  1237. pmf_do_functions(np, NULL, 0, PMF_FLAGS_ON_SLEEP, NULL);
  1238. }
  1239. static void pmac_i2c_dev_resume(struct device_node *np, int quirks)
  1240. {
  1241. DBG("dev_resume(%pOF)\n", np);
  1242. pmf_do_functions(np, NULL, 0, PMF_FLAGS_ON_WAKE, NULL);
  1243. }
  1244. void pmac_pfunc_i2c_suspend(void)
  1245. {
  1246. pmac_i2c_devscan(pmac_i2c_dev_suspend);
  1247. }
  1248. void pmac_pfunc_i2c_resume(void)
  1249. {
  1250. pmac_i2c_devscan(pmac_i2c_dev_resume);
  1251. }
  1252. /*
  1253. * Initialize us: probe all i2c busses on the machine, instantiate
  1254. * busses and platform functions as needed.
  1255. */
  1256. /* This is non-static as it might be called early by smp code */
  1257. int __init pmac_i2c_init(void)
  1258. {
  1259. static int i2c_inited;
  1260. if (i2c_inited)
  1261. return 0;
  1262. i2c_inited = 1;
  1263. /* Probe keywest-i2c busses */
  1264. kw_i2c_probe();
  1265. #ifdef CONFIG_ADB_PMU
  1266. /* Probe PMU i2c busses */
  1267. pmu_i2c_probe();
  1268. #endif
  1269. #ifdef CONFIG_PMAC_SMU
  1270. /* Probe SMU i2c busses */
  1271. smu_i2c_probe();
  1272. #endif
  1273. /* Now add plaform functions for some known devices */
  1274. pmac_i2c_devscan(pmac_i2c_dev_create);
  1275. return 0;
  1276. }
  1277. machine_arch_initcall(powermac, pmac_i2c_init);
  1278. /* Since pmac_i2c_init can be called too early for the platform device
  1279. * registration, we need to do it at a later time. In our case, subsys
  1280. * happens to fit well, though I agree it's a bit of a hack...
  1281. */
  1282. static int __init pmac_i2c_create_platform_devices(void)
  1283. {
  1284. struct pmac_i2c_bus *bus;
  1285. int i = 0;
  1286. /* In the case where we are initialized from smp_init(), we must
  1287. * not use the timer (and thus the irq). It's safe from now on
  1288. * though
  1289. */
  1290. pmac_i2c_force_poll = 0;
  1291. /* Create platform devices */
  1292. list_for_each_entry(bus, &pmac_i2c_busses, link) {
  1293. bus->platform_dev =
  1294. platform_device_alloc("i2c-powermac", i++);
  1295. if (bus->platform_dev == NULL)
  1296. return -ENOMEM;
  1297. bus->platform_dev->dev.platform_data = bus;
  1298. bus->platform_dev->dev.of_node = bus->busnode;
  1299. platform_device_add(bus->platform_dev);
  1300. }
  1301. /* Now call platform "init" functions */
  1302. pmac_i2c_devscan(pmac_i2c_dev_init);
  1303. return 0;
  1304. }
  1305. machine_subsys_initcall(powermac, pmac_i2c_create_platform_devices);