vmwgfx_surface.c 45 KB

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  1. /**************************************************************************
  2. *
  3. * Copyright © 2009-2015 VMware, Inc., Palo Alto, CA., USA
  4. * All Rights Reserved.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the
  8. * "Software"), to deal in the Software without restriction, including
  9. * without limitation the rights to use, copy, modify, merge, publish,
  10. * distribute, sub license, and/or sell copies of the Software, and to
  11. * permit persons to whom the Software is furnished to do so, subject to
  12. * the following conditions:
  13. *
  14. * The above copyright notice and this permission notice (including the
  15. * next paragraph) shall be included in all copies or substantial portions
  16. * of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25. *
  26. **************************************************************************/
  27. #include <drm/ttm/ttm_placement.h>
  28. #include "vmwgfx_drv.h"
  29. #include "vmwgfx_resource_priv.h"
  30. #include "vmwgfx_so.h"
  31. #include "vmwgfx_binding.h"
  32. #include "device_include/svga3d_surfacedefs.h"
  33. /**
  34. * struct vmw_user_surface - User-space visible surface resource
  35. *
  36. * @base: The TTM base object handling user-space visibility.
  37. * @srf: The surface metadata.
  38. * @size: TTM accounting size for the surface.
  39. * @master: master of the creating client. Used for security check.
  40. */
  41. struct vmw_user_surface {
  42. struct ttm_prime_object prime;
  43. struct vmw_surface srf;
  44. uint32_t size;
  45. struct drm_master *master;
  46. struct ttm_base_object *backup_base;
  47. };
  48. /**
  49. * struct vmw_surface_offset - Backing store mip level offset info
  50. *
  51. * @face: Surface face.
  52. * @mip: Mip level.
  53. * @bo_offset: Offset into backing store of this mip level.
  54. *
  55. */
  56. struct vmw_surface_offset {
  57. uint32_t face;
  58. uint32_t mip;
  59. uint32_t bo_offset;
  60. };
  61. static void vmw_user_surface_free(struct vmw_resource *res);
  62. static struct vmw_resource *
  63. vmw_user_surface_base_to_res(struct ttm_base_object *base);
  64. static int vmw_legacy_srf_bind(struct vmw_resource *res,
  65. struct ttm_validate_buffer *val_buf);
  66. static int vmw_legacy_srf_unbind(struct vmw_resource *res,
  67. bool readback,
  68. struct ttm_validate_buffer *val_buf);
  69. static int vmw_legacy_srf_create(struct vmw_resource *res);
  70. static int vmw_legacy_srf_destroy(struct vmw_resource *res);
  71. static int vmw_gb_surface_create(struct vmw_resource *res);
  72. static int vmw_gb_surface_bind(struct vmw_resource *res,
  73. struct ttm_validate_buffer *val_buf);
  74. static int vmw_gb_surface_unbind(struct vmw_resource *res,
  75. bool readback,
  76. struct ttm_validate_buffer *val_buf);
  77. static int vmw_gb_surface_destroy(struct vmw_resource *res);
  78. static const struct vmw_user_resource_conv user_surface_conv = {
  79. .object_type = VMW_RES_SURFACE,
  80. .base_obj_to_res = vmw_user_surface_base_to_res,
  81. .res_free = vmw_user_surface_free
  82. };
  83. const struct vmw_user_resource_conv *user_surface_converter =
  84. &user_surface_conv;
  85. static uint64_t vmw_user_surface_size;
  86. static const struct vmw_res_func vmw_legacy_surface_func = {
  87. .res_type = vmw_res_surface,
  88. .needs_backup = false,
  89. .may_evict = true,
  90. .type_name = "legacy surfaces",
  91. .backup_placement = &vmw_srf_placement,
  92. .create = &vmw_legacy_srf_create,
  93. .destroy = &vmw_legacy_srf_destroy,
  94. .bind = &vmw_legacy_srf_bind,
  95. .unbind = &vmw_legacy_srf_unbind
  96. };
  97. static const struct vmw_res_func vmw_gb_surface_func = {
  98. .res_type = vmw_res_surface,
  99. .needs_backup = true,
  100. .may_evict = true,
  101. .type_name = "guest backed surfaces",
  102. .backup_placement = &vmw_mob_placement,
  103. .create = vmw_gb_surface_create,
  104. .destroy = vmw_gb_surface_destroy,
  105. .bind = vmw_gb_surface_bind,
  106. .unbind = vmw_gb_surface_unbind
  107. };
  108. /**
  109. * struct vmw_surface_dma - SVGA3D DMA command
  110. */
  111. struct vmw_surface_dma {
  112. SVGA3dCmdHeader header;
  113. SVGA3dCmdSurfaceDMA body;
  114. SVGA3dCopyBox cb;
  115. SVGA3dCmdSurfaceDMASuffix suffix;
  116. };
  117. /**
  118. * struct vmw_surface_define - SVGA3D Surface Define command
  119. */
  120. struct vmw_surface_define {
  121. SVGA3dCmdHeader header;
  122. SVGA3dCmdDefineSurface body;
  123. };
  124. /**
  125. * struct vmw_surface_destroy - SVGA3D Surface Destroy command
  126. */
  127. struct vmw_surface_destroy {
  128. SVGA3dCmdHeader header;
  129. SVGA3dCmdDestroySurface body;
  130. };
  131. /**
  132. * vmw_surface_dma_size - Compute fifo size for a dma command.
  133. *
  134. * @srf: Pointer to a struct vmw_surface
  135. *
  136. * Computes the required size for a surface dma command for backup or
  137. * restoration of the surface represented by @srf.
  138. */
  139. static inline uint32_t vmw_surface_dma_size(const struct vmw_surface *srf)
  140. {
  141. return srf->num_sizes * sizeof(struct vmw_surface_dma);
  142. }
  143. /**
  144. * vmw_surface_define_size - Compute fifo size for a surface define command.
  145. *
  146. * @srf: Pointer to a struct vmw_surface
  147. *
  148. * Computes the required size for a surface define command for the definition
  149. * of the surface represented by @srf.
  150. */
  151. static inline uint32_t vmw_surface_define_size(const struct vmw_surface *srf)
  152. {
  153. return sizeof(struct vmw_surface_define) + srf->num_sizes *
  154. sizeof(SVGA3dSize);
  155. }
  156. /**
  157. * vmw_surface_destroy_size - Compute fifo size for a surface destroy command.
  158. *
  159. * Computes the required size for a surface destroy command for the destruction
  160. * of a hw surface.
  161. */
  162. static inline uint32_t vmw_surface_destroy_size(void)
  163. {
  164. return sizeof(struct vmw_surface_destroy);
  165. }
  166. /**
  167. * vmw_surface_destroy_encode - Encode a surface_destroy command.
  168. *
  169. * @id: The surface id
  170. * @cmd_space: Pointer to memory area in which the commands should be encoded.
  171. */
  172. static void vmw_surface_destroy_encode(uint32_t id,
  173. void *cmd_space)
  174. {
  175. struct vmw_surface_destroy *cmd = (struct vmw_surface_destroy *)
  176. cmd_space;
  177. cmd->header.id = SVGA_3D_CMD_SURFACE_DESTROY;
  178. cmd->header.size = sizeof(cmd->body);
  179. cmd->body.sid = id;
  180. }
  181. /**
  182. * vmw_surface_define_encode - Encode a surface_define command.
  183. *
  184. * @srf: Pointer to a struct vmw_surface object.
  185. * @cmd_space: Pointer to memory area in which the commands should be encoded.
  186. */
  187. static void vmw_surface_define_encode(const struct vmw_surface *srf,
  188. void *cmd_space)
  189. {
  190. struct vmw_surface_define *cmd = (struct vmw_surface_define *)
  191. cmd_space;
  192. struct drm_vmw_size *src_size;
  193. SVGA3dSize *cmd_size;
  194. uint32_t cmd_len;
  195. int i;
  196. cmd_len = sizeof(cmd->body) + srf->num_sizes * sizeof(SVGA3dSize);
  197. cmd->header.id = SVGA_3D_CMD_SURFACE_DEFINE;
  198. cmd->header.size = cmd_len;
  199. cmd->body.sid = srf->res.id;
  200. /*
  201. * Downcast of surfaceFlags, was upcasted when received from user-space,
  202. * since driver internally stores as 64 bit.
  203. * For legacy surface define only 32 bit flag is supported.
  204. */
  205. cmd->body.surfaceFlags = (SVGA3dSurface1Flags)srf->flags;
  206. cmd->body.format = srf->format;
  207. for (i = 0; i < DRM_VMW_MAX_SURFACE_FACES; ++i)
  208. cmd->body.face[i].numMipLevels = srf->mip_levels[i];
  209. cmd += 1;
  210. cmd_size = (SVGA3dSize *) cmd;
  211. src_size = srf->sizes;
  212. for (i = 0; i < srf->num_sizes; ++i, cmd_size++, src_size++) {
  213. cmd_size->width = src_size->width;
  214. cmd_size->height = src_size->height;
  215. cmd_size->depth = src_size->depth;
  216. }
  217. }
  218. /**
  219. * vmw_surface_dma_encode - Encode a surface_dma command.
  220. *
  221. * @srf: Pointer to a struct vmw_surface object.
  222. * @cmd_space: Pointer to memory area in which the commands should be encoded.
  223. * @ptr: Pointer to an SVGAGuestPtr indicating where the surface contents
  224. * should be placed or read from.
  225. * @to_surface: Boolean whether to DMA to the surface or from the surface.
  226. */
  227. static void vmw_surface_dma_encode(struct vmw_surface *srf,
  228. void *cmd_space,
  229. const SVGAGuestPtr *ptr,
  230. bool to_surface)
  231. {
  232. uint32_t i;
  233. struct vmw_surface_dma *cmd = (struct vmw_surface_dma *)cmd_space;
  234. const struct svga3d_surface_desc *desc =
  235. svga3dsurface_get_desc(srf->format);
  236. for (i = 0; i < srf->num_sizes; ++i) {
  237. SVGA3dCmdHeader *header = &cmd->header;
  238. SVGA3dCmdSurfaceDMA *body = &cmd->body;
  239. SVGA3dCopyBox *cb = &cmd->cb;
  240. SVGA3dCmdSurfaceDMASuffix *suffix = &cmd->suffix;
  241. const struct vmw_surface_offset *cur_offset = &srf->offsets[i];
  242. const struct drm_vmw_size *cur_size = &srf->sizes[i];
  243. header->id = SVGA_3D_CMD_SURFACE_DMA;
  244. header->size = sizeof(*body) + sizeof(*cb) + sizeof(*suffix);
  245. body->guest.ptr = *ptr;
  246. body->guest.ptr.offset += cur_offset->bo_offset;
  247. body->guest.pitch = svga3dsurface_calculate_pitch(desc,
  248. cur_size);
  249. body->host.sid = srf->res.id;
  250. body->host.face = cur_offset->face;
  251. body->host.mipmap = cur_offset->mip;
  252. body->transfer = ((to_surface) ? SVGA3D_WRITE_HOST_VRAM :
  253. SVGA3D_READ_HOST_VRAM);
  254. cb->x = 0;
  255. cb->y = 0;
  256. cb->z = 0;
  257. cb->srcx = 0;
  258. cb->srcy = 0;
  259. cb->srcz = 0;
  260. cb->w = cur_size->width;
  261. cb->h = cur_size->height;
  262. cb->d = cur_size->depth;
  263. suffix->suffixSize = sizeof(*suffix);
  264. suffix->maximumOffset =
  265. svga3dsurface_get_image_buffer_size(desc, cur_size,
  266. body->guest.pitch);
  267. suffix->flags.discard = 0;
  268. suffix->flags.unsynchronized = 0;
  269. suffix->flags.reserved = 0;
  270. ++cmd;
  271. }
  272. };
  273. /**
  274. * vmw_hw_surface_destroy - destroy a Device surface
  275. *
  276. * @res: Pointer to a struct vmw_resource embedded in a struct
  277. * vmw_surface.
  278. *
  279. * Destroys a the device surface associated with a struct vmw_surface if
  280. * any, and adjusts accounting and resource count accordingly.
  281. */
  282. static void vmw_hw_surface_destroy(struct vmw_resource *res)
  283. {
  284. struct vmw_private *dev_priv = res->dev_priv;
  285. struct vmw_surface *srf;
  286. void *cmd;
  287. if (res->func->destroy == vmw_gb_surface_destroy) {
  288. (void) vmw_gb_surface_destroy(res);
  289. return;
  290. }
  291. if (res->id != -1) {
  292. cmd = vmw_fifo_reserve(dev_priv, vmw_surface_destroy_size());
  293. if (unlikely(!cmd)) {
  294. DRM_ERROR("Failed reserving FIFO space for surface "
  295. "destruction.\n");
  296. return;
  297. }
  298. vmw_surface_destroy_encode(res->id, cmd);
  299. vmw_fifo_commit(dev_priv, vmw_surface_destroy_size());
  300. /*
  301. * used_memory_size_atomic, or separate lock
  302. * to avoid taking dev_priv::cmdbuf_mutex in
  303. * the destroy path.
  304. */
  305. mutex_lock(&dev_priv->cmdbuf_mutex);
  306. srf = vmw_res_to_srf(res);
  307. dev_priv->used_memory_size -= res->backup_size;
  308. mutex_unlock(&dev_priv->cmdbuf_mutex);
  309. }
  310. }
  311. /**
  312. * vmw_legacy_srf_create - Create a device surface as part of the
  313. * resource validation process.
  314. *
  315. * @res: Pointer to a struct vmw_surface.
  316. *
  317. * If the surface doesn't have a hw id.
  318. *
  319. * Returns -EBUSY if there wasn't sufficient device resources to
  320. * complete the validation. Retry after freeing up resources.
  321. *
  322. * May return other errors if the kernel is out of guest resources.
  323. */
  324. static int vmw_legacy_srf_create(struct vmw_resource *res)
  325. {
  326. struct vmw_private *dev_priv = res->dev_priv;
  327. struct vmw_surface *srf;
  328. uint32_t submit_size;
  329. uint8_t *cmd;
  330. int ret;
  331. if (likely(res->id != -1))
  332. return 0;
  333. srf = vmw_res_to_srf(res);
  334. if (unlikely(dev_priv->used_memory_size + res->backup_size >=
  335. dev_priv->memory_size))
  336. return -EBUSY;
  337. /*
  338. * Alloc id for the resource.
  339. */
  340. ret = vmw_resource_alloc_id(res);
  341. if (unlikely(ret != 0)) {
  342. DRM_ERROR("Failed to allocate a surface id.\n");
  343. goto out_no_id;
  344. }
  345. if (unlikely(res->id >= SVGA3D_MAX_SURFACE_IDS)) {
  346. ret = -EBUSY;
  347. goto out_no_fifo;
  348. }
  349. /*
  350. * Encode surface define- commands.
  351. */
  352. submit_size = vmw_surface_define_size(srf);
  353. cmd = vmw_fifo_reserve(dev_priv, submit_size);
  354. if (unlikely(!cmd)) {
  355. DRM_ERROR("Failed reserving FIFO space for surface "
  356. "creation.\n");
  357. ret = -ENOMEM;
  358. goto out_no_fifo;
  359. }
  360. vmw_surface_define_encode(srf, cmd);
  361. vmw_fifo_commit(dev_priv, submit_size);
  362. vmw_fifo_resource_inc(dev_priv);
  363. /*
  364. * Surface memory usage accounting.
  365. */
  366. dev_priv->used_memory_size += res->backup_size;
  367. return 0;
  368. out_no_fifo:
  369. vmw_resource_release_id(res);
  370. out_no_id:
  371. return ret;
  372. }
  373. /**
  374. * vmw_legacy_srf_dma - Copy backup data to or from a legacy surface.
  375. *
  376. * @res: Pointer to a struct vmw_res embedded in a struct
  377. * vmw_surface.
  378. * @val_buf: Pointer to a struct ttm_validate_buffer containing
  379. * information about the backup buffer.
  380. * @bind: Boolean wether to DMA to the surface.
  381. *
  382. * Transfer backup data to or from a legacy surface as part of the
  383. * validation process.
  384. * May return other errors if the kernel is out of guest resources.
  385. * The backup buffer will be fenced or idle upon successful completion,
  386. * and if the surface needs persistent backup storage, the backup buffer
  387. * will also be returned reserved iff @bind is true.
  388. */
  389. static int vmw_legacy_srf_dma(struct vmw_resource *res,
  390. struct ttm_validate_buffer *val_buf,
  391. bool bind)
  392. {
  393. SVGAGuestPtr ptr;
  394. struct vmw_fence_obj *fence;
  395. uint32_t submit_size;
  396. struct vmw_surface *srf = vmw_res_to_srf(res);
  397. uint8_t *cmd;
  398. struct vmw_private *dev_priv = res->dev_priv;
  399. BUG_ON(!val_buf->bo);
  400. submit_size = vmw_surface_dma_size(srf);
  401. cmd = vmw_fifo_reserve(dev_priv, submit_size);
  402. if (unlikely(!cmd)) {
  403. DRM_ERROR("Failed reserving FIFO space for surface "
  404. "DMA.\n");
  405. return -ENOMEM;
  406. }
  407. vmw_bo_get_guest_ptr(val_buf->bo, &ptr);
  408. vmw_surface_dma_encode(srf, cmd, &ptr, bind);
  409. vmw_fifo_commit(dev_priv, submit_size);
  410. /*
  411. * Create a fence object and fence the backup buffer.
  412. */
  413. (void) vmw_execbuf_fence_commands(NULL, dev_priv,
  414. &fence, NULL);
  415. vmw_bo_fence_single(val_buf->bo, fence);
  416. if (likely(fence != NULL))
  417. vmw_fence_obj_unreference(&fence);
  418. return 0;
  419. }
  420. /**
  421. * vmw_legacy_srf_bind - Perform a legacy surface bind as part of the
  422. * surface validation process.
  423. *
  424. * @res: Pointer to a struct vmw_res embedded in a struct
  425. * vmw_surface.
  426. * @val_buf: Pointer to a struct ttm_validate_buffer containing
  427. * information about the backup buffer.
  428. *
  429. * This function will copy backup data to the surface if the
  430. * backup buffer is dirty.
  431. */
  432. static int vmw_legacy_srf_bind(struct vmw_resource *res,
  433. struct ttm_validate_buffer *val_buf)
  434. {
  435. if (!res->backup_dirty)
  436. return 0;
  437. return vmw_legacy_srf_dma(res, val_buf, true);
  438. }
  439. /**
  440. * vmw_legacy_srf_unbind - Perform a legacy surface unbind as part of the
  441. * surface eviction process.
  442. *
  443. * @res: Pointer to a struct vmw_res embedded in a struct
  444. * vmw_surface.
  445. * @val_buf: Pointer to a struct ttm_validate_buffer containing
  446. * information about the backup buffer.
  447. *
  448. * This function will copy backup data from the surface.
  449. */
  450. static int vmw_legacy_srf_unbind(struct vmw_resource *res,
  451. bool readback,
  452. struct ttm_validate_buffer *val_buf)
  453. {
  454. if (unlikely(readback))
  455. return vmw_legacy_srf_dma(res, val_buf, false);
  456. return 0;
  457. }
  458. /**
  459. * vmw_legacy_srf_destroy - Destroy a device surface as part of a
  460. * resource eviction process.
  461. *
  462. * @res: Pointer to a struct vmw_res embedded in a struct
  463. * vmw_surface.
  464. */
  465. static int vmw_legacy_srf_destroy(struct vmw_resource *res)
  466. {
  467. struct vmw_private *dev_priv = res->dev_priv;
  468. uint32_t submit_size;
  469. uint8_t *cmd;
  470. BUG_ON(res->id == -1);
  471. /*
  472. * Encode the dma- and surface destroy commands.
  473. */
  474. submit_size = vmw_surface_destroy_size();
  475. cmd = vmw_fifo_reserve(dev_priv, submit_size);
  476. if (unlikely(!cmd)) {
  477. DRM_ERROR("Failed reserving FIFO space for surface "
  478. "eviction.\n");
  479. return -ENOMEM;
  480. }
  481. vmw_surface_destroy_encode(res->id, cmd);
  482. vmw_fifo_commit(dev_priv, submit_size);
  483. /*
  484. * Surface memory usage accounting.
  485. */
  486. dev_priv->used_memory_size -= res->backup_size;
  487. /*
  488. * Release the surface ID.
  489. */
  490. vmw_resource_release_id(res);
  491. vmw_fifo_resource_dec(dev_priv);
  492. return 0;
  493. }
  494. /**
  495. * vmw_surface_init - initialize a struct vmw_surface
  496. *
  497. * @dev_priv: Pointer to a device private struct.
  498. * @srf: Pointer to the struct vmw_surface to initialize.
  499. * @res_free: Pointer to a resource destructor used to free
  500. * the object.
  501. */
  502. static int vmw_surface_init(struct vmw_private *dev_priv,
  503. struct vmw_surface *srf,
  504. void (*res_free) (struct vmw_resource *res))
  505. {
  506. int ret;
  507. struct vmw_resource *res = &srf->res;
  508. BUG_ON(!res_free);
  509. ret = vmw_resource_init(dev_priv, res, true, res_free,
  510. (dev_priv->has_mob) ? &vmw_gb_surface_func :
  511. &vmw_legacy_surface_func);
  512. if (unlikely(ret != 0)) {
  513. res_free(res);
  514. return ret;
  515. }
  516. /*
  517. * The surface won't be visible to hardware until a
  518. * surface validate.
  519. */
  520. INIT_LIST_HEAD(&srf->view_list);
  521. vmw_resource_activate(res, vmw_hw_surface_destroy);
  522. return ret;
  523. }
  524. /**
  525. * vmw_user_surface_base_to_res - TTM base object to resource converter for
  526. * user visible surfaces
  527. *
  528. * @base: Pointer to a TTM base object
  529. *
  530. * Returns the struct vmw_resource embedded in a struct vmw_surface
  531. * for the user-visible object identified by the TTM base object @base.
  532. */
  533. static struct vmw_resource *
  534. vmw_user_surface_base_to_res(struct ttm_base_object *base)
  535. {
  536. return &(container_of(base, struct vmw_user_surface,
  537. prime.base)->srf.res);
  538. }
  539. /**
  540. * vmw_user_surface_free - User visible surface resource destructor
  541. *
  542. * @res: A struct vmw_resource embedded in a struct vmw_surface.
  543. */
  544. static void vmw_user_surface_free(struct vmw_resource *res)
  545. {
  546. struct vmw_surface *srf = vmw_res_to_srf(res);
  547. struct vmw_user_surface *user_srf =
  548. container_of(srf, struct vmw_user_surface, srf);
  549. struct vmw_private *dev_priv = srf->res.dev_priv;
  550. uint32_t size = user_srf->size;
  551. if (user_srf->master)
  552. drm_master_put(&user_srf->master);
  553. kfree(srf->offsets);
  554. kfree(srf->sizes);
  555. kfree(srf->snooper.image);
  556. ttm_prime_object_kfree(user_srf, prime);
  557. ttm_mem_global_free(vmw_mem_glob(dev_priv), size);
  558. }
  559. /**
  560. * vmw_user_surface_free - User visible surface TTM base object destructor
  561. *
  562. * @p_base: Pointer to a pointer to a TTM base object
  563. * embedded in a struct vmw_user_surface.
  564. *
  565. * Drops the base object's reference on its resource, and the
  566. * pointer pointed to by *p_base is set to NULL.
  567. */
  568. static void vmw_user_surface_base_release(struct ttm_base_object **p_base)
  569. {
  570. struct ttm_base_object *base = *p_base;
  571. struct vmw_user_surface *user_srf =
  572. container_of(base, struct vmw_user_surface, prime.base);
  573. struct vmw_resource *res = &user_srf->srf.res;
  574. *p_base = NULL;
  575. if (user_srf->backup_base)
  576. ttm_base_object_unref(&user_srf->backup_base);
  577. vmw_resource_unreference(&res);
  578. }
  579. /**
  580. * vmw_user_surface_destroy_ioctl - Ioctl function implementing
  581. * the user surface destroy functionality.
  582. *
  583. * @dev: Pointer to a struct drm_device.
  584. * @data: Pointer to data copied from / to user-space.
  585. * @file_priv: Pointer to a drm file private structure.
  586. */
  587. int vmw_surface_destroy_ioctl(struct drm_device *dev, void *data,
  588. struct drm_file *file_priv)
  589. {
  590. struct drm_vmw_surface_arg *arg = (struct drm_vmw_surface_arg *)data;
  591. struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
  592. return ttm_ref_object_base_unref(tfile, arg->sid, TTM_REF_USAGE);
  593. }
  594. /**
  595. * vmw_user_surface_define_ioctl - Ioctl function implementing
  596. * the user surface define functionality.
  597. *
  598. * @dev: Pointer to a struct drm_device.
  599. * @data: Pointer to data copied from / to user-space.
  600. * @file_priv: Pointer to a drm file private structure.
  601. */
  602. int vmw_surface_define_ioctl(struct drm_device *dev, void *data,
  603. struct drm_file *file_priv)
  604. {
  605. struct vmw_private *dev_priv = vmw_priv(dev);
  606. struct vmw_user_surface *user_srf;
  607. struct vmw_surface *srf;
  608. struct vmw_resource *res;
  609. struct vmw_resource *tmp;
  610. union drm_vmw_surface_create_arg *arg =
  611. (union drm_vmw_surface_create_arg *)data;
  612. struct drm_vmw_surface_create_req *req = &arg->req;
  613. struct drm_vmw_surface_arg *rep = &arg->rep;
  614. struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
  615. struct ttm_operation_ctx ctx = {
  616. .interruptible = true,
  617. .no_wait_gpu = false
  618. };
  619. int ret;
  620. int i, j;
  621. uint32_t cur_bo_offset;
  622. struct drm_vmw_size *cur_size;
  623. struct vmw_surface_offset *cur_offset;
  624. uint32_t num_sizes;
  625. uint32_t size;
  626. const struct svga3d_surface_desc *desc;
  627. if (unlikely(vmw_user_surface_size == 0))
  628. vmw_user_surface_size = ttm_round_pot(sizeof(*user_srf)) +
  629. 128;
  630. num_sizes = 0;
  631. for (i = 0; i < DRM_VMW_MAX_SURFACE_FACES; ++i) {
  632. if (req->mip_levels[i] > DRM_VMW_MAX_MIP_LEVELS)
  633. return -EINVAL;
  634. num_sizes += req->mip_levels[i];
  635. }
  636. if (num_sizes > DRM_VMW_MAX_SURFACE_FACES * DRM_VMW_MAX_MIP_LEVELS ||
  637. num_sizes == 0)
  638. return -EINVAL;
  639. size = vmw_user_surface_size + 128 +
  640. ttm_round_pot(num_sizes * sizeof(struct drm_vmw_size)) +
  641. ttm_round_pot(num_sizes * sizeof(struct vmw_surface_offset));
  642. desc = svga3dsurface_get_desc(req->format);
  643. if (unlikely(desc->block_desc == SVGA3DBLOCKDESC_NONE)) {
  644. DRM_ERROR("Invalid surface format for surface creation.\n");
  645. DRM_ERROR("Format requested is: %d\n", req->format);
  646. return -EINVAL;
  647. }
  648. ret = ttm_read_lock(&dev_priv->reservation_sem, true);
  649. if (unlikely(ret != 0))
  650. return ret;
  651. ret = ttm_mem_global_alloc(vmw_mem_glob(dev_priv),
  652. size, &ctx);
  653. if (unlikely(ret != 0)) {
  654. if (ret != -ERESTARTSYS)
  655. DRM_ERROR("Out of graphics memory for surface"
  656. " creation.\n");
  657. goto out_unlock;
  658. }
  659. user_srf = kzalloc(sizeof(*user_srf), GFP_KERNEL);
  660. if (unlikely(!user_srf)) {
  661. ret = -ENOMEM;
  662. goto out_no_user_srf;
  663. }
  664. srf = &user_srf->srf;
  665. res = &srf->res;
  666. /* Driver internally stores as 64-bit flags */
  667. srf->flags = (SVGA3dSurfaceAllFlags)req->flags;
  668. srf->format = req->format;
  669. srf->scanout = req->scanout;
  670. memcpy(srf->mip_levels, req->mip_levels, sizeof(srf->mip_levels));
  671. srf->num_sizes = num_sizes;
  672. user_srf->size = size;
  673. srf->sizes = memdup_user((struct drm_vmw_size __user *)(unsigned long)
  674. req->size_addr,
  675. sizeof(*srf->sizes) * srf->num_sizes);
  676. if (IS_ERR(srf->sizes)) {
  677. ret = PTR_ERR(srf->sizes);
  678. goto out_no_sizes;
  679. }
  680. srf->offsets = kmalloc_array(srf->num_sizes,
  681. sizeof(*srf->offsets),
  682. GFP_KERNEL);
  683. if (unlikely(!srf->offsets)) {
  684. ret = -ENOMEM;
  685. goto out_no_offsets;
  686. }
  687. srf->base_size = *srf->sizes;
  688. srf->autogen_filter = SVGA3D_TEX_FILTER_NONE;
  689. srf->multisample_count = 0;
  690. srf->multisample_pattern = SVGA3D_MS_PATTERN_NONE;
  691. srf->quality_level = SVGA3D_MS_QUALITY_NONE;
  692. cur_bo_offset = 0;
  693. cur_offset = srf->offsets;
  694. cur_size = srf->sizes;
  695. for (i = 0; i < DRM_VMW_MAX_SURFACE_FACES; ++i) {
  696. for (j = 0; j < srf->mip_levels[i]; ++j) {
  697. uint32_t stride = svga3dsurface_calculate_pitch
  698. (desc, cur_size);
  699. cur_offset->face = i;
  700. cur_offset->mip = j;
  701. cur_offset->bo_offset = cur_bo_offset;
  702. cur_bo_offset += svga3dsurface_get_image_buffer_size
  703. (desc, cur_size, stride);
  704. ++cur_offset;
  705. ++cur_size;
  706. }
  707. }
  708. res->backup_size = cur_bo_offset;
  709. if (srf->scanout &&
  710. srf->num_sizes == 1 &&
  711. srf->sizes[0].width == 64 &&
  712. srf->sizes[0].height == 64 &&
  713. srf->format == SVGA3D_A8R8G8B8) {
  714. srf->snooper.image = kzalloc(64 * 64 * 4, GFP_KERNEL);
  715. if (!srf->snooper.image) {
  716. DRM_ERROR("Failed to allocate cursor_image\n");
  717. ret = -ENOMEM;
  718. goto out_no_copy;
  719. }
  720. } else {
  721. srf->snooper.image = NULL;
  722. }
  723. user_srf->prime.base.shareable = false;
  724. user_srf->prime.base.tfile = NULL;
  725. if (drm_is_primary_client(file_priv))
  726. user_srf->master = drm_master_get(file_priv->master);
  727. /**
  728. * From this point, the generic resource management functions
  729. * destroy the object on failure.
  730. */
  731. ret = vmw_surface_init(dev_priv, srf, vmw_user_surface_free);
  732. if (unlikely(ret != 0))
  733. goto out_unlock;
  734. /*
  735. * A gb-aware client referencing a shared surface will
  736. * expect a backup buffer to be present.
  737. */
  738. if (dev_priv->has_mob && req->shareable) {
  739. uint32_t backup_handle;
  740. ret = vmw_user_bo_alloc(dev_priv, tfile,
  741. res->backup_size,
  742. true,
  743. &backup_handle,
  744. &res->backup,
  745. &user_srf->backup_base);
  746. if (unlikely(ret != 0)) {
  747. vmw_resource_unreference(&res);
  748. goto out_unlock;
  749. }
  750. }
  751. tmp = vmw_resource_reference(&srf->res);
  752. ret = ttm_prime_object_init(tfile, res->backup_size, &user_srf->prime,
  753. req->shareable, VMW_RES_SURFACE,
  754. &vmw_user_surface_base_release, NULL);
  755. if (unlikely(ret != 0)) {
  756. vmw_resource_unreference(&tmp);
  757. vmw_resource_unreference(&res);
  758. goto out_unlock;
  759. }
  760. rep->sid = user_srf->prime.base.hash.key;
  761. vmw_resource_unreference(&res);
  762. ttm_read_unlock(&dev_priv->reservation_sem);
  763. return 0;
  764. out_no_copy:
  765. kfree(srf->offsets);
  766. out_no_offsets:
  767. kfree(srf->sizes);
  768. out_no_sizes:
  769. ttm_prime_object_kfree(user_srf, prime);
  770. out_no_user_srf:
  771. ttm_mem_global_free(vmw_mem_glob(dev_priv), size);
  772. out_unlock:
  773. ttm_read_unlock(&dev_priv->reservation_sem);
  774. return ret;
  775. }
  776. static int
  777. vmw_surface_handle_reference(struct vmw_private *dev_priv,
  778. struct drm_file *file_priv,
  779. uint32_t u_handle,
  780. enum drm_vmw_handle_type handle_type,
  781. struct ttm_base_object **base_p)
  782. {
  783. struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
  784. struct vmw_user_surface *user_srf;
  785. uint32_t handle;
  786. struct ttm_base_object *base;
  787. int ret;
  788. bool require_exist = false;
  789. if (handle_type == DRM_VMW_HANDLE_PRIME) {
  790. ret = ttm_prime_fd_to_handle(tfile, u_handle, &handle);
  791. if (unlikely(ret != 0))
  792. return ret;
  793. } else {
  794. if (unlikely(drm_is_render_client(file_priv)))
  795. require_exist = true;
  796. if (READ_ONCE(vmw_fpriv(file_priv)->locked_master)) {
  797. DRM_ERROR("Locked master refused legacy "
  798. "surface reference.\n");
  799. return -EACCES;
  800. }
  801. handle = u_handle;
  802. }
  803. ret = -EINVAL;
  804. base = ttm_base_object_lookup_for_ref(dev_priv->tdev, handle);
  805. if (unlikely(!base)) {
  806. DRM_ERROR("Could not find surface to reference.\n");
  807. goto out_no_lookup;
  808. }
  809. if (unlikely(ttm_base_object_type(base) != VMW_RES_SURFACE)) {
  810. DRM_ERROR("Referenced object is not a surface.\n");
  811. goto out_bad_resource;
  812. }
  813. if (handle_type != DRM_VMW_HANDLE_PRIME) {
  814. user_srf = container_of(base, struct vmw_user_surface,
  815. prime.base);
  816. /*
  817. * Make sure the surface creator has the same
  818. * authenticating master, or is already registered with us.
  819. */
  820. if (drm_is_primary_client(file_priv) &&
  821. user_srf->master != file_priv->master)
  822. require_exist = true;
  823. ret = ttm_ref_object_add(tfile, base, TTM_REF_USAGE, NULL,
  824. require_exist);
  825. if (unlikely(ret != 0)) {
  826. DRM_ERROR("Could not add a reference to a surface.\n");
  827. goto out_bad_resource;
  828. }
  829. }
  830. *base_p = base;
  831. return 0;
  832. out_bad_resource:
  833. ttm_base_object_unref(&base);
  834. out_no_lookup:
  835. if (handle_type == DRM_VMW_HANDLE_PRIME)
  836. (void) ttm_ref_object_base_unref(tfile, handle, TTM_REF_USAGE);
  837. return ret;
  838. }
  839. /**
  840. * vmw_user_surface_define_ioctl - Ioctl function implementing
  841. * the user surface reference functionality.
  842. *
  843. * @dev: Pointer to a struct drm_device.
  844. * @data: Pointer to data copied from / to user-space.
  845. * @file_priv: Pointer to a drm file private structure.
  846. */
  847. int vmw_surface_reference_ioctl(struct drm_device *dev, void *data,
  848. struct drm_file *file_priv)
  849. {
  850. struct vmw_private *dev_priv = vmw_priv(dev);
  851. union drm_vmw_surface_reference_arg *arg =
  852. (union drm_vmw_surface_reference_arg *)data;
  853. struct drm_vmw_surface_arg *req = &arg->req;
  854. struct drm_vmw_surface_create_req *rep = &arg->rep;
  855. struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
  856. struct vmw_surface *srf;
  857. struct vmw_user_surface *user_srf;
  858. struct drm_vmw_size __user *user_sizes;
  859. struct ttm_base_object *base;
  860. int ret;
  861. ret = vmw_surface_handle_reference(dev_priv, file_priv, req->sid,
  862. req->handle_type, &base);
  863. if (unlikely(ret != 0))
  864. return ret;
  865. user_srf = container_of(base, struct vmw_user_surface, prime.base);
  866. srf = &user_srf->srf;
  867. /* Downcast of flags when sending back to user space */
  868. rep->flags = (uint32_t)srf->flags;
  869. rep->format = srf->format;
  870. memcpy(rep->mip_levels, srf->mip_levels, sizeof(srf->mip_levels));
  871. user_sizes = (struct drm_vmw_size __user *)(unsigned long)
  872. rep->size_addr;
  873. if (user_sizes)
  874. ret = copy_to_user(user_sizes, &srf->base_size,
  875. sizeof(srf->base_size));
  876. if (unlikely(ret != 0)) {
  877. DRM_ERROR("copy_to_user failed %p %u\n",
  878. user_sizes, srf->num_sizes);
  879. ttm_ref_object_base_unref(tfile, base->hash.key, TTM_REF_USAGE);
  880. ret = -EFAULT;
  881. }
  882. ttm_base_object_unref(&base);
  883. return ret;
  884. }
  885. /**
  886. * vmw_surface_define_encode - Encode a surface_define command.
  887. *
  888. * @srf: Pointer to a struct vmw_surface object.
  889. * @cmd_space: Pointer to memory area in which the commands should be encoded.
  890. */
  891. static int vmw_gb_surface_create(struct vmw_resource *res)
  892. {
  893. struct vmw_private *dev_priv = res->dev_priv;
  894. struct vmw_surface *srf = vmw_res_to_srf(res);
  895. uint32_t cmd_len, cmd_id, submit_len;
  896. int ret;
  897. struct {
  898. SVGA3dCmdHeader header;
  899. SVGA3dCmdDefineGBSurface body;
  900. } *cmd;
  901. struct {
  902. SVGA3dCmdHeader header;
  903. SVGA3dCmdDefineGBSurface_v2 body;
  904. } *cmd2;
  905. struct {
  906. SVGA3dCmdHeader header;
  907. SVGA3dCmdDefineGBSurface_v3 body;
  908. } *cmd3;
  909. if (likely(res->id != -1))
  910. return 0;
  911. vmw_fifo_resource_inc(dev_priv);
  912. ret = vmw_resource_alloc_id(res);
  913. if (unlikely(ret != 0)) {
  914. DRM_ERROR("Failed to allocate a surface id.\n");
  915. goto out_no_id;
  916. }
  917. if (unlikely(res->id >= VMWGFX_NUM_GB_SURFACE)) {
  918. ret = -EBUSY;
  919. goto out_no_fifo;
  920. }
  921. if (dev_priv->has_sm4_1 && srf->array_size > 0) {
  922. cmd_id = SVGA_3D_CMD_DEFINE_GB_SURFACE_V3;
  923. cmd_len = sizeof(cmd3->body);
  924. submit_len = sizeof(*cmd3);
  925. } else if (srf->array_size > 0) {
  926. /* has_dx checked on creation time. */
  927. cmd_id = SVGA_3D_CMD_DEFINE_GB_SURFACE_V2;
  928. cmd_len = sizeof(cmd2->body);
  929. submit_len = sizeof(*cmd2);
  930. } else {
  931. cmd_id = SVGA_3D_CMD_DEFINE_GB_SURFACE;
  932. cmd_len = sizeof(cmd->body);
  933. submit_len = sizeof(*cmd);
  934. }
  935. cmd = vmw_fifo_reserve(dev_priv, submit_len);
  936. cmd2 = (typeof(cmd2))cmd;
  937. cmd3 = (typeof(cmd3))cmd;
  938. if (unlikely(!cmd)) {
  939. DRM_ERROR("Failed reserving FIFO space for surface "
  940. "creation.\n");
  941. ret = -ENOMEM;
  942. goto out_no_fifo;
  943. }
  944. if (dev_priv->has_sm4_1 && srf->array_size > 0) {
  945. cmd3->header.id = cmd_id;
  946. cmd3->header.size = cmd_len;
  947. cmd3->body.sid = srf->res.id;
  948. cmd3->body.surfaceFlags = srf->flags;
  949. cmd3->body.format = srf->format;
  950. cmd3->body.numMipLevels = srf->mip_levels[0];
  951. cmd3->body.multisampleCount = srf->multisample_count;
  952. cmd3->body.multisamplePattern = srf->multisample_pattern;
  953. cmd3->body.qualityLevel = srf->quality_level;
  954. cmd3->body.autogenFilter = srf->autogen_filter;
  955. cmd3->body.size.width = srf->base_size.width;
  956. cmd3->body.size.height = srf->base_size.height;
  957. cmd3->body.size.depth = srf->base_size.depth;
  958. cmd3->body.arraySize = srf->array_size;
  959. } else if (srf->array_size > 0) {
  960. cmd2->header.id = cmd_id;
  961. cmd2->header.size = cmd_len;
  962. cmd2->body.sid = srf->res.id;
  963. cmd2->body.surfaceFlags = srf->flags;
  964. cmd2->body.format = srf->format;
  965. cmd2->body.numMipLevels = srf->mip_levels[0];
  966. cmd2->body.multisampleCount = srf->multisample_count;
  967. cmd2->body.autogenFilter = srf->autogen_filter;
  968. cmd2->body.size.width = srf->base_size.width;
  969. cmd2->body.size.height = srf->base_size.height;
  970. cmd2->body.size.depth = srf->base_size.depth;
  971. cmd2->body.arraySize = srf->array_size;
  972. } else {
  973. cmd->header.id = cmd_id;
  974. cmd->header.size = cmd_len;
  975. cmd->body.sid = srf->res.id;
  976. cmd->body.surfaceFlags = srf->flags;
  977. cmd->body.format = srf->format;
  978. cmd->body.numMipLevels = srf->mip_levels[0];
  979. cmd->body.multisampleCount = srf->multisample_count;
  980. cmd->body.autogenFilter = srf->autogen_filter;
  981. cmd->body.size.width = srf->base_size.width;
  982. cmd->body.size.height = srf->base_size.height;
  983. cmd->body.size.depth = srf->base_size.depth;
  984. }
  985. vmw_fifo_commit(dev_priv, submit_len);
  986. return 0;
  987. out_no_fifo:
  988. vmw_resource_release_id(res);
  989. out_no_id:
  990. vmw_fifo_resource_dec(dev_priv);
  991. return ret;
  992. }
  993. static int vmw_gb_surface_bind(struct vmw_resource *res,
  994. struct ttm_validate_buffer *val_buf)
  995. {
  996. struct vmw_private *dev_priv = res->dev_priv;
  997. struct {
  998. SVGA3dCmdHeader header;
  999. SVGA3dCmdBindGBSurface body;
  1000. } *cmd1;
  1001. struct {
  1002. SVGA3dCmdHeader header;
  1003. SVGA3dCmdUpdateGBSurface body;
  1004. } *cmd2;
  1005. uint32_t submit_size;
  1006. struct ttm_buffer_object *bo = val_buf->bo;
  1007. BUG_ON(bo->mem.mem_type != VMW_PL_MOB);
  1008. submit_size = sizeof(*cmd1) + (res->backup_dirty ? sizeof(*cmd2) : 0);
  1009. cmd1 = vmw_fifo_reserve(dev_priv, submit_size);
  1010. if (unlikely(!cmd1)) {
  1011. DRM_ERROR("Failed reserving FIFO space for surface "
  1012. "binding.\n");
  1013. return -ENOMEM;
  1014. }
  1015. cmd1->header.id = SVGA_3D_CMD_BIND_GB_SURFACE;
  1016. cmd1->header.size = sizeof(cmd1->body);
  1017. cmd1->body.sid = res->id;
  1018. cmd1->body.mobid = bo->mem.start;
  1019. if (res->backup_dirty) {
  1020. cmd2 = (void *) &cmd1[1];
  1021. cmd2->header.id = SVGA_3D_CMD_UPDATE_GB_SURFACE;
  1022. cmd2->header.size = sizeof(cmd2->body);
  1023. cmd2->body.sid = res->id;
  1024. res->backup_dirty = false;
  1025. }
  1026. vmw_fifo_commit(dev_priv, submit_size);
  1027. return 0;
  1028. }
  1029. static int vmw_gb_surface_unbind(struct vmw_resource *res,
  1030. bool readback,
  1031. struct ttm_validate_buffer *val_buf)
  1032. {
  1033. struct vmw_private *dev_priv = res->dev_priv;
  1034. struct ttm_buffer_object *bo = val_buf->bo;
  1035. struct vmw_fence_obj *fence;
  1036. struct {
  1037. SVGA3dCmdHeader header;
  1038. SVGA3dCmdReadbackGBSurface body;
  1039. } *cmd1;
  1040. struct {
  1041. SVGA3dCmdHeader header;
  1042. SVGA3dCmdInvalidateGBSurface body;
  1043. } *cmd2;
  1044. struct {
  1045. SVGA3dCmdHeader header;
  1046. SVGA3dCmdBindGBSurface body;
  1047. } *cmd3;
  1048. uint32_t submit_size;
  1049. uint8_t *cmd;
  1050. BUG_ON(bo->mem.mem_type != VMW_PL_MOB);
  1051. submit_size = sizeof(*cmd3) + (readback ? sizeof(*cmd1) : sizeof(*cmd2));
  1052. cmd = vmw_fifo_reserve(dev_priv, submit_size);
  1053. if (unlikely(!cmd)) {
  1054. DRM_ERROR("Failed reserving FIFO space for surface "
  1055. "unbinding.\n");
  1056. return -ENOMEM;
  1057. }
  1058. if (readback) {
  1059. cmd1 = (void *) cmd;
  1060. cmd1->header.id = SVGA_3D_CMD_READBACK_GB_SURFACE;
  1061. cmd1->header.size = sizeof(cmd1->body);
  1062. cmd1->body.sid = res->id;
  1063. cmd3 = (void *) &cmd1[1];
  1064. } else {
  1065. cmd2 = (void *) cmd;
  1066. cmd2->header.id = SVGA_3D_CMD_INVALIDATE_GB_SURFACE;
  1067. cmd2->header.size = sizeof(cmd2->body);
  1068. cmd2->body.sid = res->id;
  1069. cmd3 = (void *) &cmd2[1];
  1070. }
  1071. cmd3->header.id = SVGA_3D_CMD_BIND_GB_SURFACE;
  1072. cmd3->header.size = sizeof(cmd3->body);
  1073. cmd3->body.sid = res->id;
  1074. cmd3->body.mobid = SVGA3D_INVALID_ID;
  1075. vmw_fifo_commit(dev_priv, submit_size);
  1076. /*
  1077. * Create a fence object and fence the backup buffer.
  1078. */
  1079. (void) vmw_execbuf_fence_commands(NULL, dev_priv,
  1080. &fence, NULL);
  1081. vmw_bo_fence_single(val_buf->bo, fence);
  1082. if (likely(fence != NULL))
  1083. vmw_fence_obj_unreference(&fence);
  1084. return 0;
  1085. }
  1086. static int vmw_gb_surface_destroy(struct vmw_resource *res)
  1087. {
  1088. struct vmw_private *dev_priv = res->dev_priv;
  1089. struct vmw_surface *srf = vmw_res_to_srf(res);
  1090. struct {
  1091. SVGA3dCmdHeader header;
  1092. SVGA3dCmdDestroyGBSurface body;
  1093. } *cmd;
  1094. if (likely(res->id == -1))
  1095. return 0;
  1096. mutex_lock(&dev_priv->binding_mutex);
  1097. vmw_view_surface_list_destroy(dev_priv, &srf->view_list);
  1098. vmw_binding_res_list_scrub(&res->binding_head);
  1099. cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
  1100. if (unlikely(!cmd)) {
  1101. DRM_ERROR("Failed reserving FIFO space for surface "
  1102. "destruction.\n");
  1103. mutex_unlock(&dev_priv->binding_mutex);
  1104. return -ENOMEM;
  1105. }
  1106. cmd->header.id = SVGA_3D_CMD_DESTROY_GB_SURFACE;
  1107. cmd->header.size = sizeof(cmd->body);
  1108. cmd->body.sid = res->id;
  1109. vmw_fifo_commit(dev_priv, sizeof(*cmd));
  1110. mutex_unlock(&dev_priv->binding_mutex);
  1111. vmw_resource_release_id(res);
  1112. vmw_fifo_resource_dec(dev_priv);
  1113. return 0;
  1114. }
  1115. /**
  1116. * vmw_gb_surface_define_ioctl - Ioctl function implementing
  1117. * the user surface define functionality.
  1118. *
  1119. * @dev: Pointer to a struct drm_device.
  1120. * @data: Pointer to data copied from / to user-space.
  1121. * @file_priv: Pointer to a drm file private structure.
  1122. */
  1123. int vmw_gb_surface_define_ioctl(struct drm_device *dev, void *data,
  1124. struct drm_file *file_priv)
  1125. {
  1126. struct vmw_private *dev_priv = vmw_priv(dev);
  1127. struct vmw_user_surface *user_srf;
  1128. struct vmw_surface *srf;
  1129. struct vmw_resource *res;
  1130. struct vmw_resource *tmp;
  1131. union drm_vmw_gb_surface_create_arg *arg =
  1132. (union drm_vmw_gb_surface_create_arg *)data;
  1133. struct drm_vmw_gb_surface_create_req *req = &arg->req;
  1134. struct drm_vmw_gb_surface_create_rep *rep = &arg->rep;
  1135. struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
  1136. int ret;
  1137. uint32_t size;
  1138. uint32_t backup_handle = 0;
  1139. if (req->multisample_count != 0)
  1140. return -EINVAL;
  1141. if (req->mip_levels > DRM_VMW_MAX_MIP_LEVELS)
  1142. return -EINVAL;
  1143. if (unlikely(vmw_user_surface_size == 0))
  1144. vmw_user_surface_size = ttm_round_pot(sizeof(*user_srf)) +
  1145. 128;
  1146. size = vmw_user_surface_size + 128;
  1147. /* Define a surface based on the parameters. */
  1148. ret = vmw_surface_gb_priv_define(dev,
  1149. size,
  1150. (SVGA3dSurfaceAllFlags)req->svga3d_flags,
  1151. req->format,
  1152. req->drm_surface_flags & drm_vmw_surface_flag_scanout,
  1153. req->mip_levels,
  1154. req->multisample_count,
  1155. req->array_size,
  1156. req->base_size,
  1157. &srf);
  1158. if (unlikely(ret != 0))
  1159. return ret;
  1160. user_srf = container_of(srf, struct vmw_user_surface, srf);
  1161. if (drm_is_primary_client(file_priv))
  1162. user_srf->master = drm_master_get(file_priv->master);
  1163. ret = ttm_read_lock(&dev_priv->reservation_sem, true);
  1164. if (unlikely(ret != 0))
  1165. return ret;
  1166. res = &user_srf->srf.res;
  1167. if (req->buffer_handle != SVGA3D_INVALID_ID) {
  1168. ret = vmw_user_bo_lookup(tfile, req->buffer_handle,
  1169. &res->backup,
  1170. &user_srf->backup_base);
  1171. if (ret == 0) {
  1172. if (res->backup->base.num_pages * PAGE_SIZE <
  1173. res->backup_size) {
  1174. DRM_ERROR("Surface backup buffer is too small.\n");
  1175. vmw_bo_unreference(&res->backup);
  1176. ret = -EINVAL;
  1177. goto out_unlock;
  1178. } else {
  1179. backup_handle = req->buffer_handle;
  1180. }
  1181. }
  1182. } else if (req->drm_surface_flags & drm_vmw_surface_flag_create_buffer)
  1183. ret = vmw_user_bo_alloc(dev_priv, tfile,
  1184. res->backup_size,
  1185. req->drm_surface_flags &
  1186. drm_vmw_surface_flag_shareable,
  1187. &backup_handle,
  1188. &res->backup,
  1189. &user_srf->backup_base);
  1190. if (unlikely(ret != 0)) {
  1191. vmw_resource_unreference(&res);
  1192. goto out_unlock;
  1193. }
  1194. tmp = vmw_resource_reference(res);
  1195. ret = ttm_prime_object_init(tfile, res->backup_size, &user_srf->prime,
  1196. req->drm_surface_flags &
  1197. drm_vmw_surface_flag_shareable,
  1198. VMW_RES_SURFACE,
  1199. &vmw_user_surface_base_release, NULL);
  1200. if (unlikely(ret != 0)) {
  1201. vmw_resource_unreference(&tmp);
  1202. vmw_resource_unreference(&res);
  1203. goto out_unlock;
  1204. }
  1205. rep->handle = user_srf->prime.base.hash.key;
  1206. rep->backup_size = res->backup_size;
  1207. if (res->backup) {
  1208. rep->buffer_map_handle =
  1209. drm_vma_node_offset_addr(&res->backup->base.vma_node);
  1210. rep->buffer_size = res->backup->base.num_pages * PAGE_SIZE;
  1211. rep->buffer_handle = backup_handle;
  1212. } else {
  1213. rep->buffer_map_handle = 0;
  1214. rep->buffer_size = 0;
  1215. rep->buffer_handle = SVGA3D_INVALID_ID;
  1216. }
  1217. vmw_resource_unreference(&res);
  1218. out_unlock:
  1219. ttm_read_unlock(&dev_priv->reservation_sem);
  1220. return ret;
  1221. }
  1222. /**
  1223. * vmw_gb_surface_reference_ioctl - Ioctl function implementing
  1224. * the user surface reference functionality.
  1225. *
  1226. * @dev: Pointer to a struct drm_device.
  1227. * @data: Pointer to data copied from / to user-space.
  1228. * @file_priv: Pointer to a drm file private structure.
  1229. */
  1230. int vmw_gb_surface_reference_ioctl(struct drm_device *dev, void *data,
  1231. struct drm_file *file_priv)
  1232. {
  1233. struct vmw_private *dev_priv = vmw_priv(dev);
  1234. union drm_vmw_gb_surface_reference_arg *arg =
  1235. (union drm_vmw_gb_surface_reference_arg *)data;
  1236. struct drm_vmw_surface_arg *req = &arg->req;
  1237. struct drm_vmw_gb_surface_ref_rep *rep = &arg->rep;
  1238. struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
  1239. struct vmw_surface *srf;
  1240. struct vmw_user_surface *user_srf;
  1241. struct ttm_base_object *base;
  1242. uint32_t backup_handle;
  1243. int ret = -EINVAL;
  1244. ret = vmw_surface_handle_reference(dev_priv, file_priv, req->sid,
  1245. req->handle_type, &base);
  1246. if (unlikely(ret != 0))
  1247. return ret;
  1248. user_srf = container_of(base, struct vmw_user_surface, prime.base);
  1249. srf = &user_srf->srf;
  1250. if (!srf->res.backup) {
  1251. DRM_ERROR("Shared GB surface is missing a backup buffer.\n");
  1252. goto out_bad_resource;
  1253. }
  1254. mutex_lock(&dev_priv->cmdbuf_mutex); /* Protect res->backup */
  1255. ret = vmw_user_bo_reference(tfile, srf->res.backup, &backup_handle);
  1256. mutex_unlock(&dev_priv->cmdbuf_mutex);
  1257. if (unlikely(ret != 0)) {
  1258. DRM_ERROR("Could not add a reference to a GB surface "
  1259. "backup buffer.\n");
  1260. (void) ttm_ref_object_base_unref(tfile, base->hash.key,
  1261. TTM_REF_USAGE);
  1262. goto out_bad_resource;
  1263. }
  1264. rep->creq.svga3d_flags = (uint32_t)srf->flags;
  1265. rep->creq.format = srf->format;
  1266. rep->creq.mip_levels = srf->mip_levels[0];
  1267. rep->creq.drm_surface_flags = 0;
  1268. rep->creq.multisample_count = srf->multisample_count;
  1269. rep->creq.autogen_filter = srf->autogen_filter;
  1270. rep->creq.array_size = srf->array_size;
  1271. rep->creq.buffer_handle = backup_handle;
  1272. rep->creq.base_size = srf->base_size;
  1273. rep->crep.handle = user_srf->prime.base.hash.key;
  1274. rep->crep.backup_size = srf->res.backup_size;
  1275. rep->crep.buffer_handle = backup_handle;
  1276. rep->crep.buffer_map_handle =
  1277. drm_vma_node_offset_addr(&srf->res.backup->base.vma_node);
  1278. rep->crep.buffer_size = srf->res.backup->base.num_pages * PAGE_SIZE;
  1279. out_bad_resource:
  1280. ttm_base_object_unref(&base);
  1281. return ret;
  1282. }
  1283. /**
  1284. * vmw_surface_gb_priv_define - Define a private GB surface
  1285. *
  1286. * @dev: Pointer to a struct drm_device
  1287. * @user_accounting_size: Used to track user-space memory usage, set
  1288. * to 0 for kernel mode only memory
  1289. * @svga3d_flags: SVGA3d surface flags for the device
  1290. * @format: requested surface format
  1291. * @for_scanout: true if inteded to be used for scanout buffer
  1292. * @num_mip_levels: number of MIP levels
  1293. * @multisample_count:
  1294. * @array_size: Surface array size.
  1295. * @size: width, heigh, depth of the surface requested
  1296. * @user_srf_out: allocated user_srf. Set to NULL on failure.
  1297. *
  1298. * GB surfaces allocated by this function will not have a user mode handle, and
  1299. * thus will only be visible to vmwgfx. For optimization reasons the
  1300. * surface may later be given a user mode handle by another function to make
  1301. * it available to user mode drivers.
  1302. */
  1303. int vmw_surface_gb_priv_define(struct drm_device *dev,
  1304. uint32_t user_accounting_size,
  1305. SVGA3dSurfaceAllFlags svga3d_flags,
  1306. SVGA3dSurfaceFormat format,
  1307. bool for_scanout,
  1308. uint32_t num_mip_levels,
  1309. uint32_t multisample_count,
  1310. uint32_t array_size,
  1311. struct drm_vmw_size size,
  1312. struct vmw_surface **srf_out)
  1313. {
  1314. struct vmw_private *dev_priv = vmw_priv(dev);
  1315. struct vmw_user_surface *user_srf;
  1316. struct ttm_operation_ctx ctx = {
  1317. .interruptible = true,
  1318. .no_wait_gpu = false
  1319. };
  1320. struct vmw_surface *srf;
  1321. int ret;
  1322. u32 num_layers;
  1323. *srf_out = NULL;
  1324. if (for_scanout) {
  1325. uint32_t max_width, max_height;
  1326. if (!svga3dsurface_is_screen_target_format(format)) {
  1327. DRM_ERROR("Invalid Screen Target surface format.");
  1328. return -EINVAL;
  1329. }
  1330. max_width = min(dev_priv->texture_max_width,
  1331. dev_priv->stdu_max_width);
  1332. max_height = min(dev_priv->texture_max_height,
  1333. dev_priv->stdu_max_height);
  1334. if (size.width > max_width || size.height > max_height) {
  1335. DRM_ERROR("%ux%u\n, exceeds max surface size %ux%u",
  1336. size.width, size.height,
  1337. max_width, max_height);
  1338. return -EINVAL;
  1339. }
  1340. } else {
  1341. const struct svga3d_surface_desc *desc;
  1342. desc = svga3dsurface_get_desc(format);
  1343. if (unlikely(desc->block_desc == SVGA3DBLOCKDESC_NONE)) {
  1344. DRM_ERROR("Invalid surface format.\n");
  1345. return -EINVAL;
  1346. }
  1347. }
  1348. /* array_size must be null for non-GL3 host. */
  1349. if (array_size > 0 && !dev_priv->has_dx) {
  1350. DRM_ERROR("Tried to create DX surface on non-DX host.\n");
  1351. return -EINVAL;
  1352. }
  1353. ret = ttm_read_lock(&dev_priv->reservation_sem, true);
  1354. if (unlikely(ret != 0))
  1355. return ret;
  1356. ret = ttm_mem_global_alloc(vmw_mem_glob(dev_priv),
  1357. user_accounting_size, &ctx);
  1358. if (unlikely(ret != 0)) {
  1359. if (ret != -ERESTARTSYS)
  1360. DRM_ERROR("Out of graphics memory for surface"
  1361. " creation.\n");
  1362. goto out_unlock;
  1363. }
  1364. user_srf = kzalloc(sizeof(*user_srf), GFP_KERNEL);
  1365. if (unlikely(!user_srf)) {
  1366. ret = -ENOMEM;
  1367. goto out_no_user_srf;
  1368. }
  1369. *srf_out = &user_srf->srf;
  1370. user_srf->size = user_accounting_size;
  1371. user_srf->prime.base.shareable = false;
  1372. user_srf->prime.base.tfile = NULL;
  1373. srf = &user_srf->srf;
  1374. srf->flags = svga3d_flags;
  1375. srf->format = format;
  1376. srf->scanout = for_scanout;
  1377. srf->mip_levels[0] = num_mip_levels;
  1378. srf->num_sizes = 1;
  1379. srf->sizes = NULL;
  1380. srf->offsets = NULL;
  1381. srf->base_size = size;
  1382. srf->autogen_filter = SVGA3D_TEX_FILTER_NONE;
  1383. srf->array_size = array_size;
  1384. srf->multisample_count = multisample_count;
  1385. srf->multisample_pattern = SVGA3D_MS_PATTERN_NONE;
  1386. srf->quality_level = SVGA3D_MS_QUALITY_NONE;
  1387. if (array_size)
  1388. num_layers = array_size;
  1389. else if (svga3d_flags & SVGA3D_SURFACE_CUBEMAP)
  1390. num_layers = SVGA3D_MAX_SURFACE_FACES;
  1391. else
  1392. num_layers = 1;
  1393. srf->res.backup_size =
  1394. svga3dsurface_get_serialized_size(srf->format,
  1395. srf->base_size,
  1396. srf->mip_levels[0],
  1397. num_layers);
  1398. if (srf->flags & SVGA3D_SURFACE_BIND_STREAM_OUTPUT)
  1399. srf->res.backup_size += sizeof(SVGA3dDXSOState);
  1400. if (dev_priv->active_display_unit == vmw_du_screen_target &&
  1401. for_scanout)
  1402. srf->flags |= SVGA3D_SURFACE_SCREENTARGET;
  1403. /*
  1404. * From this point, the generic resource management functions
  1405. * destroy the object on failure.
  1406. */
  1407. ret = vmw_surface_init(dev_priv, srf, vmw_user_surface_free);
  1408. ttm_read_unlock(&dev_priv->reservation_sem);
  1409. return ret;
  1410. out_no_user_srf:
  1411. ttm_mem_global_free(vmw_mem_glob(dev_priv), user_accounting_size);
  1412. out_unlock:
  1413. ttm_read_unlock(&dev_priv->reservation_sem);
  1414. return ret;
  1415. }