gpu_scheduler.h 6.9 KB

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  1. /*
  2. * Copyright 2015 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. */
  23. #ifndef _DRM_GPU_SCHEDULER_H_
  24. #define _DRM_GPU_SCHEDULER_H_
  25. #include <drm/spsc_queue.h>
  26. #include <linux/dma-fence.h>
  27. struct drm_gpu_scheduler;
  28. struct drm_sched_rq;
  29. enum drm_sched_priority {
  30. DRM_SCHED_PRIORITY_MIN,
  31. DRM_SCHED_PRIORITY_LOW = DRM_SCHED_PRIORITY_MIN,
  32. DRM_SCHED_PRIORITY_NORMAL,
  33. DRM_SCHED_PRIORITY_HIGH_SW,
  34. DRM_SCHED_PRIORITY_HIGH_HW,
  35. DRM_SCHED_PRIORITY_KERNEL,
  36. DRM_SCHED_PRIORITY_MAX,
  37. DRM_SCHED_PRIORITY_INVALID = -1,
  38. DRM_SCHED_PRIORITY_UNSET = -2
  39. };
  40. /**
  41. * drm_sched_entity - A wrapper around a job queue (typically attached
  42. * to the DRM file_priv).
  43. *
  44. * Entities will emit jobs in order to their corresponding hardware
  45. * ring, and the scheduler will alternate between entities based on
  46. * scheduling policy.
  47. */
  48. struct drm_sched_entity {
  49. struct list_head list;
  50. struct drm_sched_rq *rq;
  51. spinlock_t rq_lock;
  52. struct drm_gpu_scheduler *sched;
  53. struct spsc_queue job_queue;
  54. atomic_t fence_seq;
  55. uint64_t fence_context;
  56. struct dma_fence *dependency;
  57. struct dma_fence_cb cb;
  58. atomic_t *guilty; /* points to ctx's guilty */
  59. int fini_status;
  60. struct dma_fence *last_scheduled;
  61. };
  62. /**
  63. * Run queue is a set of entities scheduling command submissions for
  64. * one specific ring. It implements the scheduling policy that selects
  65. * the next entity to emit commands from.
  66. */
  67. struct drm_sched_rq {
  68. spinlock_t lock;
  69. struct list_head entities;
  70. struct drm_sched_entity *current_entity;
  71. };
  72. struct drm_sched_fence {
  73. struct dma_fence scheduled;
  74. /* This fence is what will be signaled by the scheduler when
  75. * the job is completed.
  76. *
  77. * When setting up an out fence for the job, you should use
  78. * this, since it's available immediately upon
  79. * drm_sched_job_init(), and the fence returned by the driver
  80. * from run_job() won't be created until the dependencies have
  81. * resolved.
  82. */
  83. struct dma_fence finished;
  84. struct dma_fence_cb cb;
  85. struct dma_fence *parent;
  86. struct drm_gpu_scheduler *sched;
  87. spinlock_t lock;
  88. void *owner;
  89. };
  90. struct drm_sched_fence *to_drm_sched_fence(struct dma_fence *f);
  91. /**
  92. * drm_sched_job - A job to be run by an entity.
  93. *
  94. * A job is created by the driver using drm_sched_job_init(), and
  95. * should call drm_sched_entity_push_job() once it wants the scheduler
  96. * to schedule the job.
  97. */
  98. struct drm_sched_job {
  99. struct spsc_node queue_node;
  100. struct drm_gpu_scheduler *sched;
  101. struct drm_sched_fence *s_fence;
  102. struct dma_fence_cb finish_cb;
  103. struct work_struct finish_work;
  104. struct list_head node;
  105. struct delayed_work work_tdr;
  106. uint64_t id;
  107. atomic_t karma;
  108. enum drm_sched_priority s_priority;
  109. struct drm_sched_entity *entity;
  110. };
  111. static inline bool drm_sched_invalidate_job(struct drm_sched_job *s_job,
  112. int threshold)
  113. {
  114. return (s_job && atomic_inc_return(&s_job->karma) > threshold);
  115. }
  116. /**
  117. * Define the backend operations called by the scheduler,
  118. * these functions should be implemented in driver side
  119. */
  120. struct drm_sched_backend_ops {
  121. /* Called when the scheduler is considering scheduling this
  122. * job next, to get another struct dma_fence for this job to
  123. * block on. Once it returns NULL, run_job() may be called.
  124. */
  125. struct dma_fence *(*dependency)(struct drm_sched_job *sched_job,
  126. struct drm_sched_entity *s_entity);
  127. /* Called to execute the job once all of the dependencies have
  128. * been resolved. This may be called multiple times, if
  129. * timedout_job() has happened and drm_sched_job_recovery()
  130. * decides to try it again.
  131. */
  132. struct dma_fence *(*run_job)(struct drm_sched_job *sched_job);
  133. /* Called when a job has taken too long to execute, to trigger
  134. * GPU recovery.
  135. */
  136. void (*timedout_job)(struct drm_sched_job *sched_job);
  137. /* Called once the job's finished fence has been signaled and
  138. * it's time to clean it up.
  139. */
  140. void (*free_job)(struct drm_sched_job *sched_job);
  141. };
  142. /**
  143. * One scheduler is implemented for each hardware ring
  144. */
  145. struct drm_gpu_scheduler {
  146. const struct drm_sched_backend_ops *ops;
  147. uint32_t hw_submission_limit;
  148. long timeout;
  149. const char *name;
  150. struct drm_sched_rq sched_rq[DRM_SCHED_PRIORITY_MAX];
  151. wait_queue_head_t wake_up_worker;
  152. wait_queue_head_t job_scheduled;
  153. atomic_t hw_rq_count;
  154. atomic64_t job_id_count;
  155. struct task_struct *thread;
  156. struct list_head ring_mirror_list;
  157. spinlock_t job_list_lock;
  158. int hang_limit;
  159. };
  160. int drm_sched_init(struct drm_gpu_scheduler *sched,
  161. const struct drm_sched_backend_ops *ops,
  162. uint32_t hw_submission, unsigned hang_limit, long timeout,
  163. const char *name);
  164. void drm_sched_fini(struct drm_gpu_scheduler *sched);
  165. int drm_sched_entity_init(struct drm_gpu_scheduler *sched,
  166. struct drm_sched_entity *entity,
  167. struct drm_sched_rq *rq,
  168. atomic_t *guilty);
  169. void drm_sched_entity_do_release(struct drm_gpu_scheduler *sched,
  170. struct drm_sched_entity *entity);
  171. void drm_sched_entity_cleanup(struct drm_gpu_scheduler *sched,
  172. struct drm_sched_entity *entity);
  173. void drm_sched_entity_fini(struct drm_gpu_scheduler *sched,
  174. struct drm_sched_entity *entity);
  175. void drm_sched_entity_push_job(struct drm_sched_job *sched_job,
  176. struct drm_sched_entity *entity);
  177. void drm_sched_entity_set_rq(struct drm_sched_entity *entity,
  178. struct drm_sched_rq *rq);
  179. struct drm_sched_fence *drm_sched_fence_create(
  180. struct drm_sched_entity *s_entity, void *owner);
  181. void drm_sched_fence_scheduled(struct drm_sched_fence *fence);
  182. void drm_sched_fence_finished(struct drm_sched_fence *fence);
  183. int drm_sched_job_init(struct drm_sched_job *job,
  184. struct drm_gpu_scheduler *sched,
  185. struct drm_sched_entity *entity,
  186. void *owner);
  187. void drm_sched_hw_job_reset(struct drm_gpu_scheduler *sched,
  188. struct drm_sched_job *job);
  189. void drm_sched_job_recovery(struct drm_gpu_scheduler *sched);
  190. bool drm_sched_dependency_optimized(struct dma_fence* fence,
  191. struct drm_sched_entity *entity);
  192. void drm_sched_job_kickout(struct drm_sched_job *s_job);
  193. #endif