xhci-rcar.c 6.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * xHCI host controller driver for R-Car SoCs
  4. *
  5. * Copyright (C) 2014 Renesas Electronics Corporation
  6. */
  7. #include <linux/firmware.h>
  8. #include <linux/module.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/of.h>
  11. #include <linux/usb/phy.h>
  12. #include <linux/sys_soc.h>
  13. #include "xhci.h"
  14. #include "xhci-plat.h"
  15. #include "xhci-rcar.h"
  16. /*
  17. * - The V3 firmware is for r8a7796 (with good performance) and r8a7795 es2.0
  18. * or later.
  19. * - The V2 firmware can be used on both r8a7795 (es1.x) and r8a7796.
  20. * - The V2 firmware is possible to use on R-Car Gen2. However, the V2 causes
  21. * performance degradation. So, this driver continues to use the V1 if R-Car
  22. * Gen2.
  23. * - The V1 firmware is impossible to use on R-Car Gen3.
  24. */
  25. MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V1);
  26. MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V2);
  27. MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V3);
  28. /*** Register Offset ***/
  29. #define RCAR_USB3_INT_ENA 0x224 /* Interrupt Enable */
  30. #define RCAR_USB3_DL_CTRL 0x250 /* FW Download Control & Status */
  31. #define RCAR_USB3_FW_DATA0 0x258 /* FW Data0 */
  32. #define RCAR_USB3_LCLK 0xa44 /* LCLK Select */
  33. #define RCAR_USB3_CONF1 0xa48 /* USB3.0 Configuration1 */
  34. #define RCAR_USB3_CONF2 0xa5c /* USB3.0 Configuration2 */
  35. #define RCAR_USB3_CONF3 0xaa8 /* USB3.0 Configuration3 */
  36. #define RCAR_USB3_RX_POL 0xab0 /* USB3.0 RX Polarity */
  37. #define RCAR_USB3_TX_POL 0xab8 /* USB3.0 TX Polarity */
  38. /*** Register Settings ***/
  39. /* Interrupt Enable */
  40. #define RCAR_USB3_INT_XHC_ENA 0x00000001
  41. #define RCAR_USB3_INT_PME_ENA 0x00000002
  42. #define RCAR_USB3_INT_HSE_ENA 0x00000004
  43. #define RCAR_USB3_INT_ENA_VAL (RCAR_USB3_INT_XHC_ENA | \
  44. RCAR_USB3_INT_PME_ENA | RCAR_USB3_INT_HSE_ENA)
  45. /* FW Download Control & Status */
  46. #define RCAR_USB3_DL_CTRL_ENABLE 0x00000001
  47. #define RCAR_USB3_DL_CTRL_FW_SUCCESS 0x00000010
  48. #define RCAR_USB3_DL_CTRL_FW_SET_DATA0 0x00000100
  49. /* LCLK Select */
  50. #define RCAR_USB3_LCLK_ENA_VAL 0x01030001
  51. /* USB3.0 Configuration */
  52. #define RCAR_USB3_CONF1_VAL 0x00030204
  53. #define RCAR_USB3_CONF2_VAL 0x00030300
  54. #define RCAR_USB3_CONF3_VAL 0x13802007
  55. /* USB3.0 Polarity */
  56. #define RCAR_USB3_RX_POL_VAL BIT(21)
  57. #define RCAR_USB3_TX_POL_VAL BIT(4)
  58. /* For soc_device_attribute */
  59. #define RCAR_XHCI_FIRMWARE_V2 BIT(0) /* FIRMWARE V2 */
  60. #define RCAR_XHCI_FIRMWARE_V3 BIT(1) /* FIRMWARE V3 */
  61. static const struct soc_device_attribute rcar_quirks_match[] = {
  62. {
  63. .soc_id = "r8a7795", .revision = "ES1.*",
  64. .data = (void *)RCAR_XHCI_FIRMWARE_V2,
  65. },
  66. {
  67. .soc_id = "r8a7795",
  68. .data = (void *)RCAR_XHCI_FIRMWARE_V3,
  69. },
  70. {
  71. .soc_id = "r8a7796",
  72. .data = (void *)RCAR_XHCI_FIRMWARE_V3,
  73. },
  74. {
  75. .soc_id = "r8a77965",
  76. .data = (void *)RCAR_XHCI_FIRMWARE_V3,
  77. },
  78. { /* sentinel */ },
  79. };
  80. static void xhci_rcar_start_gen2(struct usb_hcd *hcd)
  81. {
  82. /* LCLK Select */
  83. writel(RCAR_USB3_LCLK_ENA_VAL, hcd->regs + RCAR_USB3_LCLK);
  84. /* USB3.0 Configuration */
  85. writel(RCAR_USB3_CONF1_VAL, hcd->regs + RCAR_USB3_CONF1);
  86. writel(RCAR_USB3_CONF2_VAL, hcd->regs + RCAR_USB3_CONF2);
  87. writel(RCAR_USB3_CONF3_VAL, hcd->regs + RCAR_USB3_CONF3);
  88. /* USB3.0 Polarity */
  89. writel(RCAR_USB3_RX_POL_VAL, hcd->regs + RCAR_USB3_RX_POL);
  90. writel(RCAR_USB3_TX_POL_VAL, hcd->regs + RCAR_USB3_TX_POL);
  91. }
  92. static int xhci_rcar_is_gen2(struct device *dev)
  93. {
  94. struct device_node *node = dev->of_node;
  95. return of_device_is_compatible(node, "renesas,xhci-r8a7790") ||
  96. of_device_is_compatible(node, "renesas,xhci-r8a7791") ||
  97. of_device_is_compatible(node, "renesas,xhci-r8a7793") ||
  98. of_device_is_compatible(node, "renensas,rcar-gen2-xhci");
  99. }
  100. static int xhci_rcar_is_gen3(struct device *dev)
  101. {
  102. struct device_node *node = dev->of_node;
  103. return of_device_is_compatible(node, "renesas,xhci-r8a7795") ||
  104. of_device_is_compatible(node, "renesas,xhci-r8a7796") ||
  105. of_device_is_compatible(node, "renesas,rcar-gen3-xhci");
  106. }
  107. void xhci_rcar_start(struct usb_hcd *hcd)
  108. {
  109. u32 temp;
  110. if (hcd->regs != NULL) {
  111. /* Interrupt Enable */
  112. temp = readl(hcd->regs + RCAR_USB3_INT_ENA);
  113. temp |= RCAR_USB3_INT_ENA_VAL;
  114. writel(temp, hcd->regs + RCAR_USB3_INT_ENA);
  115. if (xhci_rcar_is_gen2(hcd->self.controller))
  116. xhci_rcar_start_gen2(hcd);
  117. }
  118. }
  119. static int xhci_rcar_download_firmware(struct usb_hcd *hcd)
  120. {
  121. struct device *dev = hcd->self.controller;
  122. void __iomem *regs = hcd->regs;
  123. struct xhci_plat_priv *priv = hcd_to_xhci_priv(hcd);
  124. const struct firmware *fw;
  125. int retval, index, j, time;
  126. int timeout = 10000;
  127. u32 data, val, temp;
  128. u32 quirks = 0;
  129. const struct soc_device_attribute *attr;
  130. const char *firmware_name;
  131. attr = soc_device_match(rcar_quirks_match);
  132. if (attr)
  133. quirks = (uintptr_t)attr->data;
  134. if (quirks & RCAR_XHCI_FIRMWARE_V2)
  135. firmware_name = XHCI_RCAR_FIRMWARE_NAME_V2;
  136. else if (quirks & RCAR_XHCI_FIRMWARE_V3)
  137. firmware_name = XHCI_RCAR_FIRMWARE_NAME_V3;
  138. else
  139. firmware_name = priv->firmware_name;
  140. /* request R-Car USB3.0 firmware */
  141. retval = request_firmware(&fw, firmware_name, dev);
  142. if (retval)
  143. return retval;
  144. /* download R-Car USB3.0 firmware */
  145. temp = readl(regs + RCAR_USB3_DL_CTRL);
  146. temp |= RCAR_USB3_DL_CTRL_ENABLE;
  147. writel(temp, regs + RCAR_USB3_DL_CTRL);
  148. for (index = 0; index < fw->size; index += 4) {
  149. /* to avoid reading beyond the end of the buffer */
  150. for (data = 0, j = 3; j >= 0; j--) {
  151. if ((j + index) < fw->size)
  152. data |= fw->data[index + j] << (8 * j);
  153. }
  154. writel(data, regs + RCAR_USB3_FW_DATA0);
  155. temp = readl(regs + RCAR_USB3_DL_CTRL);
  156. temp |= RCAR_USB3_DL_CTRL_FW_SET_DATA0;
  157. writel(temp, regs + RCAR_USB3_DL_CTRL);
  158. for (time = 0; time < timeout; time++) {
  159. val = readl(regs + RCAR_USB3_DL_CTRL);
  160. if ((val & RCAR_USB3_DL_CTRL_FW_SET_DATA0) == 0)
  161. break;
  162. udelay(1);
  163. }
  164. if (time == timeout) {
  165. retval = -ETIMEDOUT;
  166. break;
  167. }
  168. }
  169. temp = readl(regs + RCAR_USB3_DL_CTRL);
  170. temp &= ~RCAR_USB3_DL_CTRL_ENABLE;
  171. writel(temp, regs + RCAR_USB3_DL_CTRL);
  172. for (time = 0; time < timeout; time++) {
  173. val = readl(regs + RCAR_USB3_DL_CTRL);
  174. if (val & RCAR_USB3_DL_CTRL_FW_SUCCESS) {
  175. retval = 0;
  176. break;
  177. }
  178. udelay(1);
  179. }
  180. if (time == timeout)
  181. retval = -ETIMEDOUT;
  182. release_firmware(fw);
  183. return retval;
  184. }
  185. /* This function needs to initialize a "phy" of usb before */
  186. int xhci_rcar_init_quirk(struct usb_hcd *hcd)
  187. {
  188. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  189. /* If hcd->regs is NULL, we don't just call the following function */
  190. if (!hcd->regs)
  191. return 0;
  192. /*
  193. * On R-Car Gen2 and Gen3, the AC64 bit (bit 0) of HCCPARAMS1 is set
  194. * to 1. However, these SoCs don't support 64-bit address memory
  195. * pointers. So, this driver clears the AC64 bit of xhci->hcc_params
  196. * to call dma_set_coherent_mask(dev, DMA_BIT_MASK(32)) in
  197. * xhci_gen_setup().
  198. */
  199. if (xhci_rcar_is_gen2(hcd->self.controller) ||
  200. xhci_rcar_is_gen3(hcd->self.controller))
  201. xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
  202. return xhci_rcar_download_firmware(hcd);
  203. }
  204. int xhci_rcar_resume_quirk(struct usb_hcd *hcd)
  205. {
  206. int ret;
  207. ret = xhci_rcar_download_firmware(hcd);
  208. if (!ret)
  209. xhci_rcar_start(hcd);
  210. return ret;
  211. }