dwc3-pci.c 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385
  1. // SPDX-License-Identifier: GPL-2.0
  2. /**
  3. * dwc3-pci.c - PCI Specific glue layer
  4. *
  5. * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
  6. *
  7. * Authors: Felipe Balbi <balbi@ti.com>,
  8. * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/slab.h>
  13. #include <linux/pci.h>
  14. #include <linux/workqueue.h>
  15. #include <linux/pm_runtime.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/gpio/consumer.h>
  18. #include <linux/acpi.h>
  19. #include <linux/delay.h>
  20. #define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 0xabcd
  21. #define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI 0xabce
  22. #define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31 0xabcf
  23. #define PCI_DEVICE_ID_INTEL_BYT 0x0f37
  24. #define PCI_DEVICE_ID_INTEL_MRFLD 0x119e
  25. #define PCI_DEVICE_ID_INTEL_BSW 0x22b7
  26. #define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30
  27. #define PCI_DEVICE_ID_INTEL_SPTH 0xa130
  28. #define PCI_DEVICE_ID_INTEL_BXT 0x0aaa
  29. #define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa
  30. #define PCI_DEVICE_ID_INTEL_APL 0x5aaa
  31. #define PCI_DEVICE_ID_INTEL_KBP 0xa2b0
  32. #define PCI_DEVICE_ID_INTEL_GLK 0x31aa
  33. #define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee
  34. #define PCI_DEVICE_ID_INTEL_CNPH 0xa36e
  35. #define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
  36. #define PCI_INTEL_BXT_FUNC_PMU_PWR 4
  37. #define PCI_INTEL_BXT_STATE_D0 0
  38. #define PCI_INTEL_BXT_STATE_D3 3
  39. /**
  40. * struct dwc3_pci - Driver private structure
  41. * @dwc3: child dwc3 platform_device
  42. * @pci: our link to PCI bus
  43. * @guid: _DSM GUID
  44. * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM
  45. */
  46. struct dwc3_pci {
  47. struct platform_device *dwc3;
  48. struct pci_dev *pci;
  49. guid_t guid;
  50. unsigned int has_dsm_for_pm:1;
  51. struct work_struct wakeup_work;
  52. };
  53. static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
  54. static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
  55. static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
  56. { "reset-gpios", &reset_gpios, 1 },
  57. { "cs-gpios", &cs_gpios, 1 },
  58. { },
  59. };
  60. static int dwc3_pci_quirks(struct dwc3_pci *dwc)
  61. {
  62. struct platform_device *dwc3 = dwc->dwc3;
  63. struct pci_dev *pdev = dwc->pci;
  64. if (pdev->vendor == PCI_VENDOR_ID_AMD &&
  65. pdev->device == PCI_DEVICE_ID_AMD_NL_USB) {
  66. struct property_entry properties[] = {
  67. PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
  68. PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
  69. PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
  70. PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
  71. PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
  72. PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
  73. PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
  74. PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
  75. PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
  76. PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
  77. PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
  78. /*
  79. * FIXME these quirks should be removed when AMD NL
  80. * tapes out
  81. */
  82. PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
  83. PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
  84. PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
  85. PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
  86. { },
  87. };
  88. return platform_device_add_properties(dwc3, properties);
  89. }
  90. if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
  91. int ret;
  92. struct property_entry properties[] = {
  93. PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
  94. PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
  95. { }
  96. };
  97. ret = platform_device_add_properties(dwc3, properties);
  98. if (ret < 0)
  99. return ret;
  100. if (pdev->device == PCI_DEVICE_ID_INTEL_BXT ||
  101. pdev->device == PCI_DEVICE_ID_INTEL_BXT_M) {
  102. guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid);
  103. dwc->has_dsm_for_pm = true;
  104. }
  105. if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
  106. struct gpio_desc *gpio;
  107. ret = devm_acpi_dev_add_driver_gpios(&pdev->dev,
  108. acpi_dwc3_byt_gpios);
  109. if (ret)
  110. dev_dbg(&pdev->dev, "failed to add mapping table\n");
  111. /*
  112. * These GPIOs will turn on the USB2 PHY. Note that we have to
  113. * put the gpio descriptors again here because the phy driver
  114. * might want to grab them, too.
  115. */
  116. gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
  117. if (IS_ERR(gpio))
  118. return PTR_ERR(gpio);
  119. gpiod_set_value_cansleep(gpio, 1);
  120. gpiod_put(gpio);
  121. gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
  122. if (IS_ERR(gpio))
  123. return PTR_ERR(gpio);
  124. if (gpio) {
  125. gpiod_set_value_cansleep(gpio, 1);
  126. gpiod_put(gpio);
  127. usleep_range(10000, 11000);
  128. }
  129. }
  130. }
  131. if (pdev->vendor == PCI_VENDOR_ID_SYNOPSYS &&
  132. (pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 ||
  133. pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI ||
  134. pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31)) {
  135. struct property_entry properties[] = {
  136. PROPERTY_ENTRY_BOOL("snps,usb3_lpm_capable"),
  137. PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
  138. PROPERTY_ENTRY_BOOL("snps,dis_enblslpm_quirk"),
  139. PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
  140. { },
  141. };
  142. return platform_device_add_properties(dwc3, properties);
  143. }
  144. return 0;
  145. }
  146. #ifdef CONFIG_PM
  147. static void dwc3_pci_resume_work(struct work_struct *work)
  148. {
  149. struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work);
  150. struct platform_device *dwc3 = dwc->dwc3;
  151. int ret;
  152. ret = pm_runtime_get_sync(&dwc3->dev);
  153. if (ret)
  154. return;
  155. pm_runtime_mark_last_busy(&dwc3->dev);
  156. pm_runtime_put_sync_autosuspend(&dwc3->dev);
  157. }
  158. #endif
  159. static int dwc3_pci_probe(struct pci_dev *pci,
  160. const struct pci_device_id *id)
  161. {
  162. struct dwc3_pci *dwc;
  163. struct resource res[2];
  164. int ret;
  165. struct device *dev = &pci->dev;
  166. ret = pcim_enable_device(pci);
  167. if (ret) {
  168. dev_err(dev, "failed to enable pci device\n");
  169. return -ENODEV;
  170. }
  171. pci_set_master(pci);
  172. dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
  173. if (!dwc)
  174. return -ENOMEM;
  175. dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
  176. if (!dwc->dwc3)
  177. return -ENOMEM;
  178. memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
  179. res[0].start = pci_resource_start(pci, 0);
  180. res[0].end = pci_resource_end(pci, 0);
  181. res[0].name = "dwc_usb3";
  182. res[0].flags = IORESOURCE_MEM;
  183. res[1].start = pci->irq;
  184. res[1].name = "dwc_usb3";
  185. res[1].flags = IORESOURCE_IRQ;
  186. ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res));
  187. if (ret) {
  188. dev_err(dev, "couldn't add resources to dwc3 device\n");
  189. goto err;
  190. }
  191. dwc->pci = pci;
  192. dwc->dwc3->dev.parent = dev;
  193. ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev));
  194. ret = dwc3_pci_quirks(dwc);
  195. if (ret)
  196. goto err;
  197. ret = platform_device_add(dwc->dwc3);
  198. if (ret) {
  199. dev_err(dev, "failed to register dwc3 device\n");
  200. goto err;
  201. }
  202. device_init_wakeup(dev, true);
  203. pci_set_drvdata(pci, dwc);
  204. pm_runtime_put(dev);
  205. #ifdef CONFIG_PM
  206. INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work);
  207. #endif
  208. return 0;
  209. err:
  210. platform_device_put(dwc->dwc3);
  211. return ret;
  212. }
  213. static void dwc3_pci_remove(struct pci_dev *pci)
  214. {
  215. struct dwc3_pci *dwc = pci_get_drvdata(pci);
  216. #ifdef CONFIG_PM
  217. cancel_work_sync(&dwc->wakeup_work);
  218. #endif
  219. device_init_wakeup(&pci->dev, false);
  220. pm_runtime_get(&pci->dev);
  221. platform_device_unregister(dwc->dwc3);
  222. }
  223. static const struct pci_device_id dwc3_pci_id_table[] = {
  224. {
  225. PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
  226. PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3),
  227. },
  228. {
  229. PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
  230. PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI),
  231. },
  232. {
  233. PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
  234. PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31),
  235. },
  236. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW), },
  237. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT), },
  238. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MRFLD), },
  239. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SPTLP), },
  240. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SPTH), },
  241. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BXT), },
  242. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BXT_M), },
  243. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL), },
  244. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBP), },
  245. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GLK), },
  246. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CNPLP), },
  247. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CNPH), },
  248. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB), },
  249. { } /* Terminating Entry */
  250. };
  251. MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
  252. #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP)
  253. static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param)
  254. {
  255. union acpi_object *obj;
  256. union acpi_object tmp;
  257. union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
  258. if (!dwc->has_dsm_for_pm)
  259. return 0;
  260. tmp.type = ACPI_TYPE_INTEGER;
  261. tmp.integer.value = param;
  262. obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid,
  263. 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4);
  264. if (!obj) {
  265. dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n");
  266. return -EIO;
  267. }
  268. ACPI_FREE(obj);
  269. return 0;
  270. }
  271. #endif /* CONFIG_PM || CONFIG_PM_SLEEP */
  272. #ifdef CONFIG_PM
  273. static int dwc3_pci_runtime_suspend(struct device *dev)
  274. {
  275. struct dwc3_pci *dwc = dev_get_drvdata(dev);
  276. if (device_can_wakeup(dev))
  277. return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
  278. return -EBUSY;
  279. }
  280. static int dwc3_pci_runtime_resume(struct device *dev)
  281. {
  282. struct dwc3_pci *dwc = dev_get_drvdata(dev);
  283. int ret;
  284. ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
  285. if (ret)
  286. return ret;
  287. queue_work(pm_wq, &dwc->wakeup_work);
  288. return 0;
  289. }
  290. #endif /* CONFIG_PM */
  291. #ifdef CONFIG_PM_SLEEP
  292. static int dwc3_pci_suspend(struct device *dev)
  293. {
  294. struct dwc3_pci *dwc = dev_get_drvdata(dev);
  295. return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
  296. }
  297. static int dwc3_pci_resume(struct device *dev)
  298. {
  299. struct dwc3_pci *dwc = dev_get_drvdata(dev);
  300. return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
  301. }
  302. #endif /* CONFIG_PM_SLEEP */
  303. static const struct dev_pm_ops dwc3_pci_dev_pm_ops = {
  304. SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume)
  305. SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
  306. NULL)
  307. };
  308. static struct pci_driver dwc3_pci_driver = {
  309. .name = "dwc3-pci",
  310. .id_table = dwc3_pci_id_table,
  311. .probe = dwc3_pci_probe,
  312. .remove = dwc3_pci_remove,
  313. .driver = {
  314. .pm = &dwc3_pci_dev_pm_ops,
  315. }
  316. };
  317. MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
  318. MODULE_LICENSE("GPL v2");
  319. MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
  320. module_pci_driver(dwc3_pci_driver);