hcd.h 28 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
  2. /*
  3. * hcd.h - DesignWare HS OTG Controller host-mode declarations
  4. *
  5. * Copyright (C) 2004-2013 Synopsys, Inc.
  6. *
  7. * Redistribution and use in source and binary forms, with or without
  8. * modification, are permitted provided that the following conditions
  9. * are met:
  10. * 1. Redistributions of source code must retain the above copyright
  11. * notice, this list of conditions, and the following disclaimer,
  12. * without modification.
  13. * 2. Redistributions in binary form must reproduce the above copyright
  14. * notice, this list of conditions and the following disclaimer in the
  15. * documentation and/or other materials provided with the distribution.
  16. * 3. The names of the above-listed copyright holders may not be used
  17. * to endorse or promote products derived from this software without
  18. * specific prior written permission.
  19. *
  20. * ALTERNATIVELY, this software may be distributed under the terms of the
  21. * GNU General Public License ("GPL") as published by the Free Software
  22. * Foundation; either version 2 of the License, or (at your option) any
  23. * later version.
  24. *
  25. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  26. * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  27. * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28. * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  29. * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  30. * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  31. * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  32. * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  33. * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  34. * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  35. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36. */
  37. #ifndef __DWC2_HCD_H__
  38. #define __DWC2_HCD_H__
  39. /*
  40. * This file contains the structures, constants, and interfaces for the
  41. * Host Contoller Driver (HCD)
  42. *
  43. * The Host Controller Driver (HCD) is responsible for translating requests
  44. * from the USB Driver into the appropriate actions on the DWC_otg controller.
  45. * It isolates the USBD from the specifics of the controller by providing an
  46. * API to the USBD.
  47. */
  48. struct dwc2_qh;
  49. /**
  50. * struct dwc2_host_chan - Software host channel descriptor
  51. *
  52. * @hc_num: Host channel number, used for register address lookup
  53. * @dev_addr: Address of the device
  54. * @ep_num: Endpoint of the device
  55. * @ep_is_in: Endpoint direction
  56. * @speed: Device speed. One of the following values:
  57. * - USB_SPEED_LOW
  58. * - USB_SPEED_FULL
  59. * - USB_SPEED_HIGH
  60. * @ep_type: Endpoint type. One of the following values:
  61. * - USB_ENDPOINT_XFER_CONTROL: 0
  62. * - USB_ENDPOINT_XFER_ISOC: 1
  63. * - USB_ENDPOINT_XFER_BULK: 2
  64. * - USB_ENDPOINT_XFER_INTR: 3
  65. * @max_packet: Max packet size in bytes
  66. * @data_pid_start: PID for initial transaction.
  67. * 0: DATA0
  68. * 1: DATA2
  69. * 2: DATA1
  70. * 3: MDATA (non-Control EP),
  71. * SETUP (Control EP)
  72. * @multi_count: Number of additional periodic transactions per
  73. * (micro)frame
  74. * @xfer_buf: Pointer to current transfer buffer position
  75. * @xfer_dma: DMA address of xfer_buf
  76. * @xfer_len: Total number of bytes to transfer
  77. * @xfer_count: Number of bytes transferred so far
  78. * @start_pkt_count: Packet count at start of transfer
  79. * @xfer_started: True if the transfer has been started
  80. * @do_ping: True if a PING request should be issued on this channel
  81. * @error_state: True if the error count for this transaction is non-zero
  82. * @halt_on_queue: True if this channel should be halted the next time a
  83. * request is queued for the channel. This is necessary in
  84. * slave mode if no request queue space is available when
  85. * an attempt is made to halt the channel.
  86. * @halt_pending: True if the host channel has been halted, but the core
  87. * is not finished flushing queued requests
  88. * @do_split: Enable split for the channel
  89. * @complete_split: Enable complete split
  90. * @hub_addr: Address of high speed hub for the split
  91. * @hub_port: Port of the low/full speed device for the split
  92. * @xact_pos: Split transaction position. One of the following values:
  93. * - DWC2_HCSPLT_XACTPOS_MID
  94. * - DWC2_HCSPLT_XACTPOS_BEGIN
  95. * - DWC2_HCSPLT_XACTPOS_END
  96. * - DWC2_HCSPLT_XACTPOS_ALL
  97. * @requests: Number of requests issued for this channel since it was
  98. * assigned to the current transfer (not counting PINGs)
  99. * @schinfo: Scheduling micro-frame bitmap
  100. * @ntd: Number of transfer descriptors for the transfer
  101. * @halt_status: Reason for halting the host channel
  102. * @hcint: Contents of the HCINT register when the interrupt came
  103. * @qh: QH for the transfer being processed by this channel
  104. * @hc_list_entry: For linking to list of host channels
  105. * @desc_list_addr: Current QH's descriptor list DMA address
  106. * @desc_list_sz: Current QH's descriptor list size
  107. * @split_order_list_entry: List entry for keeping track of the order of splits
  108. *
  109. * This structure represents the state of a single host channel when acting in
  110. * host mode. It contains the data items needed to transfer packets to an
  111. * endpoint via a host channel.
  112. */
  113. struct dwc2_host_chan {
  114. u8 hc_num;
  115. unsigned dev_addr:7;
  116. unsigned ep_num:4;
  117. unsigned ep_is_in:1;
  118. unsigned speed:4;
  119. unsigned ep_type:2;
  120. unsigned max_packet:11;
  121. unsigned data_pid_start:2;
  122. #define DWC2_HC_PID_DATA0 TSIZ_SC_MC_PID_DATA0
  123. #define DWC2_HC_PID_DATA2 TSIZ_SC_MC_PID_DATA2
  124. #define DWC2_HC_PID_DATA1 TSIZ_SC_MC_PID_DATA1
  125. #define DWC2_HC_PID_MDATA TSIZ_SC_MC_PID_MDATA
  126. #define DWC2_HC_PID_SETUP TSIZ_SC_MC_PID_SETUP
  127. unsigned multi_count:2;
  128. u8 *xfer_buf;
  129. dma_addr_t xfer_dma;
  130. u32 xfer_len;
  131. u32 xfer_count;
  132. u16 start_pkt_count;
  133. u8 xfer_started;
  134. u8 do_ping;
  135. u8 error_state;
  136. u8 halt_on_queue;
  137. u8 halt_pending;
  138. u8 do_split;
  139. u8 complete_split;
  140. u8 hub_addr;
  141. u8 hub_port;
  142. u8 xact_pos;
  143. #define DWC2_HCSPLT_XACTPOS_MID HCSPLT_XACTPOS_MID
  144. #define DWC2_HCSPLT_XACTPOS_END HCSPLT_XACTPOS_END
  145. #define DWC2_HCSPLT_XACTPOS_BEGIN HCSPLT_XACTPOS_BEGIN
  146. #define DWC2_HCSPLT_XACTPOS_ALL HCSPLT_XACTPOS_ALL
  147. u8 requests;
  148. u8 schinfo;
  149. u16 ntd;
  150. enum dwc2_halt_status halt_status;
  151. u32 hcint;
  152. struct dwc2_qh *qh;
  153. struct list_head hc_list_entry;
  154. dma_addr_t desc_list_addr;
  155. u32 desc_list_sz;
  156. struct list_head split_order_list_entry;
  157. };
  158. struct dwc2_hcd_pipe_info {
  159. u8 dev_addr;
  160. u8 ep_num;
  161. u8 pipe_type;
  162. u8 pipe_dir;
  163. u16 mps;
  164. };
  165. struct dwc2_hcd_iso_packet_desc {
  166. u32 offset;
  167. u32 length;
  168. u32 actual_length;
  169. u32 status;
  170. };
  171. struct dwc2_qtd;
  172. struct dwc2_hcd_urb {
  173. void *priv;
  174. struct dwc2_qtd *qtd;
  175. void *buf;
  176. dma_addr_t dma;
  177. void *setup_packet;
  178. dma_addr_t setup_dma;
  179. u32 length;
  180. u32 actual_length;
  181. u32 status;
  182. u32 error_count;
  183. u32 packet_count;
  184. u32 flags;
  185. u16 interval;
  186. struct dwc2_hcd_pipe_info pipe_info;
  187. struct dwc2_hcd_iso_packet_desc iso_descs[0];
  188. };
  189. /* Phases for control transfers */
  190. enum dwc2_control_phase {
  191. DWC2_CONTROL_SETUP,
  192. DWC2_CONTROL_DATA,
  193. DWC2_CONTROL_STATUS,
  194. };
  195. /* Transaction types */
  196. enum dwc2_transaction_type {
  197. DWC2_TRANSACTION_NONE,
  198. DWC2_TRANSACTION_PERIODIC,
  199. DWC2_TRANSACTION_NON_PERIODIC,
  200. DWC2_TRANSACTION_ALL,
  201. };
  202. /* The number of elements per LS bitmap (per port on multi_tt) */
  203. #define DWC2_ELEMENTS_PER_LS_BITMAP DIV_ROUND_UP(DWC2_LS_SCHEDULE_SLICES, \
  204. BITS_PER_LONG)
  205. /**
  206. * struct dwc2_tt - dwc2 data associated with a usb_tt
  207. *
  208. * @refcount: Number of Queue Heads (QHs) holding a reference.
  209. * @usb_tt: Pointer back to the official usb_tt.
  210. * @periodic_bitmaps: Bitmap for which parts of the 1ms frame are accounted
  211. * for already. Each is DWC2_ELEMENTS_PER_LS_BITMAP
  212. * elements (so sizeof(long) times that in bytes).
  213. *
  214. * This structure is stored in the hcpriv of the official usb_tt.
  215. */
  216. struct dwc2_tt {
  217. int refcount;
  218. struct usb_tt *usb_tt;
  219. unsigned long periodic_bitmaps[];
  220. };
  221. /**
  222. * struct dwc2_hs_transfer_time - Info about a transfer on the high speed bus.
  223. *
  224. * @start_schedule_us: The start time on the main bus schedule. Note that
  225. * the main bus schedule is tightly packed and this
  226. * time should be interpreted as tightly packed (so
  227. * uFrame 0 starts at 0 us, uFrame 1 starts at 100 us
  228. * instead of 125 us).
  229. * @duration_us: How long this transfer goes.
  230. */
  231. struct dwc2_hs_transfer_time {
  232. u32 start_schedule_us;
  233. u16 duration_us;
  234. };
  235. /**
  236. * struct dwc2_qh - Software queue head structure
  237. *
  238. * @hsotg: The HCD state structure for the DWC OTG controller
  239. * @ep_type: Endpoint type. One of the following values:
  240. * - USB_ENDPOINT_XFER_CONTROL
  241. * - USB_ENDPOINT_XFER_BULK
  242. * - USB_ENDPOINT_XFER_INT
  243. * - USB_ENDPOINT_XFER_ISOC
  244. * @ep_is_in: Endpoint direction
  245. * @maxp: Value from wMaxPacketSize field of Endpoint Descriptor
  246. * @dev_speed: Device speed. One of the following values:
  247. * - USB_SPEED_LOW
  248. * - USB_SPEED_FULL
  249. * - USB_SPEED_HIGH
  250. * @data_toggle: Determines the PID of the next data packet for
  251. * non-controltransfers. Ignored for control transfers.
  252. * One of the following values:
  253. * - DWC2_HC_PID_DATA0
  254. * - DWC2_HC_PID_DATA1
  255. * @ping_state: Ping state
  256. * @do_split: Full/low speed endpoint on high-speed hub requires split
  257. * @td_first: Index of first activated isochronous transfer descriptor
  258. * @td_last: Index of last activated isochronous transfer descriptor
  259. * @host_us: Bandwidth in microseconds per transfer as seen by host
  260. * @device_us: Bandwidth in microseconds per transfer as seen by device
  261. * @host_interval: Interval between transfers as seen by the host. If
  262. * the host is high speed and the device is low speed this
  263. * will be 8 times device interval.
  264. * @device_interval: Interval between transfers as seen by the device.
  265. * interval.
  266. * @next_active_frame: (Micro)frame _before_ we next need to put something on
  267. * the bus. We'll move the qh to active here. If the
  268. * host is in high speed mode this will be a uframe. If
  269. * the host is in low speed mode this will be a full frame.
  270. * @start_active_frame: If we are partway through a split transfer, this will be
  271. * what next_active_frame was when we started. Otherwise
  272. * it should always be the same as next_active_frame.
  273. * @num_hs_transfers: Number of transfers in hs_transfers.
  274. * Normally this is 1 but can be more than one for splits.
  275. * Always >= 1 unless the host is in low/full speed mode.
  276. * @hs_transfers: Transfers that are scheduled as seen by the high speed
  277. * bus. Not used if host is in low or full speed mode (but
  278. * note that it IS USED if the device is low or full speed
  279. * as long as the HOST is in high speed mode).
  280. * @ls_start_schedule_slice: Start time (in slices) on the low speed bus
  281. * schedule that's being used by this device. This
  282. * will be on the periodic_bitmap in a
  283. * "struct dwc2_tt". Not used if this device is high
  284. * speed. Note that this is in "schedule slice" which
  285. * is tightly packed.
  286. * @ntd: Actual number of transfer descriptors in a list
  287. * @qtd_list: List of QTDs for this QH
  288. * @channel: Host channel currently processing transfers for this QH
  289. * @qh_list_entry: Entry for QH in either the periodic or non-periodic
  290. * schedule
  291. * @desc_list: List of transfer descriptors
  292. * @desc_list_dma: Physical address of desc_list
  293. * @desc_list_sz: Size of descriptors list
  294. * @n_bytes: Xfer Bytes array. Each element corresponds to a transfer
  295. * descriptor and indicates original XferSize value for the
  296. * descriptor
  297. * @unreserve_timer: Timer for releasing periodic reservation.
  298. * @wait_timer: Timer used to wait before re-queuing.
  299. * @dwc_tt: Pointer to our tt info (or NULL if no tt).
  300. * @ttport: Port number within our tt.
  301. * @tt_buffer_dirty True if clear_tt_buffer_complete is pending
  302. * @unreserve_pending: True if we planned to unreserve but haven't yet.
  303. * @schedule_low_speed: True if we have a low/full speed component (either the
  304. * host is in low/full speed mode or do_split).
  305. * @want_wait: We should wait before re-queuing; only matters for non-
  306. * periodic transfers and is ignored for periodic ones.
  307. * @wait_timer_cancel: Set to true to cancel the wait_timer.
  308. *
  309. * @tt_buffer_dirty: True if EP's TT buffer is not clean.
  310. * A Queue Head (QH) holds the static characteristics of an endpoint and
  311. * maintains a list of transfers (QTDs) for that endpoint. A QH structure may
  312. * be entered in either the non-periodic or periodic schedule.
  313. */
  314. struct dwc2_qh {
  315. struct dwc2_hsotg *hsotg;
  316. u8 ep_type;
  317. u8 ep_is_in;
  318. u16 maxp;
  319. u8 dev_speed;
  320. u8 data_toggle;
  321. u8 ping_state;
  322. u8 do_split;
  323. u8 td_first;
  324. u8 td_last;
  325. u16 host_us;
  326. u16 device_us;
  327. u16 host_interval;
  328. u16 device_interval;
  329. u16 next_active_frame;
  330. u16 start_active_frame;
  331. s16 num_hs_transfers;
  332. struct dwc2_hs_transfer_time hs_transfers[DWC2_HS_SCHEDULE_UFRAMES];
  333. u32 ls_start_schedule_slice;
  334. u16 ntd;
  335. struct list_head qtd_list;
  336. struct dwc2_host_chan *channel;
  337. struct list_head qh_list_entry;
  338. struct dwc2_dma_desc *desc_list;
  339. dma_addr_t desc_list_dma;
  340. u32 desc_list_sz;
  341. u32 *n_bytes;
  342. struct timer_list unreserve_timer;
  343. struct timer_list wait_timer;
  344. struct dwc2_tt *dwc_tt;
  345. int ttport;
  346. unsigned tt_buffer_dirty:1;
  347. unsigned unreserve_pending:1;
  348. unsigned schedule_low_speed:1;
  349. unsigned want_wait:1;
  350. unsigned wait_timer_cancel:1;
  351. };
  352. /**
  353. * struct dwc2_qtd - Software queue transfer descriptor (QTD)
  354. *
  355. * @control_phase: Current phase for control transfers (Setup, Data, or
  356. * Status)
  357. * @in_process: Indicates if this QTD is currently processed by HW
  358. * @data_toggle: Determines the PID of the next data packet for the
  359. * data phase of control transfers. Ignored for other
  360. * transfer types. One of the following values:
  361. * - DWC2_HC_PID_DATA0
  362. * - DWC2_HC_PID_DATA1
  363. * @complete_split: Keeps track of the current split type for FS/LS
  364. * endpoints on a HS Hub
  365. * @isoc_split_pos: Position of the ISOC split in full/low speed
  366. * @isoc_frame_index: Index of the next frame descriptor for an isochronous
  367. * transfer. A frame descriptor describes the buffer
  368. * position and length of the data to be transferred in the
  369. * next scheduled (micro)frame of an isochronous transfer.
  370. * It also holds status for that transaction. The frame
  371. * index starts at 0.
  372. * @isoc_split_offset: Position of the ISOC split in the buffer for the
  373. * current frame
  374. * @ssplit_out_xfer_count: How many bytes transferred during SSPLIT OUT
  375. * @error_count: Holds the number of bus errors that have occurred for
  376. * a transaction within this transfer
  377. * @n_desc: Number of DMA descriptors for this QTD
  378. * @isoc_frame_index_last: Last activated frame (packet) index, used in
  379. * descriptor DMA mode only
  380. * @num_naks: Number of NAKs received on this QTD.
  381. * @urb: URB for this transfer
  382. * @qh: Queue head for this QTD
  383. * @qtd_list_entry: For linking to the QH's list of QTDs
  384. * @isoc_td_first: Index of first activated isochronous transfer
  385. * descriptor in Descriptor DMA mode
  386. * @isoc_td_last: Index of last activated isochronous transfer
  387. * descriptor in Descriptor DMA mode
  388. *
  389. * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
  390. * interrupt, or isochronous transfer. A single QTD is created for each URB
  391. * (of one of these types) submitted to the HCD. The transfer associated with
  392. * a QTD may require one or multiple transactions.
  393. *
  394. * A QTD is linked to a Queue Head, which is entered in either the
  395. * non-periodic or periodic schedule for execution. When a QTD is chosen for
  396. * execution, some or all of its transactions may be executed. After
  397. * execution, the state of the QTD is updated. The QTD may be retired if all
  398. * its transactions are complete or if an error occurred. Otherwise, it
  399. * remains in the schedule so more transactions can be executed later.
  400. */
  401. struct dwc2_qtd {
  402. enum dwc2_control_phase control_phase;
  403. u8 in_process;
  404. u8 data_toggle;
  405. u8 complete_split;
  406. u8 isoc_split_pos;
  407. u16 isoc_frame_index;
  408. u16 isoc_split_offset;
  409. u16 isoc_td_last;
  410. u16 isoc_td_first;
  411. u32 ssplit_out_xfer_count;
  412. u8 error_count;
  413. u8 n_desc;
  414. u16 isoc_frame_index_last;
  415. u16 num_naks;
  416. struct dwc2_hcd_urb *urb;
  417. struct dwc2_qh *qh;
  418. struct list_head qtd_list_entry;
  419. };
  420. #ifdef DEBUG
  421. struct hc_xfer_info {
  422. struct dwc2_hsotg *hsotg;
  423. struct dwc2_host_chan *chan;
  424. };
  425. #endif
  426. u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg);
  427. /* Gets the struct usb_hcd that contains a struct dwc2_hsotg */
  428. static inline struct usb_hcd *dwc2_hsotg_to_hcd(struct dwc2_hsotg *hsotg)
  429. {
  430. return (struct usb_hcd *)hsotg->priv;
  431. }
  432. /*
  433. * Inline used to disable one channel interrupt. Channel interrupts are
  434. * disabled when the channel is halted or released by the interrupt handler.
  435. * There is no need to handle further interrupts of that type until the
  436. * channel is re-assigned. In fact, subsequent handling may cause crashes
  437. * because the channel structures are cleaned up when the channel is released.
  438. */
  439. static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr)
  440. {
  441. u32 mask = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
  442. mask &= ~intr;
  443. dwc2_writel(mask, hsotg->regs + HCINTMSK(chnum));
  444. }
  445. void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan);
  446. void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
  447. enum dwc2_halt_status halt_status);
  448. void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
  449. struct dwc2_host_chan *chan);
  450. /*
  451. * Reads HPRT0 in preparation to modify. It keeps the WC bits 0 so that if they
  452. * are read as 1, they won't clear when written back.
  453. */
  454. static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg)
  455. {
  456. u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
  457. hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG);
  458. return hprt0;
  459. }
  460. static inline u8 dwc2_hcd_get_ep_num(struct dwc2_hcd_pipe_info *pipe)
  461. {
  462. return pipe->ep_num;
  463. }
  464. static inline u8 dwc2_hcd_get_pipe_type(struct dwc2_hcd_pipe_info *pipe)
  465. {
  466. return pipe->pipe_type;
  467. }
  468. static inline u16 dwc2_hcd_get_mps(struct dwc2_hcd_pipe_info *pipe)
  469. {
  470. return pipe->mps;
  471. }
  472. static inline u8 dwc2_hcd_get_dev_addr(struct dwc2_hcd_pipe_info *pipe)
  473. {
  474. return pipe->dev_addr;
  475. }
  476. static inline u8 dwc2_hcd_is_pipe_isoc(struct dwc2_hcd_pipe_info *pipe)
  477. {
  478. return pipe->pipe_type == USB_ENDPOINT_XFER_ISOC;
  479. }
  480. static inline u8 dwc2_hcd_is_pipe_int(struct dwc2_hcd_pipe_info *pipe)
  481. {
  482. return pipe->pipe_type == USB_ENDPOINT_XFER_INT;
  483. }
  484. static inline u8 dwc2_hcd_is_pipe_bulk(struct dwc2_hcd_pipe_info *pipe)
  485. {
  486. return pipe->pipe_type == USB_ENDPOINT_XFER_BULK;
  487. }
  488. static inline u8 dwc2_hcd_is_pipe_control(struct dwc2_hcd_pipe_info *pipe)
  489. {
  490. return pipe->pipe_type == USB_ENDPOINT_XFER_CONTROL;
  491. }
  492. static inline u8 dwc2_hcd_is_pipe_in(struct dwc2_hcd_pipe_info *pipe)
  493. {
  494. return pipe->pipe_dir == USB_DIR_IN;
  495. }
  496. static inline u8 dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info *pipe)
  497. {
  498. return !dwc2_hcd_is_pipe_in(pipe);
  499. }
  500. int dwc2_hcd_init(struct dwc2_hsotg *hsotg);
  501. void dwc2_hcd_remove(struct dwc2_hsotg *hsotg);
  502. /* Transaction Execution Functions */
  503. enum dwc2_transaction_type dwc2_hcd_select_transactions(
  504. struct dwc2_hsotg *hsotg);
  505. void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
  506. enum dwc2_transaction_type tr_type);
  507. /* Schedule Queue Functions */
  508. /* Implemented in hcd_queue.c */
  509. struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
  510. struct dwc2_hcd_urb *urb,
  511. gfp_t mem_flags);
  512. void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
  513. int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
  514. void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
  515. void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
  516. int sched_csplit);
  517. void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb);
  518. int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
  519. struct dwc2_qh *qh);
  520. /* Unlinks and frees a QTD */
  521. static inline void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg,
  522. struct dwc2_qtd *qtd,
  523. struct dwc2_qh *qh)
  524. {
  525. list_del(&qtd->qtd_list_entry);
  526. kfree(qtd);
  527. qtd = NULL;
  528. }
  529. /* Descriptor DMA support functions */
  530. void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg,
  531. struct dwc2_qh *qh);
  532. void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg,
  533. struct dwc2_host_chan *chan, int chnum,
  534. enum dwc2_halt_status halt_status);
  535. int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
  536. gfp_t mem_flags);
  537. void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
  538. /* Check if QH is non-periodic */
  539. #define dwc2_qh_is_non_per(_qh_ptr_) \
  540. ((_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_BULK || \
  541. (_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_CONTROL)
  542. #ifdef CONFIG_USB_DWC2_DEBUG_PERIODIC
  543. static inline bool dbg_hc(struct dwc2_host_chan *hc) { return true; }
  544. static inline bool dbg_qh(struct dwc2_qh *qh) { return true; }
  545. static inline bool dbg_urb(struct urb *urb) { return true; }
  546. static inline bool dbg_perio(void) { return true; }
  547. #else /* !CONFIG_USB_DWC2_DEBUG_PERIODIC */
  548. static inline bool dbg_hc(struct dwc2_host_chan *hc)
  549. {
  550. return hc->ep_type == USB_ENDPOINT_XFER_BULK ||
  551. hc->ep_type == USB_ENDPOINT_XFER_CONTROL;
  552. }
  553. static inline bool dbg_qh(struct dwc2_qh *qh)
  554. {
  555. return qh->ep_type == USB_ENDPOINT_XFER_BULK ||
  556. qh->ep_type == USB_ENDPOINT_XFER_CONTROL;
  557. }
  558. static inline bool dbg_urb(struct urb *urb)
  559. {
  560. return usb_pipetype(urb->pipe) == PIPE_BULK ||
  561. usb_pipetype(urb->pipe) == PIPE_CONTROL;
  562. }
  563. static inline bool dbg_perio(void) { return false; }
  564. #endif
  565. /* High bandwidth multiplier as encoded in highspeed endpoint descriptors */
  566. #define dwc2_hb_mult(wmaxpacketsize) (1 + (((wmaxpacketsize) >> 11) & 0x03))
  567. /* Packet size for any kind of endpoint descriptor */
  568. #define dwc2_max_packet(wmaxpacketsize) ((wmaxpacketsize) & 0x07ff)
  569. /*
  570. * Returns true if frame1 index is greater than frame2 index. The comparison
  571. * is done modulo FRLISTEN_64_SIZE. This accounts for the rollover of the
  572. * frame number when the max index frame number is reached.
  573. */
  574. static inline bool dwc2_frame_idx_num_gt(u16 fr_idx1, u16 fr_idx2)
  575. {
  576. u16 diff = fr_idx1 - fr_idx2;
  577. u16 sign = diff & (FRLISTEN_64_SIZE >> 1);
  578. return diff && !sign;
  579. }
  580. /*
  581. * Returns true if frame1 is less than or equal to frame2. The comparison is
  582. * done modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the
  583. * frame number when the max frame number is reached.
  584. */
  585. static inline int dwc2_frame_num_le(u16 frame1, u16 frame2)
  586. {
  587. return ((frame2 - frame1) & HFNUM_MAX_FRNUM) <= (HFNUM_MAX_FRNUM >> 1);
  588. }
  589. /*
  590. * Returns true if frame1 is greater than frame2. The comparison is done
  591. * modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
  592. * number when the max frame number is reached.
  593. */
  594. static inline int dwc2_frame_num_gt(u16 frame1, u16 frame2)
  595. {
  596. return (frame1 != frame2) &&
  597. ((frame1 - frame2) & HFNUM_MAX_FRNUM) < (HFNUM_MAX_FRNUM >> 1);
  598. }
  599. /*
  600. * Increments frame by the amount specified by inc. The addition is done
  601. * modulo HFNUM_MAX_FRNUM. Returns the incremented value.
  602. */
  603. static inline u16 dwc2_frame_num_inc(u16 frame, u16 inc)
  604. {
  605. return (frame + inc) & HFNUM_MAX_FRNUM;
  606. }
  607. static inline u16 dwc2_frame_num_dec(u16 frame, u16 dec)
  608. {
  609. return (frame + HFNUM_MAX_FRNUM + 1 - dec) & HFNUM_MAX_FRNUM;
  610. }
  611. static inline u16 dwc2_full_frame_num(u16 frame)
  612. {
  613. return (frame & HFNUM_MAX_FRNUM) >> 3;
  614. }
  615. static inline u16 dwc2_micro_frame_num(u16 frame)
  616. {
  617. return frame & 0x7;
  618. }
  619. /*
  620. * Returns the Core Interrupt Status register contents, ANDed with the Core
  621. * Interrupt Mask register contents
  622. */
  623. static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg)
  624. {
  625. return dwc2_readl(hsotg->regs + GINTSTS) &
  626. dwc2_readl(hsotg->regs + GINTMSK);
  627. }
  628. static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb)
  629. {
  630. return dwc2_urb->status;
  631. }
  632. static inline u32 dwc2_hcd_urb_get_actual_length(
  633. struct dwc2_hcd_urb *dwc2_urb)
  634. {
  635. return dwc2_urb->actual_length;
  636. }
  637. static inline u32 dwc2_hcd_urb_get_error_count(struct dwc2_hcd_urb *dwc2_urb)
  638. {
  639. return dwc2_urb->error_count;
  640. }
  641. static inline void dwc2_hcd_urb_set_iso_desc_params(
  642. struct dwc2_hcd_urb *dwc2_urb, int desc_num, u32 offset,
  643. u32 length)
  644. {
  645. dwc2_urb->iso_descs[desc_num].offset = offset;
  646. dwc2_urb->iso_descs[desc_num].length = length;
  647. }
  648. static inline u32 dwc2_hcd_urb_get_iso_desc_status(
  649. struct dwc2_hcd_urb *dwc2_urb, int desc_num)
  650. {
  651. return dwc2_urb->iso_descs[desc_num].status;
  652. }
  653. static inline u32 dwc2_hcd_urb_get_iso_desc_actual_length(
  654. struct dwc2_hcd_urb *dwc2_urb, int desc_num)
  655. {
  656. return dwc2_urb->iso_descs[desc_num].actual_length;
  657. }
  658. static inline int dwc2_hcd_is_bandwidth_allocated(struct dwc2_hsotg *hsotg,
  659. struct usb_host_endpoint *ep)
  660. {
  661. struct dwc2_qh *qh = ep->hcpriv;
  662. if (qh && !list_empty(&qh->qh_list_entry))
  663. return 1;
  664. return 0;
  665. }
  666. static inline u16 dwc2_hcd_get_ep_bandwidth(struct dwc2_hsotg *hsotg,
  667. struct usb_host_endpoint *ep)
  668. {
  669. struct dwc2_qh *qh = ep->hcpriv;
  670. if (!qh) {
  671. WARN_ON(1);
  672. return 0;
  673. }
  674. return qh->host_us;
  675. }
  676. void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
  677. struct dwc2_host_chan *chan, int chnum,
  678. struct dwc2_qtd *qtd);
  679. /* HCD Core API */
  680. /**
  681. * dwc2_handle_hcd_intr() - Called on every hardware interrupt
  682. *
  683. * @hsotg: The DWC2 HCD
  684. *
  685. * Returns IRQ_HANDLED if interrupt is handled
  686. * Return IRQ_NONE if interrupt is not handled
  687. */
  688. irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg);
  689. /**
  690. * dwc2_hcd_stop() - Halts the DWC_otg host mode operation
  691. *
  692. * @hsotg: The DWC2 HCD
  693. */
  694. void dwc2_hcd_stop(struct dwc2_hsotg *hsotg);
  695. /**
  696. * dwc2_hcd_is_b_host() - Returns 1 if core currently is acting as B host,
  697. * and 0 otherwise
  698. *
  699. * @hsotg: The DWC2 HCD
  700. */
  701. int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg);
  702. /**
  703. * dwc2_hcd_dump_state() - Dumps hsotg state
  704. *
  705. * @hsotg: The DWC2 HCD
  706. *
  707. * NOTE: This function will be removed once the peripheral controller code
  708. * is integrated and the driver is stable
  709. */
  710. void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg);
  711. /* URB interface */
  712. /* Transfer flags */
  713. #define URB_GIVEBACK_ASAP 0x1
  714. #define URB_SEND_ZERO_PACKET 0x2
  715. /* Host driver callbacks */
  716. struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg,
  717. void *context, gfp_t mem_flags,
  718. int *ttport);
  719. void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg,
  720. struct dwc2_tt *dwc_tt);
  721. int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context);
  722. void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
  723. int status);
  724. #endif /* __DWC2_HCD_H__ */