fw.c 22 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2013 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * The full GNU General Public License is included in this distribution in the
  15. * file called LICENSE.
  16. *
  17. * Contact Information:
  18. * wlanfae <wlanfae@realtek.com>
  19. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20. * Hsinchu 300, Taiwan.
  21. *
  22. * Larry Finger <Larry.Finger@lwfinger.net>
  23. *
  24. *****************************************************************************/
  25. #include "../wifi.h"
  26. #include "../pci.h"
  27. #include "../base.h"
  28. #include "../core.h"
  29. #include "../efuse.h"
  30. #include "reg.h"
  31. #include "def.h"
  32. #include "fw.h"
  33. static void _rtl88e_enable_fw_download(struct ieee80211_hw *hw, bool enable)
  34. {
  35. struct rtl_priv *rtlpriv = rtl_priv(hw);
  36. u8 tmp;
  37. if (enable) {
  38. tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
  39. rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp | 0x04);
  40. tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
  41. rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp | 0x01);
  42. tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL + 2);
  43. rtl_write_byte(rtlpriv, REG_MCUFWDL + 2, tmp & 0xf7);
  44. } else {
  45. tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
  46. rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp & 0xfe);
  47. rtl_write_byte(rtlpriv, REG_MCUFWDL + 1, 0x00);
  48. }
  49. }
  50. static void _rtl88e_write_fw(struct ieee80211_hw *hw,
  51. enum version_8188e version, u8 *buffer, u32 size)
  52. {
  53. struct rtl_priv *rtlpriv = rtl_priv(hw);
  54. u8 *bufferptr = (u8 *)buffer;
  55. u32 pagenums, remainsize;
  56. u32 page, offset;
  57. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "FW size is %d bytes,\n", size);
  58. rtl_fill_dummy(bufferptr, &size);
  59. pagenums = size / FW_8192C_PAGE_SIZE;
  60. remainsize = size % FW_8192C_PAGE_SIZE;
  61. if (pagenums > 8)
  62. pr_err("Page numbers should not greater then 8\n");
  63. for (page = 0; page < pagenums; page++) {
  64. offset = page * FW_8192C_PAGE_SIZE;
  65. rtl_fw_page_write(hw, page, (bufferptr + offset),
  66. FW_8192C_PAGE_SIZE);
  67. }
  68. if (remainsize) {
  69. offset = pagenums * FW_8192C_PAGE_SIZE;
  70. page = pagenums;
  71. rtl_fw_page_write(hw, page, (bufferptr + offset), remainsize);
  72. }
  73. }
  74. static int _rtl88e_fw_free_to_go(struct ieee80211_hw *hw)
  75. {
  76. struct rtl_priv *rtlpriv = rtl_priv(hw);
  77. int err = -EIO;
  78. u32 counter = 0;
  79. u32 value32;
  80. do {
  81. value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
  82. } while ((counter++ < FW_8192C_POLLING_TIMEOUT_COUNT) &&
  83. (!(value32 & FWDL_CHKSUM_RPT)));
  84. if (counter >= FW_8192C_POLLING_TIMEOUT_COUNT) {
  85. pr_err("chksum report fail! REG_MCUFWDL:0x%08x .\n",
  86. value32);
  87. goto exit;
  88. }
  89. value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
  90. value32 |= MCUFWDL_RDY;
  91. value32 &= ~WINTINI_RDY;
  92. rtl_write_dword(rtlpriv, REG_MCUFWDL, value32);
  93. rtl88e_firmware_selfreset(hw);
  94. counter = 0;
  95. do {
  96. value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
  97. if (value32 & WINTINI_RDY)
  98. return 0;
  99. udelay(FW_8192C_POLLING_DELAY);
  100. } while (counter++ < FW_8192C_POLLING_TIMEOUT_COUNT);
  101. pr_err("Polling FW ready fail!! REG_MCUFWDL:0x%08x .\n",
  102. value32);
  103. exit:
  104. return err;
  105. }
  106. int rtl88e_download_fw(struct ieee80211_hw *hw,
  107. bool buse_wake_on_wlan_fw)
  108. {
  109. struct rtl_priv *rtlpriv = rtl_priv(hw);
  110. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  111. struct rtlwifi_firmware_header *pfwheader;
  112. u8 *pfwdata;
  113. u32 fwsize;
  114. int err;
  115. enum version_8188e version = rtlhal->version;
  116. if (!rtlhal->pfirmware)
  117. return 1;
  118. pfwheader = (struct rtlwifi_firmware_header *)rtlhal->pfirmware;
  119. rtlhal->fw_version = le16_to_cpu(pfwheader->version);
  120. rtlhal->fw_subversion = pfwheader->subversion;
  121. pfwdata = rtlhal->pfirmware;
  122. fwsize = rtlhal->fwsize;
  123. RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
  124. "normal Firmware SIZE %d\n", fwsize);
  125. if (IS_FW_HEADER_EXIST(pfwheader)) {
  126. RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
  127. "Firmware Version(%d), Signature(%#x), Size(%d)\n",
  128. pfwheader->version, pfwheader->signature,
  129. (int)sizeof(struct rtlwifi_firmware_header));
  130. pfwdata = pfwdata + sizeof(struct rtlwifi_firmware_header);
  131. fwsize = fwsize - sizeof(struct rtlwifi_firmware_header);
  132. }
  133. if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) {
  134. rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
  135. rtl88e_firmware_selfreset(hw);
  136. }
  137. _rtl88e_enable_fw_download(hw, true);
  138. _rtl88e_write_fw(hw, version, pfwdata, fwsize);
  139. _rtl88e_enable_fw_download(hw, false);
  140. err = _rtl88e_fw_free_to_go(hw);
  141. if (err)
  142. pr_err("Firmware is not ready to run!\n");
  143. return 0;
  144. }
  145. static bool _rtl88e_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum)
  146. {
  147. struct rtl_priv *rtlpriv = rtl_priv(hw);
  148. u8 val_hmetfr;
  149. val_hmetfr = rtl_read_byte(rtlpriv, REG_HMETFR);
  150. if (((val_hmetfr >> boxnum) & BIT(0)) == 0)
  151. return true;
  152. return false;
  153. }
  154. static void _rtl88e_fill_h2c_command(struct ieee80211_hw *hw,
  155. u8 element_id, u32 cmd_len,
  156. u8 *cmd_b)
  157. {
  158. struct rtl_priv *rtlpriv = rtl_priv(hw);
  159. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  160. u8 boxnum;
  161. u16 box_reg = 0, box_extreg = 0;
  162. u8 u1b_tmp;
  163. bool isfw_read = false;
  164. u8 buf_index = 0;
  165. bool write_sucess = false;
  166. u8 wait_h2c_limmit = 100;
  167. u8 wait_writeh2c_limit = 100;
  168. u8 boxcontent[4], boxextcontent[4];
  169. u32 h2c_waitcounter = 0;
  170. unsigned long flag;
  171. u8 idx;
  172. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "come in\n");
  173. while (true) {
  174. spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
  175. if (rtlhal->h2c_setinprogress) {
  176. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  177. "H2C set in progress! Wait to set..element_id(%d).\n",
  178. element_id);
  179. while (rtlhal->h2c_setinprogress) {
  180. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock,
  181. flag);
  182. h2c_waitcounter++;
  183. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  184. "Wait 100 us (%d times)...\n",
  185. h2c_waitcounter);
  186. udelay(100);
  187. if (h2c_waitcounter > 1000)
  188. return;
  189. spin_lock_irqsave(&rtlpriv->locks.h2c_lock,
  190. flag);
  191. }
  192. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  193. } else {
  194. rtlhal->h2c_setinprogress = true;
  195. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  196. break;
  197. }
  198. }
  199. while (!write_sucess) {
  200. wait_writeh2c_limit--;
  201. if (wait_writeh2c_limit == 0) {
  202. pr_err("Write H2C fail because no trigger for FW INT!\n");
  203. break;
  204. }
  205. boxnum = rtlhal->last_hmeboxnum;
  206. switch (boxnum) {
  207. case 0:
  208. box_reg = REG_HMEBOX_0;
  209. box_extreg = REG_HMEBOX_EXT_0;
  210. break;
  211. case 1:
  212. box_reg = REG_HMEBOX_1;
  213. box_extreg = REG_HMEBOX_EXT_1;
  214. break;
  215. case 2:
  216. box_reg = REG_HMEBOX_2;
  217. box_extreg = REG_HMEBOX_EXT_2;
  218. break;
  219. case 3:
  220. box_reg = REG_HMEBOX_3;
  221. box_extreg = REG_HMEBOX_EXT_3;
  222. break;
  223. default:
  224. RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
  225. "switch case %#x not processed\n", boxnum);
  226. break;
  227. }
  228. isfw_read = _rtl88e_check_fw_read_last_h2c(hw, boxnum);
  229. while (!isfw_read) {
  230. wait_h2c_limmit--;
  231. if (wait_h2c_limmit == 0) {
  232. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  233. "Waiting too long for FW read clear HMEBox(%d)!\n",
  234. boxnum);
  235. break;
  236. }
  237. udelay(10);
  238. isfw_read = _rtl88e_check_fw_read_last_h2c(hw, boxnum);
  239. u1b_tmp = rtl_read_byte(rtlpriv, 0x130);
  240. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  241. "Waiting for FW read clear HMEBox(%d)!!! 0x130 = %2x\n",
  242. boxnum, u1b_tmp);
  243. }
  244. if (!isfw_read) {
  245. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  246. "Write H2C register BOX[%d] fail!!!!! Fw do not read.\n",
  247. boxnum);
  248. break;
  249. }
  250. memset(boxcontent, 0, sizeof(boxcontent));
  251. memset(boxextcontent, 0, sizeof(boxextcontent));
  252. boxcontent[0] = element_id;
  253. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  254. "Write element_id box_reg(%4x) = %2x\n",
  255. box_reg, element_id);
  256. switch (cmd_len) {
  257. case 1:
  258. case 2:
  259. case 3:
  260. /*boxcontent[0] &= ~(BIT(7));*/
  261. memcpy((u8 *)(boxcontent) + 1,
  262. cmd_b + buf_index, cmd_len);
  263. for (idx = 0; idx < 4; idx++) {
  264. rtl_write_byte(rtlpriv, box_reg + idx,
  265. boxcontent[idx]);
  266. }
  267. break;
  268. case 4:
  269. case 5:
  270. case 6:
  271. case 7:
  272. /*boxcontent[0] |= (BIT(7));*/
  273. memcpy((u8 *)(boxextcontent),
  274. cmd_b + buf_index+3, cmd_len-3);
  275. memcpy((u8 *)(boxcontent) + 1,
  276. cmd_b + buf_index, 3);
  277. for (idx = 0; idx < 2; idx++) {
  278. rtl_write_byte(rtlpriv, box_extreg + idx,
  279. boxextcontent[idx]);
  280. }
  281. for (idx = 0; idx < 4; idx++) {
  282. rtl_write_byte(rtlpriv, box_reg + idx,
  283. boxcontent[idx]);
  284. }
  285. break;
  286. default:
  287. RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
  288. "switch case %#x not processed\n", cmd_len);
  289. break;
  290. }
  291. write_sucess = true;
  292. rtlhal->last_hmeboxnum = boxnum + 1;
  293. if (rtlhal->last_hmeboxnum == 4)
  294. rtlhal->last_hmeboxnum = 0;
  295. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  296. "pHalData->last_hmeboxnum = %d\n",
  297. rtlhal->last_hmeboxnum);
  298. }
  299. spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
  300. rtlhal->h2c_setinprogress = false;
  301. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  302. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "go out\n");
  303. }
  304. void rtl88e_fill_h2c_cmd(struct ieee80211_hw *hw,
  305. u8 element_id, u32 cmd_len, u8 *cmdbuffer)
  306. {
  307. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  308. u32 tmp_cmdbuf[2];
  309. if (!rtlhal->fw_ready) {
  310. WARN_ONCE(true,
  311. "rtl8188ee: error H2C cmd because of Fw download fail!!!\n");
  312. return;
  313. }
  314. memset(tmp_cmdbuf, 0, 8);
  315. memcpy(tmp_cmdbuf, cmdbuffer, cmd_len);
  316. _rtl88e_fill_h2c_command(hw, element_id, cmd_len, (u8 *)&tmp_cmdbuf);
  317. return;
  318. }
  319. void rtl88e_firmware_selfreset(struct ieee80211_hw *hw)
  320. {
  321. u8 u1b_tmp;
  322. struct rtl_priv *rtlpriv = rtl_priv(hw);
  323. u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
  324. rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2))));
  325. rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp | BIT(2)));
  326. RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
  327. "8051Reset88E(): 8051 reset success\n");
  328. }
  329. void rtl88e_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
  330. {
  331. struct rtl_priv *rtlpriv = rtl_priv(hw);
  332. u8 u1_h2c_set_pwrmode[H2C_88E_PWEMODE_LENGTH] = { 0 };
  333. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  334. u8 rlbm, power_state = 0;
  335. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "FW LPS mode = %d\n", mode);
  336. SET_H2CCMD_PWRMODE_PARM_MODE(u1_h2c_set_pwrmode, ((mode) ? 1 : 0));
  337. rlbm = 0;/*YJ, temp, 120316. FW now not support RLBM=2.*/
  338. SET_H2CCMD_PWRMODE_PARM_RLBM(u1_h2c_set_pwrmode, rlbm);
  339. SET_H2CCMD_PWRMODE_PARM_SMART_PS(u1_h2c_set_pwrmode,
  340. (rtlpriv->mac80211.p2p) ? ppsc->smart_ps : 1);
  341. SET_H2CCMD_PWRMODE_PARM_AWAKE_INTERVAL(u1_h2c_set_pwrmode,
  342. ppsc->reg_max_lps_awakeintvl);
  343. SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(u1_h2c_set_pwrmode, 0);
  344. if (mode == FW_PS_ACTIVE_MODE)
  345. power_state |= FW_PWR_STATE_ACTIVE;
  346. else
  347. power_state |= FW_PWR_STATE_RF_OFF;
  348. SET_H2CCMD_PWRMODE_PARM_PWR_STATE(u1_h2c_set_pwrmode, power_state);
  349. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
  350. "rtl92c_set_fw_pwrmode(): u1_h2c_set_pwrmode\n",
  351. u1_h2c_set_pwrmode, H2C_88E_PWEMODE_LENGTH);
  352. rtl88e_fill_h2c_cmd(hw, H2C_88E_SETPWRMODE,
  353. H2C_88E_PWEMODE_LENGTH, u1_h2c_set_pwrmode);
  354. }
  355. void rtl88e_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus)
  356. {
  357. u8 u1_joinbssrpt_parm[1] = { 0 };
  358. SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(u1_joinbssrpt_parm, mstatus);
  359. rtl88e_fill_h2c_cmd(hw, H2C_88E_JOINBSSRPT, 1, u1_joinbssrpt_parm);
  360. }
  361. void rtl88e_set_fw_ap_off_load_cmd(struct ieee80211_hw *hw,
  362. u8 ap_offload_enable)
  363. {
  364. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  365. u8 u1_apoffload_parm[H2C_88E_AP_OFFLOAD_LENGTH] = { 0 };
  366. SET_H2CCMD_AP_OFFLOAD_ON(u1_apoffload_parm, ap_offload_enable);
  367. SET_H2CCMD_AP_OFFLOAD_HIDDEN(u1_apoffload_parm, mac->hiddenssid);
  368. SET_H2CCMD_AP_OFFLOAD_DENYANY(u1_apoffload_parm, 0);
  369. rtl88e_fill_h2c_cmd(hw, H2C_88E_AP_OFFLOAD,
  370. H2C_88E_AP_OFFLOAD_LENGTH, u1_apoffload_parm);
  371. }
  372. #define BEACON_PG 0 /* ->1 */
  373. #define PSPOLL_PG 2
  374. #define NULL_PG 3
  375. #define PROBERSP_PG 4 /* ->5 */
  376. #define TOTAL_RESERVED_PKT_LEN 768
  377. static u8 reserved_page_packet[TOTAL_RESERVED_PKT_LEN] = {
  378. /* page 0 beacon */
  379. 0x80, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
  380. 0xFF, 0xFF, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  381. 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x50, 0x08,
  382. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  383. 0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
  384. 0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
  385. 0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
  386. 0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
  387. 0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
  388. 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
  389. 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  390. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  391. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  392. 0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
  393. 0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  394. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  395. /* page 1 beacon */
  396. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  397. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  398. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  399. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  400. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  401. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  402. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  403. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  404. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  405. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  406. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  407. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  408. 0x10, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x10, 0x00,
  409. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  410. 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  411. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  412. /* page 2 ps-poll */
  413. 0xA4, 0x10, 0x01, 0xC0, 0x00, 0x40, 0x10, 0x10,
  414. 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  415. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  416. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  417. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  418. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  419. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  420. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  421. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  422. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  423. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  424. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  425. 0x18, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x00, 0x00,
  426. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
  427. 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  428. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  429. /* page 3 null */
  430. 0x48, 0x01, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
  431. 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  432. 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
  433. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  434. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  435. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  436. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  437. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  438. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  439. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  440. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  441. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  442. 0x72, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x00, 0x00,
  443. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
  444. 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  445. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  446. /* page 4 probe_resp */
  447. 0x50, 0x00, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
  448. 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  449. 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
  450. 0x9E, 0x46, 0x15, 0x32, 0x27, 0xF2, 0x2D, 0x00,
  451. 0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
  452. 0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
  453. 0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
  454. 0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
  455. 0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
  456. 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
  457. 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  458. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  459. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  460. 0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
  461. 0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  462. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  463. /* page 5 probe_resp */
  464. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  465. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  466. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  467. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  468. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  469. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  470. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  471. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  472. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  473. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  474. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  475. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  476. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  477. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  478. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  479. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  480. };
  481. void rtl88e_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished)
  482. {
  483. struct rtl_priv *rtlpriv = rtl_priv(hw);
  484. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  485. struct sk_buff *skb = NULL;
  486. u32 totalpacketlen;
  487. bool rtstatus;
  488. u8 u1rsvdpageloc[5] = { 0 };
  489. bool b_dlok = false;
  490. u8 *beacon;
  491. u8 *p_pspoll;
  492. u8 *nullfunc;
  493. u8 *p_probersp;
  494. /*---------------------------------------------------------
  495. * (1) beacon
  496. *---------------------------------------------------------
  497. */
  498. beacon = &reserved_page_packet[BEACON_PG * 128];
  499. SET_80211_HDR_ADDRESS2(beacon, mac->mac_addr);
  500. SET_80211_HDR_ADDRESS3(beacon, mac->bssid);
  501. /*-------------------------------------------------------
  502. * (2) ps-poll
  503. *--------------------------------------------------------
  504. */
  505. p_pspoll = &reserved_page_packet[PSPOLL_PG * 128];
  506. SET_80211_PS_POLL_AID(p_pspoll, (mac->assoc_id | 0xc000));
  507. SET_80211_PS_POLL_BSSID(p_pspoll, mac->bssid);
  508. SET_80211_PS_POLL_TA(p_pspoll, mac->mac_addr);
  509. SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1rsvdpageloc, PSPOLL_PG);
  510. /*--------------------------------------------------------
  511. * (3) null data
  512. *---------------------------------------------------------
  513. */
  514. nullfunc = &reserved_page_packet[NULL_PG * 128];
  515. SET_80211_HDR_ADDRESS1(nullfunc, mac->bssid);
  516. SET_80211_HDR_ADDRESS2(nullfunc, mac->mac_addr);
  517. SET_80211_HDR_ADDRESS3(nullfunc, mac->bssid);
  518. SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1rsvdpageloc, NULL_PG);
  519. /*---------------------------------------------------------
  520. * (4) probe response
  521. *----------------------------------------------------------
  522. */
  523. p_probersp = &reserved_page_packet[PROBERSP_PG * 128];
  524. SET_80211_HDR_ADDRESS1(p_probersp, mac->bssid);
  525. SET_80211_HDR_ADDRESS2(p_probersp, mac->mac_addr);
  526. SET_80211_HDR_ADDRESS3(p_probersp, mac->bssid);
  527. SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1rsvdpageloc, PROBERSP_PG);
  528. totalpacketlen = TOTAL_RESERVED_PKT_LEN;
  529. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
  530. "rtl88e_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
  531. &reserved_page_packet[0], totalpacketlen);
  532. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
  533. "rtl88e_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
  534. u1rsvdpageloc, 3);
  535. skb = dev_alloc_skb(totalpacketlen);
  536. skb_put_data(skb, &reserved_page_packet, totalpacketlen);
  537. rtstatus = rtl_cmd_send_packet(hw, skb);
  538. if (rtstatus)
  539. b_dlok = true;
  540. if (b_dlok) {
  541. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  542. "Set RSVD page location to Fw.\n");
  543. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
  544. "H2C_RSVDPAGE:\n", u1rsvdpageloc, 3);
  545. rtl88e_fill_h2c_cmd(hw, H2C_88E_RSVDPAGE,
  546. sizeof(u1rsvdpageloc), u1rsvdpageloc);
  547. } else
  548. RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
  549. "Set RSVD page location to Fw FAIL!!!!!!.\n");
  550. }
  551. /*Should check FW support p2p or not.*/
  552. static void rtl88e_set_p2p_ctw_period_cmd(struct ieee80211_hw *hw, u8 ctwindow)
  553. {
  554. u8 u1_ctwindow_period[1] = { ctwindow};
  555. rtl88e_fill_h2c_cmd(hw, H2C_88E_P2P_PS_CTW_CMD, 1, u1_ctwindow_period);
  556. }
  557. void rtl88e_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state)
  558. {
  559. struct rtl_priv *rtlpriv = rtl_priv(hw);
  560. struct rtl_ps_ctl *rtlps = rtl_psc(rtl_priv(hw));
  561. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  562. struct rtl_p2p_ps_info *p2pinfo = &(rtlps->p2p_ps_info);
  563. struct p2p_ps_offload_t *p2p_ps_offload = &rtlhal->p2p_ps_offload;
  564. u8 i;
  565. u16 ctwindow;
  566. u32 start_time, tsf_low;
  567. switch (p2p_ps_state) {
  568. case P2P_PS_DISABLE:
  569. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_DISABLE\n");
  570. memset(p2p_ps_offload, 0, sizeof(*p2p_ps_offload));
  571. break;
  572. case P2P_PS_ENABLE:
  573. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_ENABLE\n");
  574. /* update CTWindow value. */
  575. if (p2pinfo->ctwindow > 0) {
  576. p2p_ps_offload->ctwindow_en = 1;
  577. ctwindow = p2pinfo->ctwindow;
  578. rtl88e_set_p2p_ctw_period_cmd(hw, ctwindow);
  579. }
  580. /* hw only support 2 set of NoA */
  581. for (i = 0 ; i < p2pinfo->noa_num; i++) {
  582. /* To control the register setting for which NOA*/
  583. rtl_write_byte(rtlpriv, 0x5cf, (i << 4));
  584. if (i == 0)
  585. p2p_ps_offload->noa0_en = 1;
  586. else
  587. p2p_ps_offload->noa1_en = 1;
  588. /* config P2P NoA Descriptor Register */
  589. rtl_write_dword(rtlpriv, 0x5E0,
  590. p2pinfo->noa_duration[i]);
  591. rtl_write_dword(rtlpriv, 0x5E4,
  592. p2pinfo->noa_interval[i]);
  593. /*Get Current TSF value */
  594. tsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
  595. start_time = p2pinfo->noa_start_time[i];
  596. if (p2pinfo->noa_count_type[i] != 1) {
  597. while (start_time <= (tsf_low+(50*1024))) {
  598. start_time += p2pinfo->noa_interval[i];
  599. if (p2pinfo->noa_count_type[i] != 255)
  600. p2pinfo->noa_count_type[i]--;
  601. }
  602. }
  603. rtl_write_dword(rtlpriv, 0x5E8, start_time);
  604. rtl_write_dword(rtlpriv, 0x5EC,
  605. p2pinfo->noa_count_type[i]);
  606. }
  607. if ((p2pinfo->opp_ps == 1) || (p2pinfo->noa_num > 0)) {
  608. /* rst p2p circuit */
  609. rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, BIT(4));
  610. p2p_ps_offload->offload_en = 1;
  611. if (P2P_ROLE_GO == rtlpriv->mac80211.p2p) {
  612. p2p_ps_offload->role = 1;
  613. p2p_ps_offload->allstasleep = -1;
  614. } else {
  615. p2p_ps_offload->role = 0;
  616. }
  617. p2p_ps_offload->discovery = 0;
  618. }
  619. break;
  620. case P2P_PS_SCAN:
  621. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_SCAN\n");
  622. p2p_ps_offload->discovery = 1;
  623. break;
  624. case P2P_PS_SCAN_DONE:
  625. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_SCAN_DONE\n");
  626. p2p_ps_offload->discovery = 0;
  627. p2pinfo->p2p_ps_state = P2P_PS_ENABLE;
  628. break;
  629. default:
  630. break;
  631. }
  632. rtl88e_fill_h2c_cmd(hw, H2C_88E_P2P_PS_OFFLOAD, 1,
  633. (u8 *)p2p_ps_offload);
  634. }