nvm.c 18 KB

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  1. /******************************************************************************
  2. *
  3. * This file is provided under a dual BSD/GPLv2 license. When using or
  4. * redistributing this file, you may do so under either license.
  5. *
  6. * GPL LICENSE SUMMARY
  7. *
  8. * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
  9. * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10. * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  11. * Copyright(c) 2018 Intel Corporation
  12. *
  13. * This program is free software; you can redistribute it and/or modify
  14. * it under the terms of version 2 of the GNU General Public License as
  15. * published by the Free Software Foundation.
  16. *
  17. * This program is distributed in the hope that it will be useful, but
  18. * WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  20. * General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  25. * USA
  26. *
  27. * The full GNU General Public License is included in this distribution
  28. * in the file called COPYING.
  29. *
  30. * Contact Information:
  31. * Intel Linux Wireless <linuxwifi@intel.com>
  32. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  33. *
  34. * BSD LICENSE
  35. *
  36. * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
  37. * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  38. * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  39. * Copyright(c) 2018 Intel Corporation
  40. * All rights reserved.
  41. *
  42. * Redistribution and use in source and binary forms, with or without
  43. * modification, are permitted provided that the following conditions
  44. * are met:
  45. *
  46. * * Redistributions of source code must retain the above copyright
  47. * notice, this list of conditions and the following disclaimer.
  48. * * Redistributions in binary form must reproduce the above copyright
  49. * notice, this list of conditions and the following disclaimer in
  50. * the documentation and/or other materials provided with the
  51. * distribution.
  52. * * Neither the name Intel Corporation nor the names of its
  53. * contributors may be used to endorse or promote products derived
  54. * from this software without specific prior written permission.
  55. *
  56. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  57. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  58. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  59. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  60. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  61. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  62. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  63. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  64. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  65. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  66. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  67. *
  68. *****************************************************************************/
  69. #include <linux/firmware.h>
  70. #include <linux/rtnetlink.h>
  71. #include "iwl-trans.h"
  72. #include "iwl-csr.h"
  73. #include "mvm.h"
  74. #include "iwl-eeprom-parse.h"
  75. #include "iwl-eeprom-read.h"
  76. #include "iwl-nvm-parse.h"
  77. #include "iwl-prph.h"
  78. #include "fw/acpi.h"
  79. /* Default NVM size to read */
  80. #define IWL_NVM_DEFAULT_CHUNK_SIZE (2 * 1024)
  81. #define NVM_WRITE_OPCODE 1
  82. #define NVM_READ_OPCODE 0
  83. /* load nvm chunk response */
  84. enum {
  85. READ_NVM_CHUNK_SUCCEED = 0,
  86. READ_NVM_CHUNK_NOT_VALID_ADDRESS = 1
  87. };
  88. /*
  89. * prepare the NVM host command w/ the pointers to the nvm buffer
  90. * and send it to fw
  91. */
  92. static int iwl_nvm_write_chunk(struct iwl_mvm *mvm, u16 section,
  93. u16 offset, u16 length, const u8 *data)
  94. {
  95. struct iwl_nvm_access_cmd nvm_access_cmd = {
  96. .offset = cpu_to_le16(offset),
  97. .length = cpu_to_le16(length),
  98. .type = cpu_to_le16(section),
  99. .op_code = NVM_WRITE_OPCODE,
  100. };
  101. struct iwl_host_cmd cmd = {
  102. .id = NVM_ACCESS_CMD,
  103. .len = { sizeof(struct iwl_nvm_access_cmd), length },
  104. .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL,
  105. .data = { &nvm_access_cmd, data },
  106. /* data may come from vmalloc, so use _DUP */
  107. .dataflags = { 0, IWL_HCMD_DFL_DUP },
  108. };
  109. struct iwl_rx_packet *pkt;
  110. struct iwl_nvm_access_resp *nvm_resp;
  111. int ret;
  112. ret = iwl_mvm_send_cmd(mvm, &cmd);
  113. if (ret)
  114. return ret;
  115. pkt = cmd.resp_pkt;
  116. /* Extract & check NVM write response */
  117. nvm_resp = (void *)pkt->data;
  118. if (le16_to_cpu(nvm_resp->status) != READ_NVM_CHUNK_SUCCEED) {
  119. IWL_ERR(mvm,
  120. "NVM access write command failed for section %u (status = 0x%x)\n",
  121. section, le16_to_cpu(nvm_resp->status));
  122. ret = -EIO;
  123. }
  124. iwl_free_resp(&cmd);
  125. return ret;
  126. }
  127. static int iwl_nvm_read_chunk(struct iwl_mvm *mvm, u16 section,
  128. u16 offset, u16 length, u8 *data)
  129. {
  130. struct iwl_nvm_access_cmd nvm_access_cmd = {
  131. .offset = cpu_to_le16(offset),
  132. .length = cpu_to_le16(length),
  133. .type = cpu_to_le16(section),
  134. .op_code = NVM_READ_OPCODE,
  135. };
  136. struct iwl_nvm_access_resp *nvm_resp;
  137. struct iwl_rx_packet *pkt;
  138. struct iwl_host_cmd cmd = {
  139. .id = NVM_ACCESS_CMD,
  140. .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL,
  141. .data = { &nvm_access_cmd, },
  142. };
  143. int ret, bytes_read, offset_read;
  144. u8 *resp_data;
  145. cmd.len[0] = sizeof(struct iwl_nvm_access_cmd);
  146. ret = iwl_mvm_send_cmd(mvm, &cmd);
  147. if (ret)
  148. return ret;
  149. pkt = cmd.resp_pkt;
  150. /* Extract NVM response */
  151. nvm_resp = (void *)pkt->data;
  152. ret = le16_to_cpu(nvm_resp->status);
  153. bytes_read = le16_to_cpu(nvm_resp->length);
  154. offset_read = le16_to_cpu(nvm_resp->offset);
  155. resp_data = nvm_resp->data;
  156. if (ret) {
  157. if ((offset != 0) &&
  158. (ret == READ_NVM_CHUNK_NOT_VALID_ADDRESS)) {
  159. /*
  160. * meaning of NOT_VALID_ADDRESS:
  161. * driver try to read chunk from address that is
  162. * multiple of 2K and got an error since addr is empty.
  163. * meaning of (offset != 0): driver already
  164. * read valid data from another chunk so this case
  165. * is not an error.
  166. */
  167. IWL_DEBUG_EEPROM(mvm->trans->dev,
  168. "NVM access command failed on offset 0x%x since that section size is multiple 2K\n",
  169. offset);
  170. ret = 0;
  171. } else {
  172. IWL_DEBUG_EEPROM(mvm->trans->dev,
  173. "NVM access command failed with status %d (device: %s)\n",
  174. ret, mvm->cfg->name);
  175. ret = -EIO;
  176. }
  177. goto exit;
  178. }
  179. if (offset_read != offset) {
  180. IWL_ERR(mvm, "NVM ACCESS response with invalid offset %d\n",
  181. offset_read);
  182. ret = -EINVAL;
  183. goto exit;
  184. }
  185. /* Write data to NVM */
  186. memcpy(data + offset, resp_data, bytes_read);
  187. ret = bytes_read;
  188. exit:
  189. iwl_free_resp(&cmd);
  190. return ret;
  191. }
  192. static int iwl_nvm_write_section(struct iwl_mvm *mvm, u16 section,
  193. const u8 *data, u16 length)
  194. {
  195. int offset = 0;
  196. /* copy data in chunks of 2k (and remainder if any) */
  197. while (offset < length) {
  198. int chunk_size, ret;
  199. chunk_size = min(IWL_NVM_DEFAULT_CHUNK_SIZE,
  200. length - offset);
  201. ret = iwl_nvm_write_chunk(mvm, section, offset,
  202. chunk_size, data + offset);
  203. if (ret < 0)
  204. return ret;
  205. offset += chunk_size;
  206. }
  207. return 0;
  208. }
  209. /*
  210. * Reads an NVM section completely.
  211. * NICs prior to 7000 family doesn't have a real NVM, but just read
  212. * section 0 which is the EEPROM. Because the EEPROM reading is unlimited
  213. * by uCode, we need to manually check in this case that we don't
  214. * overflow and try to read more than the EEPROM size.
  215. * For 7000 family NICs, we supply the maximal size we can read, and
  216. * the uCode fills the response with as much data as we can,
  217. * without overflowing, so no check is needed.
  218. */
  219. static int iwl_nvm_read_section(struct iwl_mvm *mvm, u16 section,
  220. u8 *data, u32 size_read)
  221. {
  222. u16 length, offset = 0;
  223. int ret;
  224. /* Set nvm section read length */
  225. length = IWL_NVM_DEFAULT_CHUNK_SIZE;
  226. ret = length;
  227. /* Read the NVM until exhausted (reading less than requested) */
  228. while (ret == length) {
  229. /* Check no memory assumptions fail and cause an overflow */
  230. if ((size_read + offset + length) >
  231. mvm->cfg->base_params->eeprom_size) {
  232. IWL_ERR(mvm, "EEPROM size is too small for NVM\n");
  233. return -ENOBUFS;
  234. }
  235. ret = iwl_nvm_read_chunk(mvm, section, offset, length, data);
  236. if (ret < 0) {
  237. IWL_DEBUG_EEPROM(mvm->trans->dev,
  238. "Cannot read NVM from section %d offset %d, length %d\n",
  239. section, offset, length);
  240. return ret;
  241. }
  242. offset += ret;
  243. }
  244. iwl_nvm_fixups(mvm->trans->hw_id, section, data, offset);
  245. IWL_DEBUG_EEPROM(mvm->trans->dev,
  246. "NVM section %d read completed\n", section);
  247. return offset;
  248. }
  249. static struct iwl_nvm_data *
  250. iwl_parse_nvm_sections(struct iwl_mvm *mvm)
  251. {
  252. struct iwl_nvm_section *sections = mvm->nvm_sections;
  253. const __be16 *hw;
  254. const __le16 *sw, *calib, *regulatory, *mac_override, *phy_sku;
  255. bool lar_enabled;
  256. int regulatory_type;
  257. /* Checking for required sections */
  258. if (mvm->trans->cfg->nvm_type != IWL_NVM_EXT) {
  259. if (!mvm->nvm_sections[NVM_SECTION_TYPE_SW].data ||
  260. !mvm->nvm_sections[mvm->cfg->nvm_hw_section_num].data) {
  261. IWL_ERR(mvm, "Can't parse empty OTP/NVM sections\n");
  262. return NULL;
  263. }
  264. } else {
  265. if (mvm->trans->cfg->nvm_type == IWL_NVM_SDP)
  266. regulatory_type = NVM_SECTION_TYPE_REGULATORY_SDP;
  267. else
  268. regulatory_type = NVM_SECTION_TYPE_REGULATORY;
  269. /* SW and REGULATORY sections are mandatory */
  270. if (!mvm->nvm_sections[NVM_SECTION_TYPE_SW].data ||
  271. !mvm->nvm_sections[regulatory_type].data) {
  272. IWL_ERR(mvm,
  273. "Can't parse empty family 8000 OTP/NVM sections\n");
  274. return NULL;
  275. }
  276. /* MAC_OVERRIDE or at least HW section must exist */
  277. if (!mvm->nvm_sections[mvm->cfg->nvm_hw_section_num].data &&
  278. !mvm->nvm_sections[NVM_SECTION_TYPE_MAC_OVERRIDE].data) {
  279. IWL_ERR(mvm,
  280. "Can't parse mac_address, empty sections\n");
  281. return NULL;
  282. }
  283. /* PHY_SKU section is mandatory in B0 */
  284. if (!mvm->nvm_sections[NVM_SECTION_TYPE_PHY_SKU].data) {
  285. IWL_ERR(mvm,
  286. "Can't parse phy_sku in B0, empty sections\n");
  287. return NULL;
  288. }
  289. }
  290. hw = (const __be16 *)sections[mvm->cfg->nvm_hw_section_num].data;
  291. sw = (const __le16 *)sections[NVM_SECTION_TYPE_SW].data;
  292. calib = (const __le16 *)sections[NVM_SECTION_TYPE_CALIBRATION].data;
  293. mac_override =
  294. (const __le16 *)sections[NVM_SECTION_TYPE_MAC_OVERRIDE].data;
  295. phy_sku = (const __le16 *)sections[NVM_SECTION_TYPE_PHY_SKU].data;
  296. regulatory = mvm->trans->cfg->nvm_type == IWL_NVM_SDP ?
  297. (const __le16 *)sections[NVM_SECTION_TYPE_REGULATORY_SDP].data :
  298. (const __le16 *)sections[NVM_SECTION_TYPE_REGULATORY].data;
  299. lar_enabled = !iwlwifi_mod_params.lar_disable &&
  300. fw_has_capa(&mvm->fw->ucode_capa,
  301. IWL_UCODE_TLV_CAPA_LAR_SUPPORT);
  302. return iwl_parse_nvm_data(mvm->trans, mvm->cfg, hw, sw, calib,
  303. regulatory, mac_override, phy_sku,
  304. mvm->fw->valid_tx_ant, mvm->fw->valid_rx_ant,
  305. lar_enabled);
  306. }
  307. /* Loads the NVM data stored in mvm->nvm_sections into the NIC */
  308. int iwl_mvm_load_nvm_to_nic(struct iwl_mvm *mvm)
  309. {
  310. int i, ret = 0;
  311. struct iwl_nvm_section *sections = mvm->nvm_sections;
  312. IWL_DEBUG_EEPROM(mvm->trans->dev, "'Write to NVM\n");
  313. for (i = 0; i < ARRAY_SIZE(mvm->nvm_sections); i++) {
  314. if (!mvm->nvm_sections[i].data || !mvm->nvm_sections[i].length)
  315. continue;
  316. ret = iwl_nvm_write_section(mvm, i, sections[i].data,
  317. sections[i].length);
  318. if (ret < 0) {
  319. IWL_ERR(mvm, "iwl_mvm_send_cmd failed: %d\n", ret);
  320. break;
  321. }
  322. }
  323. return ret;
  324. }
  325. int iwl_nvm_init(struct iwl_mvm *mvm)
  326. {
  327. int ret, section;
  328. u32 size_read = 0;
  329. u8 *nvm_buffer, *temp;
  330. const char *nvm_file_C = mvm->cfg->default_nvm_file_C_step;
  331. if (WARN_ON_ONCE(mvm->cfg->nvm_hw_section_num >= NVM_MAX_NUM_SECTIONS))
  332. return -EINVAL;
  333. /* load NVM values from nic */
  334. /* Read From FW NVM */
  335. IWL_DEBUG_EEPROM(mvm->trans->dev, "Read from NVM\n");
  336. nvm_buffer = kmalloc(mvm->cfg->base_params->eeprom_size,
  337. GFP_KERNEL);
  338. if (!nvm_buffer)
  339. return -ENOMEM;
  340. for (section = 0; section < NVM_MAX_NUM_SECTIONS; section++) {
  341. /* we override the constness for initial read */
  342. ret = iwl_nvm_read_section(mvm, section, nvm_buffer,
  343. size_read);
  344. if (ret < 0)
  345. continue;
  346. size_read += ret;
  347. temp = kmemdup(nvm_buffer, ret, GFP_KERNEL);
  348. if (!temp) {
  349. ret = -ENOMEM;
  350. break;
  351. }
  352. iwl_nvm_fixups(mvm->trans->hw_id, section, temp, ret);
  353. mvm->nvm_sections[section].data = temp;
  354. mvm->nvm_sections[section].length = ret;
  355. #ifdef CONFIG_IWLWIFI_DEBUGFS
  356. switch (section) {
  357. case NVM_SECTION_TYPE_SW:
  358. mvm->nvm_sw_blob.data = temp;
  359. mvm->nvm_sw_blob.size = ret;
  360. break;
  361. case NVM_SECTION_TYPE_CALIBRATION:
  362. mvm->nvm_calib_blob.data = temp;
  363. mvm->nvm_calib_blob.size = ret;
  364. break;
  365. case NVM_SECTION_TYPE_PRODUCTION:
  366. mvm->nvm_prod_blob.data = temp;
  367. mvm->nvm_prod_blob.size = ret;
  368. break;
  369. case NVM_SECTION_TYPE_PHY_SKU:
  370. mvm->nvm_phy_sku_blob.data = temp;
  371. mvm->nvm_phy_sku_blob.size = ret;
  372. break;
  373. default:
  374. if (section == mvm->cfg->nvm_hw_section_num) {
  375. mvm->nvm_hw_blob.data = temp;
  376. mvm->nvm_hw_blob.size = ret;
  377. break;
  378. }
  379. }
  380. #endif
  381. }
  382. if (!size_read)
  383. IWL_ERR(mvm, "OTP is blank\n");
  384. kfree(nvm_buffer);
  385. /* Only if PNVM selected in the mod param - load external NVM */
  386. if (mvm->nvm_file_name) {
  387. /* read External NVM file from the mod param */
  388. ret = iwl_read_external_nvm(mvm->trans, mvm->nvm_file_name,
  389. mvm->nvm_sections);
  390. if (ret) {
  391. mvm->nvm_file_name = nvm_file_C;
  392. if ((ret == -EFAULT || ret == -ENOENT) &&
  393. mvm->nvm_file_name) {
  394. /* in case nvm file was failed try again */
  395. ret = iwl_read_external_nvm(mvm->trans,
  396. mvm->nvm_file_name,
  397. mvm->nvm_sections);
  398. if (ret)
  399. return ret;
  400. } else {
  401. return ret;
  402. }
  403. }
  404. }
  405. /* parse the relevant nvm sections */
  406. mvm->nvm_data = iwl_parse_nvm_sections(mvm);
  407. if (!mvm->nvm_data)
  408. return -ENODATA;
  409. IWL_DEBUG_EEPROM(mvm->trans->dev, "nvm version = %x\n",
  410. mvm->nvm_data->nvm_version);
  411. return 0;
  412. }
  413. struct iwl_mcc_update_resp *
  414. iwl_mvm_update_mcc(struct iwl_mvm *mvm, const char *alpha2,
  415. enum iwl_mcc_source src_id)
  416. {
  417. struct iwl_mcc_update_cmd mcc_update_cmd = {
  418. .mcc = cpu_to_le16(alpha2[0] << 8 | alpha2[1]),
  419. .source_id = (u8)src_id,
  420. };
  421. struct iwl_mcc_update_resp *resp_cp;
  422. struct iwl_rx_packet *pkt;
  423. struct iwl_host_cmd cmd = {
  424. .id = MCC_UPDATE_CMD,
  425. .flags = CMD_WANT_SKB,
  426. .data = { &mcc_update_cmd },
  427. };
  428. int ret;
  429. u32 status;
  430. int resp_len, n_channels;
  431. u16 mcc;
  432. bool resp_v2 = fw_has_capa(&mvm->fw->ucode_capa,
  433. IWL_UCODE_TLV_CAPA_LAR_SUPPORT_V2);
  434. if (WARN_ON_ONCE(!iwl_mvm_is_lar_supported(mvm)))
  435. return ERR_PTR(-EOPNOTSUPP);
  436. cmd.len[0] = sizeof(struct iwl_mcc_update_cmd);
  437. if (!resp_v2)
  438. cmd.len[0] = sizeof(struct iwl_mcc_update_cmd_v1);
  439. IWL_DEBUG_LAR(mvm, "send MCC update to FW with '%c%c' src = %d\n",
  440. alpha2[0], alpha2[1], src_id);
  441. ret = iwl_mvm_send_cmd(mvm, &cmd);
  442. if (ret)
  443. return ERR_PTR(ret);
  444. pkt = cmd.resp_pkt;
  445. /* Extract MCC response */
  446. if (resp_v2) {
  447. struct iwl_mcc_update_resp *mcc_resp = (void *)pkt->data;
  448. n_channels = __le32_to_cpu(mcc_resp->n_channels);
  449. resp_len = sizeof(struct iwl_mcc_update_resp) +
  450. n_channels * sizeof(__le32);
  451. resp_cp = kmemdup(mcc_resp, resp_len, GFP_KERNEL);
  452. if (!resp_cp) {
  453. resp_cp = ERR_PTR(-ENOMEM);
  454. goto exit;
  455. }
  456. } else {
  457. struct iwl_mcc_update_resp_v1 *mcc_resp_v1 = (void *)pkt->data;
  458. n_channels = __le32_to_cpu(mcc_resp_v1->n_channels);
  459. resp_len = sizeof(struct iwl_mcc_update_resp) +
  460. n_channels * sizeof(__le32);
  461. resp_cp = kzalloc(resp_len, GFP_KERNEL);
  462. if (!resp_cp) {
  463. resp_cp = ERR_PTR(-ENOMEM);
  464. goto exit;
  465. }
  466. resp_cp->status = mcc_resp_v1->status;
  467. resp_cp->mcc = mcc_resp_v1->mcc;
  468. resp_cp->cap = mcc_resp_v1->cap;
  469. resp_cp->source_id = mcc_resp_v1->source_id;
  470. resp_cp->n_channels = mcc_resp_v1->n_channels;
  471. memcpy(resp_cp->channels, mcc_resp_v1->channels,
  472. n_channels * sizeof(__le32));
  473. }
  474. status = le32_to_cpu(resp_cp->status);
  475. mcc = le16_to_cpu(resp_cp->mcc);
  476. /* W/A for a FW/NVM issue - returns 0x00 for the world domain */
  477. if (mcc == 0) {
  478. mcc = 0x3030; /* "00" - world */
  479. resp_cp->mcc = cpu_to_le16(mcc);
  480. }
  481. IWL_DEBUG_LAR(mvm,
  482. "MCC response status: 0x%x. new MCC: 0x%x ('%c%c') change: %d n_chans: %d\n",
  483. status, mcc, mcc >> 8, mcc & 0xff,
  484. !!(status == MCC_RESP_NEW_CHAN_PROFILE), n_channels);
  485. exit:
  486. iwl_free_resp(&cmd);
  487. return resp_cp;
  488. }
  489. int iwl_mvm_init_mcc(struct iwl_mvm *mvm)
  490. {
  491. bool tlv_lar;
  492. bool nvm_lar;
  493. int retval;
  494. struct ieee80211_regdomain *regd;
  495. char mcc[3];
  496. if (mvm->cfg->nvm_type == IWL_NVM_EXT) {
  497. tlv_lar = fw_has_capa(&mvm->fw->ucode_capa,
  498. IWL_UCODE_TLV_CAPA_LAR_SUPPORT);
  499. nvm_lar = mvm->nvm_data->lar_enabled;
  500. if (tlv_lar != nvm_lar)
  501. IWL_INFO(mvm,
  502. "Conflict between TLV & NVM regarding enabling LAR (TLV = %s NVM =%s)\n",
  503. tlv_lar ? "enabled" : "disabled",
  504. nvm_lar ? "enabled" : "disabled");
  505. }
  506. if (!iwl_mvm_is_lar_supported(mvm))
  507. return 0;
  508. /*
  509. * try to replay the last set MCC to FW. If it doesn't exist,
  510. * queue an update to cfg80211 to retrieve the default alpha2 from FW.
  511. */
  512. retval = iwl_mvm_init_fw_regd(mvm);
  513. if (retval != -ENOENT)
  514. return retval;
  515. /*
  516. * Driver regulatory hint for initial update, this also informs the
  517. * firmware we support wifi location updates.
  518. * Disallow scans that might crash the FW while the LAR regdomain
  519. * is not set.
  520. */
  521. mvm->lar_regdom_set = false;
  522. regd = iwl_mvm_get_current_regdomain(mvm, NULL);
  523. if (IS_ERR_OR_NULL(regd))
  524. return -EIO;
  525. if (iwl_mvm_is_wifi_mcc_supported(mvm) &&
  526. !iwl_acpi_get_mcc(mvm->dev, mcc)) {
  527. kfree(regd);
  528. regd = iwl_mvm_get_regdomain(mvm->hw->wiphy, mcc,
  529. MCC_SOURCE_BIOS, NULL);
  530. if (IS_ERR_OR_NULL(regd))
  531. return -EIO;
  532. }
  533. retval = regulatory_set_wiphy_regd_sync_rtnl(mvm->hw->wiphy, regd);
  534. kfree(regd);
  535. return retval;
  536. }
  537. void iwl_mvm_rx_chub_update_mcc(struct iwl_mvm *mvm,
  538. struct iwl_rx_cmd_buffer *rxb)
  539. {
  540. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  541. struct iwl_mcc_chub_notif *notif = (void *)pkt->data;
  542. enum iwl_mcc_source src;
  543. char mcc[3];
  544. struct ieee80211_regdomain *regd;
  545. lockdep_assert_held(&mvm->mutex);
  546. if (iwl_mvm_is_vif_assoc(mvm) && notif->source_id == MCC_SOURCE_WIFI) {
  547. IWL_DEBUG_LAR(mvm, "Ignore mcc update while associated\n");
  548. return;
  549. }
  550. if (WARN_ON_ONCE(!iwl_mvm_is_lar_supported(mvm)))
  551. return;
  552. mcc[0] = le16_to_cpu(notif->mcc) >> 8;
  553. mcc[1] = le16_to_cpu(notif->mcc) & 0xff;
  554. mcc[2] = '\0';
  555. src = notif->source_id;
  556. IWL_DEBUG_LAR(mvm,
  557. "RX: received chub update mcc cmd (mcc '%s' src %d)\n",
  558. mcc, src);
  559. regd = iwl_mvm_get_regdomain(mvm->hw->wiphy, mcc, src, NULL);
  560. if (IS_ERR_OR_NULL(regd))
  561. return;
  562. regulatory_set_wiphy_regd(mvm->hw->wiphy, regd);
  563. kfree(regd);
  564. }