lmc_main.c 61 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107
  1. /*
  2. * Copyright (c) 1997-2000 LAN Media Corporation (LMC)
  3. * All rights reserved. www.lanmedia.com
  4. * Generic HDLC port Copyright (C) 2008 Krzysztof Halasa <khc@pm.waw.pl>
  5. *
  6. * This code is written by:
  7. * Andrew Stanley-Jones (asj@cban.com)
  8. * Rob Braun (bbraun@vix.com),
  9. * Michael Graff (explorer@vix.com) and
  10. * Matt Thomas (matt@3am-software.com).
  11. *
  12. * With Help By:
  13. * David Boggs
  14. * Ron Crane
  15. * Alan Cox
  16. *
  17. * This software may be used and distributed according to the terms
  18. * of the GNU General Public License version 2, incorporated herein by reference.
  19. *
  20. * Driver for the LanMedia LMC5200, LMC5245, LMC1000, LMC1200 cards.
  21. *
  22. * To control link specific options lmcctl is required.
  23. * It can be obtained from ftp.lanmedia.com.
  24. *
  25. * Linux driver notes:
  26. * Linux uses the device struct lmc_private to pass private information
  27. * around.
  28. *
  29. * The initialization portion of this driver (the lmc_reset() and the
  30. * lmc_dec_reset() functions, as well as the led controls and the
  31. * lmc_initcsrs() functions.
  32. *
  33. * The watchdog function runs every second and checks to see if
  34. * we still have link, and that the timing source is what we expected
  35. * it to be. If link is lost, the interface is marked down, and
  36. * we no longer can transmit.
  37. *
  38. */
  39. #include <linux/kernel.h>
  40. #include <linux/module.h>
  41. #include <linux/string.h>
  42. #include <linux/timer.h>
  43. #include <linux/ptrace.h>
  44. #include <linux/errno.h>
  45. #include <linux/ioport.h>
  46. #include <linux/slab.h>
  47. #include <linux/interrupt.h>
  48. #include <linux/pci.h>
  49. #include <linux/delay.h>
  50. #include <linux/hdlc.h>
  51. #include <linux/in.h>
  52. #include <linux/if_arp.h>
  53. #include <linux/netdevice.h>
  54. #include <linux/etherdevice.h>
  55. #include <linux/skbuff.h>
  56. #include <linux/inet.h>
  57. #include <linux/bitops.h>
  58. #include <asm/processor.h> /* Processor type for cache alignment. */
  59. #include <asm/io.h>
  60. #include <asm/dma.h>
  61. #include <linux/uaccess.h>
  62. //#include <asm/spinlock.h>
  63. #define DRIVER_MAJOR_VERSION 1
  64. #define DRIVER_MINOR_VERSION 34
  65. #define DRIVER_SUB_VERSION 0
  66. #define DRIVER_VERSION ((DRIVER_MAJOR_VERSION << 8) + DRIVER_MINOR_VERSION)
  67. #include "lmc.h"
  68. #include "lmc_var.h"
  69. #include "lmc_ioctl.h"
  70. #include "lmc_debug.h"
  71. #include "lmc_proto.h"
  72. static int LMC_PKT_BUF_SZ = 1542;
  73. static const struct pci_device_id lmc_pci_tbl[] = {
  74. { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
  75. PCI_VENDOR_ID_LMC, PCI_ANY_ID },
  76. { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
  77. PCI_ANY_ID, PCI_VENDOR_ID_LMC },
  78. { 0 }
  79. };
  80. MODULE_DEVICE_TABLE(pci, lmc_pci_tbl);
  81. MODULE_LICENSE("GPL v2");
  82. static netdev_tx_t lmc_start_xmit(struct sk_buff *skb,
  83. struct net_device *dev);
  84. static int lmc_rx (struct net_device *dev);
  85. static int lmc_open(struct net_device *dev);
  86. static int lmc_close(struct net_device *dev);
  87. static struct net_device_stats *lmc_get_stats(struct net_device *dev);
  88. static irqreturn_t lmc_interrupt(int irq, void *dev_instance);
  89. static void lmc_initcsrs(lmc_softc_t * const sc, lmc_csrptr_t csr_base, size_t csr_size);
  90. static void lmc_softreset(lmc_softc_t * const);
  91. static void lmc_running_reset(struct net_device *dev);
  92. static int lmc_ifdown(struct net_device * const);
  93. static void lmc_watchdog(struct timer_list *t);
  94. static void lmc_reset(lmc_softc_t * const sc);
  95. static void lmc_dec_reset(lmc_softc_t * const sc);
  96. static void lmc_driver_timeout(struct net_device *dev);
  97. /*
  98. * linux reserves 16 device specific IOCTLs. We call them
  99. * LMCIOC* to control various bits of our world.
  100. */
  101. int lmc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) /*fold00*/
  102. {
  103. lmc_softc_t *sc = dev_to_sc(dev);
  104. lmc_ctl_t ctl;
  105. int ret = -EOPNOTSUPP;
  106. u16 regVal;
  107. unsigned long flags;
  108. lmc_trace(dev, "lmc_ioctl in");
  109. /*
  110. * Most functions mess with the structure
  111. * Disable interrupts while we do the polling
  112. */
  113. switch (cmd) {
  114. /*
  115. * Return current driver state. Since we keep this up
  116. * To date internally, just copy this out to the user.
  117. */
  118. case LMCIOCGINFO: /*fold01*/
  119. if (copy_to_user(ifr->ifr_data, &sc->ictl, sizeof(lmc_ctl_t)))
  120. ret = -EFAULT;
  121. else
  122. ret = 0;
  123. break;
  124. case LMCIOCSINFO: /*fold01*/
  125. if (!capable(CAP_NET_ADMIN)) {
  126. ret = -EPERM;
  127. break;
  128. }
  129. if(dev->flags & IFF_UP){
  130. ret = -EBUSY;
  131. break;
  132. }
  133. if (copy_from_user(&ctl, ifr->ifr_data, sizeof(lmc_ctl_t))) {
  134. ret = -EFAULT;
  135. break;
  136. }
  137. spin_lock_irqsave(&sc->lmc_lock, flags);
  138. sc->lmc_media->set_status (sc, &ctl);
  139. if(ctl.crc_length != sc->ictl.crc_length) {
  140. sc->lmc_media->set_crc_length(sc, ctl.crc_length);
  141. if (sc->ictl.crc_length == LMC_CTL_CRC_LENGTH_16)
  142. sc->TxDescriptControlInit |= LMC_TDES_ADD_CRC_DISABLE;
  143. else
  144. sc->TxDescriptControlInit &= ~LMC_TDES_ADD_CRC_DISABLE;
  145. }
  146. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  147. ret = 0;
  148. break;
  149. case LMCIOCIFTYPE: /*fold01*/
  150. {
  151. u16 old_type = sc->if_type;
  152. u16 new_type;
  153. if (!capable(CAP_NET_ADMIN)) {
  154. ret = -EPERM;
  155. break;
  156. }
  157. if (copy_from_user(&new_type, ifr->ifr_data, sizeof(u16))) {
  158. ret = -EFAULT;
  159. break;
  160. }
  161. if (new_type == old_type)
  162. {
  163. ret = 0 ;
  164. break; /* no change */
  165. }
  166. spin_lock_irqsave(&sc->lmc_lock, flags);
  167. lmc_proto_close(sc);
  168. sc->if_type = new_type;
  169. lmc_proto_attach(sc);
  170. ret = lmc_proto_open(sc);
  171. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  172. break;
  173. }
  174. case LMCIOCGETXINFO: /*fold01*/
  175. spin_lock_irqsave(&sc->lmc_lock, flags);
  176. sc->lmc_xinfo.Magic0 = 0xBEEFCAFE;
  177. sc->lmc_xinfo.PciCardType = sc->lmc_cardtype;
  178. sc->lmc_xinfo.PciSlotNumber = 0;
  179. sc->lmc_xinfo.DriverMajorVersion = DRIVER_MAJOR_VERSION;
  180. sc->lmc_xinfo.DriverMinorVersion = DRIVER_MINOR_VERSION;
  181. sc->lmc_xinfo.DriverSubVersion = DRIVER_SUB_VERSION;
  182. sc->lmc_xinfo.XilinxRevisionNumber =
  183. lmc_mii_readreg (sc, 0, 3) & 0xf;
  184. sc->lmc_xinfo.MaxFrameSize = LMC_PKT_BUF_SZ;
  185. sc->lmc_xinfo.link_status = sc->lmc_media->get_link_status (sc);
  186. sc->lmc_xinfo.mii_reg16 = lmc_mii_readreg (sc, 0, 16);
  187. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  188. sc->lmc_xinfo.Magic1 = 0xDEADBEEF;
  189. if (copy_to_user(ifr->ifr_data, &sc->lmc_xinfo,
  190. sizeof(struct lmc_xinfo)))
  191. ret = -EFAULT;
  192. else
  193. ret = 0;
  194. break;
  195. case LMCIOCGETLMCSTATS:
  196. spin_lock_irqsave(&sc->lmc_lock, flags);
  197. if (sc->lmc_cardtype == LMC_CARDTYPE_T1) {
  198. lmc_mii_writereg(sc, 0, 17, T1FRAMER_FERR_LSB);
  199. sc->extra_stats.framingBitErrorCount +=
  200. lmc_mii_readreg(sc, 0, 18) & 0xff;
  201. lmc_mii_writereg(sc, 0, 17, T1FRAMER_FERR_MSB);
  202. sc->extra_stats.framingBitErrorCount +=
  203. (lmc_mii_readreg(sc, 0, 18) & 0xff) << 8;
  204. lmc_mii_writereg(sc, 0, 17, T1FRAMER_LCV_LSB);
  205. sc->extra_stats.lineCodeViolationCount +=
  206. lmc_mii_readreg(sc, 0, 18) & 0xff;
  207. lmc_mii_writereg(sc, 0, 17, T1FRAMER_LCV_MSB);
  208. sc->extra_stats.lineCodeViolationCount +=
  209. (lmc_mii_readreg(sc, 0, 18) & 0xff) << 8;
  210. lmc_mii_writereg(sc, 0, 17, T1FRAMER_AERR);
  211. regVal = lmc_mii_readreg(sc, 0, 18) & 0xff;
  212. sc->extra_stats.lossOfFrameCount +=
  213. (regVal & T1FRAMER_LOF_MASK) >> 4;
  214. sc->extra_stats.changeOfFrameAlignmentCount +=
  215. (regVal & T1FRAMER_COFA_MASK) >> 2;
  216. sc->extra_stats.severelyErroredFrameCount +=
  217. regVal & T1FRAMER_SEF_MASK;
  218. }
  219. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  220. if (copy_to_user(ifr->ifr_data, &sc->lmc_device->stats,
  221. sizeof(sc->lmc_device->stats)) ||
  222. copy_to_user(ifr->ifr_data + sizeof(sc->lmc_device->stats),
  223. &sc->extra_stats, sizeof(sc->extra_stats)))
  224. ret = -EFAULT;
  225. else
  226. ret = 0;
  227. break;
  228. case LMCIOCCLEARLMCSTATS:
  229. if (!capable(CAP_NET_ADMIN)) {
  230. ret = -EPERM;
  231. break;
  232. }
  233. spin_lock_irqsave(&sc->lmc_lock, flags);
  234. memset(&sc->lmc_device->stats, 0, sizeof(sc->lmc_device->stats));
  235. memset(&sc->extra_stats, 0, sizeof(sc->extra_stats));
  236. sc->extra_stats.check = STATCHECK;
  237. sc->extra_stats.version_size = (DRIVER_VERSION << 16) +
  238. sizeof(sc->lmc_device->stats) + sizeof(sc->extra_stats);
  239. sc->extra_stats.lmc_cardtype = sc->lmc_cardtype;
  240. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  241. ret = 0;
  242. break;
  243. case LMCIOCSETCIRCUIT: /*fold01*/
  244. if (!capable(CAP_NET_ADMIN)){
  245. ret = -EPERM;
  246. break;
  247. }
  248. if(dev->flags & IFF_UP){
  249. ret = -EBUSY;
  250. break;
  251. }
  252. if (copy_from_user(&ctl, ifr->ifr_data, sizeof(lmc_ctl_t))) {
  253. ret = -EFAULT;
  254. break;
  255. }
  256. spin_lock_irqsave(&sc->lmc_lock, flags);
  257. sc->lmc_media->set_circuit_type(sc, ctl.circuit_type);
  258. sc->ictl.circuit_type = ctl.circuit_type;
  259. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  260. ret = 0;
  261. break;
  262. case LMCIOCRESET: /*fold01*/
  263. if (!capable(CAP_NET_ADMIN)){
  264. ret = -EPERM;
  265. break;
  266. }
  267. spin_lock_irqsave(&sc->lmc_lock, flags);
  268. /* Reset driver and bring back to current state */
  269. printk (" REG16 before reset +%04x\n", lmc_mii_readreg (sc, 0, 16));
  270. lmc_running_reset (dev);
  271. printk (" REG16 after reset +%04x\n", lmc_mii_readreg (sc, 0, 16));
  272. LMC_EVENT_LOG(LMC_EVENT_FORCEDRESET, LMC_CSR_READ (sc, csr_status), lmc_mii_readreg (sc, 0, 16));
  273. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  274. ret = 0;
  275. break;
  276. #ifdef DEBUG
  277. case LMCIOCDUMPEVENTLOG:
  278. if (copy_to_user(ifr->ifr_data, &lmcEventLogIndex, sizeof(u32))) {
  279. ret = -EFAULT;
  280. break;
  281. }
  282. if (copy_to_user(ifr->ifr_data + sizeof(u32), lmcEventLogBuf,
  283. sizeof(lmcEventLogBuf)))
  284. ret = -EFAULT;
  285. else
  286. ret = 0;
  287. break;
  288. #endif /* end ifdef _DBG_EVENTLOG */
  289. case LMCIOCT1CONTROL: /*fold01*/
  290. if (sc->lmc_cardtype != LMC_CARDTYPE_T1){
  291. ret = -EOPNOTSUPP;
  292. break;
  293. }
  294. break;
  295. case LMCIOCXILINX: /*fold01*/
  296. {
  297. struct lmc_xilinx_control xc; /*fold02*/
  298. if (!capable(CAP_NET_ADMIN)){
  299. ret = -EPERM;
  300. break;
  301. }
  302. /*
  303. * Stop the xwitter whlie we restart the hardware
  304. */
  305. netif_stop_queue(dev);
  306. if (copy_from_user(&xc, ifr->ifr_data, sizeof(struct lmc_xilinx_control))) {
  307. ret = -EFAULT;
  308. break;
  309. }
  310. switch(xc.command){
  311. case lmc_xilinx_reset: /*fold02*/
  312. {
  313. u16 mii;
  314. spin_lock_irqsave(&sc->lmc_lock, flags);
  315. mii = lmc_mii_readreg (sc, 0, 16);
  316. /*
  317. * Make all of them 0 and make input
  318. */
  319. lmc_gpio_mkinput(sc, 0xff);
  320. /*
  321. * make the reset output
  322. */
  323. lmc_gpio_mkoutput(sc, LMC_GEP_RESET);
  324. /*
  325. * RESET low to force configuration. This also forces
  326. * the transmitter clock to be internal, but we expect to reset
  327. * that later anyway.
  328. */
  329. sc->lmc_gpio &= ~LMC_GEP_RESET;
  330. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  331. /*
  332. * hold for more than 10 microseconds
  333. */
  334. udelay(50);
  335. sc->lmc_gpio |= LMC_GEP_RESET;
  336. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  337. /*
  338. * stop driving Xilinx-related signals
  339. */
  340. lmc_gpio_mkinput(sc, 0xff);
  341. /* Reset the frammer hardware */
  342. sc->lmc_media->set_link_status (sc, 1);
  343. sc->lmc_media->set_status (sc, NULL);
  344. // lmc_softreset(sc);
  345. {
  346. int i;
  347. for(i = 0; i < 5; i++){
  348. lmc_led_on(sc, LMC_DS3_LED0);
  349. mdelay(100);
  350. lmc_led_off(sc, LMC_DS3_LED0);
  351. lmc_led_on(sc, LMC_DS3_LED1);
  352. mdelay(100);
  353. lmc_led_off(sc, LMC_DS3_LED1);
  354. lmc_led_on(sc, LMC_DS3_LED3);
  355. mdelay(100);
  356. lmc_led_off(sc, LMC_DS3_LED3);
  357. lmc_led_on(sc, LMC_DS3_LED2);
  358. mdelay(100);
  359. lmc_led_off(sc, LMC_DS3_LED2);
  360. }
  361. }
  362. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  363. ret = 0x0;
  364. }
  365. break;
  366. case lmc_xilinx_load_prom: /*fold02*/
  367. {
  368. u16 mii;
  369. int timeout = 500000;
  370. spin_lock_irqsave(&sc->lmc_lock, flags);
  371. mii = lmc_mii_readreg (sc, 0, 16);
  372. /*
  373. * Make all of them 0 and make input
  374. */
  375. lmc_gpio_mkinput(sc, 0xff);
  376. /*
  377. * make the reset output
  378. */
  379. lmc_gpio_mkoutput(sc, LMC_GEP_DP | LMC_GEP_RESET);
  380. /*
  381. * RESET low to force configuration. This also forces
  382. * the transmitter clock to be internal, but we expect to reset
  383. * that later anyway.
  384. */
  385. sc->lmc_gpio &= ~(LMC_GEP_RESET | LMC_GEP_DP);
  386. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  387. /*
  388. * hold for more than 10 microseconds
  389. */
  390. udelay(50);
  391. sc->lmc_gpio |= LMC_GEP_DP | LMC_GEP_RESET;
  392. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  393. /*
  394. * busy wait for the chip to reset
  395. */
  396. while( (LMC_CSR_READ(sc, csr_gp) & LMC_GEP_INIT) == 0 &&
  397. (timeout-- > 0))
  398. cpu_relax();
  399. /*
  400. * stop driving Xilinx-related signals
  401. */
  402. lmc_gpio_mkinput(sc, 0xff);
  403. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  404. ret = 0x0;
  405. break;
  406. }
  407. case lmc_xilinx_load: /*fold02*/
  408. {
  409. char *data;
  410. int pos;
  411. int timeout = 500000;
  412. if (!xc.data) {
  413. ret = -EINVAL;
  414. break;
  415. }
  416. data = memdup_user(xc.data, xc.len);
  417. if (IS_ERR(data)) {
  418. ret = PTR_ERR(data);
  419. break;
  420. }
  421. printk("%s: Starting load of data Len: %d at 0x%p == 0x%p\n", dev->name, xc.len, xc.data, data);
  422. spin_lock_irqsave(&sc->lmc_lock, flags);
  423. lmc_gpio_mkinput(sc, 0xff);
  424. /*
  425. * Clear the Xilinx and start prgramming from the DEC
  426. */
  427. /*
  428. * Set ouput as:
  429. * Reset: 0 (active)
  430. * DP: 0 (active)
  431. * Mode: 1
  432. *
  433. */
  434. sc->lmc_gpio = 0x00;
  435. sc->lmc_gpio &= ~LMC_GEP_DP;
  436. sc->lmc_gpio &= ~LMC_GEP_RESET;
  437. sc->lmc_gpio |= LMC_GEP_MODE;
  438. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  439. lmc_gpio_mkoutput(sc, LMC_GEP_MODE | LMC_GEP_DP | LMC_GEP_RESET);
  440. /*
  441. * Wait at least 10 us 20 to be safe
  442. */
  443. udelay(50);
  444. /*
  445. * Clear reset and activate programming lines
  446. * Reset: Input
  447. * DP: Input
  448. * Clock: Output
  449. * Data: Output
  450. * Mode: Output
  451. */
  452. lmc_gpio_mkinput(sc, LMC_GEP_DP | LMC_GEP_RESET);
  453. /*
  454. * Set LOAD, DATA, Clock to 1
  455. */
  456. sc->lmc_gpio = 0x00;
  457. sc->lmc_gpio |= LMC_GEP_MODE;
  458. sc->lmc_gpio |= LMC_GEP_DATA;
  459. sc->lmc_gpio |= LMC_GEP_CLK;
  460. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  461. lmc_gpio_mkoutput(sc, LMC_GEP_DATA | LMC_GEP_CLK | LMC_GEP_MODE );
  462. /*
  463. * busy wait for the chip to reset
  464. */
  465. while( (LMC_CSR_READ(sc, csr_gp) & LMC_GEP_INIT) == 0 &&
  466. (timeout-- > 0))
  467. cpu_relax();
  468. printk(KERN_DEBUG "%s: Waited %d for the Xilinx to clear it's memory\n", dev->name, 500000-timeout);
  469. for(pos = 0; pos < xc.len; pos++){
  470. switch(data[pos]){
  471. case 0:
  472. sc->lmc_gpio &= ~LMC_GEP_DATA; /* Data is 0 */
  473. break;
  474. case 1:
  475. sc->lmc_gpio |= LMC_GEP_DATA; /* Data is 1 */
  476. break;
  477. default:
  478. printk(KERN_WARNING "%s Bad data in xilinx programming data at %d, got %d wanted 0 or 1\n", dev->name, pos, data[pos]);
  479. sc->lmc_gpio |= LMC_GEP_DATA; /* Assume it's 1 */
  480. }
  481. sc->lmc_gpio &= ~LMC_GEP_CLK; /* Clock to zero */
  482. sc->lmc_gpio |= LMC_GEP_MODE;
  483. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  484. udelay(1);
  485. sc->lmc_gpio |= LMC_GEP_CLK; /* Put the clack back to one */
  486. sc->lmc_gpio |= LMC_GEP_MODE;
  487. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  488. udelay(1);
  489. }
  490. if((LMC_CSR_READ(sc, csr_gp) & LMC_GEP_INIT) == 0){
  491. printk(KERN_WARNING "%s: Reprogramming FAILED. Needs to be reprogrammed. (corrupted data)\n", dev->name);
  492. }
  493. else if((LMC_CSR_READ(sc, csr_gp) & LMC_GEP_DP) == 0){
  494. printk(KERN_WARNING "%s: Reprogramming FAILED. Needs to be reprogrammed. (done)\n", dev->name);
  495. }
  496. else {
  497. printk(KERN_DEBUG "%s: Done reprogramming Xilinx, %d bits, good luck!\n", dev->name, pos);
  498. }
  499. lmc_gpio_mkinput(sc, 0xff);
  500. sc->lmc_miireg16 |= LMC_MII16_FIFO_RESET;
  501. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  502. sc->lmc_miireg16 &= ~LMC_MII16_FIFO_RESET;
  503. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  504. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  505. kfree(data);
  506. ret = 0;
  507. break;
  508. }
  509. default: /*fold02*/
  510. ret = -EBADE;
  511. break;
  512. }
  513. netif_wake_queue(dev);
  514. sc->lmc_txfull = 0;
  515. }
  516. break;
  517. default: /*fold01*/
  518. /* If we don't know what to do, give the protocol a shot. */
  519. ret = lmc_proto_ioctl (sc, ifr, cmd);
  520. break;
  521. }
  522. lmc_trace(dev, "lmc_ioctl out");
  523. return ret;
  524. }
  525. /* the watchdog process that cruises around */
  526. static void lmc_watchdog(struct timer_list *t) /*fold00*/
  527. {
  528. lmc_softc_t *sc = from_timer(sc, t, timer);
  529. struct net_device *dev = sc->lmc_device;
  530. int link_status;
  531. u32 ticks;
  532. unsigned long flags;
  533. lmc_trace(dev, "lmc_watchdog in");
  534. spin_lock_irqsave(&sc->lmc_lock, flags);
  535. if(sc->check != 0xBEAFCAFE){
  536. printk("LMC: Corrupt net_device struct, breaking out\n");
  537. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  538. return;
  539. }
  540. /* Make sure the tx jabber and rx watchdog are off,
  541. * and the transmit and receive processes are running.
  542. */
  543. LMC_CSR_WRITE (sc, csr_15, 0x00000011);
  544. sc->lmc_cmdmode |= TULIP_CMD_TXRUN | TULIP_CMD_RXRUN;
  545. LMC_CSR_WRITE (sc, csr_command, sc->lmc_cmdmode);
  546. if (sc->lmc_ok == 0)
  547. goto kick_timer;
  548. LMC_EVENT_LOG(LMC_EVENT_WATCHDOG, LMC_CSR_READ (sc, csr_status), lmc_mii_readreg (sc, 0, 16));
  549. /* --- begin time out check -----------------------------------
  550. * check for a transmit interrupt timeout
  551. * Has the packet xmt vs xmt serviced threshold been exceeded */
  552. if (sc->lmc_taint_tx == sc->lastlmc_taint_tx &&
  553. sc->lmc_device->stats.tx_packets > sc->lasttx_packets &&
  554. sc->tx_TimeoutInd == 0)
  555. {
  556. /* wait for the watchdog to come around again */
  557. sc->tx_TimeoutInd = 1;
  558. }
  559. else if (sc->lmc_taint_tx == sc->lastlmc_taint_tx &&
  560. sc->lmc_device->stats.tx_packets > sc->lasttx_packets &&
  561. sc->tx_TimeoutInd)
  562. {
  563. LMC_EVENT_LOG(LMC_EVENT_XMTINTTMO, LMC_CSR_READ (sc, csr_status), 0);
  564. sc->tx_TimeoutDisplay = 1;
  565. sc->extra_stats.tx_TimeoutCnt++;
  566. /* DEC chip is stuck, hit it with a RESET!!!! */
  567. lmc_running_reset (dev);
  568. /* look at receive & transmit process state to make sure they are running */
  569. LMC_EVENT_LOG(LMC_EVENT_RESET1, LMC_CSR_READ (sc, csr_status), 0);
  570. /* look at: DSR - 02 for Reg 16
  571. * CTS - 08
  572. * DCD - 10
  573. * RI - 20
  574. * for Reg 17
  575. */
  576. LMC_EVENT_LOG(LMC_EVENT_RESET2, lmc_mii_readreg (sc, 0, 16), lmc_mii_readreg (sc, 0, 17));
  577. /* reset the transmit timeout detection flag */
  578. sc->tx_TimeoutInd = 0;
  579. sc->lastlmc_taint_tx = sc->lmc_taint_tx;
  580. sc->lasttx_packets = sc->lmc_device->stats.tx_packets;
  581. } else {
  582. sc->tx_TimeoutInd = 0;
  583. sc->lastlmc_taint_tx = sc->lmc_taint_tx;
  584. sc->lasttx_packets = sc->lmc_device->stats.tx_packets;
  585. }
  586. /* --- end time out check ----------------------------------- */
  587. link_status = sc->lmc_media->get_link_status (sc);
  588. /*
  589. * hardware level link lost, but the interface is marked as up.
  590. * Mark it as down.
  591. */
  592. if ((link_status == 0) && (sc->last_link_status != 0)) {
  593. printk(KERN_WARNING "%s: hardware/physical link down\n", dev->name);
  594. sc->last_link_status = 0;
  595. /* lmc_reset (sc); Why reset??? The link can go down ok */
  596. /* Inform the world that link has been lost */
  597. netif_carrier_off(dev);
  598. }
  599. /*
  600. * hardware link is up, but the interface is marked as down.
  601. * Bring it back up again.
  602. */
  603. if (link_status != 0 && sc->last_link_status == 0) {
  604. printk(KERN_WARNING "%s: hardware/physical link up\n", dev->name);
  605. sc->last_link_status = 1;
  606. /* lmc_reset (sc); Again why reset??? */
  607. netif_carrier_on(dev);
  608. }
  609. /* Call media specific watchdog functions */
  610. sc->lmc_media->watchdog(sc);
  611. /*
  612. * Poke the transmitter to make sure it
  613. * never stops, even if we run out of mem
  614. */
  615. LMC_CSR_WRITE(sc, csr_rxpoll, 0);
  616. /*
  617. * Check for code that failed
  618. * and try and fix it as appropriate
  619. */
  620. if(sc->failed_ring == 1){
  621. /*
  622. * Failed to setup the recv/xmit rin
  623. * Try again
  624. */
  625. sc->failed_ring = 0;
  626. lmc_softreset(sc);
  627. }
  628. if(sc->failed_recv_alloc == 1){
  629. /*
  630. * We failed to alloc mem in the
  631. * interrupt handler, go through the rings
  632. * and rebuild them
  633. */
  634. sc->failed_recv_alloc = 0;
  635. lmc_softreset(sc);
  636. }
  637. /*
  638. * remember the timer value
  639. */
  640. kick_timer:
  641. ticks = LMC_CSR_READ (sc, csr_gp_timer);
  642. LMC_CSR_WRITE (sc, csr_gp_timer, 0xffffffffUL);
  643. sc->ictl.ticks = 0x0000ffff - (ticks & 0x0000ffff);
  644. /*
  645. * restart this timer.
  646. */
  647. sc->timer.expires = jiffies + (HZ);
  648. add_timer (&sc->timer);
  649. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  650. lmc_trace(dev, "lmc_watchdog out");
  651. }
  652. static int lmc_attach(struct net_device *dev, unsigned short encoding,
  653. unsigned short parity)
  654. {
  655. if (encoding == ENCODING_NRZ && parity == PARITY_CRC16_PR1_CCITT)
  656. return 0;
  657. return -EINVAL;
  658. }
  659. static const struct net_device_ops lmc_ops = {
  660. .ndo_open = lmc_open,
  661. .ndo_stop = lmc_close,
  662. .ndo_start_xmit = hdlc_start_xmit,
  663. .ndo_do_ioctl = lmc_ioctl,
  664. .ndo_tx_timeout = lmc_driver_timeout,
  665. .ndo_get_stats = lmc_get_stats,
  666. };
  667. static int lmc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  668. {
  669. lmc_softc_t *sc;
  670. struct net_device *dev;
  671. u16 subdevice;
  672. u16 AdapModelNum;
  673. int err;
  674. static int cards_found;
  675. /* lmc_trace(dev, "lmc_init_one in"); */
  676. err = pcim_enable_device(pdev);
  677. if (err) {
  678. printk(KERN_ERR "lmc: pci enable failed: %d\n", err);
  679. return err;
  680. }
  681. err = pci_request_regions(pdev, "lmc");
  682. if (err) {
  683. printk(KERN_ERR "lmc: pci_request_region failed\n");
  684. return err;
  685. }
  686. /*
  687. * Allocate our own device structure
  688. */
  689. sc = devm_kzalloc(&pdev->dev, sizeof(lmc_softc_t), GFP_KERNEL);
  690. if (!sc)
  691. return -ENOMEM;
  692. dev = alloc_hdlcdev(sc);
  693. if (!dev) {
  694. printk(KERN_ERR "lmc:alloc_netdev for device failed\n");
  695. return -ENOMEM;
  696. }
  697. dev->type = ARPHRD_HDLC;
  698. dev_to_hdlc(dev)->xmit = lmc_start_xmit;
  699. dev_to_hdlc(dev)->attach = lmc_attach;
  700. dev->netdev_ops = &lmc_ops;
  701. dev->watchdog_timeo = HZ; /* 1 second */
  702. dev->tx_queue_len = 100;
  703. sc->lmc_device = dev;
  704. sc->name = dev->name;
  705. sc->if_type = LMC_PPP;
  706. sc->check = 0xBEAFCAFE;
  707. dev->base_addr = pci_resource_start(pdev, 0);
  708. dev->irq = pdev->irq;
  709. pci_set_drvdata(pdev, dev);
  710. SET_NETDEV_DEV(dev, &pdev->dev);
  711. /*
  712. * This will get the protocol layer ready and do any 1 time init's
  713. * Must have a valid sc and dev structure
  714. */
  715. lmc_proto_attach(sc);
  716. /* Init the spin lock so can call it latter */
  717. spin_lock_init(&sc->lmc_lock);
  718. pci_set_master(pdev);
  719. printk(KERN_INFO "%s: detected at %lx, irq %d\n", dev->name,
  720. dev->base_addr, dev->irq);
  721. err = register_hdlc_device(dev);
  722. if (err) {
  723. printk(KERN_ERR "%s: register_netdev failed.\n", dev->name);
  724. free_netdev(dev);
  725. return err;
  726. }
  727. sc->lmc_cardtype = LMC_CARDTYPE_UNKNOWN;
  728. sc->lmc_timing = LMC_CTL_CLOCK_SOURCE_EXT;
  729. /*
  730. *
  731. * Check either the subvendor or the subdevice, some systems reverse
  732. * the setting in the bois, seems to be version and arch dependent?
  733. * Fix the error, exchange the two values
  734. */
  735. if ((subdevice = pdev->subsystem_device) == PCI_VENDOR_ID_LMC)
  736. subdevice = pdev->subsystem_vendor;
  737. switch (subdevice) {
  738. case PCI_DEVICE_ID_LMC_HSSI:
  739. printk(KERN_INFO "%s: LMC HSSI\n", dev->name);
  740. sc->lmc_cardtype = LMC_CARDTYPE_HSSI;
  741. sc->lmc_media = &lmc_hssi_media;
  742. break;
  743. case PCI_DEVICE_ID_LMC_DS3:
  744. printk(KERN_INFO "%s: LMC DS3\n", dev->name);
  745. sc->lmc_cardtype = LMC_CARDTYPE_DS3;
  746. sc->lmc_media = &lmc_ds3_media;
  747. break;
  748. case PCI_DEVICE_ID_LMC_SSI:
  749. printk(KERN_INFO "%s: LMC SSI\n", dev->name);
  750. sc->lmc_cardtype = LMC_CARDTYPE_SSI;
  751. sc->lmc_media = &lmc_ssi_media;
  752. break;
  753. case PCI_DEVICE_ID_LMC_T1:
  754. printk(KERN_INFO "%s: LMC T1\n", dev->name);
  755. sc->lmc_cardtype = LMC_CARDTYPE_T1;
  756. sc->lmc_media = &lmc_t1_media;
  757. break;
  758. default:
  759. printk(KERN_WARNING "%s: LMC UNKNOWN CARD!\n", dev->name);
  760. break;
  761. }
  762. lmc_initcsrs (sc, dev->base_addr, 8);
  763. lmc_gpio_mkinput (sc, 0xff);
  764. sc->lmc_gpio = 0; /* drive no signals yet */
  765. sc->lmc_media->defaults (sc);
  766. sc->lmc_media->set_link_status (sc, LMC_LINK_UP);
  767. /* verify that the PCI Sub System ID matches the Adapter Model number
  768. * from the MII register
  769. */
  770. AdapModelNum = (lmc_mii_readreg (sc, 0, 3) & 0x3f0) >> 4;
  771. if ((AdapModelNum != LMC_ADAP_T1 || /* detect LMC1200 */
  772. subdevice != PCI_DEVICE_ID_LMC_T1) &&
  773. (AdapModelNum != LMC_ADAP_SSI || /* detect LMC1000 */
  774. subdevice != PCI_DEVICE_ID_LMC_SSI) &&
  775. (AdapModelNum != LMC_ADAP_DS3 || /* detect LMC5245 */
  776. subdevice != PCI_DEVICE_ID_LMC_DS3) &&
  777. (AdapModelNum != LMC_ADAP_HSSI || /* detect LMC5200 */
  778. subdevice != PCI_DEVICE_ID_LMC_HSSI))
  779. printk(KERN_WARNING "%s: Model number (%d) miscompare for PCI"
  780. " Subsystem ID = 0x%04x\n",
  781. dev->name, AdapModelNum, subdevice);
  782. /*
  783. * reset clock
  784. */
  785. LMC_CSR_WRITE (sc, csr_gp_timer, 0xFFFFFFFFUL);
  786. sc->board_idx = cards_found++;
  787. sc->extra_stats.check = STATCHECK;
  788. sc->extra_stats.version_size = (DRIVER_VERSION << 16) +
  789. sizeof(sc->lmc_device->stats) + sizeof(sc->extra_stats);
  790. sc->extra_stats.lmc_cardtype = sc->lmc_cardtype;
  791. sc->lmc_ok = 0;
  792. sc->last_link_status = 0;
  793. lmc_trace(dev, "lmc_init_one out");
  794. return 0;
  795. }
  796. /*
  797. * Called from pci when removing module.
  798. */
  799. static void lmc_remove_one(struct pci_dev *pdev)
  800. {
  801. struct net_device *dev = pci_get_drvdata(pdev);
  802. if (dev) {
  803. printk(KERN_DEBUG "%s: removing...\n", dev->name);
  804. unregister_hdlc_device(dev);
  805. free_netdev(dev);
  806. }
  807. }
  808. /* After this is called, packets can be sent.
  809. * Does not initialize the addresses
  810. */
  811. static int lmc_open(struct net_device *dev)
  812. {
  813. lmc_softc_t *sc = dev_to_sc(dev);
  814. int err;
  815. lmc_trace(dev, "lmc_open in");
  816. lmc_led_on(sc, LMC_DS3_LED0);
  817. lmc_dec_reset(sc);
  818. lmc_reset(sc);
  819. LMC_EVENT_LOG(LMC_EVENT_RESET1, LMC_CSR_READ(sc, csr_status), 0);
  820. LMC_EVENT_LOG(LMC_EVENT_RESET2, lmc_mii_readreg(sc, 0, 16),
  821. lmc_mii_readreg(sc, 0, 17));
  822. if (sc->lmc_ok){
  823. lmc_trace(dev, "lmc_open lmc_ok out");
  824. return 0;
  825. }
  826. lmc_softreset (sc);
  827. /* Since we have to use PCI bus, this should work on x86,alpha,ppc */
  828. if (request_irq (dev->irq, lmc_interrupt, IRQF_SHARED, dev->name, dev)){
  829. printk(KERN_WARNING "%s: could not get irq: %d\n", dev->name, dev->irq);
  830. lmc_trace(dev, "lmc_open irq failed out");
  831. return -EAGAIN;
  832. }
  833. sc->got_irq = 1;
  834. /* Assert Terminal Active */
  835. sc->lmc_miireg16 |= LMC_MII16_LED_ALL;
  836. sc->lmc_media->set_link_status (sc, LMC_LINK_UP);
  837. /*
  838. * reset to last state.
  839. */
  840. sc->lmc_media->set_status (sc, NULL);
  841. /* setup default bits to be used in tulip_desc_t transmit descriptor
  842. * -baz */
  843. sc->TxDescriptControlInit = (
  844. LMC_TDES_INTERRUPT_ON_COMPLETION
  845. | LMC_TDES_FIRST_SEGMENT
  846. | LMC_TDES_LAST_SEGMENT
  847. | LMC_TDES_SECOND_ADDR_CHAINED
  848. | LMC_TDES_DISABLE_PADDING
  849. );
  850. if (sc->ictl.crc_length == LMC_CTL_CRC_LENGTH_16) {
  851. /* disable 32 bit CRC generated by ASIC */
  852. sc->TxDescriptControlInit |= LMC_TDES_ADD_CRC_DISABLE;
  853. }
  854. sc->lmc_media->set_crc_length(sc, sc->ictl.crc_length);
  855. /* Acknoledge the Terminal Active and light LEDs */
  856. /* dev->flags |= IFF_UP; */
  857. if ((err = lmc_proto_open(sc)) != 0)
  858. return err;
  859. netif_start_queue(dev);
  860. sc->extra_stats.tx_tbusy0++;
  861. /*
  862. * select what interrupts we want to get
  863. */
  864. sc->lmc_intrmask = 0;
  865. /* Should be using the default interrupt mask defined in the .h file. */
  866. sc->lmc_intrmask |= (TULIP_STS_NORMALINTR
  867. | TULIP_STS_RXINTR
  868. | TULIP_STS_TXINTR
  869. | TULIP_STS_ABNRMLINTR
  870. | TULIP_STS_SYSERROR
  871. | TULIP_STS_TXSTOPPED
  872. | TULIP_STS_TXUNDERFLOW
  873. | TULIP_STS_RXSTOPPED
  874. | TULIP_STS_RXNOBUF
  875. );
  876. LMC_CSR_WRITE (sc, csr_intr, sc->lmc_intrmask);
  877. sc->lmc_cmdmode |= TULIP_CMD_TXRUN;
  878. sc->lmc_cmdmode |= TULIP_CMD_RXRUN;
  879. LMC_CSR_WRITE (sc, csr_command, sc->lmc_cmdmode);
  880. sc->lmc_ok = 1; /* Run watchdog */
  881. /*
  882. * Set the if up now - pfb
  883. */
  884. sc->last_link_status = 1;
  885. /*
  886. * Setup a timer for the watchdog on probe, and start it running.
  887. * Since lmc_ok == 0, it will be a NOP for now.
  888. */
  889. timer_setup(&sc->timer, lmc_watchdog, 0);
  890. sc->timer.expires = jiffies + HZ;
  891. add_timer (&sc->timer);
  892. lmc_trace(dev, "lmc_open out");
  893. return 0;
  894. }
  895. /* Total reset to compensate for the AdTran DSU doing bad things
  896. * under heavy load
  897. */
  898. static void lmc_running_reset (struct net_device *dev) /*fold00*/
  899. {
  900. lmc_softc_t *sc = dev_to_sc(dev);
  901. lmc_trace(dev, "lmc_running_reset in");
  902. /* stop interrupts */
  903. /* Clear the interrupt mask */
  904. LMC_CSR_WRITE (sc, csr_intr, 0x00000000);
  905. lmc_dec_reset (sc);
  906. lmc_reset (sc);
  907. lmc_softreset (sc);
  908. /* sc->lmc_miireg16 |= LMC_MII16_LED_ALL; */
  909. sc->lmc_media->set_link_status (sc, 1);
  910. sc->lmc_media->set_status (sc, NULL);
  911. netif_wake_queue(dev);
  912. sc->lmc_txfull = 0;
  913. sc->extra_stats.tx_tbusy0++;
  914. sc->lmc_intrmask = TULIP_DEFAULT_INTR_MASK;
  915. LMC_CSR_WRITE (sc, csr_intr, sc->lmc_intrmask);
  916. sc->lmc_cmdmode |= (TULIP_CMD_TXRUN | TULIP_CMD_RXRUN);
  917. LMC_CSR_WRITE (sc, csr_command, sc->lmc_cmdmode);
  918. lmc_trace(dev, "lmc_runnin_reset_out");
  919. }
  920. /* This is what is called when you ifconfig down a device.
  921. * This disables the timer for the watchdog and keepalives,
  922. * and disables the irq for dev.
  923. */
  924. static int lmc_close(struct net_device *dev)
  925. {
  926. /* not calling release_region() as we should */
  927. lmc_softc_t *sc = dev_to_sc(dev);
  928. lmc_trace(dev, "lmc_close in");
  929. sc->lmc_ok = 0;
  930. sc->lmc_media->set_link_status (sc, 0);
  931. del_timer (&sc->timer);
  932. lmc_proto_close(sc);
  933. lmc_ifdown (dev);
  934. lmc_trace(dev, "lmc_close out");
  935. return 0;
  936. }
  937. /* Ends the transfer of packets */
  938. /* When the interface goes down, this is called */
  939. static int lmc_ifdown (struct net_device *dev) /*fold00*/
  940. {
  941. lmc_softc_t *sc = dev_to_sc(dev);
  942. u32 csr6;
  943. int i;
  944. lmc_trace(dev, "lmc_ifdown in");
  945. /* Don't let anything else go on right now */
  946. // dev->start = 0;
  947. netif_stop_queue(dev);
  948. sc->extra_stats.tx_tbusy1++;
  949. /* stop interrupts */
  950. /* Clear the interrupt mask */
  951. LMC_CSR_WRITE (sc, csr_intr, 0x00000000);
  952. /* Stop Tx and Rx on the chip */
  953. csr6 = LMC_CSR_READ (sc, csr_command);
  954. csr6 &= ~LMC_DEC_ST; /* Turn off the Transmission bit */
  955. csr6 &= ~LMC_DEC_SR; /* Turn off the Receive bit */
  956. LMC_CSR_WRITE (sc, csr_command, csr6);
  957. sc->lmc_device->stats.rx_missed_errors +=
  958. LMC_CSR_READ(sc, csr_missed_frames) & 0xffff;
  959. /* release the interrupt */
  960. if(sc->got_irq == 1){
  961. free_irq (dev->irq, dev);
  962. sc->got_irq = 0;
  963. }
  964. /* free skbuffs in the Rx queue */
  965. for (i = 0; i < LMC_RXDESCS; i++)
  966. {
  967. struct sk_buff *skb = sc->lmc_rxq[i];
  968. sc->lmc_rxq[i] = NULL;
  969. sc->lmc_rxring[i].status = 0;
  970. sc->lmc_rxring[i].length = 0;
  971. sc->lmc_rxring[i].buffer1 = 0xDEADBEEF;
  972. if (skb != NULL)
  973. dev_kfree_skb(skb);
  974. sc->lmc_rxq[i] = NULL;
  975. }
  976. for (i = 0; i < LMC_TXDESCS; i++)
  977. {
  978. if (sc->lmc_txq[i] != NULL)
  979. dev_kfree_skb(sc->lmc_txq[i]);
  980. sc->lmc_txq[i] = NULL;
  981. }
  982. lmc_led_off (sc, LMC_MII16_LED_ALL);
  983. netif_wake_queue(dev);
  984. sc->extra_stats.tx_tbusy0++;
  985. lmc_trace(dev, "lmc_ifdown out");
  986. return 0;
  987. }
  988. /* Interrupt handling routine. This will take an incoming packet, or clean
  989. * up after a trasmit.
  990. */
  991. static irqreturn_t lmc_interrupt (int irq, void *dev_instance) /*fold00*/
  992. {
  993. struct net_device *dev = (struct net_device *) dev_instance;
  994. lmc_softc_t *sc = dev_to_sc(dev);
  995. u32 csr;
  996. int i;
  997. s32 stat;
  998. unsigned int badtx;
  999. u32 firstcsr;
  1000. int max_work = LMC_RXDESCS;
  1001. int handled = 0;
  1002. lmc_trace(dev, "lmc_interrupt in");
  1003. spin_lock(&sc->lmc_lock);
  1004. /*
  1005. * Read the csr to find what interrupts we have (if any)
  1006. */
  1007. csr = LMC_CSR_READ (sc, csr_status);
  1008. /*
  1009. * Make sure this is our interrupt
  1010. */
  1011. if ( ! (csr & sc->lmc_intrmask)) {
  1012. goto lmc_int_fail_out;
  1013. }
  1014. firstcsr = csr;
  1015. /* always go through this loop at least once */
  1016. while (csr & sc->lmc_intrmask) {
  1017. handled = 1;
  1018. /*
  1019. * Clear interrupt bits, we handle all case below
  1020. */
  1021. LMC_CSR_WRITE (sc, csr_status, csr);
  1022. /*
  1023. * One of
  1024. * - Transmit process timed out CSR5<1>
  1025. * - Transmit jabber timeout CSR5<3>
  1026. * - Transmit underflow CSR5<5>
  1027. * - Transmit Receiver buffer unavailable CSR5<7>
  1028. * - Receive process stopped CSR5<8>
  1029. * - Receive watchdog timeout CSR5<9>
  1030. * - Early transmit interrupt CSR5<10>
  1031. *
  1032. * Is this really right? Should we do a running reset for jabber?
  1033. * (being a WAN card and all)
  1034. */
  1035. if (csr & TULIP_STS_ABNRMLINTR){
  1036. lmc_running_reset (dev);
  1037. break;
  1038. }
  1039. if (csr & TULIP_STS_RXINTR){
  1040. lmc_trace(dev, "rx interrupt");
  1041. lmc_rx (dev);
  1042. }
  1043. if (csr & (TULIP_STS_TXINTR | TULIP_STS_TXNOBUF | TULIP_STS_TXSTOPPED)) {
  1044. int n_compl = 0 ;
  1045. /* reset the transmit timeout detection flag -baz */
  1046. sc->extra_stats.tx_NoCompleteCnt = 0;
  1047. badtx = sc->lmc_taint_tx;
  1048. i = badtx % LMC_TXDESCS;
  1049. while ((badtx < sc->lmc_next_tx)) {
  1050. stat = sc->lmc_txring[i].status;
  1051. LMC_EVENT_LOG (LMC_EVENT_XMTINT, stat,
  1052. sc->lmc_txring[i].length);
  1053. /*
  1054. * If bit 31 is 1 the tulip owns it break out of the loop
  1055. */
  1056. if (stat & 0x80000000)
  1057. break;
  1058. n_compl++ ; /* i.e., have an empty slot in ring */
  1059. /*
  1060. * If we have no skbuff or have cleared it
  1061. * Already continue to the next buffer
  1062. */
  1063. if (sc->lmc_txq[i] == NULL)
  1064. continue;
  1065. /*
  1066. * Check the total error summary to look for any errors
  1067. */
  1068. if (stat & 0x8000) {
  1069. sc->lmc_device->stats.tx_errors++;
  1070. if (stat & 0x4104)
  1071. sc->lmc_device->stats.tx_aborted_errors++;
  1072. if (stat & 0x0C00)
  1073. sc->lmc_device->stats.tx_carrier_errors++;
  1074. if (stat & 0x0200)
  1075. sc->lmc_device->stats.tx_window_errors++;
  1076. if (stat & 0x0002)
  1077. sc->lmc_device->stats.tx_fifo_errors++;
  1078. } else {
  1079. sc->lmc_device->stats.tx_bytes += sc->lmc_txring[i].length & 0x7ff;
  1080. sc->lmc_device->stats.tx_packets++;
  1081. }
  1082. // dev_kfree_skb(sc->lmc_txq[i]);
  1083. dev_kfree_skb_irq(sc->lmc_txq[i]);
  1084. sc->lmc_txq[i] = NULL;
  1085. badtx++;
  1086. i = badtx % LMC_TXDESCS;
  1087. }
  1088. if (sc->lmc_next_tx - badtx > LMC_TXDESCS)
  1089. {
  1090. printk ("%s: out of sync pointer\n", dev->name);
  1091. badtx += LMC_TXDESCS;
  1092. }
  1093. LMC_EVENT_LOG(LMC_EVENT_TBUSY0, n_compl, 0);
  1094. sc->lmc_txfull = 0;
  1095. netif_wake_queue(dev);
  1096. sc->extra_stats.tx_tbusy0++;
  1097. #ifdef DEBUG
  1098. sc->extra_stats.dirtyTx = badtx;
  1099. sc->extra_stats.lmc_next_tx = sc->lmc_next_tx;
  1100. sc->extra_stats.lmc_txfull = sc->lmc_txfull;
  1101. #endif
  1102. sc->lmc_taint_tx = badtx;
  1103. /*
  1104. * Why was there a break here???
  1105. */
  1106. } /* end handle transmit interrupt */
  1107. if (csr & TULIP_STS_SYSERROR) {
  1108. u32 error;
  1109. printk (KERN_WARNING "%s: system bus error csr: %#8.8x\n", dev->name, csr);
  1110. error = csr>>23 & 0x7;
  1111. switch(error){
  1112. case 0x000:
  1113. printk(KERN_WARNING "%s: Parity Fault (bad)\n", dev->name);
  1114. break;
  1115. case 0x001:
  1116. printk(KERN_WARNING "%s: Master Abort (naughty)\n", dev->name);
  1117. break;
  1118. case 0x010:
  1119. printk(KERN_WARNING "%s: Target Abort (not so naughty)\n", dev->name);
  1120. break;
  1121. default:
  1122. printk(KERN_WARNING "%s: This bus error code was supposed to be reserved!\n", dev->name);
  1123. }
  1124. lmc_dec_reset (sc);
  1125. lmc_reset (sc);
  1126. LMC_EVENT_LOG(LMC_EVENT_RESET1, LMC_CSR_READ (sc, csr_status), 0);
  1127. LMC_EVENT_LOG(LMC_EVENT_RESET2,
  1128. lmc_mii_readreg (sc, 0, 16),
  1129. lmc_mii_readreg (sc, 0, 17));
  1130. }
  1131. if(max_work-- <= 0)
  1132. break;
  1133. /*
  1134. * Get current csr status to make sure
  1135. * we've cleared all interrupts
  1136. */
  1137. csr = LMC_CSR_READ (sc, csr_status);
  1138. } /* end interrupt loop */
  1139. LMC_EVENT_LOG(LMC_EVENT_INT, firstcsr, csr);
  1140. lmc_int_fail_out:
  1141. spin_unlock(&sc->lmc_lock);
  1142. lmc_trace(dev, "lmc_interrupt out");
  1143. return IRQ_RETVAL(handled);
  1144. }
  1145. static netdev_tx_t lmc_start_xmit(struct sk_buff *skb,
  1146. struct net_device *dev)
  1147. {
  1148. lmc_softc_t *sc = dev_to_sc(dev);
  1149. u32 flag;
  1150. int entry;
  1151. unsigned long flags;
  1152. lmc_trace(dev, "lmc_start_xmit in");
  1153. spin_lock_irqsave(&sc->lmc_lock, flags);
  1154. /* normal path, tbusy known to be zero */
  1155. entry = sc->lmc_next_tx % LMC_TXDESCS;
  1156. sc->lmc_txq[entry] = skb;
  1157. sc->lmc_txring[entry].buffer1 = virt_to_bus (skb->data);
  1158. LMC_CONSOLE_LOG("xmit", skb->data, skb->len);
  1159. #ifndef GCOM
  1160. /* If the queue is less than half full, don't interrupt */
  1161. if (sc->lmc_next_tx - sc->lmc_taint_tx < LMC_TXDESCS / 2)
  1162. {
  1163. /* Do not interrupt on completion of this packet */
  1164. flag = 0x60000000;
  1165. netif_wake_queue(dev);
  1166. }
  1167. else if (sc->lmc_next_tx - sc->lmc_taint_tx == LMC_TXDESCS / 2)
  1168. {
  1169. /* This generates an interrupt on completion of this packet */
  1170. flag = 0xe0000000;
  1171. netif_wake_queue(dev);
  1172. }
  1173. else if (sc->lmc_next_tx - sc->lmc_taint_tx < LMC_TXDESCS - 1)
  1174. {
  1175. /* Do not interrupt on completion of this packet */
  1176. flag = 0x60000000;
  1177. netif_wake_queue(dev);
  1178. }
  1179. else
  1180. {
  1181. /* This generates an interrupt on completion of this packet */
  1182. flag = 0xe0000000;
  1183. sc->lmc_txfull = 1;
  1184. netif_stop_queue(dev);
  1185. }
  1186. #else
  1187. flag = LMC_TDES_INTERRUPT_ON_COMPLETION;
  1188. if (sc->lmc_next_tx - sc->lmc_taint_tx >= LMC_TXDESCS - 1)
  1189. { /* ring full, go busy */
  1190. sc->lmc_txfull = 1;
  1191. netif_stop_queue(dev);
  1192. sc->extra_stats.tx_tbusy1++;
  1193. LMC_EVENT_LOG(LMC_EVENT_TBUSY1, entry, 0);
  1194. }
  1195. #endif
  1196. if (entry == LMC_TXDESCS - 1) /* last descriptor in ring */
  1197. flag |= LMC_TDES_END_OF_RING; /* flag as such for Tulip */
  1198. /* don't pad small packets either */
  1199. flag = sc->lmc_txring[entry].length = (skb->len) | flag |
  1200. sc->TxDescriptControlInit;
  1201. /* set the transmit timeout flag to be checked in
  1202. * the watchdog timer handler. -baz
  1203. */
  1204. sc->extra_stats.tx_NoCompleteCnt++;
  1205. sc->lmc_next_tx++;
  1206. /* give ownership to the chip */
  1207. LMC_EVENT_LOG(LMC_EVENT_XMT, flag, entry);
  1208. sc->lmc_txring[entry].status = 0x80000000;
  1209. /* send now! */
  1210. LMC_CSR_WRITE (sc, csr_txpoll, 0);
  1211. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  1212. lmc_trace(dev, "lmc_start_xmit_out");
  1213. return NETDEV_TX_OK;
  1214. }
  1215. static int lmc_rx(struct net_device *dev)
  1216. {
  1217. lmc_softc_t *sc = dev_to_sc(dev);
  1218. int i;
  1219. int rx_work_limit = LMC_RXDESCS;
  1220. unsigned int next_rx;
  1221. int rxIntLoopCnt; /* debug -baz */
  1222. int localLengthErrCnt = 0;
  1223. long stat;
  1224. struct sk_buff *skb, *nsb;
  1225. u16 len;
  1226. lmc_trace(dev, "lmc_rx in");
  1227. lmc_led_on(sc, LMC_DS3_LED3);
  1228. rxIntLoopCnt = 0; /* debug -baz */
  1229. i = sc->lmc_next_rx % LMC_RXDESCS;
  1230. next_rx = sc->lmc_next_rx;
  1231. while (((stat = sc->lmc_rxring[i].status) & LMC_RDES_OWN_BIT) != DESC_OWNED_BY_DC21X4)
  1232. {
  1233. rxIntLoopCnt++; /* debug -baz */
  1234. len = ((stat & LMC_RDES_FRAME_LENGTH) >> RDES_FRAME_LENGTH_BIT_NUMBER);
  1235. if ((stat & 0x0300) != 0x0300) { /* Check first segment and last segment */
  1236. if ((stat & 0x0000ffff) != 0x7fff) {
  1237. /* Oversized frame */
  1238. sc->lmc_device->stats.rx_length_errors++;
  1239. goto skip_packet;
  1240. }
  1241. }
  1242. if (stat & 0x00000008) { /* Catch a dribbling bit error */
  1243. sc->lmc_device->stats.rx_errors++;
  1244. sc->lmc_device->stats.rx_frame_errors++;
  1245. goto skip_packet;
  1246. }
  1247. if (stat & 0x00000004) { /* Catch a CRC error by the Xilinx */
  1248. sc->lmc_device->stats.rx_errors++;
  1249. sc->lmc_device->stats.rx_crc_errors++;
  1250. goto skip_packet;
  1251. }
  1252. if (len > LMC_PKT_BUF_SZ) {
  1253. sc->lmc_device->stats.rx_length_errors++;
  1254. localLengthErrCnt++;
  1255. goto skip_packet;
  1256. }
  1257. if (len < sc->lmc_crcSize + 2) {
  1258. sc->lmc_device->stats.rx_length_errors++;
  1259. sc->extra_stats.rx_SmallPktCnt++;
  1260. localLengthErrCnt++;
  1261. goto skip_packet;
  1262. }
  1263. if(stat & 0x00004000){
  1264. printk(KERN_WARNING "%s: Receiver descriptor error, receiver out of sync?\n", dev->name);
  1265. }
  1266. len -= sc->lmc_crcSize;
  1267. skb = sc->lmc_rxq[i];
  1268. /*
  1269. * We ran out of memory at some point
  1270. * just allocate an skb buff and continue.
  1271. */
  1272. if (!skb) {
  1273. nsb = dev_alloc_skb (LMC_PKT_BUF_SZ + 2);
  1274. if (nsb) {
  1275. sc->lmc_rxq[i] = nsb;
  1276. nsb->dev = dev;
  1277. sc->lmc_rxring[i].buffer1 = virt_to_bus(skb_tail_pointer(nsb));
  1278. }
  1279. sc->failed_recv_alloc = 1;
  1280. goto skip_packet;
  1281. }
  1282. sc->lmc_device->stats.rx_packets++;
  1283. sc->lmc_device->stats.rx_bytes += len;
  1284. LMC_CONSOLE_LOG("recv", skb->data, len);
  1285. /*
  1286. * I'm not sure of the sanity of this
  1287. * Packets could be arriving at a constant
  1288. * 44.210mbits/sec and we're going to copy
  1289. * them into a new buffer??
  1290. */
  1291. if(len > (LMC_MTU - (LMC_MTU>>2))){ /* len > LMC_MTU * 0.75 */
  1292. /*
  1293. * If it's a large packet don't copy it just hand it up
  1294. */
  1295. give_it_anyways:
  1296. sc->lmc_rxq[i] = NULL;
  1297. sc->lmc_rxring[i].buffer1 = 0x0;
  1298. skb_put (skb, len);
  1299. skb->protocol = lmc_proto_type(sc, skb);
  1300. skb_reset_mac_header(skb);
  1301. /* skb_reset_network_header(skb); */
  1302. skb->dev = dev;
  1303. lmc_proto_netif(sc, skb);
  1304. /*
  1305. * This skb will be destroyed by the upper layers, make a new one
  1306. */
  1307. nsb = dev_alloc_skb (LMC_PKT_BUF_SZ + 2);
  1308. if (nsb) {
  1309. sc->lmc_rxq[i] = nsb;
  1310. nsb->dev = dev;
  1311. sc->lmc_rxring[i].buffer1 = virt_to_bus(skb_tail_pointer(nsb));
  1312. /* Transferred to 21140 below */
  1313. }
  1314. else {
  1315. /*
  1316. * We've run out of memory, stop trying to allocate
  1317. * memory and exit the interrupt handler
  1318. *
  1319. * The chip may run out of receivers and stop
  1320. * in which care we'll try to allocate the buffer
  1321. * again. (once a second)
  1322. */
  1323. sc->extra_stats.rx_BuffAllocErr++;
  1324. LMC_EVENT_LOG(LMC_EVENT_RCVINT, stat, len);
  1325. sc->failed_recv_alloc = 1;
  1326. goto skip_out_of_mem;
  1327. }
  1328. }
  1329. else {
  1330. nsb = dev_alloc_skb(len);
  1331. if(!nsb) {
  1332. goto give_it_anyways;
  1333. }
  1334. skb_copy_from_linear_data(skb, skb_put(nsb, len), len);
  1335. nsb->protocol = lmc_proto_type(sc, nsb);
  1336. skb_reset_mac_header(nsb);
  1337. /* skb_reset_network_header(nsb); */
  1338. nsb->dev = dev;
  1339. lmc_proto_netif(sc, nsb);
  1340. }
  1341. skip_packet:
  1342. LMC_EVENT_LOG(LMC_EVENT_RCVINT, stat, len);
  1343. sc->lmc_rxring[i].status = DESC_OWNED_BY_DC21X4;
  1344. sc->lmc_next_rx++;
  1345. i = sc->lmc_next_rx % LMC_RXDESCS;
  1346. rx_work_limit--;
  1347. if (rx_work_limit < 0)
  1348. break;
  1349. }
  1350. /* detect condition for LMC1000 where DSU cable attaches and fills
  1351. * descriptors with bogus packets
  1352. *
  1353. if (localLengthErrCnt > LMC_RXDESCS - 3) {
  1354. sc->extra_stats.rx_BadPktSurgeCnt++;
  1355. LMC_EVENT_LOG(LMC_EVENT_BADPKTSURGE, localLengthErrCnt,
  1356. sc->extra_stats.rx_BadPktSurgeCnt);
  1357. } */
  1358. /* save max count of receive descriptors serviced */
  1359. if (rxIntLoopCnt > sc->extra_stats.rxIntLoopCnt)
  1360. sc->extra_stats.rxIntLoopCnt = rxIntLoopCnt; /* debug -baz */
  1361. #ifdef DEBUG
  1362. if (rxIntLoopCnt == 0)
  1363. {
  1364. for (i = 0; i < LMC_RXDESCS; i++)
  1365. {
  1366. if ((sc->lmc_rxring[i].status & LMC_RDES_OWN_BIT)
  1367. != DESC_OWNED_BY_DC21X4)
  1368. {
  1369. rxIntLoopCnt++;
  1370. }
  1371. }
  1372. LMC_EVENT_LOG(LMC_EVENT_RCVEND, rxIntLoopCnt, 0);
  1373. }
  1374. #endif
  1375. lmc_led_off(sc, LMC_DS3_LED3);
  1376. skip_out_of_mem:
  1377. lmc_trace(dev, "lmc_rx out");
  1378. return 0;
  1379. }
  1380. static struct net_device_stats *lmc_get_stats(struct net_device *dev)
  1381. {
  1382. lmc_softc_t *sc = dev_to_sc(dev);
  1383. unsigned long flags;
  1384. lmc_trace(dev, "lmc_get_stats in");
  1385. spin_lock_irqsave(&sc->lmc_lock, flags);
  1386. sc->lmc_device->stats.rx_missed_errors += LMC_CSR_READ(sc, csr_missed_frames) & 0xffff;
  1387. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  1388. lmc_trace(dev, "lmc_get_stats out");
  1389. return &sc->lmc_device->stats;
  1390. }
  1391. static struct pci_driver lmc_driver = {
  1392. .name = "lmc",
  1393. .id_table = lmc_pci_tbl,
  1394. .probe = lmc_init_one,
  1395. .remove = lmc_remove_one,
  1396. };
  1397. module_pci_driver(lmc_driver);
  1398. unsigned lmc_mii_readreg (lmc_softc_t * const sc, unsigned devaddr, unsigned regno) /*fold00*/
  1399. {
  1400. int i;
  1401. int command = (0xf6 << 10) | (devaddr << 5) | regno;
  1402. int retval = 0;
  1403. lmc_trace(sc->lmc_device, "lmc_mii_readreg in");
  1404. LMC_MII_SYNC (sc);
  1405. lmc_trace(sc->lmc_device, "lmc_mii_readreg: done sync");
  1406. for (i = 15; i >= 0; i--)
  1407. {
  1408. int dataval = (command & (1 << i)) ? 0x20000 : 0;
  1409. LMC_CSR_WRITE (sc, csr_9, dataval);
  1410. lmc_delay ();
  1411. /* __SLOW_DOWN_IO; */
  1412. LMC_CSR_WRITE (sc, csr_9, dataval | 0x10000);
  1413. lmc_delay ();
  1414. /* __SLOW_DOWN_IO; */
  1415. }
  1416. lmc_trace(sc->lmc_device, "lmc_mii_readreg: done1");
  1417. for (i = 19; i > 0; i--)
  1418. {
  1419. LMC_CSR_WRITE (sc, csr_9, 0x40000);
  1420. lmc_delay ();
  1421. /* __SLOW_DOWN_IO; */
  1422. retval = (retval << 1) | ((LMC_CSR_READ (sc, csr_9) & 0x80000) ? 1 : 0);
  1423. LMC_CSR_WRITE (sc, csr_9, 0x40000 | 0x10000);
  1424. lmc_delay ();
  1425. /* __SLOW_DOWN_IO; */
  1426. }
  1427. lmc_trace(sc->lmc_device, "lmc_mii_readreg out");
  1428. return (retval >> 1) & 0xffff;
  1429. }
  1430. void lmc_mii_writereg (lmc_softc_t * const sc, unsigned devaddr, unsigned regno, unsigned data) /*fold00*/
  1431. {
  1432. int i = 32;
  1433. int command = (0x5002 << 16) | (devaddr << 23) | (regno << 18) | data;
  1434. lmc_trace(sc->lmc_device, "lmc_mii_writereg in");
  1435. LMC_MII_SYNC (sc);
  1436. i = 31;
  1437. while (i >= 0)
  1438. {
  1439. int datav;
  1440. if (command & (1 << i))
  1441. datav = 0x20000;
  1442. else
  1443. datav = 0x00000;
  1444. LMC_CSR_WRITE (sc, csr_9, datav);
  1445. lmc_delay ();
  1446. /* __SLOW_DOWN_IO; */
  1447. LMC_CSR_WRITE (sc, csr_9, (datav | 0x10000));
  1448. lmc_delay ();
  1449. /* __SLOW_DOWN_IO; */
  1450. i--;
  1451. }
  1452. i = 2;
  1453. while (i > 0)
  1454. {
  1455. LMC_CSR_WRITE (sc, csr_9, 0x40000);
  1456. lmc_delay ();
  1457. /* __SLOW_DOWN_IO; */
  1458. LMC_CSR_WRITE (sc, csr_9, 0x50000);
  1459. lmc_delay ();
  1460. /* __SLOW_DOWN_IO; */
  1461. i--;
  1462. }
  1463. lmc_trace(sc->lmc_device, "lmc_mii_writereg out");
  1464. }
  1465. static void lmc_softreset (lmc_softc_t * const sc) /*fold00*/
  1466. {
  1467. int i;
  1468. lmc_trace(sc->lmc_device, "lmc_softreset in");
  1469. /* Initialize the receive rings and buffers. */
  1470. sc->lmc_txfull = 0;
  1471. sc->lmc_next_rx = 0;
  1472. sc->lmc_next_tx = 0;
  1473. sc->lmc_taint_rx = 0;
  1474. sc->lmc_taint_tx = 0;
  1475. /*
  1476. * Setup each one of the receiver buffers
  1477. * allocate an skbuff for each one, setup the descriptor table
  1478. * and point each buffer at the next one
  1479. */
  1480. for (i = 0; i < LMC_RXDESCS; i++)
  1481. {
  1482. struct sk_buff *skb;
  1483. if (sc->lmc_rxq[i] == NULL)
  1484. {
  1485. skb = dev_alloc_skb (LMC_PKT_BUF_SZ + 2);
  1486. if(skb == NULL){
  1487. printk(KERN_WARNING "%s: Failed to allocate receiver ring, will try again\n", sc->name);
  1488. sc->failed_ring = 1;
  1489. break;
  1490. }
  1491. else{
  1492. sc->lmc_rxq[i] = skb;
  1493. }
  1494. }
  1495. else
  1496. {
  1497. skb = sc->lmc_rxq[i];
  1498. }
  1499. skb->dev = sc->lmc_device;
  1500. /* owned by 21140 */
  1501. sc->lmc_rxring[i].status = 0x80000000;
  1502. /* used to be PKT_BUF_SZ now uses skb since we lose some to head room */
  1503. sc->lmc_rxring[i].length = skb_tailroom(skb);
  1504. /* use to be tail which is dumb since you're thinking why write
  1505. * to the end of the packj,et but since there's nothing there tail == data
  1506. */
  1507. sc->lmc_rxring[i].buffer1 = virt_to_bus (skb->data);
  1508. /* This is fair since the structure is static and we have the next address */
  1509. sc->lmc_rxring[i].buffer2 = virt_to_bus (&sc->lmc_rxring[i + 1]);
  1510. }
  1511. /*
  1512. * Sets end of ring
  1513. */
  1514. if (i != 0) {
  1515. sc->lmc_rxring[i - 1].length |= 0x02000000; /* Set end of buffers flag */
  1516. sc->lmc_rxring[i - 1].buffer2 = virt_to_bus(&sc->lmc_rxring[0]); /* Point back to the start */
  1517. }
  1518. LMC_CSR_WRITE (sc, csr_rxlist, virt_to_bus (sc->lmc_rxring)); /* write base address */
  1519. /* Initialize the transmit rings and buffers */
  1520. for (i = 0; i < LMC_TXDESCS; i++)
  1521. {
  1522. if (sc->lmc_txq[i] != NULL){ /* have buffer */
  1523. dev_kfree_skb(sc->lmc_txq[i]); /* free it */
  1524. sc->lmc_device->stats.tx_dropped++; /* We just dropped a packet */
  1525. }
  1526. sc->lmc_txq[i] = NULL;
  1527. sc->lmc_txring[i].status = 0x00000000;
  1528. sc->lmc_txring[i].buffer2 = virt_to_bus (&sc->lmc_txring[i + 1]);
  1529. }
  1530. sc->lmc_txring[i - 1].buffer2 = virt_to_bus (&sc->lmc_txring[0]);
  1531. LMC_CSR_WRITE (sc, csr_txlist, virt_to_bus (sc->lmc_txring));
  1532. lmc_trace(sc->lmc_device, "lmc_softreset out");
  1533. }
  1534. void lmc_gpio_mkinput(lmc_softc_t * const sc, u32 bits) /*fold00*/
  1535. {
  1536. lmc_trace(sc->lmc_device, "lmc_gpio_mkinput in");
  1537. sc->lmc_gpio_io &= ~bits;
  1538. LMC_CSR_WRITE(sc, csr_gp, TULIP_GP_PINSET | (sc->lmc_gpio_io));
  1539. lmc_trace(sc->lmc_device, "lmc_gpio_mkinput out");
  1540. }
  1541. void lmc_gpio_mkoutput(lmc_softc_t * const sc, u32 bits) /*fold00*/
  1542. {
  1543. lmc_trace(sc->lmc_device, "lmc_gpio_mkoutput in");
  1544. sc->lmc_gpio_io |= bits;
  1545. LMC_CSR_WRITE(sc, csr_gp, TULIP_GP_PINSET | (sc->lmc_gpio_io));
  1546. lmc_trace(sc->lmc_device, "lmc_gpio_mkoutput out");
  1547. }
  1548. void lmc_led_on(lmc_softc_t * const sc, u32 led) /*fold00*/
  1549. {
  1550. lmc_trace(sc->lmc_device, "lmc_led_on in");
  1551. if((~sc->lmc_miireg16) & led){ /* Already on! */
  1552. lmc_trace(sc->lmc_device, "lmc_led_on aon out");
  1553. return;
  1554. }
  1555. sc->lmc_miireg16 &= ~led;
  1556. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  1557. lmc_trace(sc->lmc_device, "lmc_led_on out");
  1558. }
  1559. void lmc_led_off(lmc_softc_t * const sc, u32 led) /*fold00*/
  1560. {
  1561. lmc_trace(sc->lmc_device, "lmc_led_off in");
  1562. if(sc->lmc_miireg16 & led){ /* Already set don't do anything */
  1563. lmc_trace(sc->lmc_device, "lmc_led_off aoff out");
  1564. return;
  1565. }
  1566. sc->lmc_miireg16 |= led;
  1567. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  1568. lmc_trace(sc->lmc_device, "lmc_led_off out");
  1569. }
  1570. static void lmc_reset(lmc_softc_t * const sc) /*fold00*/
  1571. {
  1572. lmc_trace(sc->lmc_device, "lmc_reset in");
  1573. sc->lmc_miireg16 |= LMC_MII16_FIFO_RESET;
  1574. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  1575. sc->lmc_miireg16 &= ~LMC_MII16_FIFO_RESET;
  1576. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  1577. /*
  1578. * make some of the GPIO pins be outputs
  1579. */
  1580. lmc_gpio_mkoutput(sc, LMC_GEP_RESET);
  1581. /*
  1582. * RESET low to force state reset. This also forces
  1583. * the transmitter clock to be internal, but we expect to reset
  1584. * that later anyway.
  1585. */
  1586. sc->lmc_gpio &= ~(LMC_GEP_RESET);
  1587. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  1588. /*
  1589. * hold for more than 10 microseconds
  1590. */
  1591. udelay(50);
  1592. /*
  1593. * stop driving Xilinx-related signals
  1594. */
  1595. lmc_gpio_mkinput(sc, LMC_GEP_RESET);
  1596. /*
  1597. * Call media specific init routine
  1598. */
  1599. sc->lmc_media->init(sc);
  1600. sc->extra_stats.resetCount++;
  1601. lmc_trace(sc->lmc_device, "lmc_reset out");
  1602. }
  1603. static void lmc_dec_reset(lmc_softc_t * const sc) /*fold00*/
  1604. {
  1605. u32 val;
  1606. lmc_trace(sc->lmc_device, "lmc_dec_reset in");
  1607. /*
  1608. * disable all interrupts
  1609. */
  1610. sc->lmc_intrmask = 0;
  1611. LMC_CSR_WRITE(sc, csr_intr, sc->lmc_intrmask);
  1612. /*
  1613. * Reset the chip with a software reset command.
  1614. * Wait 10 microseconds (actually 50 PCI cycles but at
  1615. * 33MHz that comes to two microseconds but wait a
  1616. * bit longer anyways)
  1617. */
  1618. LMC_CSR_WRITE(sc, csr_busmode, TULIP_BUSMODE_SWRESET);
  1619. udelay(25);
  1620. #ifdef __sparc__
  1621. sc->lmc_busmode = LMC_CSR_READ(sc, csr_busmode);
  1622. sc->lmc_busmode = 0x00100000;
  1623. sc->lmc_busmode &= ~TULIP_BUSMODE_SWRESET;
  1624. LMC_CSR_WRITE(sc, csr_busmode, sc->lmc_busmode);
  1625. #endif
  1626. sc->lmc_cmdmode = LMC_CSR_READ(sc, csr_command);
  1627. /*
  1628. * We want:
  1629. * no ethernet address in frames we write
  1630. * disable padding (txdesc, padding disable)
  1631. * ignore runt frames (rdes0 bit 15)
  1632. * no receiver watchdog or transmitter jabber timer
  1633. * (csr15 bit 0,14 == 1)
  1634. * if using 16-bit CRC, turn off CRC (trans desc, crc disable)
  1635. */
  1636. sc->lmc_cmdmode |= ( TULIP_CMD_PROMISCUOUS
  1637. | TULIP_CMD_FULLDUPLEX
  1638. | TULIP_CMD_PASSBADPKT
  1639. | TULIP_CMD_NOHEARTBEAT
  1640. | TULIP_CMD_PORTSELECT
  1641. | TULIP_CMD_RECEIVEALL
  1642. | TULIP_CMD_MUSTBEONE
  1643. );
  1644. sc->lmc_cmdmode &= ~( TULIP_CMD_OPERMODE
  1645. | TULIP_CMD_THRESHOLDCTL
  1646. | TULIP_CMD_STOREFWD
  1647. | TULIP_CMD_TXTHRSHLDCTL
  1648. );
  1649. LMC_CSR_WRITE(sc, csr_command, sc->lmc_cmdmode);
  1650. /*
  1651. * disable receiver watchdog and transmit jabber
  1652. */
  1653. val = LMC_CSR_READ(sc, csr_sia_general);
  1654. val |= (TULIP_WATCHDOG_TXDISABLE | TULIP_WATCHDOG_RXDISABLE);
  1655. LMC_CSR_WRITE(sc, csr_sia_general, val);
  1656. lmc_trace(sc->lmc_device, "lmc_dec_reset out");
  1657. }
  1658. static void lmc_initcsrs(lmc_softc_t * const sc, lmc_csrptr_t csr_base, /*fold00*/
  1659. size_t csr_size)
  1660. {
  1661. lmc_trace(sc->lmc_device, "lmc_initcsrs in");
  1662. sc->lmc_csrs.csr_busmode = csr_base + 0 * csr_size;
  1663. sc->lmc_csrs.csr_txpoll = csr_base + 1 * csr_size;
  1664. sc->lmc_csrs.csr_rxpoll = csr_base + 2 * csr_size;
  1665. sc->lmc_csrs.csr_rxlist = csr_base + 3 * csr_size;
  1666. sc->lmc_csrs.csr_txlist = csr_base + 4 * csr_size;
  1667. sc->lmc_csrs.csr_status = csr_base + 5 * csr_size;
  1668. sc->lmc_csrs.csr_command = csr_base + 6 * csr_size;
  1669. sc->lmc_csrs.csr_intr = csr_base + 7 * csr_size;
  1670. sc->lmc_csrs.csr_missed_frames = csr_base + 8 * csr_size;
  1671. sc->lmc_csrs.csr_9 = csr_base + 9 * csr_size;
  1672. sc->lmc_csrs.csr_10 = csr_base + 10 * csr_size;
  1673. sc->lmc_csrs.csr_11 = csr_base + 11 * csr_size;
  1674. sc->lmc_csrs.csr_12 = csr_base + 12 * csr_size;
  1675. sc->lmc_csrs.csr_13 = csr_base + 13 * csr_size;
  1676. sc->lmc_csrs.csr_14 = csr_base + 14 * csr_size;
  1677. sc->lmc_csrs.csr_15 = csr_base + 15 * csr_size;
  1678. lmc_trace(sc->lmc_device, "lmc_initcsrs out");
  1679. }
  1680. static void lmc_driver_timeout(struct net_device *dev)
  1681. {
  1682. lmc_softc_t *sc = dev_to_sc(dev);
  1683. u32 csr6;
  1684. unsigned long flags;
  1685. lmc_trace(dev, "lmc_driver_timeout in");
  1686. spin_lock_irqsave(&sc->lmc_lock, flags);
  1687. printk("%s: Xmitter busy|\n", dev->name);
  1688. sc->extra_stats.tx_tbusy_calls++;
  1689. if (jiffies - dev_trans_start(dev) < TX_TIMEOUT)
  1690. goto bug_out;
  1691. /*
  1692. * Chip seems to have locked up
  1693. * Reset it
  1694. * This whips out all our decriptor
  1695. * table and starts from scartch
  1696. */
  1697. LMC_EVENT_LOG(LMC_EVENT_XMTPRCTMO,
  1698. LMC_CSR_READ (sc, csr_status),
  1699. sc->extra_stats.tx_ProcTimeout);
  1700. lmc_running_reset (dev);
  1701. LMC_EVENT_LOG(LMC_EVENT_RESET1, LMC_CSR_READ (sc, csr_status), 0);
  1702. LMC_EVENT_LOG(LMC_EVENT_RESET2,
  1703. lmc_mii_readreg (sc, 0, 16),
  1704. lmc_mii_readreg (sc, 0, 17));
  1705. /* restart the tx processes */
  1706. csr6 = LMC_CSR_READ (sc, csr_command);
  1707. LMC_CSR_WRITE (sc, csr_command, csr6 | 0x0002);
  1708. LMC_CSR_WRITE (sc, csr_command, csr6 | 0x2002);
  1709. /* immediate transmit */
  1710. LMC_CSR_WRITE (sc, csr_txpoll, 0);
  1711. sc->lmc_device->stats.tx_errors++;
  1712. sc->extra_stats.tx_ProcTimeout++; /* -baz */
  1713. netif_trans_update(dev); /* prevent tx timeout */
  1714. bug_out:
  1715. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  1716. lmc_trace(dev, "lmc_driver_timeout out");
  1717. }