qed_ll2.c 70 KB

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  1. /* QLogic qed NIC Driver
  2. * Copyright (c) 2015-2017 QLogic Corporation
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and /or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/types.h>
  33. #include <asm/byteorder.h>
  34. #include <linux/dma-mapping.h>
  35. #include <linux/if_vlan.h>
  36. #include <linux/kernel.h>
  37. #include <linux/pci.h>
  38. #include <linux/slab.h>
  39. #include <linux/stddef.h>
  40. #include <linux/workqueue.h>
  41. #include <net/ipv6.h>
  42. #include <linux/bitops.h>
  43. #include <linux/delay.h>
  44. #include <linux/errno.h>
  45. #include <linux/etherdevice.h>
  46. #include <linux/io.h>
  47. #include <linux/list.h>
  48. #include <linux/mutex.h>
  49. #include <linux/spinlock.h>
  50. #include <linux/string.h>
  51. #include <linux/qed/qed_ll2_if.h>
  52. #include "qed.h"
  53. #include "qed_cxt.h"
  54. #include "qed_dev_api.h"
  55. #include "qed_hsi.h"
  56. #include "qed_hw.h"
  57. #include "qed_int.h"
  58. #include "qed_ll2.h"
  59. #include "qed_mcp.h"
  60. #include "qed_ooo.h"
  61. #include "qed_reg_addr.h"
  62. #include "qed_sp.h"
  63. #include "qed_rdma.h"
  64. #define QED_LL2_RX_REGISTERED(ll2) ((ll2)->rx_queue.b_cb_registred)
  65. #define QED_LL2_TX_REGISTERED(ll2) ((ll2)->tx_queue.b_cb_registred)
  66. #define QED_LL2_TX_SIZE (256)
  67. #define QED_LL2_RX_SIZE (4096)
  68. struct qed_cb_ll2_info {
  69. int rx_cnt;
  70. u32 rx_size;
  71. u8 handle;
  72. /* Lock protecting LL2 buffer lists in sleepless context */
  73. spinlock_t lock;
  74. struct list_head list;
  75. const struct qed_ll2_cb_ops *cbs;
  76. void *cb_cookie;
  77. };
  78. struct qed_ll2_buffer {
  79. struct list_head list;
  80. void *data;
  81. dma_addr_t phys_addr;
  82. };
  83. static void qed_ll2b_complete_tx_packet(void *cxt,
  84. u8 connection_handle,
  85. void *cookie,
  86. dma_addr_t first_frag_addr,
  87. bool b_last_fragment,
  88. bool b_last_packet)
  89. {
  90. struct qed_hwfn *p_hwfn = cxt;
  91. struct qed_dev *cdev = p_hwfn->cdev;
  92. struct sk_buff *skb = cookie;
  93. /* All we need to do is release the mapping */
  94. dma_unmap_single(&p_hwfn->cdev->pdev->dev, first_frag_addr,
  95. skb_headlen(skb), DMA_TO_DEVICE);
  96. if (cdev->ll2->cbs && cdev->ll2->cbs->tx_cb)
  97. cdev->ll2->cbs->tx_cb(cdev->ll2->cb_cookie, skb,
  98. b_last_fragment);
  99. dev_kfree_skb_any(skb);
  100. }
  101. static int qed_ll2_alloc_buffer(struct qed_dev *cdev,
  102. u8 **data, dma_addr_t *phys_addr)
  103. {
  104. *data = kmalloc(cdev->ll2->rx_size, GFP_ATOMIC);
  105. if (!(*data)) {
  106. DP_INFO(cdev, "Failed to allocate LL2 buffer data\n");
  107. return -ENOMEM;
  108. }
  109. *phys_addr = dma_map_single(&cdev->pdev->dev,
  110. ((*data) + NET_SKB_PAD),
  111. cdev->ll2->rx_size, DMA_FROM_DEVICE);
  112. if (dma_mapping_error(&cdev->pdev->dev, *phys_addr)) {
  113. DP_INFO(cdev, "Failed to map LL2 buffer data\n");
  114. kfree((*data));
  115. return -ENOMEM;
  116. }
  117. return 0;
  118. }
  119. static int qed_ll2_dealloc_buffer(struct qed_dev *cdev,
  120. struct qed_ll2_buffer *buffer)
  121. {
  122. spin_lock_bh(&cdev->ll2->lock);
  123. dma_unmap_single(&cdev->pdev->dev, buffer->phys_addr,
  124. cdev->ll2->rx_size, DMA_FROM_DEVICE);
  125. kfree(buffer->data);
  126. list_del(&buffer->list);
  127. cdev->ll2->rx_cnt--;
  128. if (!cdev->ll2->rx_cnt)
  129. DP_INFO(cdev, "All LL2 entries were removed\n");
  130. spin_unlock_bh(&cdev->ll2->lock);
  131. return 0;
  132. }
  133. static void qed_ll2_kill_buffers(struct qed_dev *cdev)
  134. {
  135. struct qed_ll2_buffer *buffer, *tmp_buffer;
  136. list_for_each_entry_safe(buffer, tmp_buffer, &cdev->ll2->list, list)
  137. qed_ll2_dealloc_buffer(cdev, buffer);
  138. }
  139. void qed_ll2b_complete_rx_packet(void *cxt, struct qed_ll2_comp_rx_data *data)
  140. {
  141. struct qed_hwfn *p_hwfn = cxt;
  142. struct qed_ll2_buffer *buffer = data->cookie;
  143. struct qed_dev *cdev = p_hwfn->cdev;
  144. dma_addr_t new_phys_addr;
  145. struct sk_buff *skb;
  146. bool reuse = false;
  147. int rc = -EINVAL;
  148. u8 *new_data;
  149. DP_VERBOSE(p_hwfn,
  150. (NETIF_MSG_RX_STATUS | QED_MSG_STORAGE | NETIF_MSG_PKTDATA),
  151. "Got an LL2 Rx completion: [Buffer at phys 0x%llx, offset 0x%02x] Length 0x%04x Parse_flags 0x%04x vlan 0x%04x Opaque data [0x%08x:0x%08x]\n",
  152. (u64)data->rx_buf_addr,
  153. data->u.placement_offset,
  154. data->length.packet_length,
  155. data->parse_flags,
  156. data->vlan, data->opaque_data_0, data->opaque_data_1);
  157. if ((cdev->dp_module & NETIF_MSG_PKTDATA) && buffer->data) {
  158. print_hex_dump(KERN_INFO, "",
  159. DUMP_PREFIX_OFFSET, 16, 1,
  160. buffer->data, data->length.packet_length, false);
  161. }
  162. /* Determine if data is valid */
  163. if (data->length.packet_length < ETH_HLEN)
  164. reuse = true;
  165. /* Allocate a replacement for buffer; Reuse upon failure */
  166. if (!reuse)
  167. rc = qed_ll2_alloc_buffer(p_hwfn->cdev, &new_data,
  168. &new_phys_addr);
  169. /* If need to reuse or there's no replacement buffer, repost this */
  170. if (rc)
  171. goto out_post;
  172. dma_unmap_single(&cdev->pdev->dev, buffer->phys_addr,
  173. cdev->ll2->rx_size, DMA_FROM_DEVICE);
  174. skb = build_skb(buffer->data, 0);
  175. if (!skb) {
  176. rc = -ENOMEM;
  177. goto out_post;
  178. }
  179. data->u.placement_offset += NET_SKB_PAD;
  180. skb_reserve(skb, data->u.placement_offset);
  181. skb_put(skb, data->length.packet_length);
  182. skb_checksum_none_assert(skb);
  183. /* Get parital ethernet information instead of eth_type_trans(),
  184. * Since we don't have an associated net_device.
  185. */
  186. skb_reset_mac_header(skb);
  187. skb->protocol = eth_hdr(skb)->h_proto;
  188. /* Pass SKB onward */
  189. if (cdev->ll2->cbs && cdev->ll2->cbs->rx_cb) {
  190. if (data->vlan)
  191. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
  192. data->vlan);
  193. cdev->ll2->cbs->rx_cb(cdev->ll2->cb_cookie, skb,
  194. data->opaque_data_0,
  195. data->opaque_data_1);
  196. }
  197. /* Update Buffer information and update FW producer */
  198. buffer->data = new_data;
  199. buffer->phys_addr = new_phys_addr;
  200. out_post:
  201. rc = qed_ll2_post_rx_buffer(QED_LEADING_HWFN(cdev), cdev->ll2->handle,
  202. buffer->phys_addr, 0, buffer, 1);
  203. if (rc)
  204. qed_ll2_dealloc_buffer(cdev, buffer);
  205. }
  206. static struct qed_ll2_info *__qed_ll2_handle_sanity(struct qed_hwfn *p_hwfn,
  207. u8 connection_handle,
  208. bool b_lock,
  209. bool b_only_active)
  210. {
  211. struct qed_ll2_info *p_ll2_conn, *p_ret = NULL;
  212. if (connection_handle >= QED_MAX_NUM_OF_LL2_CONNECTIONS)
  213. return NULL;
  214. if (!p_hwfn->p_ll2_info)
  215. return NULL;
  216. p_ll2_conn = &p_hwfn->p_ll2_info[connection_handle];
  217. if (b_only_active) {
  218. if (b_lock)
  219. mutex_lock(&p_ll2_conn->mutex);
  220. if (p_ll2_conn->b_active)
  221. p_ret = p_ll2_conn;
  222. if (b_lock)
  223. mutex_unlock(&p_ll2_conn->mutex);
  224. } else {
  225. p_ret = p_ll2_conn;
  226. }
  227. return p_ret;
  228. }
  229. static struct qed_ll2_info *qed_ll2_handle_sanity(struct qed_hwfn *p_hwfn,
  230. u8 connection_handle)
  231. {
  232. return __qed_ll2_handle_sanity(p_hwfn, connection_handle, false, true);
  233. }
  234. static struct qed_ll2_info *qed_ll2_handle_sanity_lock(struct qed_hwfn *p_hwfn,
  235. u8 connection_handle)
  236. {
  237. return __qed_ll2_handle_sanity(p_hwfn, connection_handle, true, true);
  238. }
  239. static struct qed_ll2_info *qed_ll2_handle_sanity_inactive(struct qed_hwfn
  240. *p_hwfn,
  241. u8 connection_handle)
  242. {
  243. return __qed_ll2_handle_sanity(p_hwfn, connection_handle, false, false);
  244. }
  245. static void qed_ll2_txq_flush(struct qed_hwfn *p_hwfn, u8 connection_handle)
  246. {
  247. bool b_last_packet = false, b_last_frag = false;
  248. struct qed_ll2_tx_packet *p_pkt = NULL;
  249. struct qed_ll2_info *p_ll2_conn;
  250. struct qed_ll2_tx_queue *p_tx;
  251. unsigned long flags = 0;
  252. dma_addr_t tx_frag;
  253. p_ll2_conn = qed_ll2_handle_sanity_inactive(p_hwfn, connection_handle);
  254. if (!p_ll2_conn)
  255. return;
  256. p_tx = &p_ll2_conn->tx_queue;
  257. spin_lock_irqsave(&p_tx->lock, flags);
  258. while (!list_empty(&p_tx->active_descq)) {
  259. p_pkt = list_first_entry(&p_tx->active_descq,
  260. struct qed_ll2_tx_packet, list_entry);
  261. if (!p_pkt)
  262. break;
  263. list_del(&p_pkt->list_entry);
  264. b_last_packet = list_empty(&p_tx->active_descq);
  265. list_add_tail(&p_pkt->list_entry, &p_tx->free_descq);
  266. spin_unlock_irqrestore(&p_tx->lock, flags);
  267. if (p_ll2_conn->input.conn_type == QED_LL2_TYPE_OOO) {
  268. struct qed_ooo_buffer *p_buffer;
  269. p_buffer = (struct qed_ooo_buffer *)p_pkt->cookie;
  270. qed_ooo_put_free_buffer(p_hwfn, p_hwfn->p_ooo_info,
  271. p_buffer);
  272. } else {
  273. p_tx->cur_completing_packet = *p_pkt;
  274. p_tx->cur_completing_bd_idx = 1;
  275. b_last_frag =
  276. p_tx->cur_completing_bd_idx == p_pkt->bd_used;
  277. tx_frag = p_pkt->bds_set[0].tx_frag;
  278. p_ll2_conn->cbs.tx_release_cb(p_ll2_conn->cbs.cookie,
  279. p_ll2_conn->my_id,
  280. p_pkt->cookie,
  281. tx_frag,
  282. b_last_frag,
  283. b_last_packet);
  284. }
  285. spin_lock_irqsave(&p_tx->lock, flags);
  286. }
  287. spin_unlock_irqrestore(&p_tx->lock, flags);
  288. }
  289. static int qed_ll2_txq_completion(struct qed_hwfn *p_hwfn, void *p_cookie)
  290. {
  291. struct qed_ll2_info *p_ll2_conn = p_cookie;
  292. struct qed_ll2_tx_queue *p_tx = &p_ll2_conn->tx_queue;
  293. u16 new_idx = 0, num_bds = 0, num_bds_in_packet = 0;
  294. struct qed_ll2_tx_packet *p_pkt;
  295. bool b_last_frag = false;
  296. unsigned long flags;
  297. int rc = -EINVAL;
  298. spin_lock_irqsave(&p_tx->lock, flags);
  299. if (p_tx->b_completing_packet) {
  300. rc = -EBUSY;
  301. goto out;
  302. }
  303. new_idx = le16_to_cpu(*p_tx->p_fw_cons);
  304. num_bds = ((s16)new_idx - (s16)p_tx->bds_idx);
  305. while (num_bds) {
  306. if (list_empty(&p_tx->active_descq))
  307. goto out;
  308. p_pkt = list_first_entry(&p_tx->active_descq,
  309. struct qed_ll2_tx_packet, list_entry);
  310. if (!p_pkt)
  311. goto out;
  312. p_tx->b_completing_packet = true;
  313. p_tx->cur_completing_packet = *p_pkt;
  314. num_bds_in_packet = p_pkt->bd_used;
  315. list_del(&p_pkt->list_entry);
  316. if (num_bds < num_bds_in_packet) {
  317. DP_NOTICE(p_hwfn,
  318. "Rest of BDs does not cover whole packet\n");
  319. goto out;
  320. }
  321. num_bds -= num_bds_in_packet;
  322. p_tx->bds_idx += num_bds_in_packet;
  323. while (num_bds_in_packet--)
  324. qed_chain_consume(&p_tx->txq_chain);
  325. p_tx->cur_completing_bd_idx = 1;
  326. b_last_frag = p_tx->cur_completing_bd_idx == p_pkt->bd_used;
  327. list_add_tail(&p_pkt->list_entry, &p_tx->free_descq);
  328. spin_unlock_irqrestore(&p_tx->lock, flags);
  329. p_ll2_conn->cbs.tx_comp_cb(p_ll2_conn->cbs.cookie,
  330. p_ll2_conn->my_id,
  331. p_pkt->cookie,
  332. p_pkt->bds_set[0].tx_frag,
  333. b_last_frag, !num_bds);
  334. spin_lock_irqsave(&p_tx->lock, flags);
  335. }
  336. p_tx->b_completing_packet = false;
  337. rc = 0;
  338. out:
  339. spin_unlock_irqrestore(&p_tx->lock, flags);
  340. return rc;
  341. }
  342. static void qed_ll2_rxq_parse_gsi(struct qed_hwfn *p_hwfn,
  343. union core_rx_cqe_union *p_cqe,
  344. struct qed_ll2_comp_rx_data *data)
  345. {
  346. data->parse_flags = le16_to_cpu(p_cqe->rx_cqe_gsi.parse_flags.flags);
  347. data->length.data_length = le16_to_cpu(p_cqe->rx_cqe_gsi.data_length);
  348. data->vlan = le16_to_cpu(p_cqe->rx_cqe_gsi.vlan);
  349. data->opaque_data_0 = le32_to_cpu(p_cqe->rx_cqe_gsi.src_mac_addrhi);
  350. data->opaque_data_1 = le16_to_cpu(p_cqe->rx_cqe_gsi.src_mac_addrlo);
  351. data->u.data_length_error = p_cqe->rx_cqe_gsi.data_length_error;
  352. data->qp_id = le16_to_cpu(p_cqe->rx_cqe_gsi.qp_id);
  353. data->src_qp = le32_to_cpu(p_cqe->rx_cqe_gsi.src_qp);
  354. }
  355. static void qed_ll2_rxq_parse_reg(struct qed_hwfn *p_hwfn,
  356. union core_rx_cqe_union *p_cqe,
  357. struct qed_ll2_comp_rx_data *data)
  358. {
  359. data->parse_flags = le16_to_cpu(p_cqe->rx_cqe_fp.parse_flags.flags);
  360. data->err_flags = le16_to_cpu(p_cqe->rx_cqe_fp.err_flags.flags);
  361. data->length.packet_length =
  362. le16_to_cpu(p_cqe->rx_cqe_fp.packet_length);
  363. data->vlan = le16_to_cpu(p_cqe->rx_cqe_fp.vlan);
  364. data->opaque_data_0 = le32_to_cpu(p_cqe->rx_cqe_fp.opaque_data.data[0]);
  365. data->opaque_data_1 = le32_to_cpu(p_cqe->rx_cqe_fp.opaque_data.data[1]);
  366. data->u.placement_offset = p_cqe->rx_cqe_fp.placement_offset;
  367. }
  368. static int
  369. qed_ll2_handle_slowpath(struct qed_hwfn *p_hwfn,
  370. struct qed_ll2_info *p_ll2_conn,
  371. union core_rx_cqe_union *p_cqe,
  372. unsigned long *p_lock_flags)
  373. {
  374. struct qed_ll2_rx_queue *p_rx = &p_ll2_conn->rx_queue;
  375. struct core_rx_slow_path_cqe *sp_cqe;
  376. sp_cqe = &p_cqe->rx_cqe_sp;
  377. if (sp_cqe->ramrod_cmd_id != CORE_RAMROD_RX_QUEUE_FLUSH) {
  378. DP_NOTICE(p_hwfn,
  379. "LL2 - unexpected Rx CQE slowpath ramrod_cmd_id:%d\n",
  380. sp_cqe->ramrod_cmd_id);
  381. return -EINVAL;
  382. }
  383. if (!p_ll2_conn->cbs.slowpath_cb) {
  384. DP_NOTICE(p_hwfn,
  385. "LL2 - received RX_QUEUE_FLUSH but no callback was provided\n");
  386. return -EINVAL;
  387. }
  388. spin_unlock_irqrestore(&p_rx->lock, *p_lock_flags);
  389. p_ll2_conn->cbs.slowpath_cb(p_ll2_conn->cbs.cookie,
  390. p_ll2_conn->my_id,
  391. le32_to_cpu(sp_cqe->opaque_data.data[0]),
  392. le32_to_cpu(sp_cqe->opaque_data.data[1]));
  393. spin_lock_irqsave(&p_rx->lock, *p_lock_flags);
  394. return 0;
  395. }
  396. static int
  397. qed_ll2_rxq_handle_completion(struct qed_hwfn *p_hwfn,
  398. struct qed_ll2_info *p_ll2_conn,
  399. union core_rx_cqe_union *p_cqe,
  400. unsigned long *p_lock_flags, bool b_last_cqe)
  401. {
  402. struct qed_ll2_rx_queue *p_rx = &p_ll2_conn->rx_queue;
  403. struct qed_ll2_rx_packet *p_pkt = NULL;
  404. struct qed_ll2_comp_rx_data data;
  405. if (!list_empty(&p_rx->active_descq))
  406. p_pkt = list_first_entry(&p_rx->active_descq,
  407. struct qed_ll2_rx_packet, list_entry);
  408. if (!p_pkt) {
  409. DP_NOTICE(p_hwfn,
  410. "[%d] LL2 Rx completion but active_descq is empty\n",
  411. p_ll2_conn->input.conn_type);
  412. return -EIO;
  413. }
  414. list_del(&p_pkt->list_entry);
  415. if (p_cqe->rx_cqe_sp.type == CORE_RX_CQE_TYPE_REGULAR)
  416. qed_ll2_rxq_parse_reg(p_hwfn, p_cqe, &data);
  417. else
  418. qed_ll2_rxq_parse_gsi(p_hwfn, p_cqe, &data);
  419. if (qed_chain_consume(&p_rx->rxq_chain) != p_pkt->rxq_bd)
  420. DP_NOTICE(p_hwfn,
  421. "Mismatch between active_descq and the LL2 Rx chain\n");
  422. list_add_tail(&p_pkt->list_entry, &p_rx->free_descq);
  423. data.connection_handle = p_ll2_conn->my_id;
  424. data.cookie = p_pkt->cookie;
  425. data.rx_buf_addr = p_pkt->rx_buf_addr;
  426. data.b_last_packet = b_last_cqe;
  427. spin_unlock_irqrestore(&p_rx->lock, *p_lock_flags);
  428. p_ll2_conn->cbs.rx_comp_cb(p_ll2_conn->cbs.cookie, &data);
  429. spin_lock_irqsave(&p_rx->lock, *p_lock_flags);
  430. return 0;
  431. }
  432. static int qed_ll2_rxq_completion(struct qed_hwfn *p_hwfn, void *cookie)
  433. {
  434. struct qed_ll2_info *p_ll2_conn = (struct qed_ll2_info *)cookie;
  435. struct qed_ll2_rx_queue *p_rx = &p_ll2_conn->rx_queue;
  436. union core_rx_cqe_union *cqe = NULL;
  437. u16 cq_new_idx = 0, cq_old_idx = 0;
  438. unsigned long flags = 0;
  439. int rc = 0;
  440. spin_lock_irqsave(&p_rx->lock, flags);
  441. cq_new_idx = le16_to_cpu(*p_rx->p_fw_cons);
  442. cq_old_idx = qed_chain_get_cons_idx(&p_rx->rcq_chain);
  443. while (cq_new_idx != cq_old_idx) {
  444. bool b_last_cqe = (cq_new_idx == cq_old_idx);
  445. cqe =
  446. (union core_rx_cqe_union *)
  447. qed_chain_consume(&p_rx->rcq_chain);
  448. cq_old_idx = qed_chain_get_cons_idx(&p_rx->rcq_chain);
  449. DP_VERBOSE(p_hwfn,
  450. QED_MSG_LL2,
  451. "LL2 [sw. cons %04x, fw. at %04x] - Got Packet of type %02x\n",
  452. cq_old_idx, cq_new_idx, cqe->rx_cqe_sp.type);
  453. switch (cqe->rx_cqe_sp.type) {
  454. case CORE_RX_CQE_TYPE_SLOW_PATH:
  455. rc = qed_ll2_handle_slowpath(p_hwfn, p_ll2_conn,
  456. cqe, &flags);
  457. break;
  458. case CORE_RX_CQE_TYPE_GSI_OFFLOAD:
  459. case CORE_RX_CQE_TYPE_REGULAR:
  460. rc = qed_ll2_rxq_handle_completion(p_hwfn, p_ll2_conn,
  461. cqe, &flags,
  462. b_last_cqe);
  463. break;
  464. default:
  465. rc = -EIO;
  466. }
  467. }
  468. spin_unlock_irqrestore(&p_rx->lock, flags);
  469. return rc;
  470. }
  471. static void qed_ll2_rxq_flush(struct qed_hwfn *p_hwfn, u8 connection_handle)
  472. {
  473. struct qed_ll2_info *p_ll2_conn = NULL;
  474. struct qed_ll2_rx_packet *p_pkt = NULL;
  475. struct qed_ll2_rx_queue *p_rx;
  476. unsigned long flags = 0;
  477. p_ll2_conn = qed_ll2_handle_sanity_inactive(p_hwfn, connection_handle);
  478. if (!p_ll2_conn)
  479. return;
  480. p_rx = &p_ll2_conn->rx_queue;
  481. spin_lock_irqsave(&p_rx->lock, flags);
  482. while (!list_empty(&p_rx->active_descq)) {
  483. p_pkt = list_first_entry(&p_rx->active_descq,
  484. struct qed_ll2_rx_packet, list_entry);
  485. if (!p_pkt)
  486. break;
  487. list_move_tail(&p_pkt->list_entry, &p_rx->free_descq);
  488. spin_unlock_irqrestore(&p_rx->lock, flags);
  489. if (p_ll2_conn->input.conn_type == QED_LL2_TYPE_OOO) {
  490. struct qed_ooo_buffer *p_buffer;
  491. p_buffer = (struct qed_ooo_buffer *)p_pkt->cookie;
  492. qed_ooo_put_free_buffer(p_hwfn, p_hwfn->p_ooo_info,
  493. p_buffer);
  494. } else {
  495. dma_addr_t rx_buf_addr = p_pkt->rx_buf_addr;
  496. void *cookie = p_pkt->cookie;
  497. bool b_last;
  498. b_last = list_empty(&p_rx->active_descq);
  499. p_ll2_conn->cbs.rx_release_cb(p_ll2_conn->cbs.cookie,
  500. p_ll2_conn->my_id,
  501. cookie,
  502. rx_buf_addr, b_last);
  503. }
  504. spin_lock_irqsave(&p_rx->lock, flags);
  505. }
  506. spin_unlock_irqrestore(&p_rx->lock, flags);
  507. }
  508. static bool
  509. qed_ll2_lb_rxq_handler_slowpath(struct qed_hwfn *p_hwfn,
  510. struct core_rx_slow_path_cqe *p_cqe)
  511. {
  512. struct ooo_opaque *iscsi_ooo;
  513. u32 cid;
  514. if (p_cqe->ramrod_cmd_id != CORE_RAMROD_RX_QUEUE_FLUSH)
  515. return false;
  516. iscsi_ooo = (struct ooo_opaque *)&p_cqe->opaque_data;
  517. if (iscsi_ooo->ooo_opcode != TCP_EVENT_DELETE_ISLES)
  518. return false;
  519. /* Need to make a flush */
  520. cid = le32_to_cpu(iscsi_ooo->cid);
  521. qed_ooo_release_connection_isles(p_hwfn, p_hwfn->p_ooo_info, cid);
  522. return true;
  523. }
  524. static int qed_ll2_lb_rxq_handler(struct qed_hwfn *p_hwfn,
  525. struct qed_ll2_info *p_ll2_conn)
  526. {
  527. struct qed_ll2_rx_queue *p_rx = &p_ll2_conn->rx_queue;
  528. u16 packet_length = 0, parse_flags = 0, vlan = 0;
  529. struct qed_ll2_rx_packet *p_pkt = NULL;
  530. u32 num_ooo_add_to_peninsula = 0, cid;
  531. union core_rx_cqe_union *cqe = NULL;
  532. u16 cq_new_idx = 0, cq_old_idx = 0;
  533. struct qed_ooo_buffer *p_buffer;
  534. struct ooo_opaque *iscsi_ooo;
  535. u8 placement_offset = 0;
  536. u8 cqe_type;
  537. cq_new_idx = le16_to_cpu(*p_rx->p_fw_cons);
  538. cq_old_idx = qed_chain_get_cons_idx(&p_rx->rcq_chain);
  539. if (cq_new_idx == cq_old_idx)
  540. return 0;
  541. while (cq_new_idx != cq_old_idx) {
  542. struct core_rx_fast_path_cqe *p_cqe_fp;
  543. cqe = qed_chain_consume(&p_rx->rcq_chain);
  544. cq_old_idx = qed_chain_get_cons_idx(&p_rx->rcq_chain);
  545. cqe_type = cqe->rx_cqe_sp.type;
  546. if (cqe_type == CORE_RX_CQE_TYPE_SLOW_PATH)
  547. if (qed_ll2_lb_rxq_handler_slowpath(p_hwfn,
  548. &cqe->rx_cqe_sp))
  549. continue;
  550. if (cqe_type != CORE_RX_CQE_TYPE_REGULAR) {
  551. DP_NOTICE(p_hwfn,
  552. "Got a non-regular LB LL2 completion [type 0x%02x]\n",
  553. cqe_type);
  554. return -EINVAL;
  555. }
  556. p_cqe_fp = &cqe->rx_cqe_fp;
  557. placement_offset = p_cqe_fp->placement_offset;
  558. parse_flags = le16_to_cpu(p_cqe_fp->parse_flags.flags);
  559. packet_length = le16_to_cpu(p_cqe_fp->packet_length);
  560. vlan = le16_to_cpu(p_cqe_fp->vlan);
  561. iscsi_ooo = (struct ooo_opaque *)&p_cqe_fp->opaque_data;
  562. qed_ooo_save_history_entry(p_hwfn, p_hwfn->p_ooo_info,
  563. iscsi_ooo);
  564. cid = le32_to_cpu(iscsi_ooo->cid);
  565. /* Process delete isle first */
  566. if (iscsi_ooo->drop_size)
  567. qed_ooo_delete_isles(p_hwfn, p_hwfn->p_ooo_info, cid,
  568. iscsi_ooo->drop_isle,
  569. iscsi_ooo->drop_size);
  570. if (iscsi_ooo->ooo_opcode == TCP_EVENT_NOP)
  571. continue;
  572. /* Now process create/add/join isles */
  573. if (list_empty(&p_rx->active_descq)) {
  574. DP_NOTICE(p_hwfn,
  575. "LL2 OOO RX chain has no submitted buffers\n"
  576. );
  577. return -EIO;
  578. }
  579. p_pkt = list_first_entry(&p_rx->active_descq,
  580. struct qed_ll2_rx_packet, list_entry);
  581. if ((iscsi_ooo->ooo_opcode == TCP_EVENT_ADD_NEW_ISLE) ||
  582. (iscsi_ooo->ooo_opcode == TCP_EVENT_ADD_ISLE_RIGHT) ||
  583. (iscsi_ooo->ooo_opcode == TCP_EVENT_ADD_ISLE_LEFT) ||
  584. (iscsi_ooo->ooo_opcode == TCP_EVENT_ADD_PEN) ||
  585. (iscsi_ooo->ooo_opcode == TCP_EVENT_JOIN)) {
  586. if (!p_pkt) {
  587. DP_NOTICE(p_hwfn,
  588. "LL2 OOO RX packet is not valid\n");
  589. return -EIO;
  590. }
  591. list_del(&p_pkt->list_entry);
  592. p_buffer = (struct qed_ooo_buffer *)p_pkt->cookie;
  593. p_buffer->packet_length = packet_length;
  594. p_buffer->parse_flags = parse_flags;
  595. p_buffer->vlan = vlan;
  596. p_buffer->placement_offset = placement_offset;
  597. qed_chain_consume(&p_rx->rxq_chain);
  598. list_add_tail(&p_pkt->list_entry, &p_rx->free_descq);
  599. switch (iscsi_ooo->ooo_opcode) {
  600. case TCP_EVENT_ADD_NEW_ISLE:
  601. qed_ooo_add_new_isle(p_hwfn,
  602. p_hwfn->p_ooo_info,
  603. cid,
  604. iscsi_ooo->ooo_isle,
  605. p_buffer);
  606. break;
  607. case TCP_EVENT_ADD_ISLE_RIGHT:
  608. qed_ooo_add_new_buffer(p_hwfn,
  609. p_hwfn->p_ooo_info,
  610. cid,
  611. iscsi_ooo->ooo_isle,
  612. p_buffer,
  613. QED_OOO_RIGHT_BUF);
  614. break;
  615. case TCP_EVENT_ADD_ISLE_LEFT:
  616. qed_ooo_add_new_buffer(p_hwfn,
  617. p_hwfn->p_ooo_info,
  618. cid,
  619. iscsi_ooo->ooo_isle,
  620. p_buffer,
  621. QED_OOO_LEFT_BUF);
  622. break;
  623. case TCP_EVENT_JOIN:
  624. qed_ooo_add_new_buffer(p_hwfn,
  625. p_hwfn->p_ooo_info,
  626. cid,
  627. iscsi_ooo->ooo_isle +
  628. 1,
  629. p_buffer,
  630. QED_OOO_LEFT_BUF);
  631. qed_ooo_join_isles(p_hwfn,
  632. p_hwfn->p_ooo_info,
  633. cid, iscsi_ooo->ooo_isle);
  634. break;
  635. case TCP_EVENT_ADD_PEN:
  636. num_ooo_add_to_peninsula++;
  637. qed_ooo_put_ready_buffer(p_hwfn,
  638. p_hwfn->p_ooo_info,
  639. p_buffer, true);
  640. break;
  641. }
  642. } else {
  643. DP_NOTICE(p_hwfn,
  644. "Unexpected event (%d) TX OOO completion\n",
  645. iscsi_ooo->ooo_opcode);
  646. }
  647. }
  648. return 0;
  649. }
  650. static void
  651. qed_ooo_submit_tx_buffers(struct qed_hwfn *p_hwfn,
  652. struct qed_ll2_info *p_ll2_conn)
  653. {
  654. struct qed_ll2_tx_pkt_info tx_pkt;
  655. struct qed_ooo_buffer *p_buffer;
  656. u16 l4_hdr_offset_w;
  657. dma_addr_t first_frag;
  658. u8 bd_flags;
  659. int rc;
  660. /* Submit Tx buffers here */
  661. while ((p_buffer = qed_ooo_get_ready_buffer(p_hwfn,
  662. p_hwfn->p_ooo_info))) {
  663. l4_hdr_offset_w = 0;
  664. bd_flags = 0;
  665. first_frag = p_buffer->rx_buffer_phys_addr +
  666. p_buffer->placement_offset;
  667. SET_FIELD(bd_flags, CORE_TX_BD_DATA_FORCE_VLAN_MODE, 1);
  668. SET_FIELD(bd_flags, CORE_TX_BD_DATA_L4_PROTOCOL, 1);
  669. memset(&tx_pkt, 0, sizeof(tx_pkt));
  670. tx_pkt.num_of_bds = 1;
  671. tx_pkt.vlan = p_buffer->vlan;
  672. tx_pkt.bd_flags = bd_flags;
  673. tx_pkt.l4_hdr_offset_w = l4_hdr_offset_w;
  674. tx_pkt.tx_dest = p_ll2_conn->tx_dest;
  675. tx_pkt.first_frag = first_frag;
  676. tx_pkt.first_frag_len = p_buffer->packet_length;
  677. tx_pkt.cookie = p_buffer;
  678. rc = qed_ll2_prepare_tx_packet(p_hwfn, p_ll2_conn->my_id,
  679. &tx_pkt, true);
  680. if (rc) {
  681. qed_ooo_put_ready_buffer(p_hwfn, p_hwfn->p_ooo_info,
  682. p_buffer, false);
  683. break;
  684. }
  685. }
  686. }
  687. static void
  688. qed_ooo_submit_rx_buffers(struct qed_hwfn *p_hwfn,
  689. struct qed_ll2_info *p_ll2_conn)
  690. {
  691. struct qed_ooo_buffer *p_buffer;
  692. int rc;
  693. while ((p_buffer = qed_ooo_get_free_buffer(p_hwfn,
  694. p_hwfn->p_ooo_info))) {
  695. rc = qed_ll2_post_rx_buffer(p_hwfn,
  696. p_ll2_conn->my_id,
  697. p_buffer->rx_buffer_phys_addr,
  698. 0, p_buffer, true);
  699. if (rc) {
  700. qed_ooo_put_free_buffer(p_hwfn,
  701. p_hwfn->p_ooo_info, p_buffer);
  702. break;
  703. }
  704. }
  705. }
  706. static int qed_ll2_lb_rxq_completion(struct qed_hwfn *p_hwfn, void *p_cookie)
  707. {
  708. struct qed_ll2_info *p_ll2_conn = (struct qed_ll2_info *)p_cookie;
  709. int rc;
  710. if (!QED_LL2_RX_REGISTERED(p_ll2_conn))
  711. return 0;
  712. rc = qed_ll2_lb_rxq_handler(p_hwfn, p_ll2_conn);
  713. if (rc)
  714. return rc;
  715. qed_ooo_submit_rx_buffers(p_hwfn, p_ll2_conn);
  716. qed_ooo_submit_tx_buffers(p_hwfn, p_ll2_conn);
  717. return 0;
  718. }
  719. static int qed_ll2_lb_txq_completion(struct qed_hwfn *p_hwfn, void *p_cookie)
  720. {
  721. struct qed_ll2_info *p_ll2_conn = (struct qed_ll2_info *)p_cookie;
  722. struct qed_ll2_tx_queue *p_tx = &p_ll2_conn->tx_queue;
  723. struct qed_ll2_tx_packet *p_pkt = NULL;
  724. struct qed_ooo_buffer *p_buffer;
  725. bool b_dont_submit_rx = false;
  726. u16 new_idx = 0, num_bds = 0;
  727. int rc;
  728. if (!QED_LL2_TX_REGISTERED(p_ll2_conn))
  729. return 0;
  730. new_idx = le16_to_cpu(*p_tx->p_fw_cons);
  731. num_bds = ((s16)new_idx - (s16)p_tx->bds_idx);
  732. if (!num_bds)
  733. return 0;
  734. while (num_bds) {
  735. if (list_empty(&p_tx->active_descq))
  736. return -EINVAL;
  737. p_pkt = list_first_entry(&p_tx->active_descq,
  738. struct qed_ll2_tx_packet, list_entry);
  739. if (!p_pkt)
  740. return -EINVAL;
  741. if (p_pkt->bd_used != 1) {
  742. DP_NOTICE(p_hwfn,
  743. "Unexpectedly many BDs(%d) in TX OOO completion\n",
  744. p_pkt->bd_used);
  745. return -EINVAL;
  746. }
  747. list_del(&p_pkt->list_entry);
  748. num_bds--;
  749. p_tx->bds_idx++;
  750. qed_chain_consume(&p_tx->txq_chain);
  751. p_buffer = (struct qed_ooo_buffer *)p_pkt->cookie;
  752. list_add_tail(&p_pkt->list_entry, &p_tx->free_descq);
  753. if (b_dont_submit_rx) {
  754. qed_ooo_put_free_buffer(p_hwfn, p_hwfn->p_ooo_info,
  755. p_buffer);
  756. continue;
  757. }
  758. rc = qed_ll2_post_rx_buffer(p_hwfn, p_ll2_conn->my_id,
  759. p_buffer->rx_buffer_phys_addr, 0,
  760. p_buffer, true);
  761. if (rc != 0) {
  762. qed_ooo_put_free_buffer(p_hwfn,
  763. p_hwfn->p_ooo_info, p_buffer);
  764. b_dont_submit_rx = true;
  765. }
  766. }
  767. qed_ooo_submit_tx_buffers(p_hwfn, p_ll2_conn);
  768. return 0;
  769. }
  770. static void qed_ll2_stop_ooo(struct qed_dev *cdev)
  771. {
  772. struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
  773. u8 *handle = &hwfn->pf_params.iscsi_pf_params.ll2_ooo_queue_id;
  774. DP_VERBOSE(cdev, QED_MSG_STORAGE, "Stopping LL2 OOO queue [%02x]\n",
  775. *handle);
  776. qed_ll2_terminate_connection(hwfn, *handle);
  777. qed_ll2_release_connection(hwfn, *handle);
  778. *handle = QED_LL2_UNUSED_HANDLE;
  779. }
  780. static int qed_sp_ll2_rx_queue_start(struct qed_hwfn *p_hwfn,
  781. struct qed_ll2_info *p_ll2_conn,
  782. u8 action_on_error)
  783. {
  784. enum qed_ll2_conn_type conn_type = p_ll2_conn->input.conn_type;
  785. struct qed_ll2_rx_queue *p_rx = &p_ll2_conn->rx_queue;
  786. struct core_rx_start_ramrod_data *p_ramrod = NULL;
  787. struct qed_spq_entry *p_ent = NULL;
  788. struct qed_sp_init_data init_data;
  789. u16 cqe_pbl_size;
  790. int rc = 0;
  791. /* Get SPQ entry */
  792. memset(&init_data, 0, sizeof(init_data));
  793. init_data.cid = p_ll2_conn->cid;
  794. init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
  795. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  796. rc = qed_sp_init_request(p_hwfn, &p_ent,
  797. CORE_RAMROD_RX_QUEUE_START,
  798. PROTOCOLID_CORE, &init_data);
  799. if (rc)
  800. return rc;
  801. p_ramrod = &p_ent->ramrod.core_rx_queue_start;
  802. p_ramrod->sb_id = cpu_to_le16(qed_int_get_sp_sb_id(p_hwfn));
  803. p_ramrod->sb_index = p_rx->rx_sb_index;
  804. p_ramrod->complete_event_flg = 1;
  805. p_ramrod->mtu = cpu_to_le16(p_ll2_conn->input.mtu);
  806. DMA_REGPAIR_LE(p_ramrod->bd_base, p_rx->rxq_chain.p_phys_addr);
  807. cqe_pbl_size = (u16)qed_chain_get_page_cnt(&p_rx->rcq_chain);
  808. p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size);
  809. DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr,
  810. qed_chain_get_pbl_phys(&p_rx->rcq_chain));
  811. p_ramrod->drop_ttl0_flg = p_ll2_conn->input.rx_drop_ttl0_flg;
  812. p_ramrod->inner_vlan_stripping_en =
  813. p_ll2_conn->input.rx_vlan_removal_en;
  814. if (test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits) &&
  815. p_ll2_conn->input.conn_type == QED_LL2_TYPE_FCOE)
  816. p_ramrod->report_outer_vlan = 1;
  817. p_ramrod->queue_id = p_ll2_conn->queue_id;
  818. p_ramrod->main_func_queue = p_ll2_conn->main_func_queue ? 1 : 0;
  819. if (test_bit(QED_MF_LL2_NON_UNICAST, &p_hwfn->cdev->mf_bits) &&
  820. p_ramrod->main_func_queue && conn_type != QED_LL2_TYPE_ROCE &&
  821. conn_type != QED_LL2_TYPE_IWARP) {
  822. p_ramrod->mf_si_bcast_accept_all = 1;
  823. p_ramrod->mf_si_mcast_accept_all = 1;
  824. } else {
  825. p_ramrod->mf_si_bcast_accept_all = 0;
  826. p_ramrod->mf_si_mcast_accept_all = 0;
  827. }
  828. p_ramrod->action_on_error.error_type = action_on_error;
  829. p_ramrod->gsi_offload_flag = p_ll2_conn->input.gsi_enable;
  830. return qed_spq_post(p_hwfn, p_ent, NULL);
  831. }
  832. static int qed_sp_ll2_tx_queue_start(struct qed_hwfn *p_hwfn,
  833. struct qed_ll2_info *p_ll2_conn)
  834. {
  835. enum qed_ll2_conn_type conn_type = p_ll2_conn->input.conn_type;
  836. struct qed_ll2_tx_queue *p_tx = &p_ll2_conn->tx_queue;
  837. struct core_tx_start_ramrod_data *p_ramrod = NULL;
  838. struct qed_spq_entry *p_ent = NULL;
  839. struct qed_sp_init_data init_data;
  840. u16 pq_id = 0, pbl_size;
  841. int rc = -EINVAL;
  842. if (!QED_LL2_TX_REGISTERED(p_ll2_conn))
  843. return 0;
  844. if (p_ll2_conn->input.conn_type == QED_LL2_TYPE_OOO)
  845. p_ll2_conn->tx_stats_en = 0;
  846. else
  847. p_ll2_conn->tx_stats_en = 1;
  848. /* Get SPQ entry */
  849. memset(&init_data, 0, sizeof(init_data));
  850. init_data.cid = p_ll2_conn->cid;
  851. init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
  852. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  853. rc = qed_sp_init_request(p_hwfn, &p_ent,
  854. CORE_RAMROD_TX_QUEUE_START,
  855. PROTOCOLID_CORE, &init_data);
  856. if (rc)
  857. return rc;
  858. p_ramrod = &p_ent->ramrod.core_tx_queue_start;
  859. p_ramrod->sb_id = cpu_to_le16(qed_int_get_sp_sb_id(p_hwfn));
  860. p_ramrod->sb_index = p_tx->tx_sb_index;
  861. p_ramrod->mtu = cpu_to_le16(p_ll2_conn->input.mtu);
  862. p_ramrod->stats_en = p_ll2_conn->tx_stats_en;
  863. p_ramrod->stats_id = p_ll2_conn->tx_stats_id;
  864. DMA_REGPAIR_LE(p_ramrod->pbl_base_addr,
  865. qed_chain_get_pbl_phys(&p_tx->txq_chain));
  866. pbl_size = qed_chain_get_page_cnt(&p_tx->txq_chain);
  867. p_ramrod->pbl_size = cpu_to_le16(pbl_size);
  868. switch (p_ll2_conn->input.tx_tc) {
  869. case PURE_LB_TC:
  870. pq_id = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB);
  871. break;
  872. case PKT_LB_TC:
  873. pq_id = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OOO);
  874. break;
  875. default:
  876. pq_id = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD);
  877. break;
  878. }
  879. p_ramrod->qm_pq_id = cpu_to_le16(pq_id);
  880. switch (conn_type) {
  881. case QED_LL2_TYPE_FCOE:
  882. p_ramrod->conn_type = PROTOCOLID_FCOE;
  883. break;
  884. case QED_LL2_TYPE_ISCSI:
  885. p_ramrod->conn_type = PROTOCOLID_ISCSI;
  886. break;
  887. case QED_LL2_TYPE_ROCE:
  888. p_ramrod->conn_type = PROTOCOLID_ROCE;
  889. break;
  890. case QED_LL2_TYPE_IWARP:
  891. p_ramrod->conn_type = PROTOCOLID_IWARP;
  892. break;
  893. case QED_LL2_TYPE_OOO:
  894. if (p_hwfn->hw_info.personality == QED_PCI_ISCSI)
  895. p_ramrod->conn_type = PROTOCOLID_ISCSI;
  896. else
  897. p_ramrod->conn_type = PROTOCOLID_IWARP;
  898. break;
  899. default:
  900. p_ramrod->conn_type = PROTOCOLID_ETH;
  901. DP_NOTICE(p_hwfn, "Unknown connection type: %d\n", conn_type);
  902. }
  903. p_ramrod->gsi_offload_flag = p_ll2_conn->input.gsi_enable;
  904. return qed_spq_post(p_hwfn, p_ent, NULL);
  905. }
  906. static int qed_sp_ll2_rx_queue_stop(struct qed_hwfn *p_hwfn,
  907. struct qed_ll2_info *p_ll2_conn)
  908. {
  909. struct core_rx_stop_ramrod_data *p_ramrod = NULL;
  910. struct qed_spq_entry *p_ent = NULL;
  911. struct qed_sp_init_data init_data;
  912. int rc = -EINVAL;
  913. /* Get SPQ entry */
  914. memset(&init_data, 0, sizeof(init_data));
  915. init_data.cid = p_ll2_conn->cid;
  916. init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
  917. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  918. rc = qed_sp_init_request(p_hwfn, &p_ent,
  919. CORE_RAMROD_RX_QUEUE_STOP,
  920. PROTOCOLID_CORE, &init_data);
  921. if (rc)
  922. return rc;
  923. p_ramrod = &p_ent->ramrod.core_rx_queue_stop;
  924. p_ramrod->complete_event_flg = 1;
  925. p_ramrod->queue_id = p_ll2_conn->queue_id;
  926. return qed_spq_post(p_hwfn, p_ent, NULL);
  927. }
  928. static int qed_sp_ll2_tx_queue_stop(struct qed_hwfn *p_hwfn,
  929. struct qed_ll2_info *p_ll2_conn)
  930. {
  931. struct qed_spq_entry *p_ent = NULL;
  932. struct qed_sp_init_data init_data;
  933. int rc = -EINVAL;
  934. /* Get SPQ entry */
  935. memset(&init_data, 0, sizeof(init_data));
  936. init_data.cid = p_ll2_conn->cid;
  937. init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
  938. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  939. rc = qed_sp_init_request(p_hwfn, &p_ent,
  940. CORE_RAMROD_TX_QUEUE_STOP,
  941. PROTOCOLID_CORE, &init_data);
  942. if (rc)
  943. return rc;
  944. return qed_spq_post(p_hwfn, p_ent, NULL);
  945. }
  946. static int
  947. qed_ll2_acquire_connection_rx(struct qed_hwfn *p_hwfn,
  948. struct qed_ll2_info *p_ll2_info)
  949. {
  950. struct qed_ll2_rx_packet *p_descq;
  951. u32 capacity;
  952. int rc = 0;
  953. if (!p_ll2_info->input.rx_num_desc)
  954. goto out;
  955. rc = qed_chain_alloc(p_hwfn->cdev,
  956. QED_CHAIN_USE_TO_CONSUME_PRODUCE,
  957. QED_CHAIN_MODE_NEXT_PTR,
  958. QED_CHAIN_CNT_TYPE_U16,
  959. p_ll2_info->input.rx_num_desc,
  960. sizeof(struct core_rx_bd),
  961. &p_ll2_info->rx_queue.rxq_chain, NULL);
  962. if (rc) {
  963. DP_NOTICE(p_hwfn, "Failed to allocate ll2 rxq chain\n");
  964. goto out;
  965. }
  966. capacity = qed_chain_get_capacity(&p_ll2_info->rx_queue.rxq_chain);
  967. p_descq = kcalloc(capacity, sizeof(struct qed_ll2_rx_packet),
  968. GFP_KERNEL);
  969. if (!p_descq) {
  970. rc = -ENOMEM;
  971. DP_NOTICE(p_hwfn, "Failed to allocate ll2 Rx desc\n");
  972. goto out;
  973. }
  974. p_ll2_info->rx_queue.descq_array = p_descq;
  975. rc = qed_chain_alloc(p_hwfn->cdev,
  976. QED_CHAIN_USE_TO_CONSUME_PRODUCE,
  977. QED_CHAIN_MODE_PBL,
  978. QED_CHAIN_CNT_TYPE_U16,
  979. p_ll2_info->input.rx_num_desc,
  980. sizeof(struct core_rx_fast_path_cqe),
  981. &p_ll2_info->rx_queue.rcq_chain, NULL);
  982. if (rc) {
  983. DP_NOTICE(p_hwfn, "Failed to allocate ll2 rcq chain\n");
  984. goto out;
  985. }
  986. DP_VERBOSE(p_hwfn, QED_MSG_LL2,
  987. "Allocated LL2 Rxq [Type %08x] with 0x%08x buffers\n",
  988. p_ll2_info->input.conn_type, p_ll2_info->input.rx_num_desc);
  989. out:
  990. return rc;
  991. }
  992. static int qed_ll2_acquire_connection_tx(struct qed_hwfn *p_hwfn,
  993. struct qed_ll2_info *p_ll2_info)
  994. {
  995. struct qed_ll2_tx_packet *p_descq;
  996. u32 desc_size;
  997. u32 capacity;
  998. int rc = 0;
  999. if (!p_ll2_info->input.tx_num_desc)
  1000. goto out;
  1001. rc = qed_chain_alloc(p_hwfn->cdev,
  1002. QED_CHAIN_USE_TO_CONSUME_PRODUCE,
  1003. QED_CHAIN_MODE_PBL,
  1004. QED_CHAIN_CNT_TYPE_U16,
  1005. p_ll2_info->input.tx_num_desc,
  1006. sizeof(struct core_tx_bd),
  1007. &p_ll2_info->tx_queue.txq_chain, NULL);
  1008. if (rc)
  1009. goto out;
  1010. capacity = qed_chain_get_capacity(&p_ll2_info->tx_queue.txq_chain);
  1011. /* First element is part of the packet, rest are flexibly added */
  1012. desc_size = (sizeof(*p_descq) +
  1013. (p_ll2_info->input.tx_max_bds_per_packet - 1) *
  1014. sizeof(p_descq->bds_set));
  1015. p_descq = kcalloc(capacity, desc_size, GFP_KERNEL);
  1016. if (!p_descq) {
  1017. rc = -ENOMEM;
  1018. goto out;
  1019. }
  1020. p_ll2_info->tx_queue.descq_mem = p_descq;
  1021. DP_VERBOSE(p_hwfn, QED_MSG_LL2,
  1022. "Allocated LL2 Txq [Type %08x] with 0x%08x buffers\n",
  1023. p_ll2_info->input.conn_type, p_ll2_info->input.tx_num_desc);
  1024. out:
  1025. if (rc)
  1026. DP_NOTICE(p_hwfn,
  1027. "Can't allocate memory for Tx LL2 with 0x%08x buffers\n",
  1028. p_ll2_info->input.tx_num_desc);
  1029. return rc;
  1030. }
  1031. static int
  1032. qed_ll2_acquire_connection_ooo(struct qed_hwfn *p_hwfn,
  1033. struct qed_ll2_info *p_ll2_info, u16 mtu)
  1034. {
  1035. struct qed_ooo_buffer *p_buf = NULL;
  1036. void *p_virt;
  1037. u16 buf_idx;
  1038. int rc = 0;
  1039. if (p_ll2_info->input.conn_type != QED_LL2_TYPE_OOO)
  1040. return rc;
  1041. /* Correct number of requested OOO buffers if needed */
  1042. if (!p_ll2_info->input.rx_num_ooo_buffers) {
  1043. u16 num_desc = p_ll2_info->input.rx_num_desc;
  1044. if (!num_desc)
  1045. return -EINVAL;
  1046. p_ll2_info->input.rx_num_ooo_buffers = num_desc * 2;
  1047. }
  1048. for (buf_idx = 0; buf_idx < p_ll2_info->input.rx_num_ooo_buffers;
  1049. buf_idx++) {
  1050. p_buf = kzalloc(sizeof(*p_buf), GFP_KERNEL);
  1051. if (!p_buf) {
  1052. rc = -ENOMEM;
  1053. goto out;
  1054. }
  1055. p_buf->rx_buffer_size = mtu + 26 + ETH_CACHE_LINE_SIZE;
  1056. p_buf->rx_buffer_size = (p_buf->rx_buffer_size +
  1057. ETH_CACHE_LINE_SIZE - 1) &
  1058. ~(ETH_CACHE_LINE_SIZE - 1);
  1059. p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
  1060. p_buf->rx_buffer_size,
  1061. &p_buf->rx_buffer_phys_addr,
  1062. GFP_KERNEL);
  1063. if (!p_virt) {
  1064. kfree(p_buf);
  1065. rc = -ENOMEM;
  1066. goto out;
  1067. }
  1068. p_buf->rx_buffer_virt_addr = p_virt;
  1069. qed_ooo_put_free_buffer(p_hwfn, p_hwfn->p_ooo_info, p_buf);
  1070. }
  1071. DP_VERBOSE(p_hwfn, QED_MSG_LL2,
  1072. "Allocated [%04x] LL2 OOO buffers [each of size 0x%08x]\n",
  1073. p_ll2_info->input.rx_num_ooo_buffers, p_buf->rx_buffer_size);
  1074. out:
  1075. return rc;
  1076. }
  1077. static int
  1078. qed_ll2_set_cbs(struct qed_ll2_info *p_ll2_info, const struct qed_ll2_cbs *cbs)
  1079. {
  1080. if (!cbs || (!cbs->rx_comp_cb ||
  1081. !cbs->rx_release_cb ||
  1082. !cbs->tx_comp_cb || !cbs->tx_release_cb || !cbs->cookie))
  1083. return -EINVAL;
  1084. p_ll2_info->cbs.rx_comp_cb = cbs->rx_comp_cb;
  1085. p_ll2_info->cbs.rx_release_cb = cbs->rx_release_cb;
  1086. p_ll2_info->cbs.tx_comp_cb = cbs->tx_comp_cb;
  1087. p_ll2_info->cbs.tx_release_cb = cbs->tx_release_cb;
  1088. p_ll2_info->cbs.slowpath_cb = cbs->slowpath_cb;
  1089. p_ll2_info->cbs.cookie = cbs->cookie;
  1090. return 0;
  1091. }
  1092. static enum core_error_handle
  1093. qed_ll2_get_error_choice(enum qed_ll2_error_handle err)
  1094. {
  1095. switch (err) {
  1096. case QED_LL2_DROP_PACKET:
  1097. return LL2_DROP_PACKET;
  1098. case QED_LL2_DO_NOTHING:
  1099. return LL2_DO_NOTHING;
  1100. case QED_LL2_ASSERT:
  1101. return LL2_ASSERT;
  1102. default:
  1103. return LL2_DO_NOTHING;
  1104. }
  1105. }
  1106. int qed_ll2_acquire_connection(void *cxt, struct qed_ll2_acquire_data *data)
  1107. {
  1108. struct qed_hwfn *p_hwfn = cxt;
  1109. qed_int_comp_cb_t comp_rx_cb, comp_tx_cb;
  1110. struct qed_ll2_info *p_ll2_info = NULL;
  1111. u8 i, *p_tx_max;
  1112. int rc;
  1113. if (!data->p_connection_handle || !p_hwfn->p_ll2_info)
  1114. return -EINVAL;
  1115. /* Find a free connection to be used */
  1116. for (i = 0; (i < QED_MAX_NUM_OF_LL2_CONNECTIONS); i++) {
  1117. mutex_lock(&p_hwfn->p_ll2_info[i].mutex);
  1118. if (p_hwfn->p_ll2_info[i].b_active) {
  1119. mutex_unlock(&p_hwfn->p_ll2_info[i].mutex);
  1120. continue;
  1121. }
  1122. p_hwfn->p_ll2_info[i].b_active = true;
  1123. p_ll2_info = &p_hwfn->p_ll2_info[i];
  1124. mutex_unlock(&p_hwfn->p_ll2_info[i].mutex);
  1125. break;
  1126. }
  1127. if (!p_ll2_info)
  1128. return -EBUSY;
  1129. memcpy(&p_ll2_info->input, &data->input, sizeof(p_ll2_info->input));
  1130. switch (data->input.tx_dest) {
  1131. case QED_LL2_TX_DEST_NW:
  1132. p_ll2_info->tx_dest = CORE_TX_DEST_NW;
  1133. break;
  1134. case QED_LL2_TX_DEST_LB:
  1135. p_ll2_info->tx_dest = CORE_TX_DEST_LB;
  1136. break;
  1137. case QED_LL2_TX_DEST_DROP:
  1138. p_ll2_info->tx_dest = CORE_TX_DEST_DROP;
  1139. break;
  1140. default:
  1141. return -EINVAL;
  1142. }
  1143. if (data->input.conn_type == QED_LL2_TYPE_OOO ||
  1144. data->input.secondary_queue)
  1145. p_ll2_info->main_func_queue = false;
  1146. else
  1147. p_ll2_info->main_func_queue = true;
  1148. /* Correct maximum number of Tx BDs */
  1149. p_tx_max = &p_ll2_info->input.tx_max_bds_per_packet;
  1150. if (*p_tx_max == 0)
  1151. *p_tx_max = CORE_LL2_TX_MAX_BDS_PER_PACKET;
  1152. else
  1153. *p_tx_max = min_t(u8, *p_tx_max,
  1154. CORE_LL2_TX_MAX_BDS_PER_PACKET);
  1155. rc = qed_ll2_set_cbs(p_ll2_info, data->cbs);
  1156. if (rc) {
  1157. DP_NOTICE(p_hwfn, "Invalid callback functions\n");
  1158. goto q_allocate_fail;
  1159. }
  1160. rc = qed_ll2_acquire_connection_rx(p_hwfn, p_ll2_info);
  1161. if (rc)
  1162. goto q_allocate_fail;
  1163. rc = qed_ll2_acquire_connection_tx(p_hwfn, p_ll2_info);
  1164. if (rc)
  1165. goto q_allocate_fail;
  1166. rc = qed_ll2_acquire_connection_ooo(p_hwfn, p_ll2_info,
  1167. data->input.mtu);
  1168. if (rc)
  1169. goto q_allocate_fail;
  1170. /* Register callbacks for the Rx/Tx queues */
  1171. if (data->input.conn_type == QED_LL2_TYPE_OOO) {
  1172. comp_rx_cb = qed_ll2_lb_rxq_completion;
  1173. comp_tx_cb = qed_ll2_lb_txq_completion;
  1174. } else {
  1175. comp_rx_cb = qed_ll2_rxq_completion;
  1176. comp_tx_cb = qed_ll2_txq_completion;
  1177. }
  1178. if (data->input.rx_num_desc) {
  1179. qed_int_register_cb(p_hwfn, comp_rx_cb,
  1180. &p_hwfn->p_ll2_info[i],
  1181. &p_ll2_info->rx_queue.rx_sb_index,
  1182. &p_ll2_info->rx_queue.p_fw_cons);
  1183. p_ll2_info->rx_queue.b_cb_registred = true;
  1184. }
  1185. if (data->input.tx_num_desc) {
  1186. qed_int_register_cb(p_hwfn,
  1187. comp_tx_cb,
  1188. &p_hwfn->p_ll2_info[i],
  1189. &p_ll2_info->tx_queue.tx_sb_index,
  1190. &p_ll2_info->tx_queue.p_fw_cons);
  1191. p_ll2_info->tx_queue.b_cb_registred = true;
  1192. }
  1193. *data->p_connection_handle = i;
  1194. return rc;
  1195. q_allocate_fail:
  1196. qed_ll2_release_connection(p_hwfn, i);
  1197. return -ENOMEM;
  1198. }
  1199. static int qed_ll2_establish_connection_rx(struct qed_hwfn *p_hwfn,
  1200. struct qed_ll2_info *p_ll2_conn)
  1201. {
  1202. enum qed_ll2_error_handle error_input;
  1203. enum core_error_handle error_mode;
  1204. u8 action_on_error = 0;
  1205. if (!QED_LL2_RX_REGISTERED(p_ll2_conn))
  1206. return 0;
  1207. DIRECT_REG_WR(p_ll2_conn->rx_queue.set_prod_addr, 0x0);
  1208. error_input = p_ll2_conn->input.ai_err_packet_too_big;
  1209. error_mode = qed_ll2_get_error_choice(error_input);
  1210. SET_FIELD(action_on_error,
  1211. CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG, error_mode);
  1212. error_input = p_ll2_conn->input.ai_err_no_buf;
  1213. error_mode = qed_ll2_get_error_choice(error_input);
  1214. SET_FIELD(action_on_error, CORE_RX_ACTION_ON_ERROR_NO_BUFF, error_mode);
  1215. return qed_sp_ll2_rx_queue_start(p_hwfn, p_ll2_conn, action_on_error);
  1216. }
  1217. static void
  1218. qed_ll2_establish_connection_ooo(struct qed_hwfn *p_hwfn,
  1219. struct qed_ll2_info *p_ll2_conn)
  1220. {
  1221. if (p_ll2_conn->input.conn_type != QED_LL2_TYPE_OOO)
  1222. return;
  1223. qed_ooo_release_all_isles(p_hwfn, p_hwfn->p_ooo_info);
  1224. qed_ooo_submit_rx_buffers(p_hwfn, p_ll2_conn);
  1225. }
  1226. int qed_ll2_establish_connection(void *cxt, u8 connection_handle)
  1227. {
  1228. struct qed_hwfn *p_hwfn = cxt;
  1229. struct qed_ll2_info *p_ll2_conn;
  1230. struct qed_ll2_tx_packet *p_pkt;
  1231. struct qed_ll2_rx_queue *p_rx;
  1232. struct qed_ll2_tx_queue *p_tx;
  1233. struct qed_ptt *p_ptt;
  1234. int rc = -EINVAL;
  1235. u32 i, capacity;
  1236. u32 desc_size;
  1237. u8 qid;
  1238. p_ptt = qed_ptt_acquire(p_hwfn);
  1239. if (!p_ptt)
  1240. return -EAGAIN;
  1241. p_ll2_conn = qed_ll2_handle_sanity_lock(p_hwfn, connection_handle);
  1242. if (!p_ll2_conn) {
  1243. rc = -EINVAL;
  1244. goto out;
  1245. }
  1246. p_rx = &p_ll2_conn->rx_queue;
  1247. p_tx = &p_ll2_conn->tx_queue;
  1248. qed_chain_reset(&p_rx->rxq_chain);
  1249. qed_chain_reset(&p_rx->rcq_chain);
  1250. INIT_LIST_HEAD(&p_rx->active_descq);
  1251. INIT_LIST_HEAD(&p_rx->free_descq);
  1252. INIT_LIST_HEAD(&p_rx->posting_descq);
  1253. spin_lock_init(&p_rx->lock);
  1254. capacity = qed_chain_get_capacity(&p_rx->rxq_chain);
  1255. for (i = 0; i < capacity; i++)
  1256. list_add_tail(&p_rx->descq_array[i].list_entry,
  1257. &p_rx->free_descq);
  1258. *p_rx->p_fw_cons = 0;
  1259. qed_chain_reset(&p_tx->txq_chain);
  1260. INIT_LIST_HEAD(&p_tx->active_descq);
  1261. INIT_LIST_HEAD(&p_tx->free_descq);
  1262. INIT_LIST_HEAD(&p_tx->sending_descq);
  1263. spin_lock_init(&p_tx->lock);
  1264. capacity = qed_chain_get_capacity(&p_tx->txq_chain);
  1265. /* First element is part of the packet, rest are flexibly added */
  1266. desc_size = (sizeof(*p_pkt) +
  1267. (p_ll2_conn->input.tx_max_bds_per_packet - 1) *
  1268. sizeof(p_pkt->bds_set));
  1269. for (i = 0; i < capacity; i++) {
  1270. p_pkt = p_tx->descq_mem + desc_size * i;
  1271. list_add_tail(&p_pkt->list_entry, &p_tx->free_descq);
  1272. }
  1273. p_tx->cur_completing_bd_idx = 0;
  1274. p_tx->bds_idx = 0;
  1275. p_tx->b_completing_packet = false;
  1276. p_tx->cur_send_packet = NULL;
  1277. p_tx->cur_send_frag_num = 0;
  1278. p_tx->cur_completing_frag_num = 0;
  1279. *p_tx->p_fw_cons = 0;
  1280. rc = qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_CORE, &p_ll2_conn->cid);
  1281. if (rc)
  1282. goto out;
  1283. qid = p_hwfn->hw_info.resc_start[QED_LL2_QUEUE] + connection_handle;
  1284. p_ll2_conn->queue_id = qid;
  1285. p_ll2_conn->tx_stats_id = qid;
  1286. p_rx->set_prod_addr = (u8 __iomem *)p_hwfn->regview +
  1287. GTT_BAR0_MAP_REG_TSDM_RAM +
  1288. TSTORM_LL2_RX_PRODS_OFFSET(qid);
  1289. p_tx->doorbell_addr = (u8 __iomem *)p_hwfn->doorbells +
  1290. qed_db_addr(p_ll2_conn->cid,
  1291. DQ_DEMS_LEGACY);
  1292. rc = qed_ll2_establish_connection_rx(p_hwfn, p_ll2_conn);
  1293. if (rc)
  1294. goto out;
  1295. rc = qed_sp_ll2_tx_queue_start(p_hwfn, p_ll2_conn);
  1296. if (rc)
  1297. goto out;
  1298. if (!QED_IS_RDMA_PERSONALITY(p_hwfn))
  1299. qed_wr(p_hwfn, p_ptt, PRS_REG_USE_LIGHT_L2, 1);
  1300. qed_ll2_establish_connection_ooo(p_hwfn, p_ll2_conn);
  1301. if (p_ll2_conn->input.conn_type == QED_LL2_TYPE_FCOE) {
  1302. if (!test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits))
  1303. qed_llh_add_protocol_filter(p_hwfn, p_ptt,
  1304. ETH_P_FCOE, 0,
  1305. QED_LLH_FILTER_ETHERTYPE);
  1306. qed_llh_add_protocol_filter(p_hwfn, p_ptt,
  1307. ETH_P_FIP, 0,
  1308. QED_LLH_FILTER_ETHERTYPE);
  1309. }
  1310. out:
  1311. qed_ptt_release(p_hwfn, p_ptt);
  1312. return rc;
  1313. }
  1314. static void qed_ll2_post_rx_buffer_notify_fw(struct qed_hwfn *p_hwfn,
  1315. struct qed_ll2_rx_queue *p_rx,
  1316. struct qed_ll2_rx_packet *p_curp)
  1317. {
  1318. struct qed_ll2_rx_packet *p_posting_packet = NULL;
  1319. struct core_ll2_rx_prod rx_prod = { 0, 0, 0 };
  1320. bool b_notify_fw = false;
  1321. u16 bd_prod, cq_prod;
  1322. /* This handles the flushing of already posted buffers */
  1323. while (!list_empty(&p_rx->posting_descq)) {
  1324. p_posting_packet = list_first_entry(&p_rx->posting_descq,
  1325. struct qed_ll2_rx_packet,
  1326. list_entry);
  1327. list_move_tail(&p_posting_packet->list_entry,
  1328. &p_rx->active_descq);
  1329. b_notify_fw = true;
  1330. }
  1331. /* This handles the supplied packet [if there is one] */
  1332. if (p_curp) {
  1333. list_add_tail(&p_curp->list_entry, &p_rx->active_descq);
  1334. b_notify_fw = true;
  1335. }
  1336. if (!b_notify_fw)
  1337. return;
  1338. bd_prod = qed_chain_get_prod_idx(&p_rx->rxq_chain);
  1339. cq_prod = qed_chain_get_prod_idx(&p_rx->rcq_chain);
  1340. rx_prod.bd_prod = cpu_to_le16(bd_prod);
  1341. rx_prod.cqe_prod = cpu_to_le16(cq_prod);
  1342. DIRECT_REG_WR(p_rx->set_prod_addr, *((u32 *)&rx_prod));
  1343. }
  1344. int qed_ll2_post_rx_buffer(void *cxt,
  1345. u8 connection_handle,
  1346. dma_addr_t addr,
  1347. u16 buf_len, void *cookie, u8 notify_fw)
  1348. {
  1349. struct qed_hwfn *p_hwfn = cxt;
  1350. struct core_rx_bd_with_buff_len *p_curb = NULL;
  1351. struct qed_ll2_rx_packet *p_curp = NULL;
  1352. struct qed_ll2_info *p_ll2_conn;
  1353. struct qed_ll2_rx_queue *p_rx;
  1354. unsigned long flags;
  1355. void *p_data;
  1356. int rc = 0;
  1357. p_ll2_conn = qed_ll2_handle_sanity(p_hwfn, connection_handle);
  1358. if (!p_ll2_conn)
  1359. return -EINVAL;
  1360. p_rx = &p_ll2_conn->rx_queue;
  1361. spin_lock_irqsave(&p_rx->lock, flags);
  1362. if (!list_empty(&p_rx->free_descq))
  1363. p_curp = list_first_entry(&p_rx->free_descq,
  1364. struct qed_ll2_rx_packet, list_entry);
  1365. if (p_curp) {
  1366. if (qed_chain_get_elem_left(&p_rx->rxq_chain) &&
  1367. qed_chain_get_elem_left(&p_rx->rcq_chain)) {
  1368. p_data = qed_chain_produce(&p_rx->rxq_chain);
  1369. p_curb = (struct core_rx_bd_with_buff_len *)p_data;
  1370. qed_chain_produce(&p_rx->rcq_chain);
  1371. }
  1372. }
  1373. /* If we're lacking entires, let's try to flush buffers to FW */
  1374. if (!p_curp || !p_curb) {
  1375. rc = -EBUSY;
  1376. p_curp = NULL;
  1377. goto out_notify;
  1378. }
  1379. /* We have an Rx packet we can fill */
  1380. DMA_REGPAIR_LE(p_curb->addr, addr);
  1381. p_curb->buff_length = cpu_to_le16(buf_len);
  1382. p_curp->rx_buf_addr = addr;
  1383. p_curp->cookie = cookie;
  1384. p_curp->rxq_bd = p_curb;
  1385. p_curp->buf_length = buf_len;
  1386. list_del(&p_curp->list_entry);
  1387. /* Check if we only want to enqueue this packet without informing FW */
  1388. if (!notify_fw) {
  1389. list_add_tail(&p_curp->list_entry, &p_rx->posting_descq);
  1390. goto out;
  1391. }
  1392. out_notify:
  1393. qed_ll2_post_rx_buffer_notify_fw(p_hwfn, p_rx, p_curp);
  1394. out:
  1395. spin_unlock_irqrestore(&p_rx->lock, flags);
  1396. return rc;
  1397. }
  1398. static void qed_ll2_prepare_tx_packet_set(struct qed_hwfn *p_hwfn,
  1399. struct qed_ll2_tx_queue *p_tx,
  1400. struct qed_ll2_tx_packet *p_curp,
  1401. struct qed_ll2_tx_pkt_info *pkt,
  1402. u8 notify_fw)
  1403. {
  1404. list_del(&p_curp->list_entry);
  1405. p_curp->cookie = pkt->cookie;
  1406. p_curp->bd_used = pkt->num_of_bds;
  1407. p_curp->notify_fw = notify_fw;
  1408. p_tx->cur_send_packet = p_curp;
  1409. p_tx->cur_send_frag_num = 0;
  1410. p_curp->bds_set[p_tx->cur_send_frag_num].tx_frag = pkt->first_frag;
  1411. p_curp->bds_set[p_tx->cur_send_frag_num].frag_len = pkt->first_frag_len;
  1412. p_tx->cur_send_frag_num++;
  1413. }
  1414. static void
  1415. qed_ll2_prepare_tx_packet_set_bd(struct qed_hwfn *p_hwfn,
  1416. struct qed_ll2_info *p_ll2,
  1417. struct qed_ll2_tx_packet *p_curp,
  1418. struct qed_ll2_tx_pkt_info *pkt)
  1419. {
  1420. struct qed_chain *p_tx_chain = &p_ll2->tx_queue.txq_chain;
  1421. u16 prod_idx = qed_chain_get_prod_idx(p_tx_chain);
  1422. struct core_tx_bd *start_bd = NULL;
  1423. enum core_roce_flavor_type roce_flavor;
  1424. enum core_tx_dest tx_dest;
  1425. u16 bd_data = 0, frag_idx;
  1426. roce_flavor = (pkt->qed_roce_flavor == QED_LL2_ROCE) ? CORE_ROCE
  1427. : CORE_RROCE;
  1428. switch (pkt->tx_dest) {
  1429. case QED_LL2_TX_DEST_NW:
  1430. tx_dest = CORE_TX_DEST_NW;
  1431. break;
  1432. case QED_LL2_TX_DEST_LB:
  1433. tx_dest = CORE_TX_DEST_LB;
  1434. break;
  1435. case QED_LL2_TX_DEST_DROP:
  1436. tx_dest = CORE_TX_DEST_DROP;
  1437. break;
  1438. default:
  1439. tx_dest = CORE_TX_DEST_LB;
  1440. break;
  1441. }
  1442. start_bd = (struct core_tx_bd *)qed_chain_produce(p_tx_chain);
  1443. if (QED_IS_IWARP_PERSONALITY(p_hwfn) &&
  1444. p_ll2->input.conn_type == QED_LL2_TYPE_OOO) {
  1445. start_bd->nw_vlan_or_lb_echo =
  1446. cpu_to_le16(IWARP_LL2_IN_ORDER_TX_QUEUE);
  1447. } else {
  1448. start_bd->nw_vlan_or_lb_echo = cpu_to_le16(pkt->vlan);
  1449. if (test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits) &&
  1450. p_ll2->input.conn_type == QED_LL2_TYPE_FCOE)
  1451. pkt->remove_stag = true;
  1452. }
  1453. SET_FIELD(start_bd->bitfield1, CORE_TX_BD_L4_HDR_OFFSET_W,
  1454. cpu_to_le16(pkt->l4_hdr_offset_w));
  1455. SET_FIELD(start_bd->bitfield1, CORE_TX_BD_TX_DST, tx_dest);
  1456. bd_data |= pkt->bd_flags;
  1457. SET_FIELD(bd_data, CORE_TX_BD_DATA_START_BD, 0x1);
  1458. SET_FIELD(bd_data, CORE_TX_BD_DATA_NBDS, pkt->num_of_bds);
  1459. SET_FIELD(bd_data, CORE_TX_BD_DATA_ROCE_FLAV, roce_flavor);
  1460. SET_FIELD(bd_data, CORE_TX_BD_DATA_IP_CSUM, !!(pkt->enable_ip_cksum));
  1461. SET_FIELD(bd_data, CORE_TX_BD_DATA_L4_CSUM, !!(pkt->enable_l4_cksum));
  1462. SET_FIELD(bd_data, CORE_TX_BD_DATA_IP_LEN, !!(pkt->calc_ip_len));
  1463. SET_FIELD(bd_data, CORE_TX_BD_DATA_DISABLE_STAG_INSERTION,
  1464. !!(pkt->remove_stag));
  1465. start_bd->bd_data.as_bitfield = cpu_to_le16(bd_data);
  1466. DMA_REGPAIR_LE(start_bd->addr, pkt->first_frag);
  1467. start_bd->nbytes = cpu_to_le16(pkt->first_frag_len);
  1468. DP_VERBOSE(p_hwfn,
  1469. (NETIF_MSG_TX_QUEUED | QED_MSG_LL2),
  1470. "LL2 [q 0x%02x cid 0x%08x type 0x%08x] Tx Producer at [0x%04x] - set with a %04x bytes %02x BDs buffer at %08x:%08x\n",
  1471. p_ll2->queue_id,
  1472. p_ll2->cid,
  1473. p_ll2->input.conn_type,
  1474. prod_idx,
  1475. pkt->first_frag_len,
  1476. pkt->num_of_bds,
  1477. le32_to_cpu(start_bd->addr.hi),
  1478. le32_to_cpu(start_bd->addr.lo));
  1479. if (p_ll2->tx_queue.cur_send_frag_num == pkt->num_of_bds)
  1480. return;
  1481. /* Need to provide the packet with additional BDs for frags */
  1482. for (frag_idx = p_ll2->tx_queue.cur_send_frag_num;
  1483. frag_idx < pkt->num_of_bds; frag_idx++) {
  1484. struct core_tx_bd **p_bd = &p_curp->bds_set[frag_idx].txq_bd;
  1485. *p_bd = (struct core_tx_bd *)qed_chain_produce(p_tx_chain);
  1486. (*p_bd)->bd_data.as_bitfield = 0;
  1487. (*p_bd)->bitfield1 = 0;
  1488. p_curp->bds_set[frag_idx].tx_frag = 0;
  1489. p_curp->bds_set[frag_idx].frag_len = 0;
  1490. }
  1491. }
  1492. /* This should be called while the Txq spinlock is being held */
  1493. static void qed_ll2_tx_packet_notify(struct qed_hwfn *p_hwfn,
  1494. struct qed_ll2_info *p_ll2_conn)
  1495. {
  1496. bool b_notify = p_ll2_conn->tx_queue.cur_send_packet->notify_fw;
  1497. struct qed_ll2_tx_queue *p_tx = &p_ll2_conn->tx_queue;
  1498. struct qed_ll2_tx_packet *p_pkt = NULL;
  1499. struct core_db_data db_msg = { 0, 0, 0 };
  1500. u16 bd_prod;
  1501. /* If there are missing BDs, don't do anything now */
  1502. if (p_ll2_conn->tx_queue.cur_send_frag_num !=
  1503. p_ll2_conn->tx_queue.cur_send_packet->bd_used)
  1504. return;
  1505. /* Push the current packet to the list and clean after it */
  1506. list_add_tail(&p_ll2_conn->tx_queue.cur_send_packet->list_entry,
  1507. &p_ll2_conn->tx_queue.sending_descq);
  1508. p_ll2_conn->tx_queue.cur_send_packet = NULL;
  1509. p_ll2_conn->tx_queue.cur_send_frag_num = 0;
  1510. /* Notify FW of packet only if requested to */
  1511. if (!b_notify)
  1512. return;
  1513. bd_prod = qed_chain_get_prod_idx(&p_ll2_conn->tx_queue.txq_chain);
  1514. while (!list_empty(&p_tx->sending_descq)) {
  1515. p_pkt = list_first_entry(&p_tx->sending_descq,
  1516. struct qed_ll2_tx_packet, list_entry);
  1517. if (!p_pkt)
  1518. break;
  1519. list_move_tail(&p_pkt->list_entry, &p_tx->active_descq);
  1520. }
  1521. SET_FIELD(db_msg.params, CORE_DB_DATA_DEST, DB_DEST_XCM);
  1522. SET_FIELD(db_msg.params, CORE_DB_DATA_AGG_CMD, DB_AGG_CMD_SET);
  1523. SET_FIELD(db_msg.params, CORE_DB_DATA_AGG_VAL_SEL,
  1524. DQ_XCM_CORE_TX_BD_PROD_CMD);
  1525. db_msg.agg_flags = DQ_XCM_CORE_DQ_CF_CMD;
  1526. db_msg.spq_prod = cpu_to_le16(bd_prod);
  1527. /* Make sure the BDs data is updated before ringing the doorbell */
  1528. wmb();
  1529. DIRECT_REG_WR(p_tx->doorbell_addr, *((u32 *)&db_msg));
  1530. DP_VERBOSE(p_hwfn,
  1531. (NETIF_MSG_TX_QUEUED | QED_MSG_LL2),
  1532. "LL2 [q 0x%02x cid 0x%08x type 0x%08x] Doorbelled [producer 0x%04x]\n",
  1533. p_ll2_conn->queue_id,
  1534. p_ll2_conn->cid,
  1535. p_ll2_conn->input.conn_type, db_msg.spq_prod);
  1536. }
  1537. int qed_ll2_prepare_tx_packet(void *cxt,
  1538. u8 connection_handle,
  1539. struct qed_ll2_tx_pkt_info *pkt,
  1540. bool notify_fw)
  1541. {
  1542. struct qed_hwfn *p_hwfn = cxt;
  1543. struct qed_ll2_tx_packet *p_curp = NULL;
  1544. struct qed_ll2_info *p_ll2_conn = NULL;
  1545. struct qed_ll2_tx_queue *p_tx;
  1546. struct qed_chain *p_tx_chain;
  1547. unsigned long flags;
  1548. int rc = 0;
  1549. p_ll2_conn = qed_ll2_handle_sanity(p_hwfn, connection_handle);
  1550. if (!p_ll2_conn)
  1551. return -EINVAL;
  1552. p_tx = &p_ll2_conn->tx_queue;
  1553. p_tx_chain = &p_tx->txq_chain;
  1554. if (pkt->num_of_bds > p_ll2_conn->input.tx_max_bds_per_packet)
  1555. return -EIO;
  1556. spin_lock_irqsave(&p_tx->lock, flags);
  1557. if (p_tx->cur_send_packet) {
  1558. rc = -EEXIST;
  1559. goto out;
  1560. }
  1561. /* Get entry, but only if we have tx elements for it */
  1562. if (!list_empty(&p_tx->free_descq))
  1563. p_curp = list_first_entry(&p_tx->free_descq,
  1564. struct qed_ll2_tx_packet, list_entry);
  1565. if (p_curp && qed_chain_get_elem_left(p_tx_chain) < pkt->num_of_bds)
  1566. p_curp = NULL;
  1567. if (!p_curp) {
  1568. rc = -EBUSY;
  1569. goto out;
  1570. }
  1571. /* Prepare packet and BD, and perhaps send a doorbell to FW */
  1572. qed_ll2_prepare_tx_packet_set(p_hwfn, p_tx, p_curp, pkt, notify_fw);
  1573. qed_ll2_prepare_tx_packet_set_bd(p_hwfn, p_ll2_conn, p_curp, pkt);
  1574. qed_ll2_tx_packet_notify(p_hwfn, p_ll2_conn);
  1575. out:
  1576. spin_unlock_irqrestore(&p_tx->lock, flags);
  1577. return rc;
  1578. }
  1579. int qed_ll2_set_fragment_of_tx_packet(void *cxt,
  1580. u8 connection_handle,
  1581. dma_addr_t addr, u16 nbytes)
  1582. {
  1583. struct qed_ll2_tx_packet *p_cur_send_packet = NULL;
  1584. struct qed_hwfn *p_hwfn = cxt;
  1585. struct qed_ll2_info *p_ll2_conn = NULL;
  1586. u16 cur_send_frag_num = 0;
  1587. struct core_tx_bd *p_bd;
  1588. unsigned long flags;
  1589. p_ll2_conn = qed_ll2_handle_sanity(p_hwfn, connection_handle);
  1590. if (!p_ll2_conn)
  1591. return -EINVAL;
  1592. if (!p_ll2_conn->tx_queue.cur_send_packet)
  1593. return -EINVAL;
  1594. p_cur_send_packet = p_ll2_conn->tx_queue.cur_send_packet;
  1595. cur_send_frag_num = p_ll2_conn->tx_queue.cur_send_frag_num;
  1596. if (cur_send_frag_num >= p_cur_send_packet->bd_used)
  1597. return -EINVAL;
  1598. /* Fill the BD information, and possibly notify FW */
  1599. p_bd = p_cur_send_packet->bds_set[cur_send_frag_num].txq_bd;
  1600. DMA_REGPAIR_LE(p_bd->addr, addr);
  1601. p_bd->nbytes = cpu_to_le16(nbytes);
  1602. p_cur_send_packet->bds_set[cur_send_frag_num].tx_frag = addr;
  1603. p_cur_send_packet->bds_set[cur_send_frag_num].frag_len = nbytes;
  1604. p_ll2_conn->tx_queue.cur_send_frag_num++;
  1605. spin_lock_irqsave(&p_ll2_conn->tx_queue.lock, flags);
  1606. qed_ll2_tx_packet_notify(p_hwfn, p_ll2_conn);
  1607. spin_unlock_irqrestore(&p_ll2_conn->tx_queue.lock, flags);
  1608. return 0;
  1609. }
  1610. int qed_ll2_terminate_connection(void *cxt, u8 connection_handle)
  1611. {
  1612. struct qed_hwfn *p_hwfn = cxt;
  1613. struct qed_ll2_info *p_ll2_conn = NULL;
  1614. int rc = -EINVAL;
  1615. struct qed_ptt *p_ptt;
  1616. p_ptt = qed_ptt_acquire(p_hwfn);
  1617. if (!p_ptt)
  1618. return -EAGAIN;
  1619. p_ll2_conn = qed_ll2_handle_sanity_lock(p_hwfn, connection_handle);
  1620. if (!p_ll2_conn) {
  1621. rc = -EINVAL;
  1622. goto out;
  1623. }
  1624. /* Stop Tx & Rx of connection, if needed */
  1625. if (QED_LL2_TX_REGISTERED(p_ll2_conn)) {
  1626. p_ll2_conn->tx_queue.b_cb_registred = false;
  1627. smp_wmb(); /* Make sure this is seen by ll2_lb_rxq_completion */
  1628. rc = qed_sp_ll2_tx_queue_stop(p_hwfn, p_ll2_conn);
  1629. if (rc)
  1630. goto out;
  1631. qed_ll2_txq_flush(p_hwfn, connection_handle);
  1632. qed_int_unregister_cb(p_hwfn, p_ll2_conn->tx_queue.tx_sb_index);
  1633. }
  1634. if (QED_LL2_RX_REGISTERED(p_ll2_conn)) {
  1635. p_ll2_conn->rx_queue.b_cb_registred = false;
  1636. smp_wmb(); /* Make sure this is seen by ll2_lb_rxq_completion */
  1637. rc = qed_sp_ll2_rx_queue_stop(p_hwfn, p_ll2_conn);
  1638. if (rc)
  1639. goto out;
  1640. qed_ll2_rxq_flush(p_hwfn, connection_handle);
  1641. qed_int_unregister_cb(p_hwfn, p_ll2_conn->rx_queue.rx_sb_index);
  1642. }
  1643. if (p_ll2_conn->input.conn_type == QED_LL2_TYPE_OOO)
  1644. qed_ooo_release_all_isles(p_hwfn, p_hwfn->p_ooo_info);
  1645. if (p_ll2_conn->input.conn_type == QED_LL2_TYPE_FCOE) {
  1646. if (!test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits))
  1647. qed_llh_remove_protocol_filter(p_hwfn, p_ptt,
  1648. ETH_P_FCOE, 0,
  1649. QED_LLH_FILTER_ETHERTYPE);
  1650. qed_llh_remove_protocol_filter(p_hwfn, p_ptt,
  1651. ETH_P_FIP, 0,
  1652. QED_LLH_FILTER_ETHERTYPE);
  1653. }
  1654. out:
  1655. qed_ptt_release(p_hwfn, p_ptt);
  1656. return rc;
  1657. }
  1658. static void qed_ll2_release_connection_ooo(struct qed_hwfn *p_hwfn,
  1659. struct qed_ll2_info *p_ll2_conn)
  1660. {
  1661. struct qed_ooo_buffer *p_buffer;
  1662. if (p_ll2_conn->input.conn_type != QED_LL2_TYPE_OOO)
  1663. return;
  1664. qed_ooo_release_all_isles(p_hwfn, p_hwfn->p_ooo_info);
  1665. while ((p_buffer = qed_ooo_get_free_buffer(p_hwfn,
  1666. p_hwfn->p_ooo_info))) {
  1667. dma_free_coherent(&p_hwfn->cdev->pdev->dev,
  1668. p_buffer->rx_buffer_size,
  1669. p_buffer->rx_buffer_virt_addr,
  1670. p_buffer->rx_buffer_phys_addr);
  1671. kfree(p_buffer);
  1672. }
  1673. }
  1674. void qed_ll2_release_connection(void *cxt, u8 connection_handle)
  1675. {
  1676. struct qed_hwfn *p_hwfn = cxt;
  1677. struct qed_ll2_info *p_ll2_conn = NULL;
  1678. p_ll2_conn = qed_ll2_handle_sanity(p_hwfn, connection_handle);
  1679. if (!p_ll2_conn)
  1680. return;
  1681. kfree(p_ll2_conn->tx_queue.descq_mem);
  1682. qed_chain_free(p_hwfn->cdev, &p_ll2_conn->tx_queue.txq_chain);
  1683. kfree(p_ll2_conn->rx_queue.descq_array);
  1684. qed_chain_free(p_hwfn->cdev, &p_ll2_conn->rx_queue.rxq_chain);
  1685. qed_chain_free(p_hwfn->cdev, &p_ll2_conn->rx_queue.rcq_chain);
  1686. qed_cxt_release_cid(p_hwfn, p_ll2_conn->cid);
  1687. qed_ll2_release_connection_ooo(p_hwfn, p_ll2_conn);
  1688. mutex_lock(&p_ll2_conn->mutex);
  1689. p_ll2_conn->b_active = false;
  1690. mutex_unlock(&p_ll2_conn->mutex);
  1691. }
  1692. int qed_ll2_alloc(struct qed_hwfn *p_hwfn)
  1693. {
  1694. struct qed_ll2_info *p_ll2_connections;
  1695. u8 i;
  1696. /* Allocate LL2's set struct */
  1697. p_ll2_connections = kcalloc(QED_MAX_NUM_OF_LL2_CONNECTIONS,
  1698. sizeof(struct qed_ll2_info), GFP_KERNEL);
  1699. if (!p_ll2_connections) {
  1700. DP_NOTICE(p_hwfn, "Failed to allocate `struct qed_ll2'\n");
  1701. return -ENOMEM;
  1702. }
  1703. for (i = 0; i < QED_MAX_NUM_OF_LL2_CONNECTIONS; i++)
  1704. p_ll2_connections[i].my_id = i;
  1705. p_hwfn->p_ll2_info = p_ll2_connections;
  1706. return 0;
  1707. }
  1708. void qed_ll2_setup(struct qed_hwfn *p_hwfn)
  1709. {
  1710. int i;
  1711. for (i = 0; i < QED_MAX_NUM_OF_LL2_CONNECTIONS; i++)
  1712. mutex_init(&p_hwfn->p_ll2_info[i].mutex);
  1713. }
  1714. void qed_ll2_free(struct qed_hwfn *p_hwfn)
  1715. {
  1716. if (!p_hwfn->p_ll2_info)
  1717. return;
  1718. kfree(p_hwfn->p_ll2_info);
  1719. p_hwfn->p_ll2_info = NULL;
  1720. }
  1721. static void _qed_ll2_get_port_stats(struct qed_hwfn *p_hwfn,
  1722. struct qed_ptt *p_ptt,
  1723. struct qed_ll2_stats *p_stats)
  1724. {
  1725. struct core_ll2_port_stats port_stats;
  1726. memset(&port_stats, 0, sizeof(port_stats));
  1727. qed_memcpy_from(p_hwfn, p_ptt, &port_stats,
  1728. BAR0_MAP_REG_TSDM_RAM +
  1729. TSTORM_LL2_PORT_STAT_OFFSET(MFW_PORT(p_hwfn)),
  1730. sizeof(port_stats));
  1731. p_stats->gsi_invalid_hdr = HILO_64_REGPAIR(port_stats.gsi_invalid_hdr);
  1732. p_stats->gsi_invalid_pkt_length =
  1733. HILO_64_REGPAIR(port_stats.gsi_invalid_pkt_length);
  1734. p_stats->gsi_unsupported_pkt_typ =
  1735. HILO_64_REGPAIR(port_stats.gsi_unsupported_pkt_typ);
  1736. p_stats->gsi_crcchksm_error =
  1737. HILO_64_REGPAIR(port_stats.gsi_crcchksm_error);
  1738. }
  1739. static void _qed_ll2_get_tstats(struct qed_hwfn *p_hwfn,
  1740. struct qed_ptt *p_ptt,
  1741. struct qed_ll2_info *p_ll2_conn,
  1742. struct qed_ll2_stats *p_stats)
  1743. {
  1744. struct core_ll2_tstorm_per_queue_stat tstats;
  1745. u8 qid = p_ll2_conn->queue_id;
  1746. u32 tstats_addr;
  1747. memset(&tstats, 0, sizeof(tstats));
  1748. tstats_addr = BAR0_MAP_REG_TSDM_RAM +
  1749. CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(qid);
  1750. qed_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, sizeof(tstats));
  1751. p_stats->packet_too_big_discard =
  1752. HILO_64_REGPAIR(tstats.packet_too_big_discard);
  1753. p_stats->no_buff_discard = HILO_64_REGPAIR(tstats.no_buff_discard);
  1754. }
  1755. static void _qed_ll2_get_ustats(struct qed_hwfn *p_hwfn,
  1756. struct qed_ptt *p_ptt,
  1757. struct qed_ll2_info *p_ll2_conn,
  1758. struct qed_ll2_stats *p_stats)
  1759. {
  1760. struct core_ll2_ustorm_per_queue_stat ustats;
  1761. u8 qid = p_ll2_conn->queue_id;
  1762. u32 ustats_addr;
  1763. memset(&ustats, 0, sizeof(ustats));
  1764. ustats_addr = BAR0_MAP_REG_USDM_RAM +
  1765. CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(qid);
  1766. qed_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, sizeof(ustats));
  1767. p_stats->rcv_ucast_bytes = HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
  1768. p_stats->rcv_mcast_bytes = HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
  1769. p_stats->rcv_bcast_bytes = HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
  1770. p_stats->rcv_ucast_pkts = HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
  1771. p_stats->rcv_mcast_pkts = HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
  1772. p_stats->rcv_bcast_pkts = HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
  1773. }
  1774. static void _qed_ll2_get_pstats(struct qed_hwfn *p_hwfn,
  1775. struct qed_ptt *p_ptt,
  1776. struct qed_ll2_info *p_ll2_conn,
  1777. struct qed_ll2_stats *p_stats)
  1778. {
  1779. struct core_ll2_pstorm_per_queue_stat pstats;
  1780. u8 stats_id = p_ll2_conn->tx_stats_id;
  1781. u32 pstats_addr;
  1782. memset(&pstats, 0, sizeof(pstats));
  1783. pstats_addr = BAR0_MAP_REG_PSDM_RAM +
  1784. CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(stats_id);
  1785. qed_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, sizeof(pstats));
  1786. p_stats->sent_ucast_bytes = HILO_64_REGPAIR(pstats.sent_ucast_bytes);
  1787. p_stats->sent_mcast_bytes = HILO_64_REGPAIR(pstats.sent_mcast_bytes);
  1788. p_stats->sent_bcast_bytes = HILO_64_REGPAIR(pstats.sent_bcast_bytes);
  1789. p_stats->sent_ucast_pkts = HILO_64_REGPAIR(pstats.sent_ucast_pkts);
  1790. p_stats->sent_mcast_pkts = HILO_64_REGPAIR(pstats.sent_mcast_pkts);
  1791. p_stats->sent_bcast_pkts = HILO_64_REGPAIR(pstats.sent_bcast_pkts);
  1792. }
  1793. int qed_ll2_get_stats(void *cxt,
  1794. u8 connection_handle, struct qed_ll2_stats *p_stats)
  1795. {
  1796. struct qed_hwfn *p_hwfn = cxt;
  1797. struct qed_ll2_info *p_ll2_conn = NULL;
  1798. struct qed_ptt *p_ptt;
  1799. memset(p_stats, 0, sizeof(*p_stats));
  1800. if ((connection_handle >= QED_MAX_NUM_OF_LL2_CONNECTIONS) ||
  1801. !p_hwfn->p_ll2_info)
  1802. return -EINVAL;
  1803. p_ll2_conn = &p_hwfn->p_ll2_info[connection_handle];
  1804. p_ptt = qed_ptt_acquire(p_hwfn);
  1805. if (!p_ptt) {
  1806. DP_ERR(p_hwfn, "Failed to acquire ptt\n");
  1807. return -EINVAL;
  1808. }
  1809. if (p_ll2_conn->input.gsi_enable)
  1810. _qed_ll2_get_port_stats(p_hwfn, p_ptt, p_stats);
  1811. _qed_ll2_get_tstats(p_hwfn, p_ptt, p_ll2_conn, p_stats);
  1812. _qed_ll2_get_ustats(p_hwfn, p_ptt, p_ll2_conn, p_stats);
  1813. if (p_ll2_conn->tx_stats_en)
  1814. _qed_ll2_get_pstats(p_hwfn, p_ptt, p_ll2_conn, p_stats);
  1815. qed_ptt_release(p_hwfn, p_ptt);
  1816. return 0;
  1817. }
  1818. static void qed_ll2b_release_rx_packet(void *cxt,
  1819. u8 connection_handle,
  1820. void *cookie,
  1821. dma_addr_t rx_buf_addr,
  1822. bool b_last_packet)
  1823. {
  1824. struct qed_hwfn *p_hwfn = cxt;
  1825. qed_ll2_dealloc_buffer(p_hwfn->cdev, cookie);
  1826. }
  1827. static void qed_ll2_register_cb_ops(struct qed_dev *cdev,
  1828. const struct qed_ll2_cb_ops *ops,
  1829. void *cookie)
  1830. {
  1831. cdev->ll2->cbs = ops;
  1832. cdev->ll2->cb_cookie = cookie;
  1833. }
  1834. struct qed_ll2_cbs ll2_cbs = {
  1835. .rx_comp_cb = &qed_ll2b_complete_rx_packet,
  1836. .rx_release_cb = &qed_ll2b_release_rx_packet,
  1837. .tx_comp_cb = &qed_ll2b_complete_tx_packet,
  1838. .tx_release_cb = &qed_ll2b_complete_tx_packet,
  1839. };
  1840. static void qed_ll2_set_conn_data(struct qed_dev *cdev,
  1841. struct qed_ll2_acquire_data *data,
  1842. struct qed_ll2_params *params,
  1843. enum qed_ll2_conn_type conn_type,
  1844. u8 *handle, bool lb)
  1845. {
  1846. memset(data, 0, sizeof(*data));
  1847. data->input.conn_type = conn_type;
  1848. data->input.mtu = params->mtu;
  1849. data->input.rx_num_desc = QED_LL2_RX_SIZE;
  1850. data->input.rx_drop_ttl0_flg = params->drop_ttl0_packets;
  1851. data->input.rx_vlan_removal_en = params->rx_vlan_stripping;
  1852. data->input.tx_num_desc = QED_LL2_TX_SIZE;
  1853. data->p_connection_handle = handle;
  1854. data->cbs = &ll2_cbs;
  1855. ll2_cbs.cookie = QED_LEADING_HWFN(cdev);
  1856. if (lb) {
  1857. data->input.tx_tc = PKT_LB_TC;
  1858. data->input.tx_dest = QED_LL2_TX_DEST_LB;
  1859. } else {
  1860. data->input.tx_tc = 0;
  1861. data->input.tx_dest = QED_LL2_TX_DEST_NW;
  1862. }
  1863. }
  1864. static int qed_ll2_start_ooo(struct qed_dev *cdev,
  1865. struct qed_ll2_params *params)
  1866. {
  1867. struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
  1868. u8 *handle = &hwfn->pf_params.iscsi_pf_params.ll2_ooo_queue_id;
  1869. struct qed_ll2_acquire_data data;
  1870. int rc;
  1871. qed_ll2_set_conn_data(cdev, &data, params,
  1872. QED_LL2_TYPE_OOO, handle, true);
  1873. rc = qed_ll2_acquire_connection(hwfn, &data);
  1874. if (rc) {
  1875. DP_INFO(cdev, "Failed to acquire LL2 OOO connection\n");
  1876. goto out;
  1877. }
  1878. rc = qed_ll2_establish_connection(hwfn, *handle);
  1879. if (rc) {
  1880. DP_INFO(cdev, "Failed to establist LL2 OOO connection\n");
  1881. goto fail;
  1882. }
  1883. return 0;
  1884. fail:
  1885. qed_ll2_release_connection(hwfn, *handle);
  1886. out:
  1887. *handle = QED_LL2_UNUSED_HANDLE;
  1888. return rc;
  1889. }
  1890. static int qed_ll2_start(struct qed_dev *cdev, struct qed_ll2_params *params)
  1891. {
  1892. struct qed_ll2_buffer *buffer, *tmp_buffer;
  1893. enum qed_ll2_conn_type conn_type;
  1894. struct qed_ll2_acquire_data data;
  1895. struct qed_ptt *p_ptt;
  1896. int rc, i;
  1897. /* Initialize LL2 locks & lists */
  1898. INIT_LIST_HEAD(&cdev->ll2->list);
  1899. spin_lock_init(&cdev->ll2->lock);
  1900. cdev->ll2->rx_size = NET_SKB_PAD + ETH_HLEN +
  1901. L1_CACHE_BYTES + params->mtu;
  1902. /*Allocate memory for LL2 */
  1903. DP_INFO(cdev, "Allocating LL2 buffers of size %08x bytes\n",
  1904. cdev->ll2->rx_size);
  1905. for (i = 0; i < QED_LL2_RX_SIZE; i++) {
  1906. buffer = kzalloc(sizeof(*buffer), GFP_KERNEL);
  1907. if (!buffer) {
  1908. DP_INFO(cdev, "Failed to allocate LL2 buffers\n");
  1909. goto fail;
  1910. }
  1911. rc = qed_ll2_alloc_buffer(cdev, (u8 **)&buffer->data,
  1912. &buffer->phys_addr);
  1913. if (rc) {
  1914. kfree(buffer);
  1915. goto fail;
  1916. }
  1917. list_add_tail(&buffer->list, &cdev->ll2->list);
  1918. }
  1919. switch (QED_LEADING_HWFN(cdev)->hw_info.personality) {
  1920. case QED_PCI_FCOE:
  1921. conn_type = QED_LL2_TYPE_FCOE;
  1922. break;
  1923. case QED_PCI_ISCSI:
  1924. conn_type = QED_LL2_TYPE_ISCSI;
  1925. break;
  1926. case QED_PCI_ETH_ROCE:
  1927. conn_type = QED_LL2_TYPE_ROCE;
  1928. break;
  1929. default:
  1930. conn_type = QED_LL2_TYPE_TEST;
  1931. }
  1932. qed_ll2_set_conn_data(cdev, &data, params, conn_type,
  1933. &cdev->ll2->handle, false);
  1934. rc = qed_ll2_acquire_connection(QED_LEADING_HWFN(cdev), &data);
  1935. if (rc) {
  1936. DP_INFO(cdev, "Failed to acquire LL2 connection\n");
  1937. goto fail;
  1938. }
  1939. rc = qed_ll2_establish_connection(QED_LEADING_HWFN(cdev),
  1940. cdev->ll2->handle);
  1941. if (rc) {
  1942. DP_INFO(cdev, "Failed to establish LL2 connection\n");
  1943. goto release_fail;
  1944. }
  1945. /* Post all Rx buffers to FW */
  1946. spin_lock_bh(&cdev->ll2->lock);
  1947. list_for_each_entry_safe(buffer, tmp_buffer, &cdev->ll2->list, list) {
  1948. rc = qed_ll2_post_rx_buffer(QED_LEADING_HWFN(cdev),
  1949. cdev->ll2->handle,
  1950. buffer->phys_addr, 0, buffer, 1);
  1951. if (rc) {
  1952. DP_INFO(cdev,
  1953. "Failed to post an Rx buffer; Deleting it\n");
  1954. dma_unmap_single(&cdev->pdev->dev, buffer->phys_addr,
  1955. cdev->ll2->rx_size, DMA_FROM_DEVICE);
  1956. kfree(buffer->data);
  1957. list_del(&buffer->list);
  1958. kfree(buffer);
  1959. } else {
  1960. cdev->ll2->rx_cnt++;
  1961. }
  1962. }
  1963. spin_unlock_bh(&cdev->ll2->lock);
  1964. if (!cdev->ll2->rx_cnt) {
  1965. DP_INFO(cdev, "Failed passing even a single Rx buffer\n");
  1966. goto release_terminate;
  1967. }
  1968. if (!is_valid_ether_addr(params->ll2_mac_address)) {
  1969. DP_INFO(cdev, "Invalid Ethernet address\n");
  1970. goto release_terminate;
  1971. }
  1972. if (QED_LEADING_HWFN(cdev)->hw_info.personality == QED_PCI_ISCSI) {
  1973. DP_VERBOSE(cdev, QED_MSG_STORAGE, "Starting OOO LL2 queue\n");
  1974. rc = qed_ll2_start_ooo(cdev, params);
  1975. if (rc) {
  1976. DP_INFO(cdev,
  1977. "Failed to initialize the OOO LL2 queue\n");
  1978. goto release_terminate;
  1979. }
  1980. }
  1981. p_ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev));
  1982. if (!p_ptt) {
  1983. DP_INFO(cdev, "Failed to acquire PTT\n");
  1984. goto release_terminate;
  1985. }
  1986. rc = qed_llh_add_mac_filter(QED_LEADING_HWFN(cdev), p_ptt,
  1987. params->ll2_mac_address);
  1988. qed_ptt_release(QED_LEADING_HWFN(cdev), p_ptt);
  1989. if (rc) {
  1990. DP_ERR(cdev, "Failed to allocate LLH filter\n");
  1991. goto release_terminate_all;
  1992. }
  1993. ether_addr_copy(cdev->ll2_mac_address, params->ll2_mac_address);
  1994. return 0;
  1995. release_terminate_all:
  1996. release_terminate:
  1997. qed_ll2_terminate_connection(QED_LEADING_HWFN(cdev), cdev->ll2->handle);
  1998. release_fail:
  1999. qed_ll2_release_connection(QED_LEADING_HWFN(cdev), cdev->ll2->handle);
  2000. fail:
  2001. qed_ll2_kill_buffers(cdev);
  2002. cdev->ll2->handle = QED_LL2_UNUSED_HANDLE;
  2003. return -EINVAL;
  2004. }
  2005. static int qed_ll2_stop(struct qed_dev *cdev)
  2006. {
  2007. struct qed_ptt *p_ptt;
  2008. int rc;
  2009. if (cdev->ll2->handle == QED_LL2_UNUSED_HANDLE)
  2010. return 0;
  2011. p_ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev));
  2012. if (!p_ptt) {
  2013. DP_INFO(cdev, "Failed to acquire PTT\n");
  2014. goto fail;
  2015. }
  2016. qed_llh_remove_mac_filter(QED_LEADING_HWFN(cdev), p_ptt,
  2017. cdev->ll2_mac_address);
  2018. qed_ptt_release(QED_LEADING_HWFN(cdev), p_ptt);
  2019. eth_zero_addr(cdev->ll2_mac_address);
  2020. if (QED_LEADING_HWFN(cdev)->hw_info.personality == QED_PCI_ISCSI)
  2021. qed_ll2_stop_ooo(cdev);
  2022. rc = qed_ll2_terminate_connection(QED_LEADING_HWFN(cdev),
  2023. cdev->ll2->handle);
  2024. if (rc)
  2025. DP_INFO(cdev, "Failed to terminate LL2 connection\n");
  2026. qed_ll2_kill_buffers(cdev);
  2027. qed_ll2_release_connection(QED_LEADING_HWFN(cdev), cdev->ll2->handle);
  2028. cdev->ll2->handle = QED_LL2_UNUSED_HANDLE;
  2029. return rc;
  2030. fail:
  2031. return -EINVAL;
  2032. }
  2033. static int qed_ll2_start_xmit(struct qed_dev *cdev, struct sk_buff *skb,
  2034. unsigned long xmit_flags)
  2035. {
  2036. struct qed_ll2_tx_pkt_info pkt;
  2037. const skb_frag_t *frag;
  2038. int rc = -EINVAL, i;
  2039. dma_addr_t mapping;
  2040. u16 vlan = 0;
  2041. u8 flags = 0;
  2042. if (unlikely(skb->ip_summed != CHECKSUM_NONE)) {
  2043. DP_INFO(cdev, "Cannot transmit a checksummed packet\n");
  2044. return -EINVAL;
  2045. }
  2046. if (1 + skb_shinfo(skb)->nr_frags > CORE_LL2_TX_MAX_BDS_PER_PACKET) {
  2047. DP_ERR(cdev, "Cannot transmit a packet with %d fragments\n",
  2048. 1 + skb_shinfo(skb)->nr_frags);
  2049. return -EINVAL;
  2050. }
  2051. mapping = dma_map_single(&cdev->pdev->dev, skb->data,
  2052. skb->len, DMA_TO_DEVICE);
  2053. if (unlikely(dma_mapping_error(&cdev->pdev->dev, mapping))) {
  2054. DP_NOTICE(cdev, "SKB mapping failed\n");
  2055. return -EINVAL;
  2056. }
  2057. /* Request HW to calculate IP csum */
  2058. if (!((vlan_get_protocol(skb) == htons(ETH_P_IPV6)) &&
  2059. ipv6_hdr(skb)->nexthdr == NEXTHDR_IPV6))
  2060. flags |= BIT(CORE_TX_BD_DATA_IP_CSUM_SHIFT);
  2061. if (skb_vlan_tag_present(skb)) {
  2062. vlan = skb_vlan_tag_get(skb);
  2063. flags |= BIT(CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT);
  2064. }
  2065. memset(&pkt, 0, sizeof(pkt));
  2066. pkt.num_of_bds = 1 + skb_shinfo(skb)->nr_frags;
  2067. pkt.vlan = vlan;
  2068. pkt.bd_flags = flags;
  2069. pkt.tx_dest = QED_LL2_TX_DEST_NW;
  2070. pkt.first_frag = mapping;
  2071. pkt.first_frag_len = skb->len;
  2072. pkt.cookie = skb;
  2073. if (test_bit(QED_MF_UFP_SPECIFIC, &cdev->mf_bits) &&
  2074. test_bit(QED_LL2_XMIT_FLAGS_FIP_DISCOVERY, &xmit_flags))
  2075. pkt.remove_stag = true;
  2076. rc = qed_ll2_prepare_tx_packet(&cdev->hwfns[0], cdev->ll2->handle,
  2077. &pkt, 1);
  2078. if (rc)
  2079. goto err;
  2080. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  2081. frag = &skb_shinfo(skb)->frags[i];
  2082. mapping = skb_frag_dma_map(&cdev->pdev->dev, frag, 0,
  2083. skb_frag_size(frag), DMA_TO_DEVICE);
  2084. if (unlikely(dma_mapping_error(&cdev->pdev->dev, mapping))) {
  2085. DP_NOTICE(cdev,
  2086. "Unable to map frag - dropping packet\n");
  2087. goto err;
  2088. }
  2089. rc = qed_ll2_set_fragment_of_tx_packet(QED_LEADING_HWFN(cdev),
  2090. cdev->ll2->handle,
  2091. mapping,
  2092. skb_frag_size(frag));
  2093. /* if failed not much to do here, partial packet has been posted
  2094. * we can't free memory, will need to wait for completion.
  2095. */
  2096. if (rc)
  2097. goto err2;
  2098. }
  2099. return 0;
  2100. err:
  2101. dma_unmap_single(&cdev->pdev->dev, mapping, skb->len, DMA_TO_DEVICE);
  2102. err2:
  2103. return rc;
  2104. }
  2105. static int qed_ll2_stats(struct qed_dev *cdev, struct qed_ll2_stats *stats)
  2106. {
  2107. if (!cdev->ll2)
  2108. return -EINVAL;
  2109. return qed_ll2_get_stats(QED_LEADING_HWFN(cdev),
  2110. cdev->ll2->handle, stats);
  2111. }
  2112. const struct qed_ll2_ops qed_ll2_ops_pass = {
  2113. .start = &qed_ll2_start,
  2114. .stop = &qed_ll2_stop,
  2115. .start_xmit = &qed_ll2_start_xmit,
  2116. .register_cb_ops = &qed_ll2_register_cb_ops,
  2117. .get_stats = &qed_ll2_stats,
  2118. };
  2119. int qed_ll2_alloc_if(struct qed_dev *cdev)
  2120. {
  2121. cdev->ll2 = kzalloc(sizeof(*cdev->ll2), GFP_KERNEL);
  2122. return cdev->ll2 ? 0 : -ENOMEM;
  2123. }
  2124. void qed_ll2_dealloc_if(struct qed_dev *cdev)
  2125. {
  2126. kfree(cdev->ll2);
  2127. cdev->ll2 = NULL;
  2128. }