qed_l2.c 81 KB

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  1. /* QLogic qed NIC Driver
  2. * Copyright (c) 2015-2017 QLogic Corporation
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and /or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/types.h>
  33. #include <asm/byteorder.h>
  34. #include <asm/param.h>
  35. #include <linux/delay.h>
  36. #include <linux/dma-mapping.h>
  37. #include <linux/etherdevice.h>
  38. #include <linux/interrupt.h>
  39. #include <linux/kernel.h>
  40. #include <linux/module.h>
  41. #include <linux/pci.h>
  42. #include <linux/slab.h>
  43. #include <linux/stddef.h>
  44. #include <linux/string.h>
  45. #include <linux/workqueue.h>
  46. #include <linux/bitops.h>
  47. #include <linux/bug.h>
  48. #include <linux/vmalloc.h>
  49. #include "qed.h"
  50. #include <linux/qed/qed_chain.h>
  51. #include "qed_cxt.h"
  52. #include "qed_dev_api.h"
  53. #include <linux/qed/qed_eth_if.h>
  54. #include "qed_hsi.h"
  55. #include "qed_hw.h"
  56. #include "qed_int.h"
  57. #include "qed_l2.h"
  58. #include "qed_mcp.h"
  59. #include "qed_reg_addr.h"
  60. #include "qed_sp.h"
  61. #include "qed_sriov.h"
  62. #define QED_MAX_SGES_NUM 16
  63. #define CRC32_POLY 0x1edc6f41
  64. struct qed_l2_info {
  65. u32 queues;
  66. unsigned long **pp_qid_usage;
  67. /* The lock is meant to synchronize access to the qid usage */
  68. struct mutex lock;
  69. };
  70. int qed_l2_alloc(struct qed_hwfn *p_hwfn)
  71. {
  72. struct qed_l2_info *p_l2_info;
  73. unsigned long **pp_qids;
  74. u32 i;
  75. if (!QED_IS_L2_PERSONALITY(p_hwfn))
  76. return 0;
  77. p_l2_info = kzalloc(sizeof(*p_l2_info), GFP_KERNEL);
  78. if (!p_l2_info)
  79. return -ENOMEM;
  80. p_hwfn->p_l2_info = p_l2_info;
  81. if (IS_PF(p_hwfn->cdev)) {
  82. p_l2_info->queues = RESC_NUM(p_hwfn, QED_L2_QUEUE);
  83. } else {
  84. u8 rx = 0, tx = 0;
  85. qed_vf_get_num_rxqs(p_hwfn, &rx);
  86. qed_vf_get_num_txqs(p_hwfn, &tx);
  87. p_l2_info->queues = max_t(u8, rx, tx);
  88. }
  89. pp_qids = kcalloc(p_l2_info->queues, sizeof(unsigned long *),
  90. GFP_KERNEL);
  91. if (!pp_qids)
  92. return -ENOMEM;
  93. p_l2_info->pp_qid_usage = pp_qids;
  94. for (i = 0; i < p_l2_info->queues; i++) {
  95. pp_qids[i] = kzalloc(MAX_QUEUES_PER_QZONE / 8, GFP_KERNEL);
  96. if (!pp_qids[i])
  97. return -ENOMEM;
  98. }
  99. return 0;
  100. }
  101. void qed_l2_setup(struct qed_hwfn *p_hwfn)
  102. {
  103. if (!QED_IS_L2_PERSONALITY(p_hwfn))
  104. return;
  105. mutex_init(&p_hwfn->p_l2_info->lock);
  106. }
  107. void qed_l2_free(struct qed_hwfn *p_hwfn)
  108. {
  109. u32 i;
  110. if (!QED_IS_L2_PERSONALITY(p_hwfn))
  111. return;
  112. if (!p_hwfn->p_l2_info)
  113. return;
  114. if (!p_hwfn->p_l2_info->pp_qid_usage)
  115. goto out_l2_info;
  116. /* Free until hit first uninitialized entry */
  117. for (i = 0; i < p_hwfn->p_l2_info->queues; i++) {
  118. if (!p_hwfn->p_l2_info->pp_qid_usage[i])
  119. break;
  120. kfree(p_hwfn->p_l2_info->pp_qid_usage[i]);
  121. }
  122. kfree(p_hwfn->p_l2_info->pp_qid_usage);
  123. out_l2_info:
  124. kfree(p_hwfn->p_l2_info);
  125. p_hwfn->p_l2_info = NULL;
  126. }
  127. static bool qed_eth_queue_qid_usage_add(struct qed_hwfn *p_hwfn,
  128. struct qed_queue_cid *p_cid)
  129. {
  130. struct qed_l2_info *p_l2_info = p_hwfn->p_l2_info;
  131. u16 queue_id = p_cid->rel.queue_id;
  132. bool b_rc = true;
  133. u8 first;
  134. mutex_lock(&p_l2_info->lock);
  135. if (queue_id >= p_l2_info->queues) {
  136. DP_NOTICE(p_hwfn,
  137. "Requested to increase usage for qzone %04x out of %08x\n",
  138. queue_id, p_l2_info->queues);
  139. b_rc = false;
  140. goto out;
  141. }
  142. first = (u8)find_first_zero_bit(p_l2_info->pp_qid_usage[queue_id],
  143. MAX_QUEUES_PER_QZONE);
  144. if (first >= MAX_QUEUES_PER_QZONE) {
  145. b_rc = false;
  146. goto out;
  147. }
  148. __set_bit(first, p_l2_info->pp_qid_usage[queue_id]);
  149. p_cid->qid_usage_idx = first;
  150. out:
  151. mutex_unlock(&p_l2_info->lock);
  152. return b_rc;
  153. }
  154. static void qed_eth_queue_qid_usage_del(struct qed_hwfn *p_hwfn,
  155. struct qed_queue_cid *p_cid)
  156. {
  157. mutex_lock(&p_hwfn->p_l2_info->lock);
  158. clear_bit(p_cid->qid_usage_idx,
  159. p_hwfn->p_l2_info->pp_qid_usage[p_cid->rel.queue_id]);
  160. mutex_unlock(&p_hwfn->p_l2_info->lock);
  161. }
  162. void qed_eth_queue_cid_release(struct qed_hwfn *p_hwfn,
  163. struct qed_queue_cid *p_cid)
  164. {
  165. bool b_legacy_vf = !!(p_cid->vf_legacy & QED_QCID_LEGACY_VF_CID);
  166. if (IS_PF(p_hwfn->cdev) && !b_legacy_vf)
  167. _qed_cxt_release_cid(p_hwfn, p_cid->cid, p_cid->vfid);
  168. /* For PF's VFs we maintain the index inside queue-zone in IOV */
  169. if (p_cid->vfid == QED_QUEUE_CID_SELF)
  170. qed_eth_queue_qid_usage_del(p_hwfn, p_cid);
  171. vfree(p_cid);
  172. }
  173. /* The internal is only meant to be directly called by PFs initializeing CIDs
  174. * for their VFs.
  175. */
  176. static struct qed_queue_cid *
  177. _qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn,
  178. u16 opaque_fid,
  179. u32 cid,
  180. struct qed_queue_start_common_params *p_params,
  181. bool b_is_rx,
  182. struct qed_queue_cid_vf_params *p_vf_params)
  183. {
  184. struct qed_queue_cid *p_cid;
  185. int rc;
  186. p_cid = vzalloc(sizeof(*p_cid));
  187. if (!p_cid)
  188. return NULL;
  189. p_cid->opaque_fid = opaque_fid;
  190. p_cid->cid = cid;
  191. p_cid->p_owner = p_hwfn;
  192. /* Fill in parameters */
  193. p_cid->rel.vport_id = p_params->vport_id;
  194. p_cid->rel.queue_id = p_params->queue_id;
  195. p_cid->rel.stats_id = p_params->stats_id;
  196. p_cid->sb_igu_id = p_params->p_sb->igu_sb_id;
  197. p_cid->b_is_rx = b_is_rx;
  198. p_cid->sb_idx = p_params->sb_idx;
  199. /* Fill-in bits related to VFs' queues if information was provided */
  200. if (p_vf_params) {
  201. p_cid->vfid = p_vf_params->vfid;
  202. p_cid->vf_qid = p_vf_params->vf_qid;
  203. p_cid->vf_legacy = p_vf_params->vf_legacy;
  204. } else {
  205. p_cid->vfid = QED_QUEUE_CID_SELF;
  206. }
  207. /* Don't try calculating the absolute indices for VFs */
  208. if (IS_VF(p_hwfn->cdev)) {
  209. p_cid->abs = p_cid->rel;
  210. goto out;
  211. }
  212. /* Calculate the engine-absolute indices of the resources.
  213. * This would guarantee they're valid later on.
  214. * In some cases [SBs] we already have the right values.
  215. */
  216. rc = qed_fw_vport(p_hwfn, p_cid->rel.vport_id, &p_cid->abs.vport_id);
  217. if (rc)
  218. goto fail;
  219. rc = qed_fw_l2_queue(p_hwfn, p_cid->rel.queue_id, &p_cid->abs.queue_id);
  220. if (rc)
  221. goto fail;
  222. /* In case of a PF configuring its VF's queues, the stats-id is already
  223. * absolute [since there's a single index that's suitable per-VF].
  224. */
  225. if (p_cid->vfid == QED_QUEUE_CID_SELF) {
  226. rc = qed_fw_vport(p_hwfn, p_cid->rel.stats_id,
  227. &p_cid->abs.stats_id);
  228. if (rc)
  229. goto fail;
  230. } else {
  231. p_cid->abs.stats_id = p_cid->rel.stats_id;
  232. }
  233. out:
  234. /* VF-images have provided the qid_usage_idx on their own.
  235. * Otherwise, we need to allocate a unique one.
  236. */
  237. if (!p_vf_params) {
  238. if (!qed_eth_queue_qid_usage_add(p_hwfn, p_cid))
  239. goto fail;
  240. } else {
  241. p_cid->qid_usage_idx = p_vf_params->qid_usage_idx;
  242. }
  243. DP_VERBOSE(p_hwfn,
  244. QED_MSG_SP,
  245. "opaque_fid: %04x CID %08x vport %02x [%02x] qzone %04x.%02x [%04x] stats %02x [%02x] SB %04x PI %02x\n",
  246. p_cid->opaque_fid,
  247. p_cid->cid,
  248. p_cid->rel.vport_id,
  249. p_cid->abs.vport_id,
  250. p_cid->rel.queue_id,
  251. p_cid->qid_usage_idx,
  252. p_cid->abs.queue_id,
  253. p_cid->rel.stats_id,
  254. p_cid->abs.stats_id, p_cid->sb_igu_id, p_cid->sb_idx);
  255. return p_cid;
  256. fail:
  257. vfree(p_cid);
  258. return NULL;
  259. }
  260. struct qed_queue_cid *
  261. qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn,
  262. u16 opaque_fid,
  263. struct qed_queue_start_common_params *p_params,
  264. bool b_is_rx,
  265. struct qed_queue_cid_vf_params *p_vf_params)
  266. {
  267. struct qed_queue_cid *p_cid;
  268. u8 vfid = QED_CXT_PF_CID;
  269. bool b_legacy_vf = false;
  270. u32 cid = 0;
  271. /* In case of legacy VFs, The CID can be derived from the additional
  272. * VF parameters - the VF assumes queue X uses CID X, so we can simply
  273. * use the vf_qid for this purpose as well.
  274. */
  275. if (p_vf_params) {
  276. vfid = p_vf_params->vfid;
  277. if (p_vf_params->vf_legacy & QED_QCID_LEGACY_VF_CID) {
  278. b_legacy_vf = true;
  279. cid = p_vf_params->vf_qid;
  280. }
  281. }
  282. /* Get a unique firmware CID for this queue, in case it's a PF.
  283. * VF's don't need a CID as the queue configuration will be done
  284. * by PF.
  285. */
  286. if (IS_PF(p_hwfn->cdev) && !b_legacy_vf) {
  287. if (_qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH,
  288. &cid, vfid)) {
  289. DP_NOTICE(p_hwfn, "Failed to acquire cid\n");
  290. return NULL;
  291. }
  292. }
  293. p_cid = _qed_eth_queue_to_cid(p_hwfn, opaque_fid, cid,
  294. p_params, b_is_rx, p_vf_params);
  295. if (!p_cid && IS_PF(p_hwfn->cdev) && !b_legacy_vf)
  296. _qed_cxt_release_cid(p_hwfn, cid, vfid);
  297. return p_cid;
  298. }
  299. static struct qed_queue_cid *
  300. qed_eth_queue_to_cid_pf(struct qed_hwfn *p_hwfn,
  301. u16 opaque_fid,
  302. bool b_is_rx,
  303. struct qed_queue_start_common_params *p_params)
  304. {
  305. return qed_eth_queue_to_cid(p_hwfn, opaque_fid, p_params, b_is_rx,
  306. NULL);
  307. }
  308. int qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn,
  309. struct qed_sp_vport_start_params *p_params)
  310. {
  311. struct vport_start_ramrod_data *p_ramrod = NULL;
  312. struct qed_spq_entry *p_ent = NULL;
  313. struct qed_sp_init_data init_data;
  314. u8 abs_vport_id = 0;
  315. int rc = -EINVAL;
  316. u16 rx_mode = 0;
  317. rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
  318. if (rc)
  319. return rc;
  320. memset(&init_data, 0, sizeof(init_data));
  321. init_data.cid = qed_spq_get_cid(p_hwfn);
  322. init_data.opaque_fid = p_params->opaque_fid;
  323. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  324. rc = qed_sp_init_request(p_hwfn, &p_ent,
  325. ETH_RAMROD_VPORT_START,
  326. PROTOCOLID_ETH, &init_data);
  327. if (rc)
  328. return rc;
  329. p_ramrod = &p_ent->ramrod.vport_start;
  330. p_ramrod->vport_id = abs_vport_id;
  331. p_ramrod->mtu = cpu_to_le16(p_params->mtu);
  332. p_ramrod->handle_ptp_pkts = p_params->handle_ptp_pkts;
  333. p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan;
  334. p_ramrod->drop_ttl0_en = p_params->drop_ttl0;
  335. p_ramrod->untagged = p_params->only_untagged;
  336. SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
  337. SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
  338. p_ramrod->rx_mode.state = cpu_to_le16(rx_mode);
  339. /* TPA related fields */
  340. memset(&p_ramrod->tpa_param, 0, sizeof(struct eth_vport_tpa_param));
  341. p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe;
  342. switch (p_params->tpa_mode) {
  343. case QED_TPA_MODE_GRO:
  344. p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
  345. p_ramrod->tpa_param.tpa_max_size = (u16)-1;
  346. p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2;
  347. p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2;
  348. p_ramrod->tpa_param.tpa_ipv4_en_flg = 1;
  349. p_ramrod->tpa_param.tpa_ipv6_en_flg = 1;
  350. p_ramrod->tpa_param.tpa_pkt_split_flg = 1;
  351. p_ramrod->tpa_param.tpa_gro_consistent_flg = 1;
  352. break;
  353. default:
  354. break;
  355. }
  356. p_ramrod->tx_switching_en = p_params->tx_switching;
  357. p_ramrod->ctl_frame_mac_check_en = !!p_params->check_mac;
  358. p_ramrod->ctl_frame_ethtype_check_en = !!p_params->check_ethtype;
  359. /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
  360. p_ramrod->sw_fid = qed_concrete_to_sw_fid(p_hwfn->cdev,
  361. p_params->concrete_fid);
  362. return qed_spq_post(p_hwfn, p_ent, NULL);
  363. }
  364. static int qed_sp_vport_start(struct qed_hwfn *p_hwfn,
  365. struct qed_sp_vport_start_params *p_params)
  366. {
  367. if (IS_VF(p_hwfn->cdev)) {
  368. return qed_vf_pf_vport_start(p_hwfn, p_params->vport_id,
  369. p_params->mtu,
  370. p_params->remove_inner_vlan,
  371. p_params->tpa_mode,
  372. p_params->max_buffers_per_cqe,
  373. p_params->only_untagged);
  374. }
  375. return qed_sp_eth_vport_start(p_hwfn, p_params);
  376. }
  377. static int
  378. qed_sp_vport_update_rss(struct qed_hwfn *p_hwfn,
  379. struct vport_update_ramrod_data *p_ramrod,
  380. struct qed_rss_params *p_rss)
  381. {
  382. struct eth_vport_rss_config *p_config;
  383. u16 capabilities = 0;
  384. int i, table_size;
  385. int rc = 0;
  386. if (!p_rss) {
  387. p_ramrod->common.update_rss_flg = 0;
  388. return rc;
  389. }
  390. p_config = &p_ramrod->rss_config;
  391. BUILD_BUG_ON(QED_RSS_IND_TABLE_SIZE != ETH_RSS_IND_TABLE_ENTRIES_NUM);
  392. rc = qed_fw_rss_eng(p_hwfn, p_rss->rss_eng_id, &p_config->rss_id);
  393. if (rc)
  394. return rc;
  395. p_ramrod->common.update_rss_flg = p_rss->update_rss_config;
  396. p_config->update_rss_capabilities = p_rss->update_rss_capabilities;
  397. p_config->update_rss_ind_table = p_rss->update_rss_ind_table;
  398. p_config->update_rss_key = p_rss->update_rss_key;
  399. p_config->rss_mode = p_rss->rss_enable ?
  400. ETH_VPORT_RSS_MODE_REGULAR :
  401. ETH_VPORT_RSS_MODE_DISABLED;
  402. SET_FIELD(capabilities,
  403. ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
  404. !!(p_rss->rss_caps & QED_RSS_IPV4));
  405. SET_FIELD(capabilities,
  406. ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
  407. !!(p_rss->rss_caps & QED_RSS_IPV6));
  408. SET_FIELD(capabilities,
  409. ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
  410. !!(p_rss->rss_caps & QED_RSS_IPV4_TCP));
  411. SET_FIELD(capabilities,
  412. ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
  413. !!(p_rss->rss_caps & QED_RSS_IPV6_TCP));
  414. SET_FIELD(capabilities,
  415. ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
  416. !!(p_rss->rss_caps & QED_RSS_IPV4_UDP));
  417. SET_FIELD(capabilities,
  418. ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
  419. !!(p_rss->rss_caps & QED_RSS_IPV6_UDP));
  420. p_config->tbl_size = p_rss->rss_table_size_log;
  421. p_config->capabilities = cpu_to_le16(capabilities);
  422. DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
  423. "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
  424. p_ramrod->common.update_rss_flg,
  425. p_config->rss_mode,
  426. p_config->update_rss_capabilities,
  427. p_config->capabilities,
  428. p_config->update_rss_ind_table, p_config->update_rss_key);
  429. table_size = min_t(int, QED_RSS_IND_TABLE_SIZE,
  430. 1 << p_config->tbl_size);
  431. for (i = 0; i < table_size; i++) {
  432. struct qed_queue_cid *p_queue = p_rss->rss_ind_table[i];
  433. if (!p_queue)
  434. return -EINVAL;
  435. p_config->indirection_table[i] =
  436. cpu_to_le16(p_queue->abs.queue_id);
  437. }
  438. DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
  439. "Configured RSS indirection table [%d entries]:\n",
  440. table_size);
  441. for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i += 0x10) {
  442. DP_VERBOSE(p_hwfn,
  443. NETIF_MSG_IFUP,
  444. "%04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x\n",
  445. le16_to_cpu(p_config->indirection_table[i]),
  446. le16_to_cpu(p_config->indirection_table[i + 1]),
  447. le16_to_cpu(p_config->indirection_table[i + 2]),
  448. le16_to_cpu(p_config->indirection_table[i + 3]),
  449. le16_to_cpu(p_config->indirection_table[i + 4]),
  450. le16_to_cpu(p_config->indirection_table[i + 5]),
  451. le16_to_cpu(p_config->indirection_table[i + 6]),
  452. le16_to_cpu(p_config->indirection_table[i + 7]),
  453. le16_to_cpu(p_config->indirection_table[i + 8]),
  454. le16_to_cpu(p_config->indirection_table[i + 9]),
  455. le16_to_cpu(p_config->indirection_table[i + 10]),
  456. le16_to_cpu(p_config->indirection_table[i + 11]),
  457. le16_to_cpu(p_config->indirection_table[i + 12]),
  458. le16_to_cpu(p_config->indirection_table[i + 13]),
  459. le16_to_cpu(p_config->indirection_table[i + 14]),
  460. le16_to_cpu(p_config->indirection_table[i + 15]));
  461. }
  462. for (i = 0; i < 10; i++)
  463. p_config->rss_key[i] = cpu_to_le32(p_rss->rss_key[i]);
  464. return rc;
  465. }
  466. static void
  467. qed_sp_update_accept_mode(struct qed_hwfn *p_hwfn,
  468. struct vport_update_ramrod_data *p_ramrod,
  469. struct qed_filter_accept_flags accept_flags)
  470. {
  471. p_ramrod->common.update_rx_mode_flg =
  472. accept_flags.update_rx_mode_config;
  473. p_ramrod->common.update_tx_mode_flg =
  474. accept_flags.update_tx_mode_config;
  475. /* Set Rx mode accept flags */
  476. if (p_ramrod->common.update_rx_mode_flg) {
  477. u8 accept_filter = accept_flags.rx_accept_filter;
  478. u16 state = 0;
  479. SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
  480. !(!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) ||
  481. !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)));
  482. SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
  483. !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED));
  484. SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
  485. !(!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) ||
  486. !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
  487. SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
  488. (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
  489. !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
  490. SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
  491. !!(accept_filter & QED_ACCEPT_BCAST));
  492. SET_FIELD(state, ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI,
  493. !!(accept_filter & QED_ACCEPT_ANY_VNI));
  494. p_ramrod->rx_mode.state = cpu_to_le16(state);
  495. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  496. "p_ramrod->rx_mode.state = 0x%x\n", state);
  497. }
  498. /* Set Tx mode accept flags */
  499. if (p_ramrod->common.update_tx_mode_flg) {
  500. u8 accept_filter = accept_flags.tx_accept_filter;
  501. u16 state = 0;
  502. SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
  503. !!(accept_filter & QED_ACCEPT_NONE));
  504. SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
  505. !!(accept_filter & QED_ACCEPT_NONE));
  506. SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
  507. (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
  508. !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
  509. SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
  510. !!(accept_filter & QED_ACCEPT_BCAST));
  511. p_ramrod->tx_mode.state = cpu_to_le16(state);
  512. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  513. "p_ramrod->tx_mode.state = 0x%x\n", state);
  514. }
  515. }
  516. static void
  517. qed_sp_vport_update_sge_tpa(struct qed_hwfn *p_hwfn,
  518. struct vport_update_ramrod_data *p_ramrod,
  519. struct qed_sge_tpa_params *p_params)
  520. {
  521. struct eth_vport_tpa_param *p_tpa;
  522. if (!p_params) {
  523. p_ramrod->common.update_tpa_param_flg = 0;
  524. p_ramrod->common.update_tpa_en_flg = 0;
  525. p_ramrod->common.update_tpa_param_flg = 0;
  526. return;
  527. }
  528. p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg;
  529. p_tpa = &p_ramrod->tpa_param;
  530. p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg;
  531. p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg;
  532. p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg;
  533. p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg;
  534. p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg;
  535. p_tpa->max_buff_num = p_params->max_buffers_per_cqe;
  536. p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg;
  537. p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg;
  538. p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg;
  539. p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num;
  540. p_tpa->tpa_max_size = p_params->tpa_max_size;
  541. p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start;
  542. p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont;
  543. }
  544. static void
  545. qed_sp_update_mcast_bin(struct qed_hwfn *p_hwfn,
  546. struct vport_update_ramrod_data *p_ramrod,
  547. struct qed_sp_vport_update_params *p_params)
  548. {
  549. int i;
  550. memset(&p_ramrod->approx_mcast.bins, 0,
  551. sizeof(p_ramrod->approx_mcast.bins));
  552. if (!p_params->update_approx_mcast_flg)
  553. return;
  554. p_ramrod->common.update_approx_mcast_flg = 1;
  555. for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
  556. u32 *p_bins = (u32 *)p_params->bins;
  557. p_ramrod->approx_mcast.bins[i] = cpu_to_le32(p_bins[i]);
  558. }
  559. }
  560. int qed_sp_vport_update(struct qed_hwfn *p_hwfn,
  561. struct qed_sp_vport_update_params *p_params,
  562. enum spq_mode comp_mode,
  563. struct qed_spq_comp_cb *p_comp_data)
  564. {
  565. struct qed_rss_params *p_rss_params = p_params->rss_params;
  566. struct vport_update_ramrod_data_cmn *p_cmn;
  567. struct qed_sp_init_data init_data;
  568. struct vport_update_ramrod_data *p_ramrod = NULL;
  569. struct qed_spq_entry *p_ent = NULL;
  570. u8 abs_vport_id = 0, val;
  571. int rc = -EINVAL;
  572. if (IS_VF(p_hwfn->cdev)) {
  573. rc = qed_vf_pf_vport_update(p_hwfn, p_params);
  574. return rc;
  575. }
  576. rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
  577. if (rc)
  578. return rc;
  579. memset(&init_data, 0, sizeof(init_data));
  580. init_data.cid = qed_spq_get_cid(p_hwfn);
  581. init_data.opaque_fid = p_params->opaque_fid;
  582. init_data.comp_mode = comp_mode;
  583. init_data.p_comp_data = p_comp_data;
  584. rc = qed_sp_init_request(p_hwfn, &p_ent,
  585. ETH_RAMROD_VPORT_UPDATE,
  586. PROTOCOLID_ETH, &init_data);
  587. if (rc)
  588. return rc;
  589. /* Copy input params to ramrod according to FW struct */
  590. p_ramrod = &p_ent->ramrod.vport_update;
  591. p_cmn = &p_ramrod->common;
  592. p_cmn->vport_id = abs_vport_id;
  593. p_cmn->rx_active_flg = p_params->vport_active_rx_flg;
  594. p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg;
  595. p_cmn->tx_active_flg = p_params->vport_active_tx_flg;
  596. p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg;
  597. p_cmn->accept_any_vlan = p_params->accept_any_vlan;
  598. val = p_params->update_accept_any_vlan_flg;
  599. p_cmn->update_accept_any_vlan_flg = val;
  600. p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg;
  601. val = p_params->update_inner_vlan_removal_flg;
  602. p_cmn->update_inner_vlan_removal_en_flg = val;
  603. p_cmn->default_vlan_en = p_params->default_vlan_enable_flg;
  604. val = p_params->update_default_vlan_enable_flg;
  605. p_cmn->update_default_vlan_en_flg = val;
  606. p_cmn->default_vlan = cpu_to_le16(p_params->default_vlan);
  607. p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg;
  608. p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg;
  609. p_ramrod->common.tx_switching_en = p_params->tx_switching_flg;
  610. p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg;
  611. p_cmn->anti_spoofing_en = p_params->anti_spoofing_en;
  612. val = p_params->update_anti_spoofing_en_flg;
  613. p_ramrod->common.update_anti_spoofing_en_flg = val;
  614. rc = qed_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
  615. if (rc) {
  616. /* Return spq entry which is taken in qed_sp_init_request()*/
  617. qed_spq_return_entry(p_hwfn, p_ent);
  618. return rc;
  619. }
  620. /* Update mcast bins for VFs, PF doesn't use this functionality */
  621. qed_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params);
  622. qed_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
  623. qed_sp_vport_update_sge_tpa(p_hwfn, p_ramrod, p_params->sge_tpa_params);
  624. return qed_spq_post(p_hwfn, p_ent, NULL);
  625. }
  626. int qed_sp_vport_stop(struct qed_hwfn *p_hwfn, u16 opaque_fid, u8 vport_id)
  627. {
  628. struct vport_stop_ramrod_data *p_ramrod;
  629. struct qed_sp_init_data init_data;
  630. struct qed_spq_entry *p_ent;
  631. u8 abs_vport_id = 0;
  632. int rc;
  633. if (IS_VF(p_hwfn->cdev))
  634. return qed_vf_pf_vport_stop(p_hwfn);
  635. rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id);
  636. if (rc)
  637. return rc;
  638. memset(&init_data, 0, sizeof(init_data));
  639. init_data.cid = qed_spq_get_cid(p_hwfn);
  640. init_data.opaque_fid = opaque_fid;
  641. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  642. rc = qed_sp_init_request(p_hwfn, &p_ent,
  643. ETH_RAMROD_VPORT_STOP,
  644. PROTOCOLID_ETH, &init_data);
  645. if (rc)
  646. return rc;
  647. p_ramrod = &p_ent->ramrod.vport_stop;
  648. p_ramrod->vport_id = abs_vport_id;
  649. return qed_spq_post(p_hwfn, p_ent, NULL);
  650. }
  651. static int
  652. qed_vf_pf_accept_flags(struct qed_hwfn *p_hwfn,
  653. struct qed_filter_accept_flags *p_accept_flags)
  654. {
  655. struct qed_sp_vport_update_params s_params;
  656. memset(&s_params, 0, sizeof(s_params));
  657. memcpy(&s_params.accept_flags, p_accept_flags,
  658. sizeof(struct qed_filter_accept_flags));
  659. return qed_vf_pf_vport_update(p_hwfn, &s_params);
  660. }
  661. static int qed_filter_accept_cmd(struct qed_dev *cdev,
  662. u8 vport,
  663. struct qed_filter_accept_flags accept_flags,
  664. u8 update_accept_any_vlan,
  665. u8 accept_any_vlan,
  666. enum spq_mode comp_mode,
  667. struct qed_spq_comp_cb *p_comp_data)
  668. {
  669. struct qed_sp_vport_update_params vport_update_params;
  670. int i, rc;
  671. /* Prepare and send the vport rx_mode change */
  672. memset(&vport_update_params, 0, sizeof(vport_update_params));
  673. vport_update_params.vport_id = vport;
  674. vport_update_params.accept_flags = accept_flags;
  675. vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
  676. vport_update_params.accept_any_vlan = accept_any_vlan;
  677. for_each_hwfn(cdev, i) {
  678. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  679. vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
  680. if (IS_VF(cdev)) {
  681. rc = qed_vf_pf_accept_flags(p_hwfn, &accept_flags);
  682. if (rc)
  683. return rc;
  684. continue;
  685. }
  686. rc = qed_sp_vport_update(p_hwfn, &vport_update_params,
  687. comp_mode, p_comp_data);
  688. if (rc) {
  689. DP_ERR(cdev, "Update rx_mode failed %d\n", rc);
  690. return rc;
  691. }
  692. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  693. "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
  694. accept_flags.rx_accept_filter,
  695. accept_flags.tx_accept_filter);
  696. if (update_accept_any_vlan)
  697. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  698. "accept_any_vlan=%d configured\n",
  699. accept_any_vlan);
  700. }
  701. return 0;
  702. }
  703. int qed_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn,
  704. struct qed_queue_cid *p_cid,
  705. u16 bd_max_bytes,
  706. dma_addr_t bd_chain_phys_addr,
  707. dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size)
  708. {
  709. struct rx_queue_start_ramrod_data *p_ramrod = NULL;
  710. struct qed_spq_entry *p_ent = NULL;
  711. struct qed_sp_init_data init_data;
  712. int rc = -EINVAL;
  713. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  714. "opaque_fid=0x%x, cid=0x%x, rx_qzone=0x%x, vport_id=0x%x, sb_id=0x%x\n",
  715. p_cid->opaque_fid, p_cid->cid,
  716. p_cid->abs.queue_id, p_cid->abs.vport_id, p_cid->sb_igu_id);
  717. /* Get SPQ entry */
  718. memset(&init_data, 0, sizeof(init_data));
  719. init_data.cid = p_cid->cid;
  720. init_data.opaque_fid = p_cid->opaque_fid;
  721. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  722. rc = qed_sp_init_request(p_hwfn, &p_ent,
  723. ETH_RAMROD_RX_QUEUE_START,
  724. PROTOCOLID_ETH, &init_data);
  725. if (rc)
  726. return rc;
  727. p_ramrod = &p_ent->ramrod.rx_queue_start;
  728. p_ramrod->sb_id = cpu_to_le16(p_cid->sb_igu_id);
  729. p_ramrod->sb_index = p_cid->sb_idx;
  730. p_ramrod->vport_id = p_cid->abs.vport_id;
  731. p_ramrod->stats_counter_id = p_cid->abs.stats_id;
  732. p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
  733. p_ramrod->complete_cqe_flg = 0;
  734. p_ramrod->complete_event_flg = 1;
  735. p_ramrod->bd_max_bytes = cpu_to_le16(bd_max_bytes);
  736. DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr);
  737. p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size);
  738. DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
  739. if (p_cid->vfid != QED_QUEUE_CID_SELF) {
  740. bool b_legacy_vf = !!(p_cid->vf_legacy &
  741. QED_QCID_LEGACY_VF_RX_PROD);
  742. p_ramrod->vf_rx_prod_index = p_cid->vf_qid;
  743. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  744. "Queue%s is meant for VF rxq[%02x]\n",
  745. b_legacy_vf ? " [legacy]" : "", p_cid->vf_qid);
  746. p_ramrod->vf_rx_prod_use_zone_a = b_legacy_vf;
  747. }
  748. return qed_spq_post(p_hwfn, p_ent, NULL);
  749. }
  750. static int
  751. qed_eth_pf_rx_queue_start(struct qed_hwfn *p_hwfn,
  752. struct qed_queue_cid *p_cid,
  753. u16 bd_max_bytes,
  754. dma_addr_t bd_chain_phys_addr,
  755. dma_addr_t cqe_pbl_addr,
  756. u16 cqe_pbl_size, void __iomem **pp_prod)
  757. {
  758. u32 init_prod_val = 0;
  759. *pp_prod = p_hwfn->regview +
  760. GTT_BAR0_MAP_REG_MSDM_RAM +
  761. MSTORM_ETH_PF_PRODS_OFFSET(p_cid->abs.queue_id);
  762. /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
  763. __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
  764. (u32 *)(&init_prod_val));
  765. return qed_eth_rxq_start_ramrod(p_hwfn, p_cid,
  766. bd_max_bytes,
  767. bd_chain_phys_addr,
  768. cqe_pbl_addr, cqe_pbl_size);
  769. }
  770. static int
  771. qed_eth_rx_queue_start(struct qed_hwfn *p_hwfn,
  772. u16 opaque_fid,
  773. struct qed_queue_start_common_params *p_params,
  774. u16 bd_max_bytes,
  775. dma_addr_t bd_chain_phys_addr,
  776. dma_addr_t cqe_pbl_addr,
  777. u16 cqe_pbl_size,
  778. struct qed_rxq_start_ret_params *p_ret_params)
  779. {
  780. struct qed_queue_cid *p_cid;
  781. int rc;
  782. /* Allocate a CID for the queue */
  783. p_cid = qed_eth_queue_to_cid_pf(p_hwfn, opaque_fid, true, p_params);
  784. if (!p_cid)
  785. return -ENOMEM;
  786. if (IS_PF(p_hwfn->cdev)) {
  787. rc = qed_eth_pf_rx_queue_start(p_hwfn, p_cid,
  788. bd_max_bytes,
  789. bd_chain_phys_addr,
  790. cqe_pbl_addr, cqe_pbl_size,
  791. &p_ret_params->p_prod);
  792. } else {
  793. rc = qed_vf_pf_rxq_start(p_hwfn, p_cid,
  794. bd_max_bytes,
  795. bd_chain_phys_addr,
  796. cqe_pbl_addr,
  797. cqe_pbl_size, &p_ret_params->p_prod);
  798. }
  799. /* Provide the caller with a reference to as handler */
  800. if (rc)
  801. qed_eth_queue_cid_release(p_hwfn, p_cid);
  802. else
  803. p_ret_params->p_handle = (void *)p_cid;
  804. return rc;
  805. }
  806. int qed_sp_eth_rx_queues_update(struct qed_hwfn *p_hwfn,
  807. void **pp_rxq_handles,
  808. u8 num_rxqs,
  809. u8 complete_cqe_flg,
  810. u8 complete_event_flg,
  811. enum spq_mode comp_mode,
  812. struct qed_spq_comp_cb *p_comp_data)
  813. {
  814. struct rx_queue_update_ramrod_data *p_ramrod = NULL;
  815. struct qed_spq_entry *p_ent = NULL;
  816. struct qed_sp_init_data init_data;
  817. struct qed_queue_cid *p_cid;
  818. int rc = -EINVAL;
  819. u8 i;
  820. memset(&init_data, 0, sizeof(init_data));
  821. init_data.comp_mode = comp_mode;
  822. init_data.p_comp_data = p_comp_data;
  823. for (i = 0; i < num_rxqs; i++) {
  824. p_cid = ((struct qed_queue_cid **)pp_rxq_handles)[i];
  825. /* Get SPQ entry */
  826. init_data.cid = p_cid->cid;
  827. init_data.opaque_fid = p_cid->opaque_fid;
  828. rc = qed_sp_init_request(p_hwfn, &p_ent,
  829. ETH_RAMROD_RX_QUEUE_UPDATE,
  830. PROTOCOLID_ETH, &init_data);
  831. if (rc)
  832. return rc;
  833. p_ramrod = &p_ent->ramrod.rx_queue_update;
  834. p_ramrod->vport_id = p_cid->abs.vport_id;
  835. p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
  836. p_ramrod->complete_cqe_flg = complete_cqe_flg;
  837. p_ramrod->complete_event_flg = complete_event_flg;
  838. rc = qed_spq_post(p_hwfn, p_ent, NULL);
  839. if (rc)
  840. return rc;
  841. }
  842. return rc;
  843. }
  844. static int
  845. qed_eth_pf_rx_queue_stop(struct qed_hwfn *p_hwfn,
  846. struct qed_queue_cid *p_cid,
  847. bool b_eq_completion_only, bool b_cqe_completion)
  848. {
  849. struct rx_queue_stop_ramrod_data *p_ramrod = NULL;
  850. struct qed_spq_entry *p_ent = NULL;
  851. struct qed_sp_init_data init_data;
  852. int rc;
  853. memset(&init_data, 0, sizeof(init_data));
  854. init_data.cid = p_cid->cid;
  855. init_data.opaque_fid = p_cid->opaque_fid;
  856. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  857. rc = qed_sp_init_request(p_hwfn, &p_ent,
  858. ETH_RAMROD_RX_QUEUE_STOP,
  859. PROTOCOLID_ETH, &init_data);
  860. if (rc)
  861. return rc;
  862. p_ramrod = &p_ent->ramrod.rx_queue_stop;
  863. p_ramrod->vport_id = p_cid->abs.vport_id;
  864. p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
  865. /* Cleaning the queue requires the completion to arrive there.
  866. * In addition, VFs require the answer to come as eqe to PF.
  867. */
  868. p_ramrod->complete_cqe_flg = ((p_cid->vfid == QED_QUEUE_CID_SELF) &&
  869. !b_eq_completion_only) ||
  870. b_cqe_completion;
  871. p_ramrod->complete_event_flg = (p_cid->vfid != QED_QUEUE_CID_SELF) ||
  872. b_eq_completion_only;
  873. return qed_spq_post(p_hwfn, p_ent, NULL);
  874. }
  875. int qed_eth_rx_queue_stop(struct qed_hwfn *p_hwfn,
  876. void *p_rxq,
  877. bool eq_completion_only, bool cqe_completion)
  878. {
  879. struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_rxq;
  880. int rc = -EINVAL;
  881. if (IS_PF(p_hwfn->cdev))
  882. rc = qed_eth_pf_rx_queue_stop(p_hwfn, p_cid,
  883. eq_completion_only,
  884. cqe_completion);
  885. else
  886. rc = qed_vf_pf_rxq_stop(p_hwfn, p_cid, cqe_completion);
  887. if (!rc)
  888. qed_eth_queue_cid_release(p_hwfn, p_cid);
  889. return rc;
  890. }
  891. int
  892. qed_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn,
  893. struct qed_queue_cid *p_cid,
  894. dma_addr_t pbl_addr, u16 pbl_size, u16 pq_id)
  895. {
  896. struct tx_queue_start_ramrod_data *p_ramrod = NULL;
  897. struct qed_spq_entry *p_ent = NULL;
  898. struct qed_sp_init_data init_data;
  899. int rc = -EINVAL;
  900. /* Get SPQ entry */
  901. memset(&init_data, 0, sizeof(init_data));
  902. init_data.cid = p_cid->cid;
  903. init_data.opaque_fid = p_cid->opaque_fid;
  904. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  905. rc = qed_sp_init_request(p_hwfn, &p_ent,
  906. ETH_RAMROD_TX_QUEUE_START,
  907. PROTOCOLID_ETH, &init_data);
  908. if (rc)
  909. return rc;
  910. p_ramrod = &p_ent->ramrod.tx_queue_start;
  911. p_ramrod->vport_id = p_cid->abs.vport_id;
  912. p_ramrod->sb_id = cpu_to_le16(p_cid->sb_igu_id);
  913. p_ramrod->sb_index = p_cid->sb_idx;
  914. p_ramrod->stats_counter_id = p_cid->abs.stats_id;
  915. p_ramrod->queue_zone_id = cpu_to_le16(p_cid->abs.queue_id);
  916. p_ramrod->same_as_last_id = cpu_to_le16(p_cid->abs.queue_id);
  917. p_ramrod->pbl_size = cpu_to_le16(pbl_size);
  918. DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr);
  919. p_ramrod->qm_pq_id = cpu_to_le16(pq_id);
  920. return qed_spq_post(p_hwfn, p_ent, NULL);
  921. }
  922. static int
  923. qed_eth_pf_tx_queue_start(struct qed_hwfn *p_hwfn,
  924. struct qed_queue_cid *p_cid,
  925. u8 tc,
  926. dma_addr_t pbl_addr,
  927. u16 pbl_size, void __iomem **pp_doorbell)
  928. {
  929. int rc;
  930. rc = qed_eth_txq_start_ramrod(p_hwfn, p_cid,
  931. pbl_addr, pbl_size,
  932. qed_get_cm_pq_idx_mcos(p_hwfn, tc));
  933. if (rc)
  934. return rc;
  935. /* Provide the caller with the necessary return values */
  936. *pp_doorbell = p_hwfn->doorbells +
  937. qed_db_addr(p_cid->cid, DQ_DEMS_LEGACY);
  938. return 0;
  939. }
  940. static int
  941. qed_eth_tx_queue_start(struct qed_hwfn *p_hwfn,
  942. u16 opaque_fid,
  943. struct qed_queue_start_common_params *p_params,
  944. u8 tc,
  945. dma_addr_t pbl_addr,
  946. u16 pbl_size,
  947. struct qed_txq_start_ret_params *p_ret_params)
  948. {
  949. struct qed_queue_cid *p_cid;
  950. int rc;
  951. p_cid = qed_eth_queue_to_cid_pf(p_hwfn, opaque_fid, false, p_params);
  952. if (!p_cid)
  953. return -EINVAL;
  954. if (IS_PF(p_hwfn->cdev))
  955. rc = qed_eth_pf_tx_queue_start(p_hwfn, p_cid, tc,
  956. pbl_addr, pbl_size,
  957. &p_ret_params->p_doorbell);
  958. else
  959. rc = qed_vf_pf_txq_start(p_hwfn, p_cid,
  960. pbl_addr, pbl_size,
  961. &p_ret_params->p_doorbell);
  962. if (rc)
  963. qed_eth_queue_cid_release(p_hwfn, p_cid);
  964. else
  965. p_ret_params->p_handle = (void *)p_cid;
  966. return rc;
  967. }
  968. static int
  969. qed_eth_pf_tx_queue_stop(struct qed_hwfn *p_hwfn, struct qed_queue_cid *p_cid)
  970. {
  971. struct qed_spq_entry *p_ent = NULL;
  972. struct qed_sp_init_data init_data;
  973. int rc;
  974. memset(&init_data, 0, sizeof(init_data));
  975. init_data.cid = p_cid->cid;
  976. init_data.opaque_fid = p_cid->opaque_fid;
  977. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  978. rc = qed_sp_init_request(p_hwfn, &p_ent,
  979. ETH_RAMROD_TX_QUEUE_STOP,
  980. PROTOCOLID_ETH, &init_data);
  981. if (rc)
  982. return rc;
  983. return qed_spq_post(p_hwfn, p_ent, NULL);
  984. }
  985. int qed_eth_tx_queue_stop(struct qed_hwfn *p_hwfn, void *p_handle)
  986. {
  987. struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_handle;
  988. int rc;
  989. if (IS_PF(p_hwfn->cdev))
  990. rc = qed_eth_pf_tx_queue_stop(p_hwfn, p_cid);
  991. else
  992. rc = qed_vf_pf_txq_stop(p_hwfn, p_cid);
  993. if (!rc)
  994. qed_eth_queue_cid_release(p_hwfn, p_cid);
  995. return rc;
  996. }
  997. static enum eth_filter_action qed_filter_action(enum qed_filter_opcode opcode)
  998. {
  999. enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
  1000. switch (opcode) {
  1001. case QED_FILTER_ADD:
  1002. action = ETH_FILTER_ACTION_ADD;
  1003. break;
  1004. case QED_FILTER_REMOVE:
  1005. action = ETH_FILTER_ACTION_REMOVE;
  1006. break;
  1007. case QED_FILTER_FLUSH:
  1008. action = ETH_FILTER_ACTION_REMOVE_ALL;
  1009. break;
  1010. default:
  1011. action = MAX_ETH_FILTER_ACTION;
  1012. }
  1013. return action;
  1014. }
  1015. static int
  1016. qed_filter_ucast_common(struct qed_hwfn *p_hwfn,
  1017. u16 opaque_fid,
  1018. struct qed_filter_ucast *p_filter_cmd,
  1019. struct vport_filter_update_ramrod_data **pp_ramrod,
  1020. struct qed_spq_entry **pp_ent,
  1021. enum spq_mode comp_mode,
  1022. struct qed_spq_comp_cb *p_comp_data)
  1023. {
  1024. u8 vport_to_add_to = 0, vport_to_remove_from = 0;
  1025. struct vport_filter_update_ramrod_data *p_ramrod;
  1026. struct eth_filter_cmd *p_first_filter;
  1027. struct eth_filter_cmd *p_second_filter;
  1028. struct qed_sp_init_data init_data;
  1029. enum eth_filter_action action;
  1030. int rc;
  1031. rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
  1032. &vport_to_remove_from);
  1033. if (rc)
  1034. return rc;
  1035. rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
  1036. &vport_to_add_to);
  1037. if (rc)
  1038. return rc;
  1039. /* Get SPQ entry */
  1040. memset(&init_data, 0, sizeof(init_data));
  1041. init_data.cid = qed_spq_get_cid(p_hwfn);
  1042. init_data.opaque_fid = opaque_fid;
  1043. init_data.comp_mode = comp_mode;
  1044. init_data.p_comp_data = p_comp_data;
  1045. rc = qed_sp_init_request(p_hwfn, pp_ent,
  1046. ETH_RAMROD_FILTERS_UPDATE,
  1047. PROTOCOLID_ETH, &init_data);
  1048. if (rc)
  1049. return rc;
  1050. *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
  1051. p_ramrod = *pp_ramrod;
  1052. p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
  1053. p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
  1054. switch (p_filter_cmd->opcode) {
  1055. case QED_FILTER_REPLACE:
  1056. case QED_FILTER_MOVE:
  1057. p_ramrod->filter_cmd_hdr.cmd_cnt = 2; break;
  1058. default:
  1059. p_ramrod->filter_cmd_hdr.cmd_cnt = 1; break;
  1060. }
  1061. p_first_filter = &p_ramrod->filter_cmds[0];
  1062. p_second_filter = &p_ramrod->filter_cmds[1];
  1063. switch (p_filter_cmd->type) {
  1064. case QED_FILTER_MAC:
  1065. p_first_filter->type = ETH_FILTER_TYPE_MAC; break;
  1066. case QED_FILTER_VLAN:
  1067. p_first_filter->type = ETH_FILTER_TYPE_VLAN; break;
  1068. case QED_FILTER_MAC_VLAN:
  1069. p_first_filter->type = ETH_FILTER_TYPE_PAIR; break;
  1070. case QED_FILTER_INNER_MAC:
  1071. p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC; break;
  1072. case QED_FILTER_INNER_VLAN:
  1073. p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN; break;
  1074. case QED_FILTER_INNER_PAIR:
  1075. p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR; break;
  1076. case QED_FILTER_INNER_MAC_VNI_PAIR:
  1077. p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
  1078. break;
  1079. case QED_FILTER_MAC_VNI_PAIR:
  1080. p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR; break;
  1081. case QED_FILTER_VNI:
  1082. p_first_filter->type = ETH_FILTER_TYPE_VNI; break;
  1083. }
  1084. if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
  1085. (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
  1086. (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
  1087. (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
  1088. (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
  1089. (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR)) {
  1090. qed_set_fw_mac_addr(&p_first_filter->mac_msb,
  1091. &p_first_filter->mac_mid,
  1092. &p_first_filter->mac_lsb,
  1093. (u8 *)p_filter_cmd->mac);
  1094. }
  1095. if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
  1096. (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
  1097. (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
  1098. (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
  1099. p_first_filter->vlan_id = cpu_to_le16(p_filter_cmd->vlan);
  1100. if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
  1101. (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
  1102. (p_first_filter->type == ETH_FILTER_TYPE_VNI))
  1103. p_first_filter->vni = cpu_to_le32(p_filter_cmd->vni);
  1104. if (p_filter_cmd->opcode == QED_FILTER_MOVE) {
  1105. p_second_filter->type = p_first_filter->type;
  1106. p_second_filter->mac_msb = p_first_filter->mac_msb;
  1107. p_second_filter->mac_mid = p_first_filter->mac_mid;
  1108. p_second_filter->mac_lsb = p_first_filter->mac_lsb;
  1109. p_second_filter->vlan_id = p_first_filter->vlan_id;
  1110. p_second_filter->vni = p_first_filter->vni;
  1111. p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
  1112. p_first_filter->vport_id = vport_to_remove_from;
  1113. p_second_filter->action = ETH_FILTER_ACTION_ADD;
  1114. p_second_filter->vport_id = vport_to_add_to;
  1115. } else if (p_filter_cmd->opcode == QED_FILTER_REPLACE) {
  1116. p_first_filter->vport_id = vport_to_add_to;
  1117. memcpy(p_second_filter, p_first_filter,
  1118. sizeof(*p_second_filter));
  1119. p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL;
  1120. p_second_filter->action = ETH_FILTER_ACTION_ADD;
  1121. } else {
  1122. action = qed_filter_action(p_filter_cmd->opcode);
  1123. if (action == MAX_ETH_FILTER_ACTION) {
  1124. DP_NOTICE(p_hwfn,
  1125. "%d is not supported yet\n",
  1126. p_filter_cmd->opcode);
  1127. return -EINVAL;
  1128. }
  1129. p_first_filter->action = action;
  1130. p_first_filter->vport_id = (p_filter_cmd->opcode ==
  1131. QED_FILTER_REMOVE) ?
  1132. vport_to_remove_from :
  1133. vport_to_add_to;
  1134. }
  1135. return 0;
  1136. }
  1137. int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn,
  1138. u16 opaque_fid,
  1139. struct qed_filter_ucast *p_filter_cmd,
  1140. enum spq_mode comp_mode,
  1141. struct qed_spq_comp_cb *p_comp_data)
  1142. {
  1143. struct vport_filter_update_ramrod_data *p_ramrod = NULL;
  1144. struct qed_spq_entry *p_ent = NULL;
  1145. struct eth_filter_cmd_header *p_header;
  1146. int rc;
  1147. rc = qed_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
  1148. &p_ramrod, &p_ent,
  1149. comp_mode, p_comp_data);
  1150. if (rc) {
  1151. DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
  1152. return rc;
  1153. }
  1154. p_header = &p_ramrod->filter_cmd_hdr;
  1155. p_header->assert_on_error = p_filter_cmd->assert_on_error;
  1156. rc = qed_spq_post(p_hwfn, p_ent, NULL);
  1157. if (rc) {
  1158. DP_ERR(p_hwfn, "Unicast filter ADD command failed %d\n", rc);
  1159. return rc;
  1160. }
  1161. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  1162. "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
  1163. (p_filter_cmd->opcode == QED_FILTER_ADD) ? "ADD" :
  1164. ((p_filter_cmd->opcode == QED_FILTER_REMOVE) ?
  1165. "REMOVE" :
  1166. ((p_filter_cmd->opcode == QED_FILTER_MOVE) ?
  1167. "MOVE" : "REPLACE")),
  1168. (p_filter_cmd->type == QED_FILTER_MAC) ? "MAC" :
  1169. ((p_filter_cmd->type == QED_FILTER_VLAN) ?
  1170. "VLAN" : "MAC & VLAN"),
  1171. p_ramrod->filter_cmd_hdr.cmd_cnt,
  1172. p_filter_cmd->is_rx_filter,
  1173. p_filter_cmd->is_tx_filter);
  1174. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  1175. "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
  1176. p_filter_cmd->vport_to_add_to,
  1177. p_filter_cmd->vport_to_remove_from,
  1178. p_filter_cmd->mac[0],
  1179. p_filter_cmd->mac[1],
  1180. p_filter_cmd->mac[2],
  1181. p_filter_cmd->mac[3],
  1182. p_filter_cmd->mac[4],
  1183. p_filter_cmd->mac[5],
  1184. p_filter_cmd->vlan);
  1185. return 0;
  1186. }
  1187. /*******************************************************************************
  1188. * Description:
  1189. * Calculates crc 32 on a buffer
  1190. * Note: crc32_length MUST be aligned to 8
  1191. * Return:
  1192. ******************************************************************************/
  1193. static u32 qed_calc_crc32c(u8 *crc32_packet,
  1194. u32 crc32_length, u32 crc32_seed, u8 complement)
  1195. {
  1196. u32 byte = 0, bit = 0, crc32_result = crc32_seed;
  1197. u8 msb = 0, current_byte = 0;
  1198. if ((!crc32_packet) ||
  1199. (crc32_length == 0) ||
  1200. ((crc32_length % 8) != 0))
  1201. return crc32_result;
  1202. for (byte = 0; byte < crc32_length; byte++) {
  1203. current_byte = crc32_packet[byte];
  1204. for (bit = 0; bit < 8; bit++) {
  1205. msb = (u8)(crc32_result >> 31);
  1206. crc32_result = crc32_result << 1;
  1207. if (msb != (0x1 & (current_byte >> bit))) {
  1208. crc32_result = crc32_result ^ CRC32_POLY;
  1209. crc32_result |= 1; /*crc32_result[0] = 1;*/
  1210. }
  1211. }
  1212. }
  1213. return crc32_result;
  1214. }
  1215. static u32 qed_crc32c_le(u32 seed, u8 *mac, u32 len)
  1216. {
  1217. u32 packet_buf[2] = { 0 };
  1218. memcpy((u8 *)(&packet_buf[0]), &mac[0], 6);
  1219. return qed_calc_crc32c((u8 *)packet_buf, 8, seed, 0);
  1220. }
  1221. u8 qed_mcast_bin_from_mac(u8 *mac)
  1222. {
  1223. u32 crc = qed_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED,
  1224. mac, ETH_ALEN);
  1225. return crc & 0xff;
  1226. }
  1227. static int
  1228. qed_sp_eth_filter_mcast(struct qed_hwfn *p_hwfn,
  1229. u16 opaque_fid,
  1230. struct qed_filter_mcast *p_filter_cmd,
  1231. enum spq_mode comp_mode,
  1232. struct qed_spq_comp_cb *p_comp_data)
  1233. {
  1234. unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
  1235. struct vport_update_ramrod_data *p_ramrod = NULL;
  1236. struct qed_spq_entry *p_ent = NULL;
  1237. struct qed_sp_init_data init_data;
  1238. u8 abs_vport_id = 0;
  1239. int rc, i;
  1240. if (p_filter_cmd->opcode == QED_FILTER_ADD)
  1241. rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
  1242. &abs_vport_id);
  1243. else
  1244. rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
  1245. &abs_vport_id);
  1246. if (rc)
  1247. return rc;
  1248. /* Get SPQ entry */
  1249. memset(&init_data, 0, sizeof(init_data));
  1250. init_data.cid = qed_spq_get_cid(p_hwfn);
  1251. init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
  1252. init_data.comp_mode = comp_mode;
  1253. init_data.p_comp_data = p_comp_data;
  1254. rc = qed_sp_init_request(p_hwfn, &p_ent,
  1255. ETH_RAMROD_VPORT_UPDATE,
  1256. PROTOCOLID_ETH, &init_data);
  1257. if (rc) {
  1258. DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
  1259. return rc;
  1260. }
  1261. p_ramrod = &p_ent->ramrod.vport_update;
  1262. p_ramrod->common.update_approx_mcast_flg = 1;
  1263. /* explicitly clear out the entire vector */
  1264. memset(&p_ramrod->approx_mcast.bins, 0,
  1265. sizeof(p_ramrod->approx_mcast.bins));
  1266. memset(bins, 0, sizeof(unsigned long) *
  1267. ETH_MULTICAST_MAC_BINS_IN_REGS);
  1268. /* filter ADD op is explicit set op and it removes
  1269. * any existing filters for the vport
  1270. */
  1271. if (p_filter_cmd->opcode == QED_FILTER_ADD) {
  1272. for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
  1273. u32 bit;
  1274. bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]);
  1275. __set_bit(bit, bins);
  1276. }
  1277. /* Convert to correct endianity */
  1278. for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
  1279. struct vport_update_ramrod_mcast *p_ramrod_bins;
  1280. u32 *p_bins = (u32 *)bins;
  1281. p_ramrod_bins = &p_ramrod->approx_mcast;
  1282. p_ramrod_bins->bins[i] = cpu_to_le32(p_bins[i]);
  1283. }
  1284. }
  1285. p_ramrod->common.vport_id = abs_vport_id;
  1286. return qed_spq_post(p_hwfn, p_ent, NULL);
  1287. }
  1288. static int qed_filter_mcast_cmd(struct qed_dev *cdev,
  1289. struct qed_filter_mcast *p_filter_cmd,
  1290. enum spq_mode comp_mode,
  1291. struct qed_spq_comp_cb *p_comp_data)
  1292. {
  1293. int rc = 0;
  1294. int i;
  1295. /* only ADD and REMOVE operations are supported for multi-cast */
  1296. if ((p_filter_cmd->opcode != QED_FILTER_ADD &&
  1297. (p_filter_cmd->opcode != QED_FILTER_REMOVE)) ||
  1298. (p_filter_cmd->num_mc_addrs > QED_MAX_MC_ADDRS))
  1299. return -EINVAL;
  1300. for_each_hwfn(cdev, i) {
  1301. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1302. u16 opaque_fid;
  1303. if (IS_VF(cdev)) {
  1304. qed_vf_pf_filter_mcast(p_hwfn, p_filter_cmd);
  1305. continue;
  1306. }
  1307. opaque_fid = p_hwfn->hw_info.opaque_fid;
  1308. rc = qed_sp_eth_filter_mcast(p_hwfn,
  1309. opaque_fid,
  1310. p_filter_cmd,
  1311. comp_mode, p_comp_data);
  1312. }
  1313. return rc;
  1314. }
  1315. static int qed_filter_ucast_cmd(struct qed_dev *cdev,
  1316. struct qed_filter_ucast *p_filter_cmd,
  1317. enum spq_mode comp_mode,
  1318. struct qed_spq_comp_cb *p_comp_data)
  1319. {
  1320. int rc = 0;
  1321. int i;
  1322. for_each_hwfn(cdev, i) {
  1323. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1324. u16 opaque_fid;
  1325. if (IS_VF(cdev)) {
  1326. rc = qed_vf_pf_filter_ucast(p_hwfn, p_filter_cmd);
  1327. continue;
  1328. }
  1329. opaque_fid = p_hwfn->hw_info.opaque_fid;
  1330. rc = qed_sp_eth_filter_ucast(p_hwfn,
  1331. opaque_fid,
  1332. p_filter_cmd,
  1333. comp_mode, p_comp_data);
  1334. if (rc)
  1335. break;
  1336. }
  1337. return rc;
  1338. }
  1339. /* Statistics related code */
  1340. static void __qed_get_vport_pstats_addrlen(struct qed_hwfn *p_hwfn,
  1341. u32 *p_addr,
  1342. u32 *p_len, u16 statistics_bin)
  1343. {
  1344. if (IS_PF(p_hwfn->cdev)) {
  1345. *p_addr = BAR0_MAP_REG_PSDM_RAM +
  1346. PSTORM_QUEUE_STAT_OFFSET(statistics_bin);
  1347. *p_len = sizeof(struct eth_pstorm_per_queue_stat);
  1348. } else {
  1349. struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
  1350. struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
  1351. *p_addr = p_resp->pfdev_info.stats_info.pstats.address;
  1352. *p_len = p_resp->pfdev_info.stats_info.pstats.len;
  1353. }
  1354. }
  1355. static void __qed_get_vport_pstats(struct qed_hwfn *p_hwfn,
  1356. struct qed_ptt *p_ptt,
  1357. struct qed_eth_stats *p_stats,
  1358. u16 statistics_bin)
  1359. {
  1360. struct eth_pstorm_per_queue_stat pstats;
  1361. u32 pstats_addr = 0, pstats_len = 0;
  1362. __qed_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len,
  1363. statistics_bin);
  1364. memset(&pstats, 0, sizeof(pstats));
  1365. qed_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len);
  1366. p_stats->common.tx_ucast_bytes +=
  1367. HILO_64_REGPAIR(pstats.sent_ucast_bytes);
  1368. p_stats->common.tx_mcast_bytes +=
  1369. HILO_64_REGPAIR(pstats.sent_mcast_bytes);
  1370. p_stats->common.tx_bcast_bytes +=
  1371. HILO_64_REGPAIR(pstats.sent_bcast_bytes);
  1372. p_stats->common.tx_ucast_pkts +=
  1373. HILO_64_REGPAIR(pstats.sent_ucast_pkts);
  1374. p_stats->common.tx_mcast_pkts +=
  1375. HILO_64_REGPAIR(pstats.sent_mcast_pkts);
  1376. p_stats->common.tx_bcast_pkts +=
  1377. HILO_64_REGPAIR(pstats.sent_bcast_pkts);
  1378. p_stats->common.tx_err_drop_pkts +=
  1379. HILO_64_REGPAIR(pstats.error_drop_pkts);
  1380. }
  1381. static void __qed_get_vport_tstats(struct qed_hwfn *p_hwfn,
  1382. struct qed_ptt *p_ptt,
  1383. struct qed_eth_stats *p_stats,
  1384. u16 statistics_bin)
  1385. {
  1386. struct tstorm_per_port_stat tstats;
  1387. u32 tstats_addr, tstats_len;
  1388. if (IS_PF(p_hwfn->cdev)) {
  1389. tstats_addr = BAR0_MAP_REG_TSDM_RAM +
  1390. TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
  1391. tstats_len = sizeof(struct tstorm_per_port_stat);
  1392. } else {
  1393. struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
  1394. struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
  1395. tstats_addr = p_resp->pfdev_info.stats_info.tstats.address;
  1396. tstats_len = p_resp->pfdev_info.stats_info.tstats.len;
  1397. }
  1398. memset(&tstats, 0, sizeof(tstats));
  1399. qed_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len);
  1400. p_stats->common.mftag_filter_discards +=
  1401. HILO_64_REGPAIR(tstats.mftag_filter_discard);
  1402. p_stats->common.mac_filter_discards +=
  1403. HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
  1404. p_stats->common.gft_filter_drop +=
  1405. HILO_64_REGPAIR(tstats.eth_gft_drop_pkt);
  1406. }
  1407. static void __qed_get_vport_ustats_addrlen(struct qed_hwfn *p_hwfn,
  1408. u32 *p_addr,
  1409. u32 *p_len, u16 statistics_bin)
  1410. {
  1411. if (IS_PF(p_hwfn->cdev)) {
  1412. *p_addr = BAR0_MAP_REG_USDM_RAM +
  1413. USTORM_QUEUE_STAT_OFFSET(statistics_bin);
  1414. *p_len = sizeof(struct eth_ustorm_per_queue_stat);
  1415. } else {
  1416. struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
  1417. struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
  1418. *p_addr = p_resp->pfdev_info.stats_info.ustats.address;
  1419. *p_len = p_resp->pfdev_info.stats_info.ustats.len;
  1420. }
  1421. }
  1422. static void __qed_get_vport_ustats(struct qed_hwfn *p_hwfn,
  1423. struct qed_ptt *p_ptt,
  1424. struct qed_eth_stats *p_stats,
  1425. u16 statistics_bin)
  1426. {
  1427. struct eth_ustorm_per_queue_stat ustats;
  1428. u32 ustats_addr = 0, ustats_len = 0;
  1429. __qed_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len,
  1430. statistics_bin);
  1431. memset(&ustats, 0, sizeof(ustats));
  1432. qed_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len);
  1433. p_stats->common.rx_ucast_bytes +=
  1434. HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
  1435. p_stats->common.rx_mcast_bytes +=
  1436. HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
  1437. p_stats->common.rx_bcast_bytes +=
  1438. HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
  1439. p_stats->common.rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
  1440. p_stats->common.rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
  1441. p_stats->common.rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
  1442. }
  1443. static void __qed_get_vport_mstats_addrlen(struct qed_hwfn *p_hwfn,
  1444. u32 *p_addr,
  1445. u32 *p_len, u16 statistics_bin)
  1446. {
  1447. if (IS_PF(p_hwfn->cdev)) {
  1448. *p_addr = BAR0_MAP_REG_MSDM_RAM +
  1449. MSTORM_QUEUE_STAT_OFFSET(statistics_bin);
  1450. *p_len = sizeof(struct eth_mstorm_per_queue_stat);
  1451. } else {
  1452. struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
  1453. struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
  1454. *p_addr = p_resp->pfdev_info.stats_info.mstats.address;
  1455. *p_len = p_resp->pfdev_info.stats_info.mstats.len;
  1456. }
  1457. }
  1458. static void __qed_get_vport_mstats(struct qed_hwfn *p_hwfn,
  1459. struct qed_ptt *p_ptt,
  1460. struct qed_eth_stats *p_stats,
  1461. u16 statistics_bin)
  1462. {
  1463. struct eth_mstorm_per_queue_stat mstats;
  1464. u32 mstats_addr = 0, mstats_len = 0;
  1465. __qed_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len,
  1466. statistics_bin);
  1467. memset(&mstats, 0, sizeof(mstats));
  1468. qed_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len);
  1469. p_stats->common.no_buff_discards +=
  1470. HILO_64_REGPAIR(mstats.no_buff_discard);
  1471. p_stats->common.packet_too_big_discard +=
  1472. HILO_64_REGPAIR(mstats.packet_too_big_discard);
  1473. p_stats->common.ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard);
  1474. p_stats->common.tpa_coalesced_pkts +=
  1475. HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
  1476. p_stats->common.tpa_coalesced_events +=
  1477. HILO_64_REGPAIR(mstats.tpa_coalesced_events);
  1478. p_stats->common.tpa_aborts_num +=
  1479. HILO_64_REGPAIR(mstats.tpa_aborts_num);
  1480. p_stats->common.tpa_coalesced_bytes +=
  1481. HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
  1482. }
  1483. static void __qed_get_vport_port_stats(struct qed_hwfn *p_hwfn,
  1484. struct qed_ptt *p_ptt,
  1485. struct qed_eth_stats *p_stats)
  1486. {
  1487. struct qed_eth_stats_common *p_common = &p_stats->common;
  1488. struct port_stats port_stats;
  1489. int j;
  1490. memset(&port_stats, 0, sizeof(port_stats));
  1491. qed_memcpy_from(p_hwfn, p_ptt, &port_stats,
  1492. p_hwfn->mcp_info->port_addr +
  1493. offsetof(struct public_port, stats),
  1494. sizeof(port_stats));
  1495. p_common->rx_64_byte_packets += port_stats.eth.r64;
  1496. p_common->rx_65_to_127_byte_packets += port_stats.eth.r127;
  1497. p_common->rx_128_to_255_byte_packets += port_stats.eth.r255;
  1498. p_common->rx_256_to_511_byte_packets += port_stats.eth.r511;
  1499. p_common->rx_512_to_1023_byte_packets += port_stats.eth.r1023;
  1500. p_common->rx_1024_to_1518_byte_packets += port_stats.eth.r1518;
  1501. p_common->rx_crc_errors += port_stats.eth.rfcs;
  1502. p_common->rx_mac_crtl_frames += port_stats.eth.rxcf;
  1503. p_common->rx_pause_frames += port_stats.eth.rxpf;
  1504. p_common->rx_pfc_frames += port_stats.eth.rxpp;
  1505. p_common->rx_align_errors += port_stats.eth.raln;
  1506. p_common->rx_carrier_errors += port_stats.eth.rfcr;
  1507. p_common->rx_oversize_packets += port_stats.eth.rovr;
  1508. p_common->rx_jabbers += port_stats.eth.rjbr;
  1509. p_common->rx_undersize_packets += port_stats.eth.rund;
  1510. p_common->rx_fragments += port_stats.eth.rfrg;
  1511. p_common->tx_64_byte_packets += port_stats.eth.t64;
  1512. p_common->tx_65_to_127_byte_packets += port_stats.eth.t127;
  1513. p_common->tx_128_to_255_byte_packets += port_stats.eth.t255;
  1514. p_common->tx_256_to_511_byte_packets += port_stats.eth.t511;
  1515. p_common->tx_512_to_1023_byte_packets += port_stats.eth.t1023;
  1516. p_common->tx_1024_to_1518_byte_packets += port_stats.eth.t1518;
  1517. p_common->tx_pause_frames += port_stats.eth.txpf;
  1518. p_common->tx_pfc_frames += port_stats.eth.txpp;
  1519. p_common->rx_mac_bytes += port_stats.eth.rbyte;
  1520. p_common->rx_mac_uc_packets += port_stats.eth.rxuca;
  1521. p_common->rx_mac_mc_packets += port_stats.eth.rxmca;
  1522. p_common->rx_mac_bc_packets += port_stats.eth.rxbca;
  1523. p_common->rx_mac_frames_ok += port_stats.eth.rxpok;
  1524. p_common->tx_mac_bytes += port_stats.eth.tbyte;
  1525. p_common->tx_mac_uc_packets += port_stats.eth.txuca;
  1526. p_common->tx_mac_mc_packets += port_stats.eth.txmca;
  1527. p_common->tx_mac_bc_packets += port_stats.eth.txbca;
  1528. p_common->tx_mac_ctrl_frames += port_stats.eth.txcf;
  1529. for (j = 0; j < 8; j++) {
  1530. p_common->brb_truncates += port_stats.brb.brb_truncate[j];
  1531. p_common->brb_discards += port_stats.brb.brb_discard[j];
  1532. }
  1533. if (QED_IS_BB(p_hwfn->cdev)) {
  1534. struct qed_eth_stats_bb *p_bb = &p_stats->bb;
  1535. p_bb->rx_1519_to_1522_byte_packets +=
  1536. port_stats.eth.u0.bb0.r1522;
  1537. p_bb->rx_1519_to_2047_byte_packets +=
  1538. port_stats.eth.u0.bb0.r2047;
  1539. p_bb->rx_2048_to_4095_byte_packets +=
  1540. port_stats.eth.u0.bb0.r4095;
  1541. p_bb->rx_4096_to_9216_byte_packets +=
  1542. port_stats.eth.u0.bb0.r9216;
  1543. p_bb->rx_9217_to_16383_byte_packets +=
  1544. port_stats.eth.u0.bb0.r16383;
  1545. p_bb->tx_1519_to_2047_byte_packets +=
  1546. port_stats.eth.u1.bb1.t2047;
  1547. p_bb->tx_2048_to_4095_byte_packets +=
  1548. port_stats.eth.u1.bb1.t4095;
  1549. p_bb->tx_4096_to_9216_byte_packets +=
  1550. port_stats.eth.u1.bb1.t9216;
  1551. p_bb->tx_9217_to_16383_byte_packets +=
  1552. port_stats.eth.u1.bb1.t16383;
  1553. p_bb->tx_lpi_entry_count += port_stats.eth.u2.bb2.tlpiec;
  1554. p_bb->tx_total_collisions += port_stats.eth.u2.bb2.tncl;
  1555. } else {
  1556. struct qed_eth_stats_ah *p_ah = &p_stats->ah;
  1557. p_ah->rx_1519_to_max_byte_packets +=
  1558. port_stats.eth.u0.ah0.r1519_to_max;
  1559. p_ah->tx_1519_to_max_byte_packets =
  1560. port_stats.eth.u1.ah1.t1519_to_max;
  1561. }
  1562. p_common->link_change_count = qed_rd(p_hwfn, p_ptt,
  1563. p_hwfn->mcp_info->port_addr +
  1564. offsetof(struct public_port,
  1565. link_change_count));
  1566. }
  1567. static void __qed_get_vport_stats(struct qed_hwfn *p_hwfn,
  1568. struct qed_ptt *p_ptt,
  1569. struct qed_eth_stats *stats,
  1570. u16 statistics_bin, bool b_get_port_stats)
  1571. {
  1572. __qed_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin);
  1573. __qed_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin);
  1574. __qed_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin);
  1575. __qed_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin);
  1576. if (b_get_port_stats && p_hwfn->mcp_info)
  1577. __qed_get_vport_port_stats(p_hwfn, p_ptt, stats);
  1578. }
  1579. static void _qed_get_vport_stats(struct qed_dev *cdev,
  1580. struct qed_eth_stats *stats)
  1581. {
  1582. u8 fw_vport = 0;
  1583. int i;
  1584. memset(stats, 0, sizeof(*stats));
  1585. for_each_hwfn(cdev, i) {
  1586. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1587. struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
  1588. : NULL;
  1589. if (IS_PF(cdev)) {
  1590. /* The main vport index is relative first */
  1591. if (qed_fw_vport(p_hwfn, 0, &fw_vport)) {
  1592. DP_ERR(p_hwfn, "No vport available!\n");
  1593. goto out;
  1594. }
  1595. }
  1596. if (IS_PF(cdev) && !p_ptt) {
  1597. DP_ERR(p_hwfn, "Failed to acquire ptt\n");
  1598. continue;
  1599. }
  1600. __qed_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport,
  1601. IS_PF(cdev) ? true : false);
  1602. out:
  1603. if (IS_PF(cdev) && p_ptt)
  1604. qed_ptt_release(p_hwfn, p_ptt);
  1605. }
  1606. }
  1607. void qed_get_vport_stats(struct qed_dev *cdev, struct qed_eth_stats *stats)
  1608. {
  1609. u32 i;
  1610. if (!cdev) {
  1611. memset(stats, 0, sizeof(*stats));
  1612. return;
  1613. }
  1614. _qed_get_vport_stats(cdev, stats);
  1615. if (!cdev->reset_stats)
  1616. return;
  1617. /* Reduce the statistics baseline */
  1618. for (i = 0; i < sizeof(struct qed_eth_stats) / sizeof(u64); i++)
  1619. ((u64 *)stats)[i] -= ((u64 *)cdev->reset_stats)[i];
  1620. }
  1621. /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
  1622. void qed_reset_vport_stats(struct qed_dev *cdev)
  1623. {
  1624. int i;
  1625. for_each_hwfn(cdev, i) {
  1626. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1627. struct eth_mstorm_per_queue_stat mstats;
  1628. struct eth_ustorm_per_queue_stat ustats;
  1629. struct eth_pstorm_per_queue_stat pstats;
  1630. struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
  1631. : NULL;
  1632. u32 addr = 0, len = 0;
  1633. if (IS_PF(cdev) && !p_ptt) {
  1634. DP_ERR(p_hwfn, "Failed to acquire ptt\n");
  1635. continue;
  1636. }
  1637. memset(&mstats, 0, sizeof(mstats));
  1638. __qed_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0);
  1639. qed_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len);
  1640. memset(&ustats, 0, sizeof(ustats));
  1641. __qed_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0);
  1642. qed_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len);
  1643. memset(&pstats, 0, sizeof(pstats));
  1644. __qed_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0);
  1645. qed_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len);
  1646. if (IS_PF(cdev))
  1647. qed_ptt_release(p_hwfn, p_ptt);
  1648. }
  1649. /* PORT statistics are not necessarily reset, so we need to
  1650. * read and create a baseline for future statistics.
  1651. * Link change stat is maintained by MFW, return its value as is.
  1652. */
  1653. if (!cdev->reset_stats) {
  1654. DP_INFO(cdev, "Reset stats not allocated\n");
  1655. } else {
  1656. _qed_get_vport_stats(cdev, cdev->reset_stats);
  1657. cdev->reset_stats->common.link_change_count = 0;
  1658. }
  1659. }
  1660. static enum gft_profile_type
  1661. qed_arfs_mode_to_hsi(enum qed_filter_config_mode mode)
  1662. {
  1663. if (mode == QED_FILTER_CONFIG_MODE_5_TUPLE)
  1664. return GFT_PROFILE_TYPE_4_TUPLE;
  1665. if (mode == QED_FILTER_CONFIG_MODE_IP_DEST)
  1666. return GFT_PROFILE_TYPE_IP_DST_ADDR;
  1667. if (mode == QED_FILTER_CONFIG_MODE_IP_SRC)
  1668. return GFT_PROFILE_TYPE_IP_SRC_ADDR;
  1669. return GFT_PROFILE_TYPE_L4_DST_PORT;
  1670. }
  1671. void qed_arfs_mode_configure(struct qed_hwfn *p_hwfn,
  1672. struct qed_ptt *p_ptt,
  1673. struct qed_arfs_config_params *p_cfg_params)
  1674. {
  1675. if (p_cfg_params->mode != QED_FILTER_CONFIG_MODE_DISABLE) {
  1676. qed_gft_config(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
  1677. p_cfg_params->tcp,
  1678. p_cfg_params->udp,
  1679. p_cfg_params->ipv4,
  1680. p_cfg_params->ipv6,
  1681. qed_arfs_mode_to_hsi(p_cfg_params->mode));
  1682. DP_VERBOSE(p_hwfn,
  1683. QED_MSG_SP,
  1684. "Configured Filtering: tcp = %s, udp = %s, ipv4 = %s, ipv6 =%s mode=%08x\n",
  1685. p_cfg_params->tcp ? "Enable" : "Disable",
  1686. p_cfg_params->udp ? "Enable" : "Disable",
  1687. p_cfg_params->ipv4 ? "Enable" : "Disable",
  1688. p_cfg_params->ipv6 ? "Enable" : "Disable",
  1689. (u32)p_cfg_params->mode);
  1690. } else {
  1691. DP_VERBOSE(p_hwfn, QED_MSG_SP, "Disabled Filtering\n");
  1692. qed_gft_disable(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
  1693. }
  1694. }
  1695. int
  1696. qed_configure_rfs_ntuple_filter(struct qed_hwfn *p_hwfn,
  1697. struct qed_spq_comp_cb *p_cb,
  1698. struct qed_ntuple_filter_params *p_params)
  1699. {
  1700. struct rx_update_gft_filter_data *p_ramrod = NULL;
  1701. struct qed_spq_entry *p_ent = NULL;
  1702. struct qed_sp_init_data init_data;
  1703. u16 abs_rx_q_id = 0;
  1704. u8 abs_vport_id = 0;
  1705. int rc = -EINVAL;
  1706. /* Get SPQ entry */
  1707. memset(&init_data, 0, sizeof(init_data));
  1708. init_data.cid = qed_spq_get_cid(p_hwfn);
  1709. init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
  1710. if (p_cb) {
  1711. init_data.comp_mode = QED_SPQ_MODE_CB;
  1712. init_data.p_comp_data = p_cb;
  1713. } else {
  1714. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  1715. }
  1716. rc = qed_sp_init_request(p_hwfn, &p_ent,
  1717. ETH_RAMROD_GFT_UPDATE_FILTER,
  1718. PROTOCOLID_ETH, &init_data);
  1719. if (rc)
  1720. return rc;
  1721. p_ramrod = &p_ent->ramrod.rx_update_gft;
  1722. DMA_REGPAIR_LE(p_ramrod->pkt_hdr_addr, p_params->addr);
  1723. p_ramrod->pkt_hdr_length = cpu_to_le16(p_params->length);
  1724. if (p_params->b_is_drop) {
  1725. p_ramrod->vport_id = cpu_to_le16(ETH_GFT_TRASHCAN_VPORT);
  1726. } else {
  1727. rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
  1728. if (rc)
  1729. return rc;
  1730. if (p_params->qid != QED_RFS_NTUPLE_QID_RSS) {
  1731. rc = qed_fw_l2_queue(p_hwfn, p_params->qid,
  1732. &abs_rx_q_id);
  1733. if (rc)
  1734. return rc;
  1735. p_ramrod->rx_qid_valid = 1;
  1736. p_ramrod->rx_qid = cpu_to_le16(abs_rx_q_id);
  1737. }
  1738. p_ramrod->vport_id = cpu_to_le16((u16)abs_vport_id);
  1739. }
  1740. p_ramrod->flow_id_valid = 0;
  1741. p_ramrod->flow_id = 0;
  1742. p_ramrod->filter_action = p_params->b_is_add ? GFT_ADD_FILTER
  1743. : GFT_DELETE_FILTER;
  1744. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  1745. "V[%0x], Q[%04x] - %s filter from 0x%llx [length %04xb]\n",
  1746. abs_vport_id, abs_rx_q_id,
  1747. p_params->b_is_add ? "Adding" : "Removing",
  1748. (u64)p_params->addr, p_params->length);
  1749. return qed_spq_post(p_hwfn, p_ent, NULL);
  1750. }
  1751. int qed_get_rxq_coalesce(struct qed_hwfn *p_hwfn,
  1752. struct qed_ptt *p_ptt,
  1753. struct qed_queue_cid *p_cid, u16 *p_rx_coal)
  1754. {
  1755. u32 coalesce, address, is_valid;
  1756. struct cau_sb_entry sb_entry;
  1757. u8 timer_res;
  1758. int rc;
  1759. rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
  1760. p_cid->sb_igu_id * sizeof(u64),
  1761. (u64)(uintptr_t)&sb_entry, 2, 0);
  1762. if (rc) {
  1763. DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
  1764. return rc;
  1765. }
  1766. timer_res = GET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0);
  1767. address = BAR0_MAP_REG_USDM_RAM +
  1768. USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
  1769. coalesce = qed_rd(p_hwfn, p_ptt, address);
  1770. is_valid = GET_FIELD(coalesce, COALESCING_TIMESET_VALID);
  1771. if (!is_valid)
  1772. return -EINVAL;
  1773. coalesce = GET_FIELD(coalesce, COALESCING_TIMESET_TIMESET);
  1774. *p_rx_coal = (u16)(coalesce << timer_res);
  1775. return 0;
  1776. }
  1777. int qed_get_txq_coalesce(struct qed_hwfn *p_hwfn,
  1778. struct qed_ptt *p_ptt,
  1779. struct qed_queue_cid *p_cid, u16 *p_tx_coal)
  1780. {
  1781. u32 coalesce, address, is_valid;
  1782. struct cau_sb_entry sb_entry;
  1783. u8 timer_res;
  1784. int rc;
  1785. rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
  1786. p_cid->sb_igu_id * sizeof(u64),
  1787. (u64)(uintptr_t)&sb_entry, 2, 0);
  1788. if (rc) {
  1789. DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
  1790. return rc;
  1791. }
  1792. timer_res = GET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1);
  1793. address = BAR0_MAP_REG_XSDM_RAM +
  1794. XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
  1795. coalesce = qed_rd(p_hwfn, p_ptt, address);
  1796. is_valid = GET_FIELD(coalesce, COALESCING_TIMESET_VALID);
  1797. if (!is_valid)
  1798. return -EINVAL;
  1799. coalesce = GET_FIELD(coalesce, COALESCING_TIMESET_TIMESET);
  1800. *p_tx_coal = (u16)(coalesce << timer_res);
  1801. return 0;
  1802. }
  1803. int qed_get_queue_coalesce(struct qed_hwfn *p_hwfn, u16 *p_coal, void *handle)
  1804. {
  1805. struct qed_queue_cid *p_cid = handle;
  1806. struct qed_ptt *p_ptt;
  1807. int rc = 0;
  1808. if (IS_VF(p_hwfn->cdev)) {
  1809. rc = qed_vf_pf_get_coalesce(p_hwfn, p_coal, p_cid);
  1810. if (rc)
  1811. DP_NOTICE(p_hwfn, "Unable to read queue coalescing\n");
  1812. return rc;
  1813. }
  1814. p_ptt = qed_ptt_acquire(p_hwfn);
  1815. if (!p_ptt)
  1816. return -EAGAIN;
  1817. if (p_cid->b_is_rx) {
  1818. rc = qed_get_rxq_coalesce(p_hwfn, p_ptt, p_cid, p_coal);
  1819. if (rc)
  1820. goto out;
  1821. } else {
  1822. rc = qed_get_txq_coalesce(p_hwfn, p_ptt, p_cid, p_coal);
  1823. if (rc)
  1824. goto out;
  1825. }
  1826. out:
  1827. qed_ptt_release(p_hwfn, p_ptt);
  1828. return rc;
  1829. }
  1830. static int qed_fill_eth_dev_info(struct qed_dev *cdev,
  1831. struct qed_dev_eth_info *info)
  1832. {
  1833. int i;
  1834. memset(info, 0, sizeof(*info));
  1835. info->num_tc = 1;
  1836. if (IS_PF(cdev)) {
  1837. int max_vf_vlan_filters = 0;
  1838. int max_vf_mac_filters = 0;
  1839. if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
  1840. u16 num_queues = 0;
  1841. /* Since the feature controls only queue-zones,
  1842. * make sure we have the contexts [rx, tx, xdp] to
  1843. * match.
  1844. */
  1845. for_each_hwfn(cdev, i) {
  1846. struct qed_hwfn *hwfn = &cdev->hwfns[i];
  1847. u16 l2_queues = (u16)FEAT_NUM(hwfn,
  1848. QED_PF_L2_QUE);
  1849. u16 cids;
  1850. cids = hwfn->pf_params.eth_pf_params.num_cons;
  1851. num_queues += min_t(u16, l2_queues, cids / 3);
  1852. }
  1853. /* queues might theoretically be >256, but interrupts'
  1854. * upper-limit guarantes that it would fit in a u8.
  1855. */
  1856. if (cdev->int_params.fp_msix_cnt) {
  1857. u8 irqs = cdev->int_params.fp_msix_cnt;
  1858. info->num_queues = (u8)min_t(u16,
  1859. num_queues, irqs);
  1860. }
  1861. } else {
  1862. info->num_queues = cdev->num_hwfns;
  1863. }
  1864. if (IS_QED_SRIOV(cdev)) {
  1865. max_vf_vlan_filters = cdev->p_iov_info->total_vfs *
  1866. QED_ETH_VF_NUM_VLAN_FILTERS;
  1867. max_vf_mac_filters = cdev->p_iov_info->total_vfs *
  1868. QED_ETH_VF_NUM_MAC_FILTERS;
  1869. }
  1870. info->num_vlan_filters = RESC_NUM(QED_LEADING_HWFN(cdev),
  1871. QED_VLAN) -
  1872. max_vf_vlan_filters;
  1873. info->num_mac_filters = RESC_NUM(QED_LEADING_HWFN(cdev),
  1874. QED_MAC) -
  1875. max_vf_mac_filters;
  1876. ether_addr_copy(info->port_mac,
  1877. cdev->hwfns[0].hw_info.hw_mac_addr);
  1878. info->xdp_supported = true;
  1879. } else {
  1880. u16 total_cids = 0;
  1881. /* Determine queues & XDP support */
  1882. for_each_hwfn(cdev, i) {
  1883. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1884. u8 queues, cids;
  1885. qed_vf_get_num_cids(p_hwfn, &cids);
  1886. qed_vf_get_num_rxqs(p_hwfn, &queues);
  1887. info->num_queues += queues;
  1888. total_cids += cids;
  1889. }
  1890. /* Enable VF XDP in case PF guarntees sufficient connections */
  1891. if (total_cids >= info->num_queues * 3)
  1892. info->xdp_supported = true;
  1893. qed_vf_get_num_vlan_filters(&cdev->hwfns[0],
  1894. (u8 *)&info->num_vlan_filters);
  1895. qed_vf_get_num_mac_filters(&cdev->hwfns[0],
  1896. (u8 *)&info->num_mac_filters);
  1897. qed_vf_get_port_mac(&cdev->hwfns[0], info->port_mac);
  1898. info->is_legacy = !!cdev->hwfns[0].vf_iov_info->b_pre_fp_hsi;
  1899. }
  1900. qed_fill_dev_info(cdev, &info->common);
  1901. if (IS_VF(cdev))
  1902. eth_zero_addr(info->common.hw_mac);
  1903. return 0;
  1904. }
  1905. static void qed_register_eth_ops(struct qed_dev *cdev,
  1906. struct qed_eth_cb_ops *ops, void *cookie)
  1907. {
  1908. cdev->protocol_ops.eth = ops;
  1909. cdev->ops_cookie = cookie;
  1910. /* For VF, we start bulletin reading */
  1911. if (IS_VF(cdev))
  1912. qed_vf_start_iov_wq(cdev);
  1913. }
  1914. static bool qed_check_mac(struct qed_dev *cdev, u8 *mac)
  1915. {
  1916. if (IS_PF(cdev))
  1917. return true;
  1918. return qed_vf_check_mac(&cdev->hwfns[0], mac);
  1919. }
  1920. static int qed_start_vport(struct qed_dev *cdev,
  1921. struct qed_start_vport_params *params)
  1922. {
  1923. int rc, i;
  1924. for_each_hwfn(cdev, i) {
  1925. struct qed_sp_vport_start_params start = { 0 };
  1926. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1927. start.tpa_mode = params->gro_enable ? QED_TPA_MODE_GRO :
  1928. QED_TPA_MODE_NONE;
  1929. start.remove_inner_vlan = params->remove_inner_vlan;
  1930. start.only_untagged = true; /* untagged only */
  1931. start.drop_ttl0 = params->drop_ttl0;
  1932. start.opaque_fid = p_hwfn->hw_info.opaque_fid;
  1933. start.concrete_fid = p_hwfn->hw_info.concrete_fid;
  1934. start.handle_ptp_pkts = params->handle_ptp_pkts;
  1935. start.vport_id = params->vport_id;
  1936. start.max_buffers_per_cqe = 16;
  1937. start.mtu = params->mtu;
  1938. rc = qed_sp_vport_start(p_hwfn, &start);
  1939. if (rc) {
  1940. DP_ERR(cdev, "Failed to start VPORT\n");
  1941. return rc;
  1942. }
  1943. rc = qed_hw_start_fastpath(p_hwfn);
  1944. if (rc) {
  1945. DP_ERR(cdev, "Failed to start VPORT fastpath\n");
  1946. return rc;
  1947. }
  1948. DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
  1949. "Started V-PORT %d with MTU %d\n",
  1950. start.vport_id, start.mtu);
  1951. }
  1952. if (params->clear_stats)
  1953. qed_reset_vport_stats(cdev);
  1954. return 0;
  1955. }
  1956. static int qed_stop_vport(struct qed_dev *cdev, u8 vport_id)
  1957. {
  1958. int rc, i;
  1959. for_each_hwfn(cdev, i) {
  1960. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1961. rc = qed_sp_vport_stop(p_hwfn,
  1962. p_hwfn->hw_info.opaque_fid, vport_id);
  1963. if (rc) {
  1964. DP_ERR(cdev, "Failed to stop VPORT\n");
  1965. return rc;
  1966. }
  1967. }
  1968. return 0;
  1969. }
  1970. static int qed_update_vport_rss(struct qed_dev *cdev,
  1971. struct qed_update_vport_rss_params *input,
  1972. struct qed_rss_params *rss)
  1973. {
  1974. int i, fn;
  1975. /* Update configuration with what's correct regardless of CMT */
  1976. rss->update_rss_config = 1;
  1977. rss->rss_enable = 1;
  1978. rss->update_rss_capabilities = 1;
  1979. rss->update_rss_ind_table = 1;
  1980. rss->update_rss_key = 1;
  1981. rss->rss_caps = input->rss_caps;
  1982. memcpy(rss->rss_key, input->rss_key, QED_RSS_KEY_SIZE * sizeof(u32));
  1983. /* In regular scenario, we'd simply need to take input handlers.
  1984. * But in CMT, we'd have to split the handlers according to the
  1985. * engine they were configured on. We'd then have to understand
  1986. * whether RSS is really required, since 2-queues on CMT doesn't
  1987. * require RSS.
  1988. */
  1989. if (cdev->num_hwfns == 1) {
  1990. memcpy(rss->rss_ind_table,
  1991. input->rss_ind_table,
  1992. QED_RSS_IND_TABLE_SIZE * sizeof(void *));
  1993. rss->rss_table_size_log = 7;
  1994. return 0;
  1995. }
  1996. /* Start by copying the non-spcific information to the 2nd copy */
  1997. memcpy(&rss[1], &rss[0], sizeof(struct qed_rss_params));
  1998. /* CMT should be round-robin */
  1999. for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
  2000. struct qed_queue_cid *cid = input->rss_ind_table[i];
  2001. struct qed_rss_params *t_rss;
  2002. if (cid->p_owner == QED_LEADING_HWFN(cdev))
  2003. t_rss = &rss[0];
  2004. else
  2005. t_rss = &rss[1];
  2006. t_rss->rss_ind_table[i / cdev->num_hwfns] = cid;
  2007. }
  2008. /* Make sure RSS is actually required */
  2009. for_each_hwfn(cdev, fn) {
  2010. for (i = 1; i < QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns; i++) {
  2011. if (rss[fn].rss_ind_table[i] !=
  2012. rss[fn].rss_ind_table[0])
  2013. break;
  2014. }
  2015. if (i == QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns) {
  2016. DP_VERBOSE(cdev, NETIF_MSG_IFUP,
  2017. "CMT - 1 queue per-hwfn; Disabling RSS\n");
  2018. return -EINVAL;
  2019. }
  2020. rss[fn].rss_table_size_log = 6;
  2021. }
  2022. return 0;
  2023. }
  2024. static int qed_update_vport(struct qed_dev *cdev,
  2025. struct qed_update_vport_params *params)
  2026. {
  2027. struct qed_sp_vport_update_params sp_params;
  2028. struct qed_rss_params *rss;
  2029. int rc = 0, i;
  2030. if (!cdev)
  2031. return -ENODEV;
  2032. rss = vzalloc(array_size(sizeof(*rss), cdev->num_hwfns));
  2033. if (!rss)
  2034. return -ENOMEM;
  2035. memset(&sp_params, 0, sizeof(sp_params));
  2036. /* Translate protocol params into sp params */
  2037. sp_params.vport_id = params->vport_id;
  2038. sp_params.update_vport_active_rx_flg = params->update_vport_active_flg;
  2039. sp_params.update_vport_active_tx_flg = params->update_vport_active_flg;
  2040. sp_params.vport_active_rx_flg = params->vport_active_flg;
  2041. sp_params.vport_active_tx_flg = params->vport_active_flg;
  2042. sp_params.update_tx_switching_flg = params->update_tx_switching_flg;
  2043. sp_params.tx_switching_flg = params->tx_switching_flg;
  2044. sp_params.accept_any_vlan = params->accept_any_vlan;
  2045. sp_params.update_accept_any_vlan_flg =
  2046. params->update_accept_any_vlan_flg;
  2047. /* Prepare the RSS configuration */
  2048. if (params->update_rss_flg)
  2049. if (qed_update_vport_rss(cdev, &params->rss_params, rss))
  2050. params->update_rss_flg = 0;
  2051. for_each_hwfn(cdev, i) {
  2052. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  2053. if (params->update_rss_flg)
  2054. sp_params.rss_params = &rss[i];
  2055. sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
  2056. rc = qed_sp_vport_update(p_hwfn, &sp_params,
  2057. QED_SPQ_MODE_EBLOCK,
  2058. NULL);
  2059. if (rc) {
  2060. DP_ERR(cdev, "Failed to update VPORT\n");
  2061. goto out;
  2062. }
  2063. DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
  2064. "Updated V-PORT %d: active_flag %d [update %d]\n",
  2065. params->vport_id, params->vport_active_flg,
  2066. params->update_vport_active_flg);
  2067. }
  2068. out:
  2069. vfree(rss);
  2070. return rc;
  2071. }
  2072. static int qed_start_rxq(struct qed_dev *cdev,
  2073. u8 rss_num,
  2074. struct qed_queue_start_common_params *p_params,
  2075. u16 bd_max_bytes,
  2076. dma_addr_t bd_chain_phys_addr,
  2077. dma_addr_t cqe_pbl_addr,
  2078. u16 cqe_pbl_size,
  2079. struct qed_rxq_start_ret_params *ret_params)
  2080. {
  2081. struct qed_hwfn *p_hwfn;
  2082. int rc, hwfn_index;
  2083. hwfn_index = rss_num % cdev->num_hwfns;
  2084. p_hwfn = &cdev->hwfns[hwfn_index];
  2085. p_params->queue_id = p_params->queue_id / cdev->num_hwfns;
  2086. p_params->stats_id = p_params->vport_id;
  2087. rc = qed_eth_rx_queue_start(p_hwfn,
  2088. p_hwfn->hw_info.opaque_fid,
  2089. p_params,
  2090. bd_max_bytes,
  2091. bd_chain_phys_addr,
  2092. cqe_pbl_addr, cqe_pbl_size, ret_params);
  2093. if (rc) {
  2094. DP_ERR(cdev, "Failed to start RXQ#%d\n", p_params->queue_id);
  2095. return rc;
  2096. }
  2097. DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
  2098. "Started RX-Q %d [rss_num %d] on V-PORT %d and SB igu %d\n",
  2099. p_params->queue_id, rss_num, p_params->vport_id,
  2100. p_params->p_sb->igu_sb_id);
  2101. return 0;
  2102. }
  2103. static int qed_stop_rxq(struct qed_dev *cdev, u8 rss_id, void *handle)
  2104. {
  2105. int rc, hwfn_index;
  2106. struct qed_hwfn *p_hwfn;
  2107. hwfn_index = rss_id % cdev->num_hwfns;
  2108. p_hwfn = &cdev->hwfns[hwfn_index];
  2109. rc = qed_eth_rx_queue_stop(p_hwfn, handle, false, false);
  2110. if (rc) {
  2111. DP_ERR(cdev, "Failed to stop RXQ#%02x\n", rss_id);
  2112. return rc;
  2113. }
  2114. return 0;
  2115. }
  2116. static int qed_start_txq(struct qed_dev *cdev,
  2117. u8 rss_num,
  2118. struct qed_queue_start_common_params *p_params,
  2119. dma_addr_t pbl_addr,
  2120. u16 pbl_size,
  2121. struct qed_txq_start_ret_params *ret_params)
  2122. {
  2123. struct qed_hwfn *p_hwfn;
  2124. int rc, hwfn_index;
  2125. hwfn_index = rss_num % cdev->num_hwfns;
  2126. p_hwfn = &cdev->hwfns[hwfn_index];
  2127. p_params->queue_id = p_params->queue_id / cdev->num_hwfns;
  2128. p_params->stats_id = p_params->vport_id;
  2129. rc = qed_eth_tx_queue_start(p_hwfn,
  2130. p_hwfn->hw_info.opaque_fid,
  2131. p_params, 0,
  2132. pbl_addr, pbl_size, ret_params);
  2133. if (rc) {
  2134. DP_ERR(cdev, "Failed to start TXQ#%d\n", p_params->queue_id);
  2135. return rc;
  2136. }
  2137. DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
  2138. "Started TX-Q %d [rss_num %d] on V-PORT %d and SB igu %d\n",
  2139. p_params->queue_id, rss_num, p_params->vport_id,
  2140. p_params->p_sb->igu_sb_id);
  2141. return 0;
  2142. }
  2143. #define QED_HW_STOP_RETRY_LIMIT (10)
  2144. static int qed_fastpath_stop(struct qed_dev *cdev)
  2145. {
  2146. int rc;
  2147. rc = qed_hw_stop_fastpath(cdev);
  2148. if (rc) {
  2149. DP_ERR(cdev, "Failed to stop Fastpath\n");
  2150. return rc;
  2151. }
  2152. return 0;
  2153. }
  2154. static int qed_stop_txq(struct qed_dev *cdev, u8 rss_id, void *handle)
  2155. {
  2156. struct qed_hwfn *p_hwfn;
  2157. int rc, hwfn_index;
  2158. hwfn_index = rss_id % cdev->num_hwfns;
  2159. p_hwfn = &cdev->hwfns[hwfn_index];
  2160. rc = qed_eth_tx_queue_stop(p_hwfn, handle);
  2161. if (rc) {
  2162. DP_ERR(cdev, "Failed to stop TXQ#%02x\n", rss_id);
  2163. return rc;
  2164. }
  2165. return 0;
  2166. }
  2167. static int qed_tunn_configure(struct qed_dev *cdev,
  2168. struct qed_tunn_params *tunn_params)
  2169. {
  2170. struct qed_tunnel_info tunn_info;
  2171. int i, rc;
  2172. memset(&tunn_info, 0, sizeof(tunn_info));
  2173. if (tunn_params->update_vxlan_port) {
  2174. tunn_info.vxlan_port.b_update_port = true;
  2175. tunn_info.vxlan_port.port = tunn_params->vxlan_port;
  2176. }
  2177. if (tunn_params->update_geneve_port) {
  2178. tunn_info.geneve_port.b_update_port = true;
  2179. tunn_info.geneve_port.port = tunn_params->geneve_port;
  2180. }
  2181. for_each_hwfn(cdev, i) {
  2182. struct qed_hwfn *hwfn = &cdev->hwfns[i];
  2183. struct qed_ptt *p_ptt;
  2184. struct qed_tunnel_info *tun;
  2185. tun = &hwfn->cdev->tunnel;
  2186. if (IS_PF(cdev)) {
  2187. p_ptt = qed_ptt_acquire(hwfn);
  2188. if (!p_ptt)
  2189. return -EAGAIN;
  2190. } else {
  2191. p_ptt = NULL;
  2192. }
  2193. rc = qed_sp_pf_update_tunn_cfg(hwfn, p_ptt, &tunn_info,
  2194. QED_SPQ_MODE_EBLOCK, NULL);
  2195. if (rc) {
  2196. if (IS_PF(cdev))
  2197. qed_ptt_release(hwfn, p_ptt);
  2198. return rc;
  2199. }
  2200. if (IS_PF_SRIOV(hwfn)) {
  2201. u16 vxlan_port, geneve_port;
  2202. int j;
  2203. vxlan_port = tun->vxlan_port.port;
  2204. geneve_port = tun->geneve_port.port;
  2205. qed_for_each_vf(hwfn, j) {
  2206. qed_iov_bulletin_set_udp_ports(hwfn, j,
  2207. vxlan_port,
  2208. geneve_port);
  2209. }
  2210. qed_schedule_iov(hwfn, QED_IOV_WQ_BULLETIN_UPDATE_FLAG);
  2211. }
  2212. if (IS_PF(cdev))
  2213. qed_ptt_release(hwfn, p_ptt);
  2214. }
  2215. return 0;
  2216. }
  2217. static int qed_configure_filter_rx_mode(struct qed_dev *cdev,
  2218. enum qed_filter_rx_mode_type type)
  2219. {
  2220. struct qed_filter_accept_flags accept_flags;
  2221. memset(&accept_flags, 0, sizeof(accept_flags));
  2222. accept_flags.update_rx_mode_config = 1;
  2223. accept_flags.update_tx_mode_config = 1;
  2224. accept_flags.rx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
  2225. QED_ACCEPT_MCAST_MATCHED |
  2226. QED_ACCEPT_BCAST;
  2227. accept_flags.tx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
  2228. QED_ACCEPT_MCAST_MATCHED |
  2229. QED_ACCEPT_BCAST;
  2230. if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
  2231. accept_flags.rx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED |
  2232. QED_ACCEPT_MCAST_UNMATCHED;
  2233. accept_flags.tx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
  2234. } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
  2235. accept_flags.rx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
  2236. accept_flags.tx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
  2237. }
  2238. return qed_filter_accept_cmd(cdev, 0, accept_flags, false, false,
  2239. QED_SPQ_MODE_CB, NULL);
  2240. }
  2241. static int qed_configure_filter_ucast(struct qed_dev *cdev,
  2242. struct qed_filter_ucast_params *params)
  2243. {
  2244. struct qed_filter_ucast ucast;
  2245. if (!params->vlan_valid && !params->mac_valid) {
  2246. DP_NOTICE(cdev,
  2247. "Tried configuring a unicast filter, but both MAC and VLAN are not set\n");
  2248. return -EINVAL;
  2249. }
  2250. memset(&ucast, 0, sizeof(ucast));
  2251. switch (params->type) {
  2252. case QED_FILTER_XCAST_TYPE_ADD:
  2253. ucast.opcode = QED_FILTER_ADD;
  2254. break;
  2255. case QED_FILTER_XCAST_TYPE_DEL:
  2256. ucast.opcode = QED_FILTER_REMOVE;
  2257. break;
  2258. case QED_FILTER_XCAST_TYPE_REPLACE:
  2259. ucast.opcode = QED_FILTER_REPLACE;
  2260. break;
  2261. default:
  2262. DP_NOTICE(cdev, "Unknown unicast filter type %d\n",
  2263. params->type);
  2264. }
  2265. if (params->vlan_valid && params->mac_valid) {
  2266. ucast.type = QED_FILTER_MAC_VLAN;
  2267. ether_addr_copy(ucast.mac, params->mac);
  2268. ucast.vlan = params->vlan;
  2269. } else if (params->mac_valid) {
  2270. ucast.type = QED_FILTER_MAC;
  2271. ether_addr_copy(ucast.mac, params->mac);
  2272. } else {
  2273. ucast.type = QED_FILTER_VLAN;
  2274. ucast.vlan = params->vlan;
  2275. }
  2276. ucast.is_rx_filter = true;
  2277. ucast.is_tx_filter = true;
  2278. return qed_filter_ucast_cmd(cdev, &ucast, QED_SPQ_MODE_CB, NULL);
  2279. }
  2280. static int qed_configure_filter_mcast(struct qed_dev *cdev,
  2281. struct qed_filter_mcast_params *params)
  2282. {
  2283. struct qed_filter_mcast mcast;
  2284. int i;
  2285. memset(&mcast, 0, sizeof(mcast));
  2286. switch (params->type) {
  2287. case QED_FILTER_XCAST_TYPE_ADD:
  2288. mcast.opcode = QED_FILTER_ADD;
  2289. break;
  2290. case QED_FILTER_XCAST_TYPE_DEL:
  2291. mcast.opcode = QED_FILTER_REMOVE;
  2292. break;
  2293. default:
  2294. DP_NOTICE(cdev, "Unknown multicast filter type %d\n",
  2295. params->type);
  2296. }
  2297. mcast.num_mc_addrs = params->num;
  2298. for (i = 0; i < mcast.num_mc_addrs; i++)
  2299. ether_addr_copy(mcast.mac[i], params->mac[i]);
  2300. return qed_filter_mcast_cmd(cdev, &mcast, QED_SPQ_MODE_CB, NULL);
  2301. }
  2302. static int qed_configure_filter(struct qed_dev *cdev,
  2303. struct qed_filter_params *params)
  2304. {
  2305. enum qed_filter_rx_mode_type accept_flags;
  2306. switch (params->type) {
  2307. case QED_FILTER_TYPE_UCAST:
  2308. return qed_configure_filter_ucast(cdev, &params->filter.ucast);
  2309. case QED_FILTER_TYPE_MCAST:
  2310. return qed_configure_filter_mcast(cdev, &params->filter.mcast);
  2311. case QED_FILTER_TYPE_RX_MODE:
  2312. accept_flags = params->filter.accept_flags;
  2313. return qed_configure_filter_rx_mode(cdev, accept_flags);
  2314. default:
  2315. DP_NOTICE(cdev, "Unknown filter type %d\n", (int)params->type);
  2316. return -EINVAL;
  2317. }
  2318. }
  2319. static int qed_configure_arfs_searcher(struct qed_dev *cdev,
  2320. enum qed_filter_config_mode mode)
  2321. {
  2322. struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
  2323. struct qed_arfs_config_params arfs_config_params;
  2324. memset(&arfs_config_params, 0, sizeof(arfs_config_params));
  2325. arfs_config_params.tcp = true;
  2326. arfs_config_params.udp = true;
  2327. arfs_config_params.ipv4 = true;
  2328. arfs_config_params.ipv6 = true;
  2329. arfs_config_params.mode = mode;
  2330. qed_arfs_mode_configure(p_hwfn, p_hwfn->p_arfs_ptt,
  2331. &arfs_config_params);
  2332. return 0;
  2333. }
  2334. static void
  2335. qed_arfs_sp_response_handler(struct qed_hwfn *p_hwfn,
  2336. void *cookie,
  2337. union event_ring_data *data, u8 fw_return_code)
  2338. {
  2339. struct qed_common_cb_ops *op = p_hwfn->cdev->protocol_ops.common;
  2340. void *dev = p_hwfn->cdev->ops_cookie;
  2341. op->arfs_filter_op(dev, cookie, fw_return_code);
  2342. }
  2343. static int
  2344. qed_ntuple_arfs_filter_config(struct qed_dev *cdev,
  2345. void *cookie,
  2346. struct qed_ntuple_filter_params *params)
  2347. {
  2348. struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
  2349. struct qed_spq_comp_cb cb;
  2350. int rc = -EINVAL;
  2351. cb.function = qed_arfs_sp_response_handler;
  2352. cb.cookie = cookie;
  2353. if (params->b_is_vf) {
  2354. if (!qed_iov_is_valid_vfid(p_hwfn, params->vf_id, false,
  2355. false)) {
  2356. DP_INFO(p_hwfn, "vfid 0x%02x is out of bounds\n",
  2357. params->vf_id);
  2358. return rc;
  2359. }
  2360. params->vport_id = params->vf_id + 1;
  2361. params->qid = QED_RFS_NTUPLE_QID_RSS;
  2362. }
  2363. rc = qed_configure_rfs_ntuple_filter(p_hwfn, &cb, params);
  2364. if (rc)
  2365. DP_NOTICE(p_hwfn,
  2366. "Failed to issue a-RFS filter configuration\n");
  2367. else
  2368. DP_VERBOSE(p_hwfn, NETIF_MSG_DRV,
  2369. "Successfully issued a-RFS filter configuration\n");
  2370. return rc;
  2371. }
  2372. static int qed_get_coalesce(struct qed_dev *cdev, u16 *coal, void *handle)
  2373. {
  2374. struct qed_queue_cid *p_cid = handle;
  2375. struct qed_hwfn *p_hwfn;
  2376. int rc;
  2377. p_hwfn = p_cid->p_owner;
  2378. rc = qed_get_queue_coalesce(p_hwfn, coal, handle);
  2379. if (rc)
  2380. DP_NOTICE(p_hwfn, "Unable to read queue coalescing\n");
  2381. return rc;
  2382. }
  2383. static int qed_fp_cqe_completion(struct qed_dev *dev,
  2384. u8 rss_id, struct eth_slow_path_rx_cqe *cqe)
  2385. {
  2386. return qed_eth_cqe_completion(&dev->hwfns[rss_id % dev->num_hwfns],
  2387. cqe);
  2388. }
  2389. static int qed_req_bulletin_update_mac(struct qed_dev *cdev, u8 *mac)
  2390. {
  2391. int i, ret;
  2392. if (IS_PF(cdev))
  2393. return 0;
  2394. for_each_hwfn(cdev, i) {
  2395. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  2396. ret = qed_vf_pf_bulletin_update_mac(p_hwfn, mac);
  2397. if (ret)
  2398. return ret;
  2399. }
  2400. return 0;
  2401. }
  2402. #ifdef CONFIG_QED_SRIOV
  2403. extern const struct qed_iov_hv_ops qed_iov_ops_pass;
  2404. #endif
  2405. #ifdef CONFIG_DCB
  2406. extern const struct qed_eth_dcbnl_ops qed_dcbnl_ops_pass;
  2407. #endif
  2408. extern const struct qed_eth_ptp_ops qed_ptp_ops_pass;
  2409. static const struct qed_eth_ops qed_eth_ops_pass = {
  2410. .common = &qed_common_ops_pass,
  2411. #ifdef CONFIG_QED_SRIOV
  2412. .iov = &qed_iov_ops_pass,
  2413. #endif
  2414. #ifdef CONFIG_DCB
  2415. .dcb = &qed_dcbnl_ops_pass,
  2416. #endif
  2417. .ptp = &qed_ptp_ops_pass,
  2418. .fill_dev_info = &qed_fill_eth_dev_info,
  2419. .register_ops = &qed_register_eth_ops,
  2420. .check_mac = &qed_check_mac,
  2421. .vport_start = &qed_start_vport,
  2422. .vport_stop = &qed_stop_vport,
  2423. .vport_update = &qed_update_vport,
  2424. .q_rx_start = &qed_start_rxq,
  2425. .q_rx_stop = &qed_stop_rxq,
  2426. .q_tx_start = &qed_start_txq,
  2427. .q_tx_stop = &qed_stop_txq,
  2428. .filter_config = &qed_configure_filter,
  2429. .fastpath_stop = &qed_fastpath_stop,
  2430. .eth_cqe_completion = &qed_fp_cqe_completion,
  2431. .get_vport_stats = &qed_get_vport_stats,
  2432. .tunn_config = &qed_tunn_configure,
  2433. .ntuple_filter_config = &qed_ntuple_arfs_filter_config,
  2434. .configure_arfs_searcher = &qed_configure_arfs_searcher,
  2435. .get_coalesce = &qed_get_coalesce,
  2436. .req_bulletin_update_mac = &qed_req_bulletin_update_mac,
  2437. };
  2438. const struct qed_eth_ops *qed_get_eth_ops(void)
  2439. {
  2440. return &qed_eth_ops_pass;
  2441. }
  2442. EXPORT_SYMBOL(qed_get_eth_ops);
  2443. void qed_put_eth_ops(void)
  2444. {
  2445. /* TODO - reference count for module? */
  2446. }
  2447. EXPORT_SYMBOL(qed_put_eth_ops);