w90p910_ether.c 25 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Nuvoton technology corporation.
  3. *
  4. * Wan ZongShun <mcuos.com@gmail.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation;version 2 of the License.
  9. *
  10. */
  11. #include <linux/module.h>
  12. #include <linux/init.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/mii.h>
  15. #include <linux/netdevice.h>
  16. #include <linux/etherdevice.h>
  17. #include <linux/skbuff.h>
  18. #include <linux/ethtool.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/clk.h>
  21. #include <linux/gfp.h>
  22. #define DRV_MODULE_NAME "w90p910-emc"
  23. #define DRV_MODULE_VERSION "0.1"
  24. /* Ethernet MAC Registers */
  25. #define REG_CAMCMR 0x00
  26. #define REG_CAMEN 0x04
  27. #define REG_CAMM_BASE 0x08
  28. #define REG_CAML_BASE 0x0c
  29. #define REG_TXDLSA 0x88
  30. #define REG_RXDLSA 0x8C
  31. #define REG_MCMDR 0x90
  32. #define REG_MIID 0x94
  33. #define REG_MIIDA 0x98
  34. #define REG_FFTCR 0x9C
  35. #define REG_TSDR 0xa0
  36. #define REG_RSDR 0xa4
  37. #define REG_DMARFC 0xa8
  38. #define REG_MIEN 0xac
  39. #define REG_MISTA 0xb0
  40. #define REG_CTXDSA 0xcc
  41. #define REG_CTXBSA 0xd0
  42. #define REG_CRXDSA 0xd4
  43. #define REG_CRXBSA 0xd8
  44. /* mac controller bit */
  45. #define MCMDR_RXON 0x01
  46. #define MCMDR_ACP (0x01 << 3)
  47. #define MCMDR_SPCRC (0x01 << 5)
  48. #define MCMDR_TXON (0x01 << 8)
  49. #define MCMDR_FDUP (0x01 << 18)
  50. #define MCMDR_ENMDC (0x01 << 19)
  51. #define MCMDR_OPMOD (0x01 << 20)
  52. #define SWR (0x01 << 24)
  53. /* cam command regiser */
  54. #define CAMCMR_AUP 0x01
  55. #define CAMCMR_AMP (0x01 << 1)
  56. #define CAMCMR_ABP (0x01 << 2)
  57. #define CAMCMR_CCAM (0x01 << 3)
  58. #define CAMCMR_ECMP (0x01 << 4)
  59. #define CAM0EN 0x01
  60. /* mac mii controller bit */
  61. #define MDCCR (0x0a << 20)
  62. #define PHYAD (0x01 << 8)
  63. #define PHYWR (0x01 << 16)
  64. #define PHYBUSY (0x01 << 17)
  65. #define PHYPRESP (0x01 << 18)
  66. #define CAM_ENTRY_SIZE 0x08
  67. /* rx and tx status */
  68. #define TXDS_TXCP (0x01 << 19)
  69. #define RXDS_CRCE (0x01 << 17)
  70. #define RXDS_PTLE (0x01 << 19)
  71. #define RXDS_RXGD (0x01 << 20)
  72. #define RXDS_ALIE (0x01 << 21)
  73. #define RXDS_RP (0x01 << 22)
  74. /* mac interrupt status*/
  75. #define MISTA_EXDEF (0x01 << 19)
  76. #define MISTA_TXBERR (0x01 << 24)
  77. #define MISTA_TDU (0x01 << 23)
  78. #define MISTA_RDU (0x01 << 10)
  79. #define MISTA_RXBERR (0x01 << 11)
  80. #define ENSTART 0x01
  81. #define ENRXINTR 0x01
  82. #define ENRXGD (0x01 << 4)
  83. #define ENRXBERR (0x01 << 11)
  84. #define ENTXINTR (0x01 << 16)
  85. #define ENTXCP (0x01 << 18)
  86. #define ENTXABT (0x01 << 21)
  87. #define ENTXBERR (0x01 << 24)
  88. #define ENMDC (0x01 << 19)
  89. #define PHYBUSY (0x01 << 17)
  90. #define MDCCR_VAL 0xa00000
  91. /* rx and tx owner bit */
  92. #define RX_OWEN_DMA (0x01 << 31)
  93. #define RX_OWEN_CPU (~(0x03 << 30))
  94. #define TX_OWEN_DMA (0x01 << 31)
  95. #define TX_OWEN_CPU (~(0x01 << 31))
  96. /* tx frame desc controller bit */
  97. #define MACTXINTEN 0x04
  98. #define CRCMODE 0x02
  99. #define PADDINGMODE 0x01
  100. /* fftcr controller bit */
  101. #define TXTHD (0x03 << 8)
  102. #define BLENGTH (0x01 << 20)
  103. /* global setting for driver */
  104. #define RX_DESC_SIZE 50
  105. #define TX_DESC_SIZE 10
  106. #define MAX_RBUFF_SZ 0x600
  107. #define MAX_TBUFF_SZ 0x600
  108. #define TX_TIMEOUT (HZ/2)
  109. #define DELAY 1000
  110. #define CAM0 0x0
  111. static int w90p910_mdio_read(struct net_device *dev, int phy_id, int reg);
  112. struct w90p910_rxbd {
  113. unsigned int sl;
  114. unsigned int buffer;
  115. unsigned int reserved;
  116. unsigned int next;
  117. };
  118. struct w90p910_txbd {
  119. unsigned int mode;
  120. unsigned int buffer;
  121. unsigned int sl;
  122. unsigned int next;
  123. };
  124. struct recv_pdesc {
  125. struct w90p910_rxbd desclist[RX_DESC_SIZE];
  126. char recv_buf[RX_DESC_SIZE][MAX_RBUFF_SZ];
  127. };
  128. struct tran_pdesc {
  129. struct w90p910_txbd desclist[TX_DESC_SIZE];
  130. char tran_buf[TX_DESC_SIZE][MAX_TBUFF_SZ];
  131. };
  132. struct w90p910_ether {
  133. struct recv_pdesc *rdesc;
  134. struct tran_pdesc *tdesc;
  135. dma_addr_t rdesc_phys;
  136. dma_addr_t tdesc_phys;
  137. struct platform_device *pdev;
  138. struct resource *res;
  139. struct sk_buff *skb;
  140. struct clk *clk;
  141. struct clk *rmiiclk;
  142. struct mii_if_info mii;
  143. struct timer_list check_timer;
  144. void __iomem *reg;
  145. int rxirq;
  146. int txirq;
  147. unsigned int cur_tx;
  148. unsigned int cur_rx;
  149. unsigned int finish_tx;
  150. unsigned int rx_packets;
  151. unsigned int rx_bytes;
  152. unsigned int start_tx_ptr;
  153. unsigned int start_rx_ptr;
  154. unsigned int linkflag;
  155. };
  156. static void update_linkspeed_register(struct net_device *dev,
  157. unsigned int speed, unsigned int duplex)
  158. {
  159. struct w90p910_ether *ether = netdev_priv(dev);
  160. unsigned int val;
  161. val = __raw_readl(ether->reg + REG_MCMDR);
  162. if (speed == SPEED_100) {
  163. /* 100 full/half duplex */
  164. if (duplex == DUPLEX_FULL) {
  165. val |= (MCMDR_OPMOD | MCMDR_FDUP);
  166. } else {
  167. val |= MCMDR_OPMOD;
  168. val &= ~MCMDR_FDUP;
  169. }
  170. } else {
  171. /* 10 full/half duplex */
  172. if (duplex == DUPLEX_FULL) {
  173. val |= MCMDR_FDUP;
  174. val &= ~MCMDR_OPMOD;
  175. } else {
  176. val &= ~(MCMDR_FDUP | MCMDR_OPMOD);
  177. }
  178. }
  179. __raw_writel(val, ether->reg + REG_MCMDR);
  180. }
  181. static void update_linkspeed(struct net_device *dev)
  182. {
  183. struct w90p910_ether *ether = netdev_priv(dev);
  184. struct platform_device *pdev;
  185. unsigned int bmsr, bmcr, lpa, speed, duplex;
  186. pdev = ether->pdev;
  187. if (!mii_link_ok(&ether->mii)) {
  188. ether->linkflag = 0x0;
  189. netif_carrier_off(dev);
  190. dev_warn(&pdev->dev, "%s: Link down.\n", dev->name);
  191. return;
  192. }
  193. if (ether->linkflag == 1)
  194. return;
  195. bmsr = w90p910_mdio_read(dev, ether->mii.phy_id, MII_BMSR);
  196. bmcr = w90p910_mdio_read(dev, ether->mii.phy_id, MII_BMCR);
  197. if (bmcr & BMCR_ANENABLE) {
  198. if (!(bmsr & BMSR_ANEGCOMPLETE))
  199. return;
  200. lpa = w90p910_mdio_read(dev, ether->mii.phy_id, MII_LPA);
  201. if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF))
  202. speed = SPEED_100;
  203. else
  204. speed = SPEED_10;
  205. if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL))
  206. duplex = DUPLEX_FULL;
  207. else
  208. duplex = DUPLEX_HALF;
  209. } else {
  210. speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
  211. duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
  212. }
  213. update_linkspeed_register(dev, speed, duplex);
  214. dev_info(&pdev->dev, "%s: Link now %i-%s\n", dev->name, speed,
  215. (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex");
  216. ether->linkflag = 0x01;
  217. netif_carrier_on(dev);
  218. }
  219. static void w90p910_check_link(struct timer_list *t)
  220. {
  221. struct w90p910_ether *ether = from_timer(ether, t, check_timer);
  222. struct net_device *dev = ether->mii.dev;
  223. update_linkspeed(dev);
  224. mod_timer(&ether->check_timer, jiffies + msecs_to_jiffies(1000));
  225. }
  226. static void w90p910_write_cam(struct net_device *dev,
  227. unsigned int x, unsigned char *pval)
  228. {
  229. struct w90p910_ether *ether = netdev_priv(dev);
  230. unsigned int msw, lsw;
  231. msw = (pval[0] << 24) | (pval[1] << 16) | (pval[2] << 8) | pval[3];
  232. lsw = (pval[4] << 24) | (pval[5] << 16);
  233. __raw_writel(lsw, ether->reg + REG_CAML_BASE + x * CAM_ENTRY_SIZE);
  234. __raw_writel(msw, ether->reg + REG_CAMM_BASE + x * CAM_ENTRY_SIZE);
  235. }
  236. static int w90p910_init_desc(struct net_device *dev)
  237. {
  238. struct w90p910_ether *ether;
  239. struct w90p910_txbd *tdesc;
  240. struct w90p910_rxbd *rdesc;
  241. struct platform_device *pdev;
  242. unsigned int i;
  243. ether = netdev_priv(dev);
  244. pdev = ether->pdev;
  245. ether->tdesc = dma_alloc_coherent(&pdev->dev, sizeof(struct tran_pdesc),
  246. &ether->tdesc_phys, GFP_KERNEL);
  247. if (!ether->tdesc)
  248. return -ENOMEM;
  249. ether->rdesc = dma_alloc_coherent(&pdev->dev, sizeof(struct recv_pdesc),
  250. &ether->rdesc_phys, GFP_KERNEL);
  251. if (!ether->rdesc) {
  252. dma_free_coherent(&pdev->dev, sizeof(struct tran_pdesc),
  253. ether->tdesc, ether->tdesc_phys);
  254. return -ENOMEM;
  255. }
  256. for (i = 0; i < TX_DESC_SIZE; i++) {
  257. unsigned int offset;
  258. tdesc = &(ether->tdesc->desclist[i]);
  259. if (i == TX_DESC_SIZE - 1)
  260. offset = offsetof(struct tran_pdesc, desclist[0]);
  261. else
  262. offset = offsetof(struct tran_pdesc, desclist[i + 1]);
  263. tdesc->next = ether->tdesc_phys + offset;
  264. tdesc->buffer = ether->tdesc_phys +
  265. offsetof(struct tran_pdesc, tran_buf[i]);
  266. tdesc->sl = 0;
  267. tdesc->mode = 0;
  268. }
  269. ether->start_tx_ptr = ether->tdesc_phys;
  270. for (i = 0; i < RX_DESC_SIZE; i++) {
  271. unsigned int offset;
  272. rdesc = &(ether->rdesc->desclist[i]);
  273. if (i == RX_DESC_SIZE - 1)
  274. offset = offsetof(struct recv_pdesc, desclist[0]);
  275. else
  276. offset = offsetof(struct recv_pdesc, desclist[i + 1]);
  277. rdesc->next = ether->rdesc_phys + offset;
  278. rdesc->sl = RX_OWEN_DMA;
  279. rdesc->buffer = ether->rdesc_phys +
  280. offsetof(struct recv_pdesc, recv_buf[i]);
  281. }
  282. ether->start_rx_ptr = ether->rdesc_phys;
  283. return 0;
  284. }
  285. static void w90p910_set_fifo_threshold(struct net_device *dev)
  286. {
  287. struct w90p910_ether *ether = netdev_priv(dev);
  288. unsigned int val;
  289. val = TXTHD | BLENGTH;
  290. __raw_writel(val, ether->reg + REG_FFTCR);
  291. }
  292. static void w90p910_return_default_idle(struct net_device *dev)
  293. {
  294. struct w90p910_ether *ether = netdev_priv(dev);
  295. unsigned int val;
  296. val = __raw_readl(ether->reg + REG_MCMDR);
  297. val |= SWR;
  298. __raw_writel(val, ether->reg + REG_MCMDR);
  299. }
  300. static void w90p910_trigger_rx(struct net_device *dev)
  301. {
  302. struct w90p910_ether *ether = netdev_priv(dev);
  303. __raw_writel(ENSTART, ether->reg + REG_RSDR);
  304. }
  305. static void w90p910_trigger_tx(struct net_device *dev)
  306. {
  307. struct w90p910_ether *ether = netdev_priv(dev);
  308. __raw_writel(ENSTART, ether->reg + REG_TSDR);
  309. }
  310. static void w90p910_enable_mac_interrupt(struct net_device *dev)
  311. {
  312. struct w90p910_ether *ether = netdev_priv(dev);
  313. unsigned int val;
  314. val = ENTXINTR | ENRXINTR | ENRXGD | ENTXCP;
  315. val |= ENTXBERR | ENRXBERR | ENTXABT;
  316. __raw_writel(val, ether->reg + REG_MIEN);
  317. }
  318. static void w90p910_get_and_clear_int(struct net_device *dev,
  319. unsigned int *val)
  320. {
  321. struct w90p910_ether *ether = netdev_priv(dev);
  322. *val = __raw_readl(ether->reg + REG_MISTA);
  323. __raw_writel(*val, ether->reg + REG_MISTA);
  324. }
  325. static void w90p910_set_global_maccmd(struct net_device *dev)
  326. {
  327. struct w90p910_ether *ether = netdev_priv(dev);
  328. unsigned int val;
  329. val = __raw_readl(ether->reg + REG_MCMDR);
  330. val |= MCMDR_SPCRC | MCMDR_ENMDC | MCMDR_ACP | ENMDC;
  331. __raw_writel(val, ether->reg + REG_MCMDR);
  332. }
  333. static void w90p910_enable_cam(struct net_device *dev)
  334. {
  335. struct w90p910_ether *ether = netdev_priv(dev);
  336. unsigned int val;
  337. w90p910_write_cam(dev, CAM0, dev->dev_addr);
  338. val = __raw_readl(ether->reg + REG_CAMEN);
  339. val |= CAM0EN;
  340. __raw_writel(val, ether->reg + REG_CAMEN);
  341. }
  342. static void w90p910_enable_cam_command(struct net_device *dev)
  343. {
  344. struct w90p910_ether *ether = netdev_priv(dev);
  345. unsigned int val;
  346. val = CAMCMR_ECMP | CAMCMR_ABP | CAMCMR_AMP;
  347. __raw_writel(val, ether->reg + REG_CAMCMR);
  348. }
  349. static void w90p910_enable_tx(struct net_device *dev, unsigned int enable)
  350. {
  351. struct w90p910_ether *ether = netdev_priv(dev);
  352. unsigned int val;
  353. val = __raw_readl(ether->reg + REG_MCMDR);
  354. if (enable)
  355. val |= MCMDR_TXON;
  356. else
  357. val &= ~MCMDR_TXON;
  358. __raw_writel(val, ether->reg + REG_MCMDR);
  359. }
  360. static void w90p910_enable_rx(struct net_device *dev, unsigned int enable)
  361. {
  362. struct w90p910_ether *ether = netdev_priv(dev);
  363. unsigned int val;
  364. val = __raw_readl(ether->reg + REG_MCMDR);
  365. if (enable)
  366. val |= MCMDR_RXON;
  367. else
  368. val &= ~MCMDR_RXON;
  369. __raw_writel(val, ether->reg + REG_MCMDR);
  370. }
  371. static void w90p910_set_curdest(struct net_device *dev)
  372. {
  373. struct w90p910_ether *ether = netdev_priv(dev);
  374. __raw_writel(ether->start_rx_ptr, ether->reg + REG_RXDLSA);
  375. __raw_writel(ether->start_tx_ptr, ether->reg + REG_TXDLSA);
  376. }
  377. static void w90p910_reset_mac(struct net_device *dev)
  378. {
  379. struct w90p910_ether *ether = netdev_priv(dev);
  380. w90p910_enable_tx(dev, 0);
  381. w90p910_enable_rx(dev, 0);
  382. w90p910_set_fifo_threshold(dev);
  383. w90p910_return_default_idle(dev);
  384. if (!netif_queue_stopped(dev))
  385. netif_stop_queue(dev);
  386. w90p910_init_desc(dev);
  387. netif_trans_update(dev); /* prevent tx timeout */
  388. ether->cur_tx = 0x0;
  389. ether->finish_tx = 0x0;
  390. ether->cur_rx = 0x0;
  391. w90p910_set_curdest(dev);
  392. w90p910_enable_cam(dev);
  393. w90p910_enable_cam_command(dev);
  394. w90p910_enable_mac_interrupt(dev);
  395. w90p910_enable_tx(dev, 1);
  396. w90p910_enable_rx(dev, 1);
  397. w90p910_trigger_tx(dev);
  398. w90p910_trigger_rx(dev);
  399. netif_trans_update(dev); /* prevent tx timeout */
  400. if (netif_queue_stopped(dev))
  401. netif_wake_queue(dev);
  402. }
  403. static void w90p910_mdio_write(struct net_device *dev,
  404. int phy_id, int reg, int data)
  405. {
  406. struct w90p910_ether *ether = netdev_priv(dev);
  407. struct platform_device *pdev;
  408. unsigned int val, i;
  409. pdev = ether->pdev;
  410. __raw_writel(data, ether->reg + REG_MIID);
  411. val = (phy_id << 0x08) | reg;
  412. val |= PHYBUSY | PHYWR | MDCCR_VAL;
  413. __raw_writel(val, ether->reg + REG_MIIDA);
  414. for (i = 0; i < DELAY; i++) {
  415. if ((__raw_readl(ether->reg + REG_MIIDA) & PHYBUSY) == 0)
  416. break;
  417. }
  418. if (i == DELAY)
  419. dev_warn(&pdev->dev, "mdio write timed out\n");
  420. }
  421. static int w90p910_mdio_read(struct net_device *dev, int phy_id, int reg)
  422. {
  423. struct w90p910_ether *ether = netdev_priv(dev);
  424. struct platform_device *pdev;
  425. unsigned int val, i, data;
  426. pdev = ether->pdev;
  427. val = (phy_id << 0x08) | reg;
  428. val |= PHYBUSY | MDCCR_VAL;
  429. __raw_writel(val, ether->reg + REG_MIIDA);
  430. for (i = 0; i < DELAY; i++) {
  431. if ((__raw_readl(ether->reg + REG_MIIDA) & PHYBUSY) == 0)
  432. break;
  433. }
  434. if (i == DELAY) {
  435. dev_warn(&pdev->dev, "mdio read timed out\n");
  436. data = 0xffff;
  437. } else {
  438. data = __raw_readl(ether->reg + REG_MIID);
  439. }
  440. return data;
  441. }
  442. static int w90p910_set_mac_address(struct net_device *dev, void *addr)
  443. {
  444. struct sockaddr *address = addr;
  445. if (!is_valid_ether_addr(address->sa_data))
  446. return -EADDRNOTAVAIL;
  447. memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
  448. w90p910_write_cam(dev, CAM0, dev->dev_addr);
  449. return 0;
  450. }
  451. static int w90p910_ether_close(struct net_device *dev)
  452. {
  453. struct w90p910_ether *ether = netdev_priv(dev);
  454. struct platform_device *pdev;
  455. pdev = ether->pdev;
  456. dma_free_coherent(&pdev->dev, sizeof(struct recv_pdesc),
  457. ether->rdesc, ether->rdesc_phys);
  458. dma_free_coherent(&pdev->dev, sizeof(struct tran_pdesc),
  459. ether->tdesc, ether->tdesc_phys);
  460. netif_stop_queue(dev);
  461. del_timer_sync(&ether->check_timer);
  462. clk_disable(ether->rmiiclk);
  463. clk_disable(ether->clk);
  464. free_irq(ether->txirq, dev);
  465. free_irq(ether->rxirq, dev);
  466. return 0;
  467. }
  468. static int w90p910_send_frame(struct net_device *dev,
  469. unsigned char *data, int length)
  470. {
  471. struct w90p910_ether *ether;
  472. struct w90p910_txbd *txbd;
  473. struct platform_device *pdev;
  474. unsigned char *buffer;
  475. ether = netdev_priv(dev);
  476. pdev = ether->pdev;
  477. txbd = &ether->tdesc->desclist[ether->cur_tx];
  478. buffer = ether->tdesc->tran_buf[ether->cur_tx];
  479. if (length > 1514) {
  480. dev_err(&pdev->dev, "send data %d bytes, check it\n", length);
  481. length = 1514;
  482. }
  483. txbd->sl = length & 0xFFFF;
  484. memcpy(buffer, data, length);
  485. txbd->mode = TX_OWEN_DMA | PADDINGMODE | CRCMODE | MACTXINTEN;
  486. w90p910_enable_tx(dev, 1);
  487. w90p910_trigger_tx(dev);
  488. if (++ether->cur_tx >= TX_DESC_SIZE)
  489. ether->cur_tx = 0;
  490. txbd = &ether->tdesc->desclist[ether->cur_tx];
  491. if (txbd->mode & TX_OWEN_DMA)
  492. netif_stop_queue(dev);
  493. return 0;
  494. }
  495. static int w90p910_ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
  496. {
  497. struct w90p910_ether *ether = netdev_priv(dev);
  498. if (!(w90p910_send_frame(dev, skb->data, skb->len))) {
  499. ether->skb = skb;
  500. dev_kfree_skb_irq(skb);
  501. return 0;
  502. }
  503. return -EAGAIN;
  504. }
  505. static irqreturn_t w90p910_tx_interrupt(int irq, void *dev_id)
  506. {
  507. struct w90p910_ether *ether;
  508. struct w90p910_txbd *txbd;
  509. struct platform_device *pdev;
  510. struct net_device *dev;
  511. unsigned int cur_entry, entry, status;
  512. dev = dev_id;
  513. ether = netdev_priv(dev);
  514. pdev = ether->pdev;
  515. w90p910_get_and_clear_int(dev, &status);
  516. cur_entry = __raw_readl(ether->reg + REG_CTXDSA);
  517. entry = ether->tdesc_phys +
  518. offsetof(struct tran_pdesc, desclist[ether->finish_tx]);
  519. while (entry != cur_entry) {
  520. txbd = &ether->tdesc->desclist[ether->finish_tx];
  521. if (++ether->finish_tx >= TX_DESC_SIZE)
  522. ether->finish_tx = 0;
  523. if (txbd->sl & TXDS_TXCP) {
  524. dev->stats.tx_packets++;
  525. dev->stats.tx_bytes += txbd->sl & 0xFFFF;
  526. } else {
  527. dev->stats.tx_errors++;
  528. }
  529. txbd->sl = 0x0;
  530. txbd->mode = 0x0;
  531. if (netif_queue_stopped(dev))
  532. netif_wake_queue(dev);
  533. entry = ether->tdesc_phys +
  534. offsetof(struct tran_pdesc, desclist[ether->finish_tx]);
  535. }
  536. if (status & MISTA_EXDEF) {
  537. dev_err(&pdev->dev, "emc defer exceed interrupt\n");
  538. } else if (status & MISTA_TXBERR) {
  539. dev_err(&pdev->dev, "emc bus error interrupt\n");
  540. w90p910_reset_mac(dev);
  541. } else if (status & MISTA_TDU) {
  542. if (netif_queue_stopped(dev))
  543. netif_wake_queue(dev);
  544. }
  545. return IRQ_HANDLED;
  546. }
  547. static void netdev_rx(struct net_device *dev)
  548. {
  549. struct w90p910_ether *ether;
  550. struct w90p910_rxbd *rxbd;
  551. struct platform_device *pdev;
  552. struct sk_buff *skb;
  553. unsigned char *data;
  554. unsigned int length, status, val, entry;
  555. ether = netdev_priv(dev);
  556. pdev = ether->pdev;
  557. rxbd = &ether->rdesc->desclist[ether->cur_rx];
  558. do {
  559. val = __raw_readl(ether->reg + REG_CRXDSA);
  560. entry = ether->rdesc_phys +
  561. offsetof(struct recv_pdesc, desclist[ether->cur_rx]);
  562. if (val == entry)
  563. break;
  564. status = rxbd->sl;
  565. length = status & 0xFFFF;
  566. if (status & RXDS_RXGD) {
  567. data = ether->rdesc->recv_buf[ether->cur_rx];
  568. skb = netdev_alloc_skb(dev, length + 2);
  569. if (!skb) {
  570. dev->stats.rx_dropped++;
  571. return;
  572. }
  573. skb_reserve(skb, 2);
  574. skb_put(skb, length);
  575. skb_copy_to_linear_data(skb, data, length);
  576. skb->protocol = eth_type_trans(skb, dev);
  577. dev->stats.rx_packets++;
  578. dev->stats.rx_bytes += length;
  579. netif_rx(skb);
  580. } else {
  581. dev->stats.rx_errors++;
  582. if (status & RXDS_RP) {
  583. dev_err(&pdev->dev, "rx runt err\n");
  584. dev->stats.rx_length_errors++;
  585. } else if (status & RXDS_CRCE) {
  586. dev_err(&pdev->dev, "rx crc err\n");
  587. dev->stats.rx_crc_errors++;
  588. } else if (status & RXDS_ALIE) {
  589. dev_err(&pdev->dev, "rx alignment err\n");
  590. dev->stats.rx_frame_errors++;
  591. } else if (status & RXDS_PTLE) {
  592. dev_err(&pdev->dev, "rx longer err\n");
  593. dev->stats.rx_over_errors++;
  594. }
  595. }
  596. rxbd->sl = RX_OWEN_DMA;
  597. rxbd->reserved = 0x0;
  598. if (++ether->cur_rx >= RX_DESC_SIZE)
  599. ether->cur_rx = 0;
  600. rxbd = &ether->rdesc->desclist[ether->cur_rx];
  601. } while (1);
  602. }
  603. static irqreturn_t w90p910_rx_interrupt(int irq, void *dev_id)
  604. {
  605. struct net_device *dev;
  606. struct w90p910_ether *ether;
  607. struct platform_device *pdev;
  608. unsigned int status;
  609. dev = dev_id;
  610. ether = netdev_priv(dev);
  611. pdev = ether->pdev;
  612. w90p910_get_and_clear_int(dev, &status);
  613. if (status & MISTA_RDU) {
  614. netdev_rx(dev);
  615. w90p910_trigger_rx(dev);
  616. return IRQ_HANDLED;
  617. } else if (status & MISTA_RXBERR) {
  618. dev_err(&pdev->dev, "emc rx bus error\n");
  619. w90p910_reset_mac(dev);
  620. }
  621. netdev_rx(dev);
  622. return IRQ_HANDLED;
  623. }
  624. static int w90p910_ether_open(struct net_device *dev)
  625. {
  626. struct w90p910_ether *ether;
  627. struct platform_device *pdev;
  628. ether = netdev_priv(dev);
  629. pdev = ether->pdev;
  630. w90p910_reset_mac(dev);
  631. w90p910_set_fifo_threshold(dev);
  632. w90p910_set_curdest(dev);
  633. w90p910_enable_cam(dev);
  634. w90p910_enable_cam_command(dev);
  635. w90p910_enable_mac_interrupt(dev);
  636. w90p910_set_global_maccmd(dev);
  637. w90p910_enable_rx(dev, 1);
  638. clk_enable(ether->rmiiclk);
  639. clk_enable(ether->clk);
  640. ether->rx_packets = 0x0;
  641. ether->rx_bytes = 0x0;
  642. if (request_irq(ether->txirq, w90p910_tx_interrupt,
  643. 0x0, pdev->name, dev)) {
  644. dev_err(&pdev->dev, "register irq tx failed\n");
  645. return -EAGAIN;
  646. }
  647. if (request_irq(ether->rxirq, w90p910_rx_interrupt,
  648. 0x0, pdev->name, dev)) {
  649. dev_err(&pdev->dev, "register irq rx failed\n");
  650. free_irq(ether->txirq, dev);
  651. return -EAGAIN;
  652. }
  653. mod_timer(&ether->check_timer, jiffies + msecs_to_jiffies(1000));
  654. netif_start_queue(dev);
  655. w90p910_trigger_rx(dev);
  656. dev_info(&pdev->dev, "%s is OPENED\n", dev->name);
  657. return 0;
  658. }
  659. static void w90p910_ether_set_multicast_list(struct net_device *dev)
  660. {
  661. struct w90p910_ether *ether;
  662. unsigned int rx_mode;
  663. ether = netdev_priv(dev);
  664. if (dev->flags & IFF_PROMISC)
  665. rx_mode = CAMCMR_AUP | CAMCMR_AMP | CAMCMR_ABP | CAMCMR_ECMP;
  666. else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev))
  667. rx_mode = CAMCMR_AMP | CAMCMR_ABP | CAMCMR_ECMP;
  668. else
  669. rx_mode = CAMCMR_ECMP | CAMCMR_ABP;
  670. __raw_writel(rx_mode, ether->reg + REG_CAMCMR);
  671. }
  672. static int w90p910_ether_ioctl(struct net_device *dev,
  673. struct ifreq *ifr, int cmd)
  674. {
  675. struct w90p910_ether *ether = netdev_priv(dev);
  676. struct mii_ioctl_data *data = if_mii(ifr);
  677. return generic_mii_ioctl(&ether->mii, data, cmd, NULL);
  678. }
  679. static void w90p910_get_drvinfo(struct net_device *dev,
  680. struct ethtool_drvinfo *info)
  681. {
  682. strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
  683. strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
  684. }
  685. static int w90p910_get_link_ksettings(struct net_device *dev,
  686. struct ethtool_link_ksettings *cmd)
  687. {
  688. struct w90p910_ether *ether = netdev_priv(dev);
  689. mii_ethtool_get_link_ksettings(&ether->mii, cmd);
  690. return 0;
  691. }
  692. static int w90p910_set_link_ksettings(struct net_device *dev,
  693. const struct ethtool_link_ksettings *cmd)
  694. {
  695. struct w90p910_ether *ether = netdev_priv(dev);
  696. return mii_ethtool_set_link_ksettings(&ether->mii, cmd);
  697. }
  698. static int w90p910_nway_reset(struct net_device *dev)
  699. {
  700. struct w90p910_ether *ether = netdev_priv(dev);
  701. return mii_nway_restart(&ether->mii);
  702. }
  703. static u32 w90p910_get_link(struct net_device *dev)
  704. {
  705. struct w90p910_ether *ether = netdev_priv(dev);
  706. return mii_link_ok(&ether->mii);
  707. }
  708. static const struct ethtool_ops w90p910_ether_ethtool_ops = {
  709. .get_drvinfo = w90p910_get_drvinfo,
  710. .nway_reset = w90p910_nway_reset,
  711. .get_link = w90p910_get_link,
  712. .get_link_ksettings = w90p910_get_link_ksettings,
  713. .set_link_ksettings = w90p910_set_link_ksettings,
  714. };
  715. static const struct net_device_ops w90p910_ether_netdev_ops = {
  716. .ndo_open = w90p910_ether_open,
  717. .ndo_stop = w90p910_ether_close,
  718. .ndo_start_xmit = w90p910_ether_start_xmit,
  719. .ndo_set_rx_mode = w90p910_ether_set_multicast_list,
  720. .ndo_set_mac_address = w90p910_set_mac_address,
  721. .ndo_do_ioctl = w90p910_ether_ioctl,
  722. .ndo_validate_addr = eth_validate_addr,
  723. };
  724. static void __init get_mac_address(struct net_device *dev)
  725. {
  726. struct w90p910_ether *ether = netdev_priv(dev);
  727. struct platform_device *pdev;
  728. char addr[ETH_ALEN];
  729. pdev = ether->pdev;
  730. addr[0] = 0x00;
  731. addr[1] = 0x02;
  732. addr[2] = 0xac;
  733. addr[3] = 0x55;
  734. addr[4] = 0x88;
  735. addr[5] = 0xa8;
  736. if (is_valid_ether_addr(addr))
  737. memcpy(dev->dev_addr, &addr, ETH_ALEN);
  738. else
  739. dev_err(&pdev->dev, "invalid mac address\n");
  740. }
  741. static int w90p910_ether_setup(struct net_device *dev)
  742. {
  743. struct w90p910_ether *ether = netdev_priv(dev);
  744. dev->netdev_ops = &w90p910_ether_netdev_ops;
  745. dev->ethtool_ops = &w90p910_ether_ethtool_ops;
  746. dev->tx_queue_len = 16;
  747. dev->dma = 0x0;
  748. dev->watchdog_timeo = TX_TIMEOUT;
  749. get_mac_address(dev);
  750. ether->cur_tx = 0x0;
  751. ether->cur_rx = 0x0;
  752. ether->finish_tx = 0x0;
  753. ether->linkflag = 0x0;
  754. ether->mii.phy_id = 0x01;
  755. ether->mii.phy_id_mask = 0x1f;
  756. ether->mii.reg_num_mask = 0x1f;
  757. ether->mii.dev = dev;
  758. ether->mii.mdio_read = w90p910_mdio_read;
  759. ether->mii.mdio_write = w90p910_mdio_write;
  760. timer_setup(&ether->check_timer, w90p910_check_link, 0);
  761. return 0;
  762. }
  763. static int w90p910_ether_probe(struct platform_device *pdev)
  764. {
  765. struct w90p910_ether *ether;
  766. struct net_device *dev;
  767. int error;
  768. dev = alloc_etherdev(sizeof(struct w90p910_ether));
  769. if (!dev)
  770. return -ENOMEM;
  771. ether = netdev_priv(dev);
  772. ether->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  773. if (ether->res == NULL) {
  774. dev_err(&pdev->dev, "failed to get I/O memory\n");
  775. error = -ENXIO;
  776. goto failed_free;
  777. }
  778. if (!request_mem_region(ether->res->start,
  779. resource_size(ether->res), pdev->name)) {
  780. dev_err(&pdev->dev, "failed to request I/O memory\n");
  781. error = -EBUSY;
  782. goto failed_free;
  783. }
  784. ether->reg = ioremap(ether->res->start, resource_size(ether->res));
  785. if (ether->reg == NULL) {
  786. dev_err(&pdev->dev, "failed to remap I/O memory\n");
  787. error = -ENXIO;
  788. goto failed_free_mem;
  789. }
  790. ether->txirq = platform_get_irq(pdev, 0);
  791. if (ether->txirq < 0) {
  792. dev_err(&pdev->dev, "failed to get ether tx irq\n");
  793. error = -ENXIO;
  794. goto failed_free_io;
  795. }
  796. ether->rxirq = platform_get_irq(pdev, 1);
  797. if (ether->rxirq < 0) {
  798. dev_err(&pdev->dev, "failed to get ether rx irq\n");
  799. error = -ENXIO;
  800. goto failed_free_io;
  801. }
  802. platform_set_drvdata(pdev, dev);
  803. ether->clk = clk_get(&pdev->dev, NULL);
  804. if (IS_ERR(ether->clk)) {
  805. dev_err(&pdev->dev, "failed to get ether clock\n");
  806. error = PTR_ERR(ether->clk);
  807. goto failed_free_io;
  808. }
  809. ether->rmiiclk = clk_get(&pdev->dev, "RMII");
  810. if (IS_ERR(ether->rmiiclk)) {
  811. dev_err(&pdev->dev, "failed to get ether clock\n");
  812. error = PTR_ERR(ether->rmiiclk);
  813. goto failed_put_clk;
  814. }
  815. ether->pdev = pdev;
  816. w90p910_ether_setup(dev);
  817. error = register_netdev(dev);
  818. if (error != 0) {
  819. dev_err(&pdev->dev, "Register EMC w90p910 FAILED\n");
  820. error = -ENODEV;
  821. goto failed_put_rmiiclk;
  822. }
  823. return 0;
  824. failed_put_rmiiclk:
  825. clk_put(ether->rmiiclk);
  826. failed_put_clk:
  827. clk_put(ether->clk);
  828. failed_free_io:
  829. iounmap(ether->reg);
  830. failed_free_mem:
  831. release_mem_region(ether->res->start, resource_size(ether->res));
  832. failed_free:
  833. free_netdev(dev);
  834. return error;
  835. }
  836. static int w90p910_ether_remove(struct platform_device *pdev)
  837. {
  838. struct net_device *dev = platform_get_drvdata(pdev);
  839. struct w90p910_ether *ether = netdev_priv(dev);
  840. unregister_netdev(dev);
  841. clk_put(ether->rmiiclk);
  842. clk_put(ether->clk);
  843. iounmap(ether->reg);
  844. release_mem_region(ether->res->start, resource_size(ether->res));
  845. del_timer_sync(&ether->check_timer);
  846. free_netdev(dev);
  847. return 0;
  848. }
  849. static struct platform_driver w90p910_ether_driver = {
  850. .probe = w90p910_ether_probe,
  851. .remove = w90p910_ether_remove,
  852. .driver = {
  853. .name = "nuc900-emc",
  854. },
  855. };
  856. module_platform_driver(w90p910_ether_driver);
  857. MODULE_AUTHOR("Wan ZongShun <mcuos.com@gmail.com>");
  858. MODULE_DESCRIPTION("w90p910 MAC driver!");
  859. MODULE_LICENSE("GPL");
  860. MODULE_ALIAS("platform:nuc900-emc");