ocelot_board.c 6.8 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * Microsemi Ocelot Switch driver
  4. *
  5. * Copyright (c) 2017 Microsemi Corporation
  6. */
  7. #include <linux/interrupt.h>
  8. #include <linux/module.h>
  9. #include <linux/netdevice.h>
  10. #include <linux/of_mdio.h>
  11. #include <linux/of_platform.h>
  12. #include <linux/skbuff.h>
  13. #include "ocelot.h"
  14. static int ocelot_parse_ifh(u32 *ifh, struct frame_info *info)
  15. {
  16. int i;
  17. u8 llen, wlen;
  18. /* The IFH is in network order, switch to CPU order */
  19. for (i = 0; i < IFH_LEN; i++)
  20. ifh[i] = ntohl((__force __be32)ifh[i]);
  21. wlen = (ifh[1] >> 7) & 0xff;
  22. llen = (ifh[1] >> 15) & 0x3f;
  23. info->len = OCELOT_BUFFER_CELL_SZ * wlen + llen - 80;
  24. info->port = (ifh[2] & GENMASK(14, 11)) >> 11;
  25. info->cpuq = (ifh[3] & GENMASK(27, 20)) >> 20;
  26. info->tag_type = (ifh[3] & GENMASK(16, 16)) >> 16;
  27. info->vid = ifh[3] & GENMASK(11, 0);
  28. return 0;
  29. }
  30. static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh,
  31. u32 *rval)
  32. {
  33. u32 val;
  34. u32 bytes_valid;
  35. val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  36. if (val == XTR_NOT_READY) {
  37. if (ifh)
  38. return -EIO;
  39. do {
  40. val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  41. } while (val == XTR_NOT_READY);
  42. }
  43. switch (val) {
  44. case XTR_ABORT:
  45. return -EIO;
  46. case XTR_EOF_0:
  47. case XTR_EOF_1:
  48. case XTR_EOF_2:
  49. case XTR_EOF_3:
  50. case XTR_PRUNED:
  51. bytes_valid = XTR_VALID_BYTES(val);
  52. val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  53. if (val == XTR_ESCAPE)
  54. *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  55. else
  56. *rval = val;
  57. return bytes_valid;
  58. case XTR_ESCAPE:
  59. *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  60. return 4;
  61. default:
  62. *rval = val;
  63. return 4;
  64. }
  65. }
  66. static irqreturn_t ocelot_xtr_irq_handler(int irq, void *arg)
  67. {
  68. struct ocelot *ocelot = arg;
  69. int i = 0, grp = 0;
  70. int err = 0;
  71. if (!(ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)))
  72. return IRQ_NONE;
  73. do {
  74. struct sk_buff *skb;
  75. struct net_device *dev;
  76. u32 *buf;
  77. int sz, len;
  78. u32 ifh[4];
  79. u32 val;
  80. struct frame_info info;
  81. for (i = 0; i < IFH_LEN; i++) {
  82. err = ocelot_rx_frame_word(ocelot, grp, true, &ifh[i]);
  83. if (err != 4)
  84. break;
  85. }
  86. if (err != 4)
  87. break;
  88. ocelot_parse_ifh(ifh, &info);
  89. dev = ocelot->ports[info.port]->dev;
  90. skb = netdev_alloc_skb(dev, info.len);
  91. if (unlikely(!skb)) {
  92. netdev_err(dev, "Unable to allocate sk_buff\n");
  93. err = -ENOMEM;
  94. break;
  95. }
  96. buf = (u32 *)skb_put(skb, info.len);
  97. len = 0;
  98. do {
  99. sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
  100. *buf++ = val;
  101. len += sz;
  102. } while ((sz == 4) && (len < info.len));
  103. if (sz < 0) {
  104. err = sz;
  105. break;
  106. }
  107. /* Everything we see on an interface that is in the HW bridge
  108. * has already been forwarded.
  109. */
  110. if (ocelot->bridge_mask & BIT(info.port))
  111. skb->offload_fwd_mark = 1;
  112. skb->protocol = eth_type_trans(skb, dev);
  113. netif_rx(skb);
  114. dev->stats.rx_bytes += len;
  115. dev->stats.rx_packets++;
  116. } while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp));
  117. if (err)
  118. while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp))
  119. ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  120. return IRQ_HANDLED;
  121. }
  122. static const struct of_device_id mscc_ocelot_match[] = {
  123. { .compatible = "mscc,vsc7514-switch" },
  124. { }
  125. };
  126. MODULE_DEVICE_TABLE(of, mscc_ocelot_match);
  127. static int mscc_ocelot_probe(struct platform_device *pdev)
  128. {
  129. int err, irq;
  130. unsigned int i;
  131. struct device_node *np = pdev->dev.of_node;
  132. struct device_node *ports, *portnp;
  133. struct ocelot *ocelot;
  134. u32 val;
  135. struct {
  136. enum ocelot_target id;
  137. char *name;
  138. } res[] = {
  139. { SYS, "sys" },
  140. { REW, "rew" },
  141. { QSYS, "qsys" },
  142. { ANA, "ana" },
  143. { QS, "qs" },
  144. { HSIO, "hsio" },
  145. };
  146. if (!np && !pdev->dev.platform_data)
  147. return -ENODEV;
  148. ocelot = devm_kzalloc(&pdev->dev, sizeof(*ocelot), GFP_KERNEL);
  149. if (!ocelot)
  150. return -ENOMEM;
  151. platform_set_drvdata(pdev, ocelot);
  152. ocelot->dev = &pdev->dev;
  153. for (i = 0; i < ARRAY_SIZE(res); i++) {
  154. struct regmap *target;
  155. target = ocelot_io_platform_init(ocelot, pdev, res[i].name);
  156. if (IS_ERR(target))
  157. return PTR_ERR(target);
  158. ocelot->targets[res[i].id] = target;
  159. }
  160. err = ocelot_chip_init(ocelot);
  161. if (err)
  162. return err;
  163. irq = platform_get_irq_byname(pdev, "xtr");
  164. if (irq < 0)
  165. return -ENODEV;
  166. err = devm_request_threaded_irq(&pdev->dev, irq, NULL,
  167. ocelot_xtr_irq_handler, IRQF_ONESHOT,
  168. "frame extraction", ocelot);
  169. if (err)
  170. return err;
  171. regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1);
  172. regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
  173. do {
  174. msleep(1);
  175. regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT],
  176. &val);
  177. } while (val);
  178. regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
  179. regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1);
  180. ocelot->num_cpu_ports = 1; /* 1 port on the switch, two groups */
  181. ports = of_get_child_by_name(np, "ethernet-ports");
  182. if (!ports) {
  183. dev_err(&pdev->dev, "no ethernet-ports child node found\n");
  184. return -ENODEV;
  185. }
  186. ocelot->num_phys_ports = of_get_child_count(ports);
  187. ocelot->ports = devm_kcalloc(&pdev->dev, ocelot->num_phys_ports,
  188. sizeof(struct ocelot_port *), GFP_KERNEL);
  189. INIT_LIST_HEAD(&ocelot->multicast);
  190. ocelot_init(ocelot);
  191. ocelot_rmw(ocelot, HSIO_HW_CFG_DEV1G_4_MODE |
  192. HSIO_HW_CFG_DEV1G_6_MODE |
  193. HSIO_HW_CFG_DEV1G_9_MODE,
  194. HSIO_HW_CFG_DEV1G_4_MODE |
  195. HSIO_HW_CFG_DEV1G_6_MODE |
  196. HSIO_HW_CFG_DEV1G_9_MODE,
  197. HSIO_HW_CFG);
  198. for_each_available_child_of_node(ports, portnp) {
  199. struct device_node *phy_node;
  200. struct phy_device *phy;
  201. struct resource *res;
  202. void __iomem *regs;
  203. char res_name[8];
  204. u32 port;
  205. if (of_property_read_u32(portnp, "reg", &port))
  206. continue;
  207. snprintf(res_name, sizeof(res_name), "port%d", port);
  208. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  209. res_name);
  210. regs = devm_ioremap_resource(&pdev->dev, res);
  211. if (IS_ERR(regs))
  212. continue;
  213. phy_node = of_parse_phandle(portnp, "phy-handle", 0);
  214. if (!phy_node)
  215. continue;
  216. phy = of_phy_find_device(phy_node);
  217. if (!phy)
  218. continue;
  219. err = ocelot_probe_port(ocelot, port, regs, phy);
  220. if (err) {
  221. dev_err(&pdev->dev, "failed to probe ports\n");
  222. goto err_probe_ports;
  223. }
  224. }
  225. register_netdevice_notifier(&ocelot_netdevice_nb);
  226. dev_info(&pdev->dev, "Ocelot switch probed\n");
  227. return 0;
  228. err_probe_ports:
  229. return err;
  230. }
  231. static int mscc_ocelot_remove(struct platform_device *pdev)
  232. {
  233. struct ocelot *ocelot = platform_get_drvdata(pdev);
  234. ocelot_deinit(ocelot);
  235. unregister_netdevice_notifier(&ocelot_netdevice_nb);
  236. return 0;
  237. }
  238. static struct platform_driver mscc_ocelot_driver = {
  239. .probe = mscc_ocelot_probe,
  240. .remove = mscc_ocelot_remove,
  241. .driver = {
  242. .name = "ocelot-switch",
  243. .of_match_table = mscc_ocelot_match,
  244. },
  245. };
  246. module_platform_driver(mscc_ocelot_driver);
  247. MODULE_DESCRIPTION("Microsemi Ocelot switch driver");
  248. MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>");
  249. MODULE_LICENSE("Dual MIT/GPL");